SN74LVC1G99DCTRE4 [TI]
SPECIALTY LOGIC CIRCUIT, PDSO8, GREEN, PLASTIC, SSOP-8;
| 型号： | SN74LVC1G99DCTRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY LOGIC CIRCUIT, PDSO8, GREEN, PLASTIC, SSOP-8 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总25页 (文件大小：721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUT
Check for Samples: SN74LVC1G99
1
FEATURES
•
Available in Texas Instruments NanoFree™
•
Input Hysteresis Allows for Slow Input
Package
Transition Time and Better Noise Immunity at
Input
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 6.7 ns at 3.3 V
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Offers Nine Different Logic Functions in a
Single Package
1000-V Charged-Device Model (C101)
•
Ioff Supports Partial-Power-Down Mode
Operation
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
4 5
GND
B
C
D
VCC
Y
1
2
3
4
8
7
6
5
OE
A
VCC
Y
1
2
3
4
8
7
6
5
OE
A
3 6
2 7
1 8
A
Y
B
D
VCC
OE
GND
C
B
D
GND
C
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G99 is operational from 1.65 V to 5.5 V.
The SN74LVC1G99 features configurable multiple functions with a 3-state output. The output is disabled when
the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.
The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer.
All inputs can be connected to VCC or GND.
This device functions as an independent inverter, but because of Schmitt action, it has different input threshold
levels for positive-going (VT+) and negative-going (VT–) signals.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
Table 1. ORDERING INFORMATION
TA
PACKAGE(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
DE_
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000 SN74LVC1G99YZPR
Reel of 3000 SN74LVC1G99DCTR
Reel of 250 SN74LVC1G99DCTT
Reel of 3000 SN74LVC1G99DCUR
Reel of 250 SN74LVC1G99DCUT
SSOP – DCT
C99_ _ _
C99_
–40°C to 85°C
VSSOP – DCU
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
2
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technologies are a major breakthrough in IC packaging concepts, using the die as the
package.
FUNCTION TABLE
INPUTS
OUTPUT
OE
L
D
C
B
A
Y
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
H
H
L
H
H
H
L
L
H
H
H
L
H
L
L
L
L
H
L
L
H
L
H
L
H
L
H
L
L
H
L
H
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
L
H
H
L
H
H
H
H
L
H
H or L
H or L
H or L
H or L
Z
Copyright © 2004–2011, Texas Instruments Incorporated
3
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
OE
A
3
5
B
C
7
Y
6
D
FUNCTION SELECTION TABLE
PRIMARY FUNCTION
COMPLEMENTARY FUNCTION
PAGE
3-state buffer
3
3
4
4
5
5
5
6
6
6
7
7
3-state inverter
3-state 2-in-1 data selector MUX
3-state 2-in-1 data selector MUX, inverted out
3-state 2-input AND
3-state 2-input NOR, both inputs inverted
3-state 2-input NOR, one input inverted
3-state 2-input NOR
3-state 2-input AND, one input inverted
3-state 2-input AND, both inputs inverted
3-state 2-input NAND
3-state 2-input OR, both inputs inverted
3-state 2-input OR, one input inverted
3-state 2-input OR
3-state 2-input NAND, one input inverted
3-state 2-input NAND, both inputs inverted
3-state 2-input XOR
3-state 2-input XNOR
3-state 2-input XOR, one input inverted
3-STATE BUFFER FUNCTIONS AVAILABLE
OE
Input
Y
FUNCTION
OE
A
Input
H or L
L
B
H or L
Input
H
C
L
D
L
H
L
Input
Input
L
L
3-state buffer
L
H
L
H
H
H or L
L
Input
Input
Input
H or L
L
H
L
H or L
4
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
3-STATE INVERTER FUNCTIONS AVAILABLE
OE
Input
Y
FUNCTION
OE
A
Input
X
B
H or L
Input
H
C
L
D
H
H
H
L
Input
Input
L
H
3-state buffer
L
H
L
L
H
H or L
H
Input
Input
Input
H or L
H
H
H
H or L
3-STATE MUX FUNCTIONS AVAILABLE
A/B
A/B
Input 1
Input 2
Input 1
Input 2
Y
Y
FUNCTION
OE
A
B
C
D
L
3-state 2-to-1, data selector MUX
3-state 2-to-1, data selector MUX
Input 1
Input 2
Input 1
Input 2
Input 2
Input 1
Input 2
Input 1
Input 1 or Input 2
Input 2 or Input 1
Input 1 or Input 2
Input 2 or Input 1
L
L
3-state 2-to-1, data selector MUX, inverted out
3-state 2-to-1, data selector MUX, inverted out
H
H
Copyright © 2004–2011, Texas Instruments Incorporated
5
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
3-STATE AND/NOR/OR FUNCTIONS AVAILABLE
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state NOR
OE
A
L
L
B
C
D
L
L
2
2
3-state AND
3-state AND
Input 1
Input 2
Input 2
Input 1
L
3-state NOR
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
Y
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state NOR
OE
A
Input 2
H
B
L
C
D
L
2
2
3-state AND
3-state AND
Input 1
Input 2
L
3-state NOR
Input 1
H
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state NOR
OE
A
Input 1
H
B
L
C
D
L
2
2
3-state AND
3-state AND
Input 2
Input 1
L
3-state NOR
Input 2
H
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
3-state NOR
OE
A
B
H
H
C
D
2
2
3-state AND, both inverted inputs
3-state AND, both inverted inputs
Input 1
Input 2
Input 2
Input 1
H
H
L
3-state NOR
6
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
3-STATE NAND/OR FUNCTIONS AVAILABLE
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
Y
Y
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state OR
OE
A
L
L
B
C
D
H
H
2
2
3-state NAND
3-state NAND
Input 1
Input 2
Input 2
Input 1
L
3-state OR
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state OR
OE
A
Input 2
H
B
L
C
D
H
L
2
2
3-state NAND
3-state NAND
Input 1
Input 2
L
3-state OR
Input 1
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state OR
OE
A
Input 1
H
B
L
C
D
H
L
2
2
3-state NAND
3-state NAND
Input 2
Input 1
L
3-state OR
Input 2
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
NO. OF INPUTS AND/NAND FUNCTION
OR/NOR FUNCTION
3-state OR
OE
A
B
H
H
C
D
L
L
2
2
3-state NAND
3-state NAND
Input 1
Input 2
Input 2
Input 1
L
3-state OR
Copyright © 2004–2011, Texas Instruments Incorporated
7
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
3-STATE XOR/XNOR FUNCTIONS AVAILABLE
OE
Input 1
Input 2
Y
FUNCTION
OE
A
B
C
L
D
Input 1
Input 2
H or L
H or L
L
H or L
H or L
Input 1
Input 2
H
Input 2
Input 1
Input 2
Input 1
Input 2
Input 1
L
H
H
3-state XOR
L
Input 1
Input 2
L
H
OE
Input 1
Input 2
Y
Y
Y
FUNCTION
OE
A
B
C
D
3-state XOR
L
H
L
Input 1
Input 2
OE
Input 1
Input 2
FUNCTION
OE
A
B
C
D
3-state XOR
L
H
L
Input 1
Input 2
OE
Input 1
Input 2
FUNCTION
OE
A
H
H
B
L
L
C
D
3-state XNOR
3-state XNOR
Input 1
Input 2
Input 2
Input 1
L
8
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
6.5
6.5
V
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
O < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
V
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
220
DCT package
DCU package
YZP package
θJA
Package thermal impedance(4)
227 °C/W
102
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
1.65
1.5
0
MAX
UNIT
Operating
5.5
VCC
Supply voltage
V
Data retention only
VI
Input voltage
5.5
VCC
–4
–8
–16
–24
–32
4
V
V
VO
Output voltage
0
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
24
32
20
10
5
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Δt/Δv
Input transition rise or fall rate
ns/V
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2004–2011, Texas Instruments Incorporated
9
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V
2.3 V
3 V
MIN TYP(1)
0.79
MAX UNIT
1.26
VT+
1.11
1.66
Positive-going
input threshold
voltage
1.5
1.97
2.84
3.43
0.72
0.97
1.24
1.89
2.39
0.72
0.87
0.97
1.14
1.21
V
V
V
4.5 V
5.5 V
1.65 V
2.3 V
3 V
2.16
2.61
0.39
VT–
0.58
Negative-
going input
threshold
voltage
0.84
4.5 V
5.5 V
1.65 V
2.3 V
3 V
1.41
1.87
0.37
0.48
ΔVT
Hysteresis
0.56
(VT+ – VT–
)
4.5 V
5.5 V
0.71
0.71
1.65 V to
5.5 V
IOH = –100 μA
VCC – 0.1
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
1.65 V
2.3 V
1.2
1.9
2.4
2.3
3.8
VOH
V
3 V
4.5 V
1.65 V to
5.5 V
IOL = 100 μA
0.1
IOL = 4 mA
1.65 V
2.3 V
0.45
0.3
IOL = 8 mA
VOL
V
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
0.4
3 V
0.55
0.55
±5
4.5 V
0 V to 5.5 V
0 V
II
μA
μA
Ioff
±10
1.65 V to
5.5 V
IOZ
ICC
VO = VCC or GND
VI = 5.5 V or GND,
±10
μA
μA
1.65 V to
5.5 V
IO = 0
10
ΔICC
Ci
One input at VCC – 0.6 V,
VI = VCC or GND
Other inputs at VCC or GND
3 V to 5.5 V
3.3 V
500
μA
pF
pF
3.5
6
Co
VO = VCC or GND
3.3 V
(1) TA = 25°C
10
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
4.5
4.4
4.4
4.3
3.4
4
MAX
MIN
2.5
2.4
2.4
2.4
2.1
2.7
MAX
MIN
1.8
1.8
1.9
1.7
1.3
3.5
MAX
MIN
1.3
1.3
1.3
1.3
1
MAX
A
B
30.1
28.3
29.1
25.1
24.7
15.5
11.3
10.8
11.7
10.2
10
7.5
7.2
7.6
6.7
5.8
7
4.8
4.7
5
tpd
Y
ns
C
D
4.5
3.8
5.5
ten
OE
OE
Y
Y
ns
ns
tdis
7.5
2
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
4.6
4.6
4.4
4.3
4.2
3.7
MAX
MIN
2.6
2.6
2.5
2.5
2.4
2
MAX
MIN
2.4
2.3
2.5
2.4
2
MAX
MIN
1.8
1.8
1.8
1.6
1.7
1
MAX
A
B
30.8
28.9
29.8
25.7
25.2
15
11.7
11.3
12.3
10.7
11.3
5.8
8.4
8.2
8.6
7.6
7
5.5
5.4
5.7
5.2
4.7
4.5
tpd
Y
ns
C
D
ten
OE
OE
Y
Y
ns
ns
tdis
2.1
5.6
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
19
20
22
27
pF
Copyright © 2004–2011, Texas Instruments Incorporated
11
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
15 pF
15 pF
15 pF
15 pF
1 MW
0.15 V
0.15 V
0.3 V
1 MW
1 MW
1 MW
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
12
Copyright © 2004–2011, Texas Instruments Incorporated
SN74LVC1G99
www.ti.com
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
PARAMETER MEASUREMENT INFORMATION (continued)
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2004–2011, Texas Instruments Incorporated
13
SN74LVC1G99
SCES609F –SEPTEMBER 2004–REVISED APRIL 2011
www.ti.com
REVISION HISTORY
Changes from Revision E (October 2007) to Revision F
Page
•
•
Changed document template from TIMS format to DocZone format. .................................................................................. 1
Changed 3-State Mux graphic to fix labeling error. .............................................................................................................. 5
14
Copyright © 2004–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
SN74LVC1G99DCTR
SN74LVC1G99DCTRE4
SN74LVC1G99DCTRG4
SN74LVC1G99DCTT
SN74LVC1G99DCTTE4
SN74LVC1G99DCTTG4
SN74LVC1G99DCUR
SN74LVC1G99DCURE4
SN74LVC1G99DCUT
SN74LVC1G99DCUTE4
SN74LVC1G99DCUTG4
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SM8
SM8
SM8
SM8
SM8
SM8
US8
US8
US8
US8
US8
DCT
8
8
8
8
8
8
8
8
8
8
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
C99
Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCT
DCT
DCT
DCT
DCT
DCU
DCU
DCU
DCU
DCU
3000
3000
250
Green (RoHS
& no Sb/Br)
C99
Z
Green (RoHS
& no Sb/Br)
C99
Z
Green (RoHS
& no Sb/Br)
C99
Z
250
Green (RoHS
& no Sb/Br)
C99
Z
250
Green (RoHS
& no Sb/Br)
C99
Z
3000
3000
250
Green (RoHS
& no Sb/Br)
C99R
C99R
C99R
C99R
C99R
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
SN74LVC1G99YEPR
SN74LVC1G99YZPR
OBSOLETE
ACTIVE
DSBGA
DSBGA
YEP
YZP
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(DE2 ~ DE7 ~ DEN)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G99 :
Automotive: SN74LVC1G99-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G99DCUR
SN74LVC1G99YZPR
US8
DCU
YZP
8
8
3000
3000
180.0
180.0
8.4
8.4
2.25
1.02
3.35
2.02
1.05
0.63
4.0
4.0
8.0
8.0
Q3
Q1
DSBGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G99DCUR
SN74LVC1G99YZPR
US8
DCU
YZP
8
8
3000
3000
202.0
220.0
201.0
220.0
28.0
34.0
DSBGA
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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