SN74LVC1GX04DBVR [TI]
CRYSTAL OSCILLATOR DRIVER; 晶体振荡器驱动器
| 型号： | SN74LVC1GX04DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CRYSTAL OSCILLATOR DRIVER |
| 文件： | 总13页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢃ
ꢆꢋꢌꢀ ꢍꢎꢄ ꢏ ꢀꢆꢐ ꢄꢄ ꢎꢍꢏꢋ ꢑ ꢋꢐ ꢅ ꢒꢋ
SCES581 − JULY 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in Texas Instruments NanoStar
and NanoFree Packages
D
D
D
Supports 5-V V
Operation
CC
1
2
3
6
5
4
NC
GND
X1
Y
V
X2
Inputs Accept Voltages to 5.5 V
CC
One Unbuffered Inverter (SN74LVC1GU04)
and One Buffered Inverter (SN74LVC1G04)
NC − No internal connection
D
Suitable for Commonly Used Clock
Frequencies:
− 15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
YEP OR YZP PACKAGE
(BOTTOM VIEW)
3 4
2 5
1 6
X1
GND
DNU
X2
D
D
D
D
Max t of 2.4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
V
Y
CC
CC
24-mA Output Drive at 3.3 V
DNU − Do not use
I
Supports Partial-Power-Down Mode
off
Operation
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVC1GX04 is designed for 1.65-V to 5.5-V V
operation. This device incorporates the
CC
SN74LVC1GU04 (inverter with unbuffered output) and the SN74LVC1G04 (inverter) functions into a single
device. The LVC1GX04 is optimized for use in crystal oscillator applications.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1GX04YEPR
SN74LVC1GX04YZPR
Reel of 3000
_ _ _ _
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1GX04DBVR
SN74LVC1GX04DBVT
SN74LVC1GX04DCKR
SOT (SOT-23) − DBV
CX4_
D2_
SOT (SC-70) − DCK
Reel of 250
SN74LVC1GX04DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES581 − JULY 2004
description/ordering information (continued)
The X1 and X2 can be connected to a crystal or resonator in oscillator applications. The device provides an
additional buffered inverter (Y) for signal conditioning (see Figure 3). The additional buffered inverter improves
the signal quality of the crystal oscillator output by making it rail to rail.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I (Y output only). The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
OUTPUTS
INPUT
X1
X2
L
Y
H
L
H
L
H
logic diagram (positive logic)
6
4
Y
3
X1
X2
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to Y output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES581 − JULY 2004
recommended operating conditions (see Note 4)
MIN
1.65
1.5
2
MAX
UNIT
Operating
5.5
Data retention only
V
CC
Supply voltage
V
Crystal oscillator use
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 1.65 V to 5.5 V
= 1.65 V to 5.5 V
0.75 × V
CC
V
V
V
IH
IL
I
CC
0.25 × V
CC
CC
0
0
0
5.5
X2, Y
Y output only, Power-down mode, V
V
CC
5.5
V
O
Output voltage
V
= 0 V
CC
V
V
= 1.65 V
= 2.3 V
−4
−8
CC
CC
−16
−24
−32
4
I
High-level output current
mA
OH
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
20
10
10
85
I
Low-level output current
mA
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
= 5 V 0.5 V
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES581 − JULY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
V − 0.1
CC
MAX
UNIT
CC
I
I
I
I
I
= −100 mA
= −4 mA
1.65 V to 5.5 V
1.65 V
OH
OH
OH
OH
OH
1.2
1.9
2.4
2.3
= −8 mA
2.3 V
V
OH
V = 5.5 V or GND
I
V
= −16 mA
= −24 mA
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
I
I
I
I
I
I
= −32 mA
= 100 mA
= 4 mA
OH
OL
OL
OL
OL
OL
0.1
0.45
0.3
= 8 mA
2.3 V
V
OL
V = 5.5 V or GND
I
V
= 16 mA
= 24 mA
0.4
3 V
0.55
4.5 V
0 to 5.5 V
0
0.55
5
I
= 32 mA
OL
I
I
I
X1 input
X1, Y
V = 5.5 V or GND
mA
mA
mA
pF
I
I
V or V = 5.5 V
10
10
off
I
O
V = 5.5 V or GND,
I = 0
O
1.65 V to 5.5 V
3.3 V
CC
I
C
V = V
or GND
= 3.3 V, T = 25°C.
7
i
I
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
V
= 5 V
CC
0.15 V
CC
CC
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1
4
0.8
2.2
2.6
6
0.6
2
2.4
5
0.5
1.5
2
X2
t
pd
X1
ns
‡
Y
3.5
10
3.5
‡
X2 − no external load
switching characteristics over recommended operating free-air temperature range, C = 30 pF or
L
50 pF (unless otherwise noted) (see Figure 2)
V
= 1.8 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
V
= 5 V
CC
0.15 V
CC
CC
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1.1
3.8
7
0.8
2
4
0.8
2
3.7
7.8
0.8
2
3
5
ns
ns
X2
t
pd
X1
‡
Y
18
7.4
‡
X2 − no external load
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
CC
TYP
35
PARAMETER
TEST CONDITIONS
UNIT
TYP
22
TYP
22
TYP
24
C
Power dissipation capacitance
f = 10 MHz
pF
pd
4
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SCES581 − JULY 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
Open
GND
t
t
/t
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
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SCES581 − JULY 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢃ
ꢆꢋꢌꢀ ꢍꢎꢄ ꢏ ꢀꢆꢐ ꢄꢄ ꢎꢍꢏ ꢋ ꢑ ꢋꢐ ꢅ ꢒꢋ
SCES581 − JULY 2004
APPLICATION INFORMATION
Figure 3 shows a typical application of the SN74LVC1X04 in a Pierce oscillator circuit. The buffered inverter
(SN74LVC1G04 portion) produces a rail-to-rail voltage waveform. The recommended load for the crystal shown in
this example is 16 pF. The value of the recommended load (C ) can be found in the crystal manufacturer’s data sheet.
L
C C
1
2
Values of C and C are chosen so that
and C ≅ C . R is the current-limiting resistor and the value
1 2 s
C
+
1
2
L
C ) C
2
1
depends on the maximum power dissipation of the crystal. Generally, the recommended value of R is specified in
s
the crystal manufacturer’s data sheet and, usually, this value is approximately equal to the reactance of C at
2
resonance frequency, i.e., R + X . R is the feedback resistor that is used to bias the inverter in the linear region
F
s
C
2
of operation. Usually, the value is chosen to be within 1 MΩ to 10 MΩ.
SN74LVC1GU04
Portion
SN74LVC1G04
Portion
Y
X2
X1
C
LOAD
R
LOAD
R
≅ 2.2 MΩ
F
R
≅ 1 kΩ
s
C
≅ 16 pF
L
C
≅ 32 pF
C ≅ 32 pF
2
1
a) Logic Diagram View
Figure 3. Oscillator Circuit
7
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ꢆ ꢋꢌꢀ ꢍꢎ ꢄ ꢏꢀꢆ ꢐ ꢄꢄ ꢎꢍꢏ ꢋ ꢑꢋ ꢐ ꢅꢒ ꢋ
SCES581 − JULY 2004
APPLICATION INFORMATION
6
Y
1
NC
C
R
LOAD
LOAD
2
5
4
GND
V
CC
X1
X2
3
R
≅ 2.2 MΩ
F
R
C
≅ 1 kΩ
s
2
C
= 16 pF
L
C
≅ 32 pF
≅ 32 pF
1
b) Oscillator Circuit in DBV or DCK Pinout
Figure 3. Oscillator Circuit (Continued)
practical design tips
D
The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This
decreases the closed-loop gain of the oscillator circuit. The value of R can be decreased to increase the
s
closed-loop gain, while maintaining the power dissipation of the crystal within the maximum limit.
R and C form a low-pass filter and reduce spurious oscillations. Component values can be adjusted,
D
D
D
s
2
based on the desired cutoff frequency.
C can be increased over C to increase the phase shift and help in start-up of the oscillator. Increasing C
2
2
1
may affect the duty cycle of the output voltage.
At high frequency, phase shift due to R becomes significant. In this case, R can be replaced by a capacitor
s
s
to reduce the phase shift.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆꢋꢌꢀ ꢍꢎꢄ ꢏ ꢀꢆꢐ ꢄꢄ ꢎꢍꢏ ꢋ ꢑ ꢋꢐ ꢅ ꢒꢋ
SCES581 − JULY 2004
APPLICATION INFORMATION
testing
After the selection of proper component values, the oscillator circuit should be tested using these components.
To ensure that the oscillator circuit performs within the recommended operating conditions, follow these steps:
1. Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
2. When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest V
and highest V
.
CC
CC
3. Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
9
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MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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