SN74LVC1T45_技术文档

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SCES515E − DECEMBER 2003 − REVISED MAY 2004

D

Available in the Texas Instruments

NanoStar and NanoFree Packages

Fully Configurable Dual-Rail Design Allows

Each Port to Operate Over the Full 1.65-V to

5.5-V Power-Supply Range

D

I

Supports Partial-Power-Down Mode

off

Operation

Max Data Rates

− 420 Mbps (3.3-V to 5-V Translation)

− 210 Mbps (Translate to 3.3 V)

− 140 Mbps (Translate to 2.5 V)

− 75 Mbps (Translate to 1.8 V)

D

V

Isolation Feature − If Either V

Input

CC

Is at GND, Both Ports Are in the

High-Impedance State

D

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D

DIR Input Circuit Referenced to V

CCA

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

Low Power Consumption, 4-µA Max I

CC

24-mA Output Drive at 3.3 V

− 1000-V Charged-Device Model (C101)

YEP OR YZP PACKAGE

(BOTTOM VIEW)

DBV OR DCK PACKAGE

(TOP VIEW)

3 4

2 5

1 6

A

GND

B

DIR

1

2

3

6

5

4

V

GND

V

CCB

DIR

CCA

V

CCB

CCA

A

B

description/ordering information

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is

designed to track V . V accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track

CCA CCA

V

. V

accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional

CCB CCB

translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between data buses. The device transmits

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

T

A

PACKAGE

‡

NanoStar − WCSP (DSBGA)

0.23-mm Large Bump − YEP

SN74LVC1T45YEPR

SN74LVC1T45YZPR

Reel of 3000

_ _ _TA_

NanoFree − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

−40°C to 85°C

Reel of 3000

Reel of 250

Reel of 3000

SN74LVC1T45DBVR

SN74LVC1T45DBVT

SN74LVC1T45DCKR

SOT (SOT-23) − DBV

CT1_

TA_

SOT (SC-70) − DCK

Reel of 250

SN74LVC1T45DCKT

†

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site. Pin

1 identifier indicates solder-bump composition

^{(1 = SnPb,}• = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

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Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢕꢊ ꢈ ꢖ ꢆ ꢗꢁ ꢘꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅ ꢗꢄꢈꢑꢋ ꢌ ꢈꢔ ꢑꢁ ꢀꢄ ꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐꢈ ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

description/ordering information (continued)

The SN74LVC1T45 is designed so that the DIR input circuit is supplied by V

.

CCA

This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,

off

preventing damaging current backflow through the device when it is powered down.

The V isolation feature ensures that if either V input is at GND, both ports are in the high-impedance state.

CC

NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

FUNCTION TABLE

INPUT

OPERATION

DIR

L

B data to A bus

A data to B bus

H

logic diagram (positive logic)

5

DIR

3

A

4

B

V

CCA

V

CCB

2

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ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

and V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

CCA

CCB

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

I

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5V

CCA

CCB

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

IK

OK

I

Output clamp current, I

O

CC

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W

JA

DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W

YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The value of V is provided in the recommended operating conditions table.

CC

3. The package thermal impedance is calculated in accordance with JESD 51-7.

3

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ꢒꢐꢈ ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

recommended operating conditions (see Notes 4 through 8)

V

CCI

V

CCO

MIN

1.65

MAX

5.5

UNIT

V

CCA

Supply voltage

V

5.5

CCB

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

V

× 0.65

1.7

CCI

High-level input

voltage

Data inputs

(see Note 7)

V

IH

V

IL

V

IH

V

IL

V

2

4.5 V to 5.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

V

× 0.7

CCI

V

× 0.35

CCI

0.7

0.8

Low-level input

voltage

Data inputs

(see Note 7)

4.5 V to 5.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

V

× 0.3

CCI

V

CCA

× 0.65

1.7

DIR

High-level input

voltage

(Referenced to V

)

CCA

2

(see Note 8)

4.5 V to 5.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

V

× 0.7

CCA

V

CCA

× 0.35

0.7

DIR

Low-level input

voltage

(Referenced to V

CCA

0.8

(see Note 8)

4.5 V to 5.5 V

V

× 0.3

5.5

CCA

V

Input voltage

0

V

I

Output voltage

V

CCO

O

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

−4

−8

−24

−32

4

I

High-level output current

Low-level output current

mA

OH

4.5 V to 5.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

8

I

OL

24

32

20

10

5

4.5 V to 5.5 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

Data input

Input transition rise or

fall rate

∆t/∆v

ns/V

4.5 V to 5.5 V

1.65 V to 5.5 V

Control input

Operating free-air temperature

NOTES: 4. V is the V associated with the data input port.

5

T

−40

85

°C

A

CCI

CCO

CC

is the V associated with the output port.

CC

5.

V

6. All unused data inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CCI

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7. For V

8. For V

values not specified in the data sheet, V

= V

x 0.7 V, V

= V

CCI

x 0.3 V.

CCI

IH(min)

CCI

IL(max)

x 0.7 V, V

= V

CCA

IL(max)

CCA

4

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SCES515E − DECEMBER 2003 − REVISED MAY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Notes 9 and 10)

T

A

= 25°C

−40°C to 85°C

PARAMETER

TEST CONDITIONS

UNIT

V

CCB

CCA

MIN

TYP

MAX

MIN

−0.1

MAX

V

I

= −100 µA, V = V

IH

1.65 V to 4.5 V 1.65 V to 4.5 V

CCO

OH

OL

I

= −4 mA,

= −8 mA,

= −24 mA,

= −32 mA,

= 100 µA,

= 4 mA,

V = V

I

1.65V

2.3 V

3 V

1.65 V

2.3 V

3 V

1.2

1.9

2.4

3.8

IH

IL

V = V

I

V

OH

V

V = V

I

V = V

I

4.5 V

V = V

I

1.65 V to 4.5 V 1.65 V to 4.5 V

0.1

0.45

0.3

V = V

I

1.65 V

2.3 V

3 V

1.65 V

2.3 V

3 V

= 8 mA,

V = V

I

V

OL

V

= 24 mA,

= 32 mA,

V = V

I

0.55

V = V

I

4.5 V

DIR

input

I

V = V

I CCA

or GND

1.65 V to 5.5 V 1.65 V to 5.5 V

1

2

µA

A port

B port

0 V

0 to 5.5 V

0 V

1

2

I

V or V = 0 to 5.5 V

µA

off

I

O

0 to 5.5 V

A or B

ports

I

V

O

= V

CCO

or GND

1.65 V to 5.5 V 1.65 V to 5.5 V

1

2

OZ

3

2

0

3

0

2

V = V

I

or

CCI

5.5 V

0 V

I

= 0

µA

CCA

O

GND

5.5 V

1.65 V to 5.5 V 1.65 V to 5.5 V

V = V

I

CCI

5.5 V

0 V

I

= 0

µA

CCB

O

GND

5.5 V

V = V

I

or

CCI

I

1.65 V to 5.5 V 1.65 V to 5.5 V

4

CCA + CCB

O

GND

A port at V

− 0.6 V,

, B port = OPEN

CCA

A port

DIR

50

DIR at V

CCA

∆I

3 V to 5.5 V

µA

DIR at V

B port = OPEN,

− 0.6 V,

CCA

50

A port at V

or GND

− 0.6 V,

CCA

B port at V

DIR at GND, A port = OPEN

CCB

B port

3 V to 5.5 V

3.3 V

3 V to 5.5 V

3.3 V

µA

pF

CCB

DIR

input

C

V = V

I CCA

or GND

2.5

6

i

A or B

ports

V = V

O CCA/B

or GND

3.3 V

io

NOTES: 9. V

is the V

associated with the output port.

associated with the input port.

CC

CCO

V is the V

CCI

CC

10.

5

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SCES515E − DECEMBER 2003 − REVISED MAY 2004

switching characteristics over recommended operating free-air temperature range,

= 1.8 V 0.15 V (unless otherwise noted) (see Figure 1)

V

CCA

V

= 1.8 V

0.15 V

V

= 2.5 V

0.2 V

V

= 3.3 V

0.3 V

V

= 5 V

CCB

0.5 V

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

3

MAX

17.7

14.3

17.7

14.3

19.4

10.5

21.9

16

MIN

2.2

2.3

2.1

4.8

2.1

4.9

3.7

MAX

10.3

8.5

MIN

1.7

1.8

2.1

2

MAX

8.3

MIN

1.4

1.7

1.9

1.8

5.1

3.1

2.8

2.4

MAX

7.2

t

PLH

PHL

PLH

PHL

PHZ

B

A

B

A

B

A

ns

2.8

3

7.1

7

16

15.5

12.6

18.4

10.7

10.3

8.4

15.1

12.2

17.1

10.9

8.2

B

2.8

5.2

2.3

7.4

4.2

12.9

18.5

10.5

11.5

9.2

t

4.7

2.4

4.6

3.3

DIR

t

PLZ

t

PHZ

t

6.4

PLZ

†

t

33.7

36.2

28.2

25.2

24.4

20.8

23.9

22.9

19

21.5

20.4

18.1

PZH

†

t

PZL

†

t

PZH

†

t

33.7

27

25.5

24.1

PZL

†

The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.

switching characteristics over recommended operating free-air temperature range,

= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)

V

CCA

V

= 1.8 V

0.15 V

V

= 2.5 V

0.2 V

V

= 3.3 V

0.3 V

V

= 5 V

CCB

0.5 V

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

2.3

2.1

2.2

3

MAX

16

MIN

1.5

1.4

1.5

1.4

3.1

1.3

4.1

3.2

MAX

8.5

MIN

1.3

1.4

1.3

2.8

1.3

3.9

2.8

MAX

6.4

5.4

8

MIN

1.1

0.9

1

MAX

5.1

t

PLH

PHL

PLH

PHL

PHZ

B

A

B

A

B

A

ns

12.9

10.3

8.5

7.5

4.6

8.5

7.5

B

7.5

7

0.9

3.2

1

6.2

t

8.1

5.9

10.2

8.4

16.4

17.2

12.3

8.1

DIR

t

1.3

6.5

3.9

5.9

5.8

PLZ

t

23.7

18.9

29.2

32.2

21.9

11.4

9.6

2.4

1.8

7.1

PHZ

t

5.3

PLZ

†

t

18.1

18.9

14.4

12.8

13.3

10.9

PZH

†

t

PZL

t

PZH

†

t

21

15.6

13.5

12.7

PZL

†

The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ

ꢀꢊ ꢁꢋ ꢄ ꢌꢍꢎꢊ ꢈ ꢏꢐꢑ ꢄꢍꢀ ꢐꢒꢒꢄꢓ ꢎꢐꢀ ꢈ ꢔꢑꢁꢀ ꢆꢌ ꢊ ꢅꢌ ꢔ

ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

switching characteristics over recommended operating free-air temperature range,

= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)

V

CCA

V

= 1.8 V

0.15 V

V

= 2.5 V

0.2 V

V

= 3.3 V

0.3 V

V

= 5 V

CCB

0.5 V

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

2.1

2

MAX

15.5

12.6

8.3

MIN

1.4

1.3

3

MAX

8

MIN

0.7

0.8

0.7

0.8

2.8

2.2

2.9

2.4

MAX

5.8

5

MIN

0.7

0.6

0.7

3.4

2.2

2.4

1.7

MAX

4.4

4

t

PLH

PHL

PLH

PHL

PHZ

B

A

B

A

B

A

ns

7

1.7

1.8

2.9

1.8

5.4

3.3

6.4

5.4

7.3

5.6

10.1

7.8

14.2

15.5

13.6

5.8

5

5.4

4.5

7.3

5.7

6.8

4.9

10.3

11.3

10.1

B

7.1

t

7.3

5.7

8.8

7.1

12.9

13.8

11.5

DIR

t

5.6

1.6

3.9

2.9

PLZ

t

20.5

14.5

22.8

27.6

21.1

PHZ

t

PLZ

†

t

PZH

†

t

PZL

†

t

PZH

†

t

19.9

14.3

12.3

11.3

PZL

†

The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.

switching characteristics over recommended operating free-air temperature range,

= 5 V 0.5 V (unless otherwise noted) (see Figure 1)

V

CCA

V

= 1.8 V

0.15 V

V

= 2.5 V

0.2 V

V

= 3.3 V

0.3 V

V

= 5 V

CCB

0.5 V

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

1.9

1.8

1.4

1.7

2.1

0.9

4.8

4.2

MAX

15.1

12.2

7.2

MIN

1

MAX

7.5

MIN

0.6

0.7

2.2

1

MAX

5.4

4.5

4.4

4

MIN

0.5

2.2

0.9

2.5

1.6

MAX

3.9

3.5

3.9

3.5

5.4

3.7

6.5

4.5

8.4

10

t

PLH

PHL

PLH

PHL

PHZ

B

A

B

A

B

A

ns

0.9

1

6.2

5.1

B

7

0.9

2.2

1

4.6

t

5.4

5.5

3.7

8.5

7

DIR

t

3.8

PLZ

t

20.2

14.8

22

2.5

9.8

1

PHZ

t

7.4

2.5

PLZ

†

t

12.5

14.4

11.3

11.4

12.5

9.1

PZH

†

t

27.2

18.9

PZL

t

7.6

PZH

†

t

17.6

11.6

10

8.9

PZL

†

The enable time is a calculated value, derived using the formula shown in the section entitled enable times on page 16.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢃ ꢉ

ꢀ ꢊꢁ ꢋꢄ ꢌꢍ ꢎꢊ ꢈ ꢏ ꢐꢑ ꢄꢍꢀ ꢐꢒ ꢒꢄꢓ ꢎꢐ ꢀ ꢈꢔ ꢑꢁ ꢀꢆꢌ ꢊꢅꢌ ꢔ

ꢕ

ꢊ

ꢈ

ꢖ

ꢆ

ꢗ

ꢁ

ꢘꢊ

ꢋ

ꢐ

ꢔ

ꢑ

ꢎ

ꢄ

ꢌ

ꢅ

ꢗ

ꢄ

ꢈ

ꢑ

ꢋ

ꢌ

ꢈ

ꢔ

ꢑ

ꢁ

ꢀ

ꢄ

ꢑꢈ

ꢊ

ꢗ

ꢁ

ꢑ

ꢁ

ꢏ

ꢙ

ꢍ

ꢀ

ꢈ

ꢑ

ꢈ

ꢌ

ꢗ

ꢐ

ꢈ

ꢒ

ꢐ

ꢈ

ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

operating characteristics, T = 25°C

A

V

=

V

=

V

=

V

=

CCA

= 1.8 V

CCA

= 2.5 V

CCA

= 3.3 V

CCA

V

= 5 V

PARAMETER

CCB

TYP

CCB

TYP

CCB

TYP

CCB

TEST CONDITIONS

UNIT

TYP

A port input, B port output

B port input, A port output

A port input, B port output

B port input, A port output

3

18

3

4

19

4

20

4

21

4

†

C

pdA

C

= 0,

L

pF

f = 10 MHz,

t = t =1 ns

r

f

pdB

†

Power-dissipation capacitance per transceiver

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ

ꢀꢊ ꢁꢋ ꢄ ꢌꢍꢎꢊ ꢈ ꢏꢐꢑ ꢄꢍꢀ ꢐꢒꢒꢄꢓ ꢎꢐꢀ ꢈ ꢔꢑꢁꢀ ꢆꢌ ꢊ ꢅꢌ ꢔ

ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

power-up considerations

A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,

oscillations, or other anomalies. Take the following precautions to guard against such power-up problems:

1. Connect ground before any supply voltage is applied.

2. Power up V

.

CCA

3. V

can be ramped up along with or after V

.

CCB

CCA

typical total static power consumption (I

+ I

)

CCA

CCB

Table 1

V

CCA

V

UNIT

CCB

0 V

0

1.8 V

2.5 V

<1

3.3 V

<1

5 V

<1

2

0 V

<1

<2

2

1.8 V

2.5 V

3.3 V

5 V

<1

<2

µA

<2

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢃ ꢉ

ꢀ ꢊꢁ ꢋꢄ ꢌꢍ ꢎꢊ ꢈ ꢏ ꢐꢑ ꢄꢍꢀ ꢐꢒ ꢒꢄꢓ ꢎꢐ ꢀ ꢈꢔ ꢑꢁ ꢀꢆꢌ ꢊꢅꢌ ꢔ

ꢕꢊ ꢈ ꢖ ꢆ ꢗꢁ ꢘꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅ ꢗꢄꢈꢑꢋ ꢌ ꢈꢔ ꢑꢁ ꢀꢄ ꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐꢈ ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE

T = 25°C, V

= 1.8 V

A

CCA

10

9

10

9

8

7

6

5

4

3

2

1

0

V

= 1.8 V

CCB

8

V

= 1.8 V

= 2.5 V

CCB

7

6

V

= 2.5 V

= 3.3 V

CCB

V

CCB

5

CCB

4

V

CCB

= 5 V

= 3.3 V

= 5 V

CCB

3

V

CCB

2

1

0

5

10

15

C

20

25

30

35

10

15

C

20

− pF

25

30

35

0

5

− pF

L

TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE

T = 25°C, V

= 1.8 V

A

CCA

10

9

8

7

6

5

4

3

2

1

0

V

= 1.8 V

= 2.5 V

CCB

8

7

6

5

4

3

2

1

0

CCB

V

= 1.8 V

CCB

V

= 3.3 V

= 5 V

CCB

V

CCB

V

CCB

V

CCB

= 2.5 V

= 3.3 V

= 5 V

0

5

10

15

20

− pF

25

30

35

10

15

20

− pF

25

30

35

0

5

C

L

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ

ꢀꢊ ꢁꢋ ꢄ ꢌꢍꢎꢊ ꢈ ꢏꢐꢑ ꢄꢍꢀ ꢐꢒꢒꢄꢓ ꢎꢐꢀ ꢈ ꢔꢑꢁꢀ ꢆꢌ ꢊ ꢅꢌ ꢔ

ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE

T = 25°C, V

= 2.5 V

A

CCA

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

V

= 1.8 V

CCB

V

= 1.8 V

= 2.5 V

CCB

V

CCB

= 2.5 V

V

CCB

V

= 3.3 V

= 5 V

CCB

V

= 3.3 V

= 5 V

CCB

0

10

15

C

20

− pF

25

30

35

0

5

10

15

C

20

− pF

25

30

35

5

L

TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE

T = 25°C, V

= 2.5 V

A

CCA

10

9

8

7

6

5

4

3

2

1

10

9

8

7

6

5

4

3

2

1

0

V

= 1.8 V

CCB

V

= 1.8 V

= 2.5 V

CCB

V

CCB

V

CCB

= 2.5 V

= 3.3 V

V

CCB

V

CCB

= 5 V

V

CCB

V

CCB

= 3.3 V

= 5 V

0

5

10

15

C

20

− pF

L

25

30

35

0

5

10

15

20

− pF

25

30

35

C

L

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢃ ꢉ

ꢀ ꢊꢁ ꢋꢄ ꢌꢍ ꢎꢊ ꢈ ꢏ ꢐꢑ ꢄꢍꢀ ꢐꢒ ꢒꢄꢓ ꢎꢐ ꢀ ꢈꢔ ꢑꢁ ꢀꢆꢌ ꢊꢅꢌ ꢔ

ꢕꢊ ꢈ ꢖ ꢆ ꢗꢁ ꢘꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅ ꢗꢄꢈꢑꢋ ꢌ ꢈꢔ ꢑꢁ ꢀꢄ ꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐꢈ ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY (A TO B) vs LOAD CAPACITANCE

T = 25°C, V

= 3.3 V

A

CCA

10

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

V

CCB

= 1.8 V

V

= 1.8 V

= 2.5 V

CCB

V

= 2.5 V

= 3.3 V

CCB

V

CCB

= 5 V

V

= 3.3 V

= 5 V

CCB

0

10

15

25

10

15

C

20

− pF

25

30

35

5

0

5

20

− pF

30

35

C

L

TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE

T = 25°C, V

= 3.3 V

A

CCA

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

V

= 1.8 V

= 2.5 V

CCB

V

= 1.8 V

= 2.5 V

CCB

V

CCB

V

CCB

V

CCB

V

CCB

= 3.3 V

= 5 V

V

= 3.3 V

= 5 V

CCB

0

10

15

20

25

30

35

5

35

10

15

20

25

30

0

5

C − pF

L

C

− pF

L

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ

ꢀꢊ ꢁꢋ ꢄ ꢌꢍꢎꢊ ꢈ ꢏꢐꢑ ꢄꢍꢀ ꢐꢒꢒꢄꢓ ꢎꢐꢀ ꢈ ꢔꢑꢁꢀ ꢆꢌ ꢊ ꢅꢌ ꢔ

ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE

T = 25°C, V = 5 V

A

CCA

10

9

8

7

6

5

4

3

2

1

0

9

8

V

CCB

= 1.8 V

7

V

= 1.8 V

= 2.5 V

CCB

6

5

4

3

2

V

= 2.5 V

= 3.3 V

CCB

V

CCB

V

= 5 V

10

CCB

V

CCB

V

CCB

= 3.3 V

= 5 V

1

0

35

15

20

25

30

0

5

0

5

10

15

20

− pF

25

30

35

C

− pF

L

C

L

TYPICAL PROPAGATION DELAY (B TO A) vs LOAD CAPACITANCE

T = 25°C, V

= 5 V

A

CCA

10

9

8

7

6

5

4

3

2

9

8

7

6

5

4

3

2

1

0

V

= 1.8 V

= 2.5 V

CCB

V

= 1.8 V

= 2.5 V

CCB

V

CCB

V

CCB

V

CCB

= 3.3 V

= 5 V

V

= 3.3 V

= 5 V

CCB

1

CCB

0

5

0

10

15

C

20

− pF

25

30

35

25

30

35

10

15

C

20

− pF

5

L

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢃ ꢉ

ꢀ ꢊꢁ ꢋꢄ ꢌꢍ ꢎꢊ ꢈ ꢏ ꢐꢑ ꢄꢍꢀ ꢐꢒ ꢒꢄꢓ ꢎꢐ ꢀ ꢈꢔ ꢑꢁ ꢀꢆꢌ ꢊꢅꢌ ꢔ

ꢕ

ꢊ

ꢈ

ꢖ

ꢆ

ꢗ

ꢁ

ꢘꢊ

ꢋ

ꢐ

ꢔ

ꢑ

ꢎ

ꢄ

ꢌ

ꢅ

ꢗ

ꢄ

ꢈ

ꢑ

ꢋ

ꢌ

ꢈ

ꢔ

ꢑ

ꢁ

ꢀ

ꢄ

ꢑꢈ

ꢊ

ꢗ

ꢁ

ꢑ

ꢁ

ꢏ

ꢙ

ꢍ

ꢀ

ꢈ

ꢑ

ꢈ

ꢌ

ꢗ

ꢐ

ꢈ

ꢒ

ꢐ

ꢈ

ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

2 × V

CCO

TEST

S1

R

Open

GND

t

Open

L

pd

/t

From Output

Under Test

t

2 × V

CCO

GND

PLZ PZL

/t

PHZ PZH

t

C

L

R

L

(see Note A)

t

LOAD CIRCUIT

w

V

CCI

V /2

CCI

V /2

CCI

Input

V

TP

C

R

V

CCO

L

0 V

1.8 V 0.15 V

2.5 V 0.2 V

3.3 V 0.3 V

5 V 0.5 V

2 kΩ

0.15 V

0.3 V

15 pF

VOLTAGE WAVEFORMS

PULSE DURATION

0.3 V

V

CCA

Output

Control

(low-level

enabling)

V

CCA

/2

V

CCA

/2

0 V

t

PLZ

PZL

V

CCO

Output

Waveform 1

V

CCI

V

CCO

/2

Input

t

V /2

CCI

V /2

CCI

V

OL

+ V

TP

S1 at 2 × V

CCO

OL

0 V

(see Note B)

t

PZH

PHZ

t

PLH

PHL

Output

Waveform 2

S1 at GND

V

OH

V

OH

V

OH

− V

TP

V

CCO

Output

V

CCO

/2

V

/2

CCO

(see Note B)

0 V

V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A.

C

includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.

O

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

G.

H.

I.

t

V

and t

PHL

are the same as t

.

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

are the same as t .

pd

.

en

is the V

associated with the input port.

associated with the output port.

CCI

CC

is the V

CCO

J. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ

ꢀꢊ ꢁꢋ ꢄ ꢌꢍꢎꢊ ꢈ ꢏꢐꢑ ꢄꢍꢀ ꢐꢒꢒꢄꢓ ꢎꢐꢀ ꢈ ꢔꢑꢁꢀ ꢆꢌ ꢊ ꢅꢌ ꢔ

ꢕ ꢊ ꢈꢖ ꢆꢗ ꢁꢘ ꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅꢗ ꢄꢈꢑꢋ ꢌ ꢈ ꢔꢑꢁꢀ ꢄꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐ ꢈꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

APPLICATION INFORMATION

The following circuit is an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting

application.

V

CC1

V

CC1

V

CC2

V

CC2

1

2

3

6

5

4

SYSTEM-1

SYSTEM-2

NAME

FUNCTION

DESCRIPTION

1

V

SYSTEM-1 supply voltage (1.65 V to 5.5 V)

Device GND

V

CCA

CC1

2

3

4

5

6

GND

A

GND

OUT

IN

Output level depends on V

CC1

voltage.

B

Input threshold value depends on V voltage.

CC2

DIR

The GND (low level) determines B port to A port direction.

SYSTEM-2 supply voltage (1.65 V to 5.5 V)

DIR

V

CCB

V

CC2

Figure 3. Unidirectional Logic Level-Shifting Application

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢃ ꢉ

ꢀ ꢊꢁ ꢋꢄ ꢌꢍ ꢎꢊ ꢈ ꢏ ꢐꢑ ꢄꢍꢀ ꢐꢒ ꢒꢄꢓ ꢎꢐ ꢀ ꢈꢔ ꢑꢁ ꢀꢆꢌ ꢊꢅꢌ ꢔ

ꢕꢊ ꢈ ꢖ ꢆ ꢗꢁ ꢘꢊ ꢋꢐ ꢔ ꢑꢎꢄ ꢌ ꢅ ꢗꢄꢈꢑꢋ ꢌ ꢈꢔ ꢑꢁ ꢀꢄ ꢑꢈ ꢊꢗ ꢁ ꢑꢁꢏ ꢙ ꢍꢀꢈꢑꢈ ꢌ ꢗ ꢐꢈ ꢒꢐꢈ ꢀ

SCES515E − DECEMBER 2003 − REVISED MAY 2004

APPLICATION INFORMATION

Figure 4 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Since the

SN74LVC1T45 does not have an output enable (OE) pin, the system designer should take precautions to avoid

bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

V

CC1

V

CC1

V

CC2

V

CC2

Pullup/Down

or Bus Hold

Pullup/Down

or Bus Hold

I/O-1

I/O-2

†

1

2

3

6

5

4

DIR CTRL

SYSTEM-1

SYSTEM-2

Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from

SYSTEM-2 to SYSTEM-1.

STATE

DIR CTRL

I/O 1

I/O 2

DESCRIPTION

1

H

SYSTEM-1 data to SYSTEM-2

OUT

IN

SYSTEM-2 is getting ready to send data to

SYSTEM-1. I/O-1 and I/O-2 are disabled.

The bus-line state depends on pullup or pulldown.

2

H

HI-Z

†

DIR bit is flipped. I/O-1 and I/O-2 still are disabled.

The bus-line state depends on pullup or pulldown.

3

4

L

HI-Z

OUT

HI-Z

IN

†

SYSTEM-2 data to SYSTEM-1

†

SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.

Figure 4. Bidirectional Logic Level-Shifting Application

enable times

Calculate the enable times for the SN74LVC1T45 using the following formulas:

1. t

2. t

3. t

4. t

(DIR to A) = t

(DIR to B) + t

(DIR to A) + t

(B to A)

(A to B)

PZH

PZL

PZH

PZL

PLZ

PLH

PHL

PLH

PHL

(DIR to A) = t

(DIR to B) = t

PHZ

PLZ

PHZ

(DIR to B) = t

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is

switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then

the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the

B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

12-Sep-2005

PACKAGING INFORMATION

Orderable Device

SN74LVC1T45DBVR

SN74LVC1T45DBVRE4

SN74LVC1T45DBVT

SN74LVC1T45DBVTE4

SN74LVC1T45DCKR

SN74LVC1T45DCKRG4

SN74LVC1T45DCKT

SN74LVC1T45DCKTE4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOT-23

DBV

6

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOT-23

SC70

DBV

DCK

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SC70

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SC70

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SC70

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC1T45YEPR

SN74LVC1T45YZPR

ACTIVE

WCSP

YEP

YZP

6

3000

TBD

SNPB

Level-1-260C-UNLIM

Pb-Free

(RoHS)

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDS114 – FEBRUARY 2002

DCK (R-PDSO-G6)

PLASTIC SMALL-OUTLINE PACKAGE

0,30

0,15

M

0,10

0,65

6

4

0,13 NOM

1,40 2,40

1,10 1,80

1

3

Gage Plane

2,15

1,85

0,15

0°–8°

0,46

0,26

Seating Plane

0,10

1,10

0,80

0,10

0,00

4093553-3/D 01/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-203

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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Post Office Box 655303 Dallas, Texas 75265


型号：	SN74LVC1T45
厂家：	TEXAS INSTRUMENTS
描述：	SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 可配置电压转换和3态输出的单位双电源总线收发器总线收发器输出元件
文件：	总22页 (文件大小：421K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LVC1T45 [TI]

相关型号：

SN74LVC1T45-EP

SN74LVC1T45-Q1

SN74LVC1T45DBVR

SN74LVC1T45DBVRE4

SN74LVC1T45DBVRG4

SN74LVC1T45DBVT

SN74LVC1T45DBVTE4

SN74LVC1T45DBVTG4

SN74LVC1T45DCKR

SN74LVC1T45DCKRE4

SN74LVC1T45DCKRG4

SN74LVC1T45DCKT