SN74LVC2G126DCU [TI]
LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, PLASTIC, TSSOP-8;
| 型号： | SN74LVC2G126DCU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, PLASTIC, TSSOP-8 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES205J–APRIL 1999–REVISED JANUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4 ns at 3.3 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
4 5
GND
2Y
2A
1Y
VCC
2OE
1Y
1
2
3
4
8
7
6
5
1OE
1A
VCC
2OE
1Y
1
2
3
4
8
7
6
5
1OE
1A
3 6
2 7
1 8
1A
2OE
VCC
2Y
1OE
GND
2A
2Y
GND
2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74LVC2G126YZPR
_ _ _CN_
C26_ _ _
Reel of 3000
Reel of 3000
Reel of 250
SN74LVC2G126DCTR
SN74LVC2G126DCUR
SN74LVC2G126DCUT
–40°C to 85°C
VSSOP – DCU
C26_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES205J–APRIL 1999–REVISED JANUARY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
OUTPUT
Y
A
H
L
H
H
L
H
L
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
1A
2
6
3
1Y
2Y
7
5
2OE
2A
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC Supply voltage range
6.5
6.5
6.5
V
V
VI
Input voltage range(2)
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
±50
±100
220
DCT package
DCU package
YZP package
θJA
Package thermal impedance(4)
227 °C/W
102
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES205J–APRIL 1999–REVISED JANUARY 2007
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
5
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES205J–APRIL 1999–REVISED JANUARY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
VOH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.4
3 V
0.55
0.55
4.5 V
A or OE
inputs
II
VI = 5.5 V or GND
0 to 5.5 V
±5
µA
Ioff
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = 5.5 V or GND,
0
±10
10
µA
µA
µA
µA
IOZ
ICC
∆ICC
3.6 V
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
10
One input at VCC – 0.6 V,
Other inputs at VCC or GND
500
Data inputs
3.5
4
CI
VI = VCC or GND
3.3 V
3.3 V
pF
pF
Control
inputs
Co
VO = VCC or GND
6.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.5
3.5
1.7
MAX
MIN
1.7
1.7
1
MAX
MIN MAX
MIN
1
MAX
tpd
ten
tdis
A
Y
Y
Y
9.8
10
4.9
5
1.4
1.5
1
4
4.1
4.4
3.2
3.1
3.3
ns
ns
ns
OE
OE
1
12.6
5.7
1
Operating Characteristics
TA = 25°
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
19
2
TYP
19
2
TYP
20
2
TYP
22
3
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
f = 10 MHz
pF
4
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SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES205J–APRIL 1999–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2013
PACKAGING INFORMATION
Orderable Device
74LVC2G126DCTRE4
74LVC2G126DCTRG4
74LVC2G126DCURE4
74LVC2G126DCURG4
74LVC2G126DCUTE4
74LVC2G126DCUTG4
SN74LVC2G126DCTR
SN74LVC2G126DCUR
SN74LVC2G126DCUT
SN74LVC2G126YZPR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SM8
SM8
US8
DCT
8
8
8
8
8
8
8
8
8
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
C26
Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCT
DCU
DCU
DCU
DCU
DCT
DCU
DCU
YZP
3000
3000
3000
250
Green (RoHS
& no Sb/Br)
C26
Z
Green (RoHS
& no Sb/Br)
(C26Q ~ C26R)
(C26Q ~ C26R)
(C26Q ~ C26R)
(C26Q ~ C26R)
US8
Green (RoHS
& no Sb/Br)
US8
Green (RoHS
& no Sb/Br)
US8
250
Green (RoHS
& no Sb/Br)
SM8
US8
3000
3000
250
Green (RoHS
& no Sb/Br)
C26
Z
Green (RoHS
& no Sb/Br)
(C26Q ~ C26R)
(C26Q ~ C26R)
(CN7 ~ CNN)
US8
Green (RoHS
& no Sb/Br)
DSBGA
3000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Aug-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G126DCUR
SN74LVC2G126YZPR
US8
DCU
YZP
8
8
3000
3000
180.0
178.0
8.4
9.2
2.25
1.02
3.35
2.02
1.05
0.63
4.0
4.0
8.0
8.0
Q3
Q1
DSBGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC2G126DCUR
SN74LVC2G126YZPR
US8
DCU
YZP
8
8
3000
3000
202.0
220.0
201.0
220.0
28.0
35.0
DSBGA
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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