SN74LVC2G74MDCUTEP [TI]
具有清零和预置端的增强型产品单路正边沿触发式 D 型触发器 | DCU | 8 | -55 to 125;
| 型号： | SN74LVC2G74MDCUTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有清零和预置端的增强型产品单路正边沿触发式 D 型触发器 | DCU | 8 | -55 to 125 触发器 |
| 文件： | 总12页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC2G74-EP
www.ti.com ....................................................................................................................................................................................................... SCES718–MAY 2008
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
1
FEATURES
•
Controlled Baseline
•
•
•
•
•
Inputs Accept Voltages to 5.5 V
Max tpd of 7.9 ns at 3.3 V
–
–
–
One Assembly Site
One Test Site
Low Power Consumption, 10 µA Max ICC
±24 mA Output Drive at 3.3 V
One Fabrication Site
•
•
Extended Temperature Performance of –55°C
to 125°C
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
•
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
•
•
•
Enhanced Product-Change Notification
Ioff Supports Partial Power Down Mode
Operation
(1)
Qualification Pedigree
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Supports 5-V VCC Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
VCC
PRE
CLR
Q
1
2
3
4
8
7
6
5
CLK
D
Q
GND
DESCRIPTION/ORDERING INFORMATION
This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC2G74-EP
SCES718–MAY 2008 ....................................................................................................................................................................................................... www.ti.com
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
–55°C to 125°C
VSSOP – DCU
Reel of 250
SN74LVC2G74MDCUTEP CHB
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCU: The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
Q
L
H
L
X
L
H(1)
H
H(1)
L
L
X
H
H
↑
H
L
H
H
↑
L
H
H
H
L
X
Q0
Q 0
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
7
1
PRE
CLK
C
C
C
5
Q
TG
C
C
C
C
2
6
D
TG
TG
TG
3
Q
C
C
C
CLR
2
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Product Folder Link(s): SN74LVC2G74-EP
SN74LVC2G74-EP
www.ti.com ....................................................................................................................................................................................................... SCES718–MAY 2008
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC Supply voltage range
6.5
6.5
6.5
V
V
VI
Input voltage range(2)
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
θJA
DCU package
227 °C/W
150 °C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2008, Texas Instruments Incorporated
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3
Product Folder Link(s): SN74LVC2G74-EP
SN74LVC2G74-EP
SCES718–MAY 2008 ....................................................................................................................................................................................................... www.ti.com
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–24
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
24
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
5
TA
–55
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Product Folder Link(s): SN74LVC2G74-EP
SN74LVC2G74-EP
www.ti.com ....................................................................................................................................................................................................... SCES718–MAY 2008
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
VOH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 24 mA
0.4
3 V
0.55
0.55
4.5 V
Data or
control inputs
II
VI = 5.5 V or GND
0 to 5.5 V
±5
µA
Ioff
VI or VO = 5.5 V
0
±10
10
µA
µA
µA
pF
ICC
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
ΔICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
500
Ci
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
200
fclock
tw
175
MHz
ns
CLK
2.7
2.7
1.3
1.2
1.2
2
2
Pulse duration
PRE or CLR low
Data
1.1
1.2
0.5
tsu
th
Setup time, before CLK↑
Hold time, data after CLK↑
ns
ns
PRE or CLR inactive
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
200
1.4
MAX
fmax
175
2.2
2.6
1.7
MHz
Q
Q
7.9
8.2
7.9
6.1
6.4
6.1
CLK
tpd
1.6
ns
PRE or CLR
Q or Q
1.6
Copyright © 2008, Texas Instruments Incorporated
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SN74LVC2G74-EP
SCES718–MAY 2008 ....................................................................................................................................................................................................... www.ti.com
Operating Characteristics
TA = 25°C
VCC = 3.3 V
TYP
VCC = 5 V
TYP
PARAMETER
TEST CONDITIONS
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
37
40
pF
6
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G74-EP
SN74LVC2G74-EP
www.ti.com ....................................................................................................................................................................................................... SCES718–MAY 2008
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2008, Texas Instruments Incorporated
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PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC2G74MDCUTEP US8
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
US8 DCU
SPQ
Length (mm) Width (mm) Height (mm)
202.0 201.0 28.0
SN74LVC2G74MDCUTEP
8
250
Pack Materials-Page 2
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