SN74LVC540ANSRG4 [TI]
Octal Buffer/Driver With 3-State Outputs 20-SO -40 to 125;
| 型号： | SN74LVC540ANSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal Buffer/Driver With 3-State Outputs 20-SO -40 to 125 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总27页 (文件大小：1091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN54LVC540A, SN74LVC540A
SCAS297N –JANUARY 1993–REVISED JUNE 2014
SNx4LVC540A Octal Buffers/Drivers with 3-State Outputs
1 Features
2 Applications
1
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
•
•
•
Handset: Smartphone
Network Switch
Health and Fitness; Wearables
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
3 Description
The SN54LVC540A octal buffer/driver is designed for
2.7-V to 3.6-V VCC operation, and the SN74LVC540A
octal buffer/driver is designed for 1.65-V to 3.6-V VCC
operation.
•
•
•
•
•
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC
)
Device Information(1)
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
PART NUMBER
PACKAGE
BODY SIZE (NOM)
12.80 mm × 7.50 mm
12.60 mm × 5.30 mm
7.50 mm × 5.30 mm
5.00 mm × 4.40 mm
6.50 mm × 4.40 mm
SIOC (20)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
SO (20)
SN74LVC540A
SSOP (20)
TVSOP (20)
TSSOP (20)
ESD Protection Exceeds JESD 22
–
–
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
4 Simplified Schematic
1
OE1
OE2
19
2
18
Y1
A1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC540A, SN74LVC540A
SCAS297N –JANUARY 1993–REVISED JUNE 2014
www.ti.com
Table of Contents
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes.......................................... 9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Related Links ........................................................ 12
13.2 Trademarks........................................................... 12
13.3 Electrostatic Discharge Caution............................ 12
13.4 Glossary................................................................ 12
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics, SN54LVC540A ............... 6
7.7 Switching Characteristics, SN74LVC540A ............... 6
7.8 Operating Characteristics.......................................... 7
7.9 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
14 Mechanical, Packaging, and Orderable
8
9
Information ........................................................... 12
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (May 2005) to Revision N
Page
•
•
•
•
•
•
•
•
•
•
•
Updated document to new data sheet standards................................................................................................................... 1
Deleted Ordering Information table. ....................................................................................................................................... 1
Added Military Disclaimer to Features list. ............................................................................................................................ 1
Added Device Information table. ............................................................................................................................................ 1
Added Handling Ratings table. .............................................................................................................................................. 4
Changed MAX ambient temperature to 125°C....................................................................................................................... 5
Added Thermal Information table. .......................................................................................................................................... 5
Added Typical Characteristics. .............................................................................................................................................. 7
Added Device and Documentation Support. ........................................................................................................................ 12
Added ESD warning. ............................................................................................................................................................ 12
Added Mechanical, Packaging, and Orderable Information................................................................................................. 12
2
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Product Folder Links: SN54LVC540A SN74LVC540A
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SCAS297N –JANUARY 1993–REVISED JUNE 2014
6 Pin Configuration and Functions
SN54LVC540A . . . J OR W PACKAGE
SN74LVC540A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
SN54LVC540A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
VCC
OE2
Y1
3
2
1
20 19
18
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
A2
4
5
6
7
8
A3
Y2
17
16
15
14
A4
Y3
A5
Y4
A6
Y5
9
10 11 12 13
A7
Y6
A8
Y7
GND
Y8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
OE1
A1
NO.
1
I
I
Output enable
A1 input
2
A2
3
I
A2 input
A3
4
I
A3 input
A4
5
I
A4 input
A5
6
I
A5 input
A6
7
I
A6 input
A7
8
I
A7 input
A8
9
I
A8 input
GND
Y8
10
11
12
13
14
15
16
17
18
19
20
–
O
O
O
O
O
O
O
O
I
Ground pin
Y8 output
Y7 output
Y6 output
Y5 output
Y4 output
Y3 output
Y2 output
Y1 output
Output enable
Power pin
Y7
Y6
Y5
Y4
Y3
Y2
Y1
OE2
VCC
–
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SCAS297N –JANUARY 1993–REVISED JUNE 2014
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7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
±50
±100
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
0
2000
1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
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SCAS297N –JANUARY 1993–REVISED JUNE 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN54LVC540A
SN74LVC540A
UNIT
MIN
2
MAX
MIN
1.65
1.5
MAX
Operating
3.6
3.6
VCC
Supply voltage
V
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
2
0.35 × VCC
0.7
0.8
5.5
VCC
5.5
–4
VIL
Low-level input voltage
0.8
5.5
VI
Input voltage
0
0
0
0
0
0
V
V
High or low state
3-state
VCC
5.5
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
mA
–12
–24
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
Low-level output current
mA
°C
12
24
12
24
TA
Operating free-air temperature
–55
125
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC540A
THERMAL METRIC(1)
DB
DGV
DW
20 PINS
88.3
51.1
50.9
20.0
50.5
–
NS
PW
UNIT
RθJA
Junction-to-ambient thermal resistance
94.5
56.2
49.7
18.1
49.2
–
114.7
29.8
56.2
0.8
74.7
40.5
42.3
14.3
41.9
–
102.5
35.9
53.5
2.2
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
55.5
–
52.9
–
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1993–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC540A
MIN TYP(1) MAX
SN74LVC540A
MIN TYP(1) MAX
VCC – 0.2
PARAMETER
TEST CONDITIONS
VCC
UNIT
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
IOH = –100 μA
VCC – 0.2
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
2.2
2.4
2.2
IOH = –12 mA
IOH = –24 mA
IOL = 100 μA
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
0.2
0.2
IOL = 4 mA
0.45
0.7
0.4
0.55
±5
VOL
V
IOL = 8 mA
IOL = 12 mA
2.7 V
0.4
0.55
±5
IOL = 24 mA
3 V
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
One input at VCC – 0.6 V,
3.6 V
μA
μA
μA
Ioff
IOZ
0
±10
±10
10
3.6 V
±15
10
ICC
IO = 0
3.6 V
μA
μA
10
10
ΔICC
2.7 V to 3.6 V
500
500
Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
3.3 V
4
4
pF
pF
Co
VO = VCC or GND
5.5
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
7.6 Switching Characteristics, SN54LVC540A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC540A
VCC = 3.3 V
± 0.3 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
UNIT
MIN
MAX
tpd
ten
tdis
A
Y
Y
Y
7.1
8
1
1
1
5.3
6.6
7.4
ns
ns
ns
OE
OE
8.2
7.7 Switching Characteristics, SN74LVC540A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC540A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
7.1
8
MIN
1.4
1.1
1.8
MAX
tpd
ten
A
Y
Y
Y
16.4
16.5
15.9
7.8
10.5
9
5.3
6.6
7.4
1
ns
ns
ns
ns
OE
OE
1
1
1
tdis
1
1
1
8.2
tsk(o)
6
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SCAS297N –JANUARY 1993–REVISED JUNE 2014
7.8 Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
63
3
TYP
56
3
TYP
31
3
Outputs enabled
Outputs disabled
Power dissipation capacitance per
Cpd
f = 10 MHz
pF
buffer/driver
7.9 Typical Characteristics
4
6
5
4
3
2
1
0
TPD
TPD
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
-100
-50
0
50
100
150
VCC (V)
Temperature (°C)
D001
D001
Figure 1. TPD Across Temperature at 25°C
Figure 2. TPD Across Temperature at 3.3 V
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8 Parameter Measurement Information
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs
and outputs on opposite sides of the package that facilitate printed circuit board layout. The 3-state control gate
is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs
are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the
use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified
for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current
backflow through the devices when they are powered down. To ensure the high-impedance state during power
up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
1
OE1
19
OE2
2
18
A1
Y1
To Seven Other Channels
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
Operates from 1.65 V to 3.6 V
Allows down voltage translation
Inputs accept voltages to 5.5 V
Ioff Feature
Allows voltages on the inputs and outputs when VCC is 0 V
–
–
–
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
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10 Application and Implementation
10.1 Application Information
The SN74LVC540A is a high drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched . It can produce 24 mA of drive current at 3.3 V
making it ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are
5.5 V tolerant allowing it to translate down to VCC
.
10.2 Typical Application
Regulated 3.6 V
VCC
OE1
A1
OE2
Y1
uC
System Logic
LEDs
uC or
System Logic
A8
Y8
GND
Figure 5. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
–
–
–
Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
.
2. Recommend Output Conditions
–
–
Load currents should not exceed 25 mA per output and 50 mA total for the part.
Outputs should not be pulled above VCC
.
10
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Typical Application (continued)
10.2.3 Application Curves
300
250
200
150
100
50
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
0
0
10
20
30
40
50
60
Frequency - MHz
D003
Figure 6. ICC vs Frequency at 3.3 V
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IO’s so they also cannot float when disabled.
12.2 Layout Example
V
cc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Layout Diagram
Copyright © 1993–2014, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: SN54LVC540A SN74LVC540A
SN54LVC540A, SN74LVC540A
SCAS297N –JANUARY 1993–REVISED JUNE 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
SN54LVC540A
SN74LVC540A
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Documentation Feedback
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC540A SN74LVC540A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-9759401Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9759401Q2A
SNJ54LVC
540AFK
5962-9759401QRA
5962-9759401QSA
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9759401QR
A
SNJ54LVC540AJ
W
5962-9759401QS
A
SNJ54LVC540AW
SN74LVC540ADBLE
SN74LVC540ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
20
20
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LC540A
SN74LVC540ADBRE4
SN74LVC540ADGVR
SN74LVC540ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
TVSOP
SOIC
SOIC
SOIC
SO
DB
DGV
DW
DW
DW
NS
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LC540A
Green (RoHS
& no Sb/Br)
LC540A
Green (RoHS
& no Sb/Br)
LVC540A
LVC540A
LVC540A
LVC540A
LVC540A
LC540A
SN74LVC540ADWG4
SN74LVC540ADWR
SN74LVC540ANSR
SN74LVC540ANSRG4
SN74LVC540APW
25
Green (RoHS
& no Sb/Br)
2000
2000
2000
70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SO
NS
Green (RoHS
& no Sb/Br)
TSSOP
PW
Green (RoHS
& no Sb/Br)
SN74LVC540APWLE
SN74LVC540APWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LC540A
LC540A
SN74LVC540APWRE4
ACTIVE
TSSOP
PW
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74LVC540APWRG4
SN74LVC540APWT
SNJ54LVC540AFK
ACTIVE
TSSOP
TSSOP
LCCC
PW
20
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
LC540A
ACTIVE
ACTIVE
PW
FK
250
1
Green (RoHS
& no Sb/Br)
-40 to 85
LC540A
TBD
-55 to 125
5962-
9759401Q2A
SNJ54LVC
540AFK
SNJ54LVC540AJ
SNJ54LVC540AW
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9759401QR
A
SNJ54LVC540AJ
W
5962-9759401QS
A
SNJ54LVC540AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC540A, SN74LVC540A :
Catalog: SN74LVC540A
•
Automotive: SN74LVC540A-Q1, SN74LVC540A-Q1
•
Enhanced Product: SN74LVC540A-EP, SN74LVC540A-EP
•
Military: SN54LVC540A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC540ADBR
SN74LVC540ADGVR
SN74LVC540ADWR
SN74LVC540ANSR
SN74LVC540APWR
SN74LVC540APWT
SSOP
TVSOP
SOIC
DB
DGV
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
24.4
24.4
16.4
16.4
8.2
6.9
7.5
5.6
2.5
1.6
2.7
2.5
1.6
1.6
12.0
8.0
16.0
12.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
10.8
8.2
13.3
13.0
7.1
12.0
12.0
8.0
SO
TSSOP
TSSOP
PW
PW
6.95
6.95
7.1
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC540ADBR
SN74LVC540ADGVR
SN74LVC540ADWR
SN74LVC540ANSR
SN74LVC540APWR
SN74LVC540APWT
SSOP
TVSOP
SOIC
DB
DGV
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
45.0
45.0
38.0
38.0
SO
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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相关型号：
SN74LVC540APWG4
LVC/LCX/Z SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20
TI
SN74LVC540APWTG4
LVC/LCX/Z SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20
TI
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