SN74LVC574APW [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74LVC574APW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
SN54LVC574A . . . J OR W PACKAGE
SN74LVC574A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
OE
1D
V
CC
1Q
1
2
3
4
5
6
7
8
9
10
20
19
CC
A
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
2D
3D
4D
18 2Q
17 3Q
16 4Q
= 3.3 V, T = 25°C
A
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
5D
6D
7D
8D
15
14
13
12
11
5Q
6Q
7Q
8Q
CLK
3.3-V V
)
CC
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
GND
SN54LVC574A . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and DIPs (J)
3
2 1 20 19
18
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
description
9 10 11 12 13
The SN54LVC574A octal edge-triggered D-type
flip-flop is designed for 2.7-V to 3.6-V V
CC
operation and the SN74LVC574A octal
edge-triggered D-type flip-flop is designed for
1.65-V to 3.6-V V
operation.
CC
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
description (continued)
The SN54LVC574A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC574A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q
0
H
Z
†
logic symbol
1
OE
EN
C1
11
CLK
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
19
1Q
2
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
CC
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC574A
SN74LVC574A
UNIT
MIN
2
MAX
MIN
MAX
Operating
3.6
1.65
1.5
3.6
V
V
Supply voltage
V
CC
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
High-level input voltage
V
V
IH
2
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
5.5
0.8
V
V
Input voltage
0
0
0
0
0
0
5.5
V
V
I
High or low state
3 state
V
V
CC
5.5
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–4
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
–24
–12
–24
4
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
I
12
24
12
24
6
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
6
0
ns/V
T
–55
125
–40
85
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC574A
SN74LVC574A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
†
TYP
†
TYP
MIN
MAX
MIN
V –0.2
CC
MAX
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
I
= –100 µA
OH
V
CC
–0.2
I
I
= –4 mA
= –8 mA
1.2
1.7
2.2
2.4
2.2
OH
V
OH
V
OH
2.7 V
2.2
2.4
2.2
I
I
I
= –12 mA
= –24 mA
= 100 µA
OH
OH
OL
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
0.2
0.2
I
I
I
I
= 4 mA
= 8 mA
= 12 mA
= 24 mA
0.45
0.7
0.4
0.55
±5
OL
OL
OL
OL
V
OL
V
2.7 V
0.4
0.55
±5
3 V
I
I
I
V = 0 to 5.5 V
I
3.6 V
µA
µA
µA
I
V or V = 5.5 V
0
±10
±10
10
I
O
off
V
= 0 to 5.5 V
3.6 V
±15
10
O
OZ
V = V
or GND
I
CC
I
I
O
= 0
3.6 V
µA
µA
CC
‡
3.6 V ≤ V ≤ 5.5 V
10
10
I
One input at V
– 0.6 V,
or GND
CC
Other inputs at V
∆I
CC
2.7 V to 3.6 V
500
500
CC
V = V or GND
CC
C
C
3.3 V
3.3 V
4
4
pF
pF
i
I
V
= V
or GND
5.5
5.5
o
O
CC
†
‡
All typical values are at V
This applies in the disabled state only.
= 3.3 V, T = 25°C.
A
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 3)
SN54LVC574A
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3.3
2
3.3
2
w
ns
su
h
2
2
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
SN74LVC574A
V = 1.8 V
CC
± 0.15 V
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
†
†
150
150
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
†
†
†
†
3.3
2
3.3
2
w
†
†
ns
su
h
1.5
1.5
ns
†
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC574A
FROM
(INPUT)
TO
(OUTPUT)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
PARAMETER
UNIT
CC
MIN
MIN
150
1
MAX
f
t
t
t
150
MHz
ns
max
CLK
OE
Q
Q
Q
8
9
7
7
7.5
6.4
pd
1
ns
en
0.5
ns
OE
dis
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC574A
FROM
(INPUT)
TO
(OUTPUT)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
MAX
PARAMETER
UNIT
CC
MIN
†
MAX
MIN
†
MAX
MIN
MIN
150
2.2
MAX
f
t
t
t
t
150
MHz
ns
max
CLK
OE
Q
Q
Q
†
†
†
†
†
†
†
†
8
8.5
7
7
7.5
6.4
1
pd
†
†
1.5
ns
en
†
†
1.7
ns
OE
dis
‡
ns
sk(o)
†
‡
This information was not available at the time of publication.
Skew between any two outputs of the same package switching in the same direction
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V = 3.3 V
CC
CC
± 0.2 V
TEST
CONDITIONS
± 0.15 V
TYP
†
± 0.3 V
PARAMETER
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
†
43
Power dissipation capacitance
per flip-flop
C
f = 10 MHz
pF
pd
†
†
15
†
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1k Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
Open
L
PLZ PZL
1k Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301J – JANUARY 1993 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
Open
500 Ω
t
Open
6 V
pd
/t
From Output
Under Test
t
GND
PLZ PZL
t
/t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
(see Note B)
V
OL
OH
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
V
V
– 0.3 V
OH
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
8
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