SN74LVC574AQDWRQ1 [TI]

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
SN74LVC574AQDWRQ1
型号: SN74LVC574AQDWRQ1
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
八路边沿触发D型触发器具有三态输出

触发器 输出元件
文件: 总11页 (文件大小:219K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74LVC574A-Q1  
www.ti.com ............................................................................................................................................... SCAS715BSEPTEMBER 2003REVISED APRIL 2008  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
1
FEATURES  
DW OR PW PACKAGE  
Qualified for Automotive Applications  
(TOP VIEW)  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
1Q  
2D  
3D  
4D  
5D  
18 2Q  
17 3Q  
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7 ns at 3.3 V  
16  
15  
14  
13  
12  
11  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
6D  
7D  
8D  
GND  
Typical VOHV (Output VOH Undershoot) > 2 V at  
VCC = 3.3 V, TA = 25°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V VCC  
)
Ioff Supports Partial-Power-Down Mode  
Operation  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance  
loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of thIs device as a translator in  
a mixed 3.3-V/5-V system environment.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74LVC574A-Q1  
SCAS715BSEPTEMBER 2003REVISED APRIL 2008 ............................................................................................................................................... www.ti.com  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Reel of 2000  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC574AQDWRQ1  
TOP-SIDE MARKING  
L574AQ1  
L574AQ1  
SOIC – DW  
–40°C to 125°C  
TSSOP – PW  
SN74LVC574AQPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
FUNCTION TABLE  
(EACH FLIP-FLOP)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
X
X
X
Q0  
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
OE  
11  
CLK  
C1  
1D  
19  
1Q  
2
1D  
To Seven Other Channels  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
MAX  
6.5  
UNIT  
V
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Voltage range applied to any output in the high or low state(2)(3)  
6.5  
V
VO  
VO  
IIK  
6.5  
V
–0.5 VCC + 0.5  
V
Input clamp current  
VI < 0  
–50  
–50  
±50  
±100  
58  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCC or GND  
DW package  
PW package  
θJA  
Package thermal impedance(4)  
Storage temperature range  
°C/W  
°C  
83  
Tstg  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The value of VCC is provided in the recommended operating conditions table.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
2
Submit Documentation Feedback  
Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN74LVC574A-Q1  
SN74LVC574A-Q1  
www.ti.com ............................................................................................................................................... SCAS715BSEPTEMBER 2003REVISED APRIL 2008  
Recommended Operating Conditions(1)  
MIN  
2
MAX UNIT  
Operating  
3.6  
V
VCC  
Supply voltage  
Data retention only  
VCC = 2.7 V to 3.6 V  
VCC = 2.7 V to 3.6 V  
1.5  
2
VIH  
VIL  
VI  
High-level input voltage  
Low-level input voltage  
Input voltage  
V
0.8  
5.5  
VCC  
5.5  
–12  
–24  
12  
V
V
0
0
0
High or low state  
3-state  
VO  
IOH  
IOL  
Output voltage  
V
VCC = 2.7 V  
VCC = 3 V  
High-level output current  
Low-level output current  
mA  
mA  
VCC = 2.7 V  
VCC = 3 V  
24  
Δt/Δv  
Input transition rise or fall rate  
Operating free-air temperature  
6
ns/V  
TA  
–40  
125  
°C  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
2.7 V to 3.6 V  
2.7 V  
MIN TYP(1) MAX UNIT  
VCC – 0.2  
IOH = –100 µA  
2.2  
2.4  
2.2  
VOH  
IOH = –12 mA  
V
3 V  
IOH = –24 mA  
IOL = 100 µA  
3 V  
2.7 V to 3.6 V  
2.7 V  
0.2  
0.4  
0.55  
±5  
VOL  
IOL = 12 mA  
V
IOL = 24 mA  
3 V  
II  
VI = 0 to 5.5 V  
VO = 0 to 5.5 V  
VI = VCC or GND  
3.6 V VI 5.5 V(2)  
3.6 V  
µA  
µA  
IOZ  
3.6 V  
±15  
10  
ICC  
IO = 0  
3.6 V  
µA  
10  
ΔICC  
Ci  
One input at VCC – 0.6 V,  
VI = VCC or GND  
Other inputs at VCC or GND  
2.7 V to 3.6 V  
3.3 V  
500  
µA  
pF  
pF  
4
Co  
VO = VCC or GND  
3.3 V  
5.5  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This applies in the disabled state only.  
Timing Requirements  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 3.3 V  
± 0.3 V  
VCC = 2.7 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
150  
fclock  
tw  
Clock frequency  
150  
MHz  
ns  
Pulse duration, CLK high or low  
Setup time, data before CLK↑  
Hold time, data after CLK↑  
3.3  
2
3.3  
2
tsu  
th  
ns  
2
2
ns  
Copyright © 2003–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): SN74LVC574A-Q1  
SN74LVC574A-Q1  
SCAS715BSEPTEMBER 2003REVISED APRIL 2008 ............................................................................................................................................... www.ti.com  
Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 3.3 V  
± 0.3 V  
VCC = 2.7 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
fmax  
tpd  
150  
150  
1
MHz  
ns  
CLK  
OE  
Q
Q
Q
8
9
7
7
7.5  
6.4  
ten  
1
ns  
tdis  
OE  
0.5  
ns  
Operating Characteristics  
TA = 25°C  
VCC = 2.5 V  
VCC = 3.3 V  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
TYP  
60  
9
TYP  
43  
Outputs enabled  
Outputs disabled  
Cpd  
Power dissipation capacitance per flip-flop  
f = 10 MHz  
pF  
15  
4
Submit Documentation Feedback  
Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN74LVC574A-Q1  
SN74LVC574A-Q1  
www.ti.com ............................................................................................................................................... SCAS715BSEPTEMBER 2003REVISED APRIL 2008  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
/t  
S1  
GND  
t
t
Open  
PLH PHL  
C
L
t
/t  
V
LOAD  
GND  
R
L
PLZ PZL  
(see Note A)  
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUTS  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
V
I
t /t  
r f  
2.7 V  
2.7 V  
2.7 V  
2.5 ns  
2.5 ns  
1.5 V  
1.5 V  
6 V  
6 V  
50 pF  
50 pF  
500 Ω  
500 Ω  
0.3 V  
0.3 V  
3.3 V ± 0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
h
su  
V
I
V
I
Input  
V
M
V
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
I
V
I
Output  
Control  
V
M
V
M
Input  
V
M
V
M
0 V  
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
V
V
OH  
V
V
/2  
LOAD  
V
V
V
M
M
Output  
V
V
M
S1 at V  
LOAD  
V
+ V  
OL  
OL  
(see Note B)  
OL  
t
PHL  
PLH  
t
t
PHZ  
PZH  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
V
OH  
V
- V  
V
M
OH  
M
Output  
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
Copyright © 2003–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): SN74LVC574A-Q1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Aug-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CLVC574AQDWRG4Q1  
CLVC574AQPWRG4Q1  
SN74LVC574AQDWRQ1  
SN74LVC574AQPWRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
TSSOP  
SOIC  
DW  
PW  
DW  
PW  
20  
20  
20  
20  
2000  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN74LVC574A-Q1 :  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Aug-2012  
Catalog: SN74LVC574A  
Enhanced Product: SN74LVC574A-EP  
Military: SN54LVC574A  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
Military - QML certified for Military and Defense Applications  
Addendum-Page 2  
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