SN74LVC646ADW [TI]
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 八路总线收发器和寄存器具有三态输出
| 型号： | SN74LVC646ADW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
SN74LVC646A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
= 3.3 V, T = 25°C
CC
A
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
2
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
OH
3
= 3.3 V, T = 25°C
CC
A
4
Power Off Disables Outputs, Permitting
Live Insertion
5
6
7
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
8
9
3.3-V V
)
CC
10
11
12
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
B8
Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, and Ceramic Chip Carriers (FK)
4
3
2
1
28 27 26
25
A1
A2
A3
NC
A4
A5
A6
OE
B1
B2
NC
B3
B4
B5
5
description
24
23
22
21
20
19
6
The SN54LVC646A octal bus transceiver and
7
register is designed for 2.7-V to 3.6-V V
8
CC
operation and the SN74LVC646A octal bus
transceiver and register is designed for 1.65-V to
9
10
11
3.6-V V
operation.
CC
12 13 14 15 16 17 18
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on
the A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
are performed with the ’LVC646A.
NC – No internal connection
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
description (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LVC646A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC646A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
OE
X
X
H
H
L
†
†
†
↑
X
Unspecified
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
Input
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
21
3
1
23
2
22
SBA
L
21
3
DIR
H
1
23
CLKAB CLKBA SAB
L
2
22
SBA
X
DIR CLKAB CLKBA SAB
L
OE
L
OE
L
X
X
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
↑
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
†
logic symbol
21
OE
G3
3
DIR
3 EN1 [BA]
3 EN2 [AB]
23
22
1
CLKBA
SBA
C4
G5
CLKAB
SAB
C6
G7
2
20
4D
2
B1
5
≥1
4
A1
1
5 1
≥1
6D
7
7
1
5
19
18
17
16
15
14
13
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
6
7
8
9
10
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, and PW packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
logic diagram (positive logic)
21
OE
3
DIR
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, and PW packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V : (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
CC
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC646A
SN74LVC646A
UNIT
MIN
MAX
MIN
MAX
Operating
2
3.6
1.65
1.5
3.6
V
V
Supply voltage
V
CC
Data retention only
1.5
2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65×V
CC
High-level input voltage
1.7
2
V
V
IH
0.35×V
CC
V
IL
Low-level input voltage
0.7
0.8
5.5
0.8
5.5
V
V
Input voltage
0
0
0
0
0
0
V
V
I
High or low state
3 state
V
V
CC
5.5
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–4
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
–24
–12
–24
4
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
I
12
24
12
24
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
0
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC646A
SN74LVC646A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
†
TYP
†
TYP
MIN
MAX
MIN
V –0.2
CC
MAX
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
I
= –100 µA
OH
V
CC
–0.2
I
I
= –4 mA
= –8 mA
1.2
1.7
2.2
2.4
2.2
OH
V
OH
V
OH
2.7 V
2.2
2.4
2.2
I
I
I
= –12 mA
= –24 mA
= 100 µA
OH
OH
OL
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
0.2
0.2
I
I
I
I
= 4 mA
= 8 mA
= 12 mA
= 24 mA
0.45
0.7
0.4
0.55
±5
OL
OL
OL
OL
V
OL
V
2.7 V
0.4
0.55
±5
3 V
I
I
I
Control inputs V = 0 to 5.5 V
I
3.6 V
µA
µA
µA
I
V or V = 5.5 V
0
±10
±10
10
I
O
off
‡
V
= 0 to 5.5 V
3.6 V
±15
10
O
OZ
V = V
or GND
I
CC
I
I
O
= 0
3.6 V
µA
µA
CC
§
3.6 V ≤ V ≤ 5.5 V
10
10
I
One input at V
– 0.6 V,
CC
Other inputs at
or GND
∆I
CC
2.7 V to 3.6 V
500
500
V
CC
Control inputs V = V
C
C
or GND
3.3 V
3.3 V
4.5
7.5
4.5
7.5
pF
pF
i
I
CC
= V
A or B ports
V
or GND
io
O
CC
†
‡
§
All typical values are at V
For I/O ports, the parameter I
OZ
This applies in the disabled state only.
= 3.3 V, T = 25°C.
CC
A
includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 4)
SN54LVC646A
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration
3.3
1.6
1.7
3.3
1.5
1.7
w
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
h
ns
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 4)
SN74LVC646A
V = 1.8 V
CC
± 0.15 V
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
†
†
150
150
MHz
ns
clock
Pulse duration
†
†
†
†
†
†
3.3
1.6
1.7
3.3
1.5
1.7
w
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
h
ns
†
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 4)
SN54LVC646A
FROM
(INPUT)
TO
(OUTPUT)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
PARAMETER
UNIT
CC
MIN
MIN
150
1
MAX
f
t
150
MHz
ns
max
A or B
CLK
B or A
A or B
7.9
8.8
7.4
8.4
8.6
8.2
7.5
8.3
7.9
1
pd
SBA or SAB
OE
9.9
1
t
t
t
t
A
A
B
B
10.2
8.9
1
ns
ns
ns
ns
en
dis
en
dis
1
OE
10.4
8.7
1
DIR
1
DIR
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 4)
SN74LVC646A
FROM
(INPUT)
TO
(OUTPUT)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
MAX
PARAMETER
UNIT
CC
MIN
†
MAX
MIN
†
MAX
MIN
MIN
150
1.4
1.3
1.4
1
MAX
f
t
150
MHz
ns
max
A or B
CLK
B or A
A or B
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
7.9
8.8
7.4
8.4
8.6
8.2
7.5
8.3
7.9
†
†
pd
SBA or SAB
OE
†
†
9.9
t
t
t
t
A
A
B
B
†
†
10.2
8.9
ns
ns
ns
ns
en
dis
en
dis
†
†
1
OE
†
†
10.4
8.7
1.2
1.1
DIR
†
†
DIR
†
This information was not available at the time of publication.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
TEST
CONDITIONS
± 0.15 V
TYP
†
PARAMETER
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
†
75
Power dissipation capacitance
per transceiver
C
f = 10 MHz
pF
pd
†
†
9
†
This information was not available at the time of publication.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1k Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
Open
L
PLZ PZL
1k Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2 ns, t ≤2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2 ns, t ≤2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS302G – JANUARY 1993 – REVISED JUNE1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
3 V
Output
Waveform 1
S1 at 6 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OH
(see Note B)
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
V
OH
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2.5 ns, t ≤2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 4. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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