SN74LVCH16240ADLR [TI]
具有总线保持和三态输出的 16 通道、2V 至 3.6V 反相器 | DL | 48 | -40 to 85;
| 型号： | SN74LVCH16240ADLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有总线保持和三态输出的 16 通道、2V 至 3.6V 反相器 | DL | 48 | -40 to 85 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1
2
3
4
5
6
7
8
9
48
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
V
42
V
Power Off Disables Outputs, Permitting
Live Insertion
CC
CC
2Y1
2Y2
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
V
18
31
V
CC
CC
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
3.3-V V
)
CC
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V V operation.
CC
TheSN74LVCH16240Aisdesignedspecificallytoimproveboththeperformanceanddensityof3-statememory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting
outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16240A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
†
logic symbol
1
1OE
2OE
3OE
EN1
EN2
EN3
EN4
48
25
24
4OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
1
1
1
2
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
46
35
33
32
14
1A2
3A2
3A3
3A4
3Y2
44
16
1A3
3Y3
43
17
1A4
3Y4
48
24
30
2OE
4OE
4A1
41
8
9
19
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
40
29
27
26
20
2A2
4A2
4A3
4A4
4Y2
38
11
12
22
2A3
4Y3
37
23
2A4
4Y4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
CC
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
MIN
1.65
1.5
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
5.5
V
V
I
High or low state
3 state
V
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–4
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
–24
4
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
I
12
24
10
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
ns/V
T
–40
85
°C
A
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
V –0.2
CC
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –8 mA
1.65 V to 3.6 V
1.65 V
2.3 V
OH
OH
OH
1.2
1.7
2.2
2.4
2.2
V
V
OH
OL
2.7 V
I
= –12 mA
OH
3 V
I
I
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
V
= 8 mA
V
= 12 mA
= 24 mA
2.7 V
0.4
3 V
0.55
±5
I
I
V = 0 to 5.5 V
3.6 V
µA
I
I
V = 0.58 V
‡
‡
I
1.65 V
2.3 V
3 V
V = 1.07 V
I
V = 0.7 V
45
I
V = 1.7 V
–45
75
µA
I(hold)
I
V = 0.8 V
I
V = 2 V
–75
I
§
V = 0 to 3.6 V
3.6 V
0
±500
±10
±10
20
I
I
I
V or V = 5.5 V
µA
µA
off
I
O
V
O
= 0 to 5.5 V
3.6 V
OZ
V = V
I
or GND
CC
I
I
O
= 0
3.6 V
µA
µA
CC
¶
3.6 V ≤ V ≤ 5.5 V
20
I
One input at V
– 0.6 V,
or GND
CC
Other inputs at V
∆I
CC
2.7 V to 3.6 V
500
CC
or GND
C
C
V = V
3.3 V
3.3 V
5
6
pF
pF
i
I
CC
= V
V
O
or GND
o
CC
†
‡
§
¶
All typical values are at V
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
This applies in the disabled state only.
= 3.3 V, T = 25°C.
CC
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
‡
MAX
MIN
‡
MAX
MIN
MAX
5
MIN
1
MAX
4.2
t
t
t
A
Y
Y
Y
‡
‡
‡
‡
‡
‡
ns
ns
ns
pd
en
dis
‡
‡
5.8
6.6
1.5
1.5
4.7
OE
OE
‡
‡
5.9
‡
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
TEST
CONDITIONS
± 0.15 V
TYP
†
PARAMETER
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
†
34
Power dissipation capacitance
per buffer/driver
C
f = 10 MHz
pF
pd
†
†
3
†
This information was not available at the time of publication.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1k Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
Open
L
PLZ PZL
1k Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH16240A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS566G – MARCH 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
Output
2.7 V
0 V
1.5 V
1.5 V
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
(see Note B)
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1998, Texas Instruments Incorporated
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