SN74LVCH16244AZRDR [TI]
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74LVCH16244AZRDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总17页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
2
3
4
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
5
6
•
•
•
Typical VOHV (Output VOH Undershoot) >2 V
at VCC = 3.3 V, TA = 25°C
7
V
CC
V
CC
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
Ioff Supports Partial-Power-Down Mode
Operation
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC
)
•
•
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
V
CC
V
CC
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
4Y1
4Y2
GND
4Y3
4Y4
4OE
4A1
4A2
GND
4A3
4A4
3OE
DESCRIPTION/ORDERING INFORMATION
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74LVCH16244A is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVCH16244AGRDR
SN74LVCH16244AZRDR
SN74LVCH16244ADL
TOP-SIDE MARKING
FBGA – GRD
Tape and reel
Tube
LDH244A
FBGA – ZRD (Pb-free)
SSOP – DL
SN74LVCH16244ADLR
74LVCH16244ADLRG4
SN74LVCH16244ADGGR
74LVCH16244ADGGRG4
SN74LVCH16244ADGVR
74LVCH16244ADGVRE4
SN74LVCH16244AGQLR
SN74LVCH16244AZQLR
LVCH16244A
Tape and reel
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
Tape and reel
LVCH16244A
LDH244A
VFBGA – GQL
LDH244A
VFBGA – ZQL (Pb-free)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
abc
abc
(1) NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y3
4Y4
NC
1OE
NC
2OE
NC
NC
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A3
4A4
A
B
C
D
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
NC
1A2
1A4
2A2
2A4
3A2
3A4
4A2
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
4OE
3OE
(1) NC – No internal connection
2
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
25
1OE
1A1
1A2
1A3
1A4
3OE
47
2
3
5
6
36
35
33
32
13
14
16
17
1Y1
1Y2
1Y3
1Y4
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
46
44
43
48
41
40
24
30
29
2OE
2A1
2A2
2A3
2A4
4OE
4A1
4A2
4A3
4A4
8
9
19
20
22
23
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
38
37
11
12
27
26
Pin numbers shown are for the DGG, DGV, and DL packages.
3
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
6.5
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
DGV package
58
θJA
Package thermal impedance(4)
DL package
63
°C/W
°C
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX
VCC – 0.2
UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
VOL
IOL = 8 mA
V
IOL = 12 mA
IOL = 24 mA
VI = 0 to 5.5 V
VI = 0.58 V
2.7 V
0.4
3 V
0.55
±5
II
3.6 V
µA
15
–15
45
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
–45
75
µA
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V(2)
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V
0
±500
±10
±10
20
Ioff
µA
µA
IOZ
3.6 V
ICC
IO = 0
3.6 V
µA
3.6 V ≤ VI ≤ 5.5 V(3)
20
∆ICC
Ci
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
5.5
6
Co
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current required to switch the input from one state to another.
(3) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.5
1.5
MAX
MIN
1
MAX
MIN
1
MAX
MIN
1.1
1
MAX
tpd
ten
A
Y
Y
Y
6.6
7.5
3.9
4.7
5.3
4.7
5.8
6.2
4.1
4.6
5.8
1
ns
ns
ns
ns
OE
OE
1
1
tdis
10.3
1
1
1.8
tsk(o)
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
33
2
TYP
32
2
TYP
35
3
Outputs enabled
Outputs disabled
Power dissipation capacitance
Cpd
f = 10 MHz
pF
per buffer/driver
5
SN74LVCH16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES494A–OCTOBER 2003–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
74LVCH16244ADGGRG4
74LVCH16244ADGVRE4
74LVCH16244ADGVRG4
74LVCH16244ADLRG4
SN74LVCH16244ADGGR
SN74LVCH16244ADGVR
SN74LVCH16244ADL
ACTIVE
TSSOP
TVSOP
TVSOP
SSOP
DGG
48
48
48
48
48
48
48
48
48
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
LVCH16244A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
DGV
DGV
DL
2000
2000
1000
2000
2000
25
Green (RoHS
& no Sb/Br)
LDH244A
Green (RoHS
& no Sb/Br)
LDH244A
Green (RoHS
& no Sb/Br)
LVCH16244A
LVCH16244A
LDH244A
TSSOP
TVSOP
SSOP
DGG
DGV
DL
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
LVCH16244A
LVCH16244A
LVCH16244A
LDH244A
SN74LVCH16244ADLG4
SN74LVCH16244ADLR
SN74LVCH16244AGQLR
SSOP
DL
25
Green (RoHS
& no Sb/Br)
SSOP
DL
1000
Green (RoHS
& no Sb/Br)
BGA
GQL
TBD
MICROSTAR
JUNIOR
SN74LVCH16244AGRDR
SN74LVCH16244AZQLR
SN74LVCH16244AZRDR
OBSOLETE
ACTIVE
BGA
MICROSTAR
JUNIOR
GRD
ZQL
ZRD
54
56
54
TBD
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
LDH244A
LDH244A
LDH244A
BGA
MICROSTAR
JUNIOR
1000
1000
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ACTIVE
BGA
MICROSTAR
JUNIOR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVCH16244ADGGR TSSOP
SN74LVCH16244ADGVR TVSOP
DGG
DGV
DL
48
48
48
56
2000
2000
1000
1000
330.0
330.0
330.0
330.0
24.4
16.4
32.4
16.4
8.6
7.1
15.8
10.2
1.8
1.6
3.1
1.5
12.0
12.0
16.0
8.0
24.0
16.0
32.0
16.0
Q1
Q1
Q1
Q1
SN74LVCH16244ADLR
SSOP
11.35 16.2
SN74LVCH16244AZQLR BGA MI
ZQL
4.8
7.3
CROSTA
R JUNI
OR
SN74LVCH16244AZRDR BGA MI
ZRD
54
1000
330.0
16.4
5.8
8.3
1.55
8.0
16.0
Q1
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCH16244ADGGR
SN74LVCH16244ADGVR
SN74LVCH16244ADLR
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
56
2000
2000
1000
1000
367.0
367.0
367.0
333.2
367.0
367.0
367.0
345.9
45.0
38.0
55.0
28.6
SN74LVCH16244AZQLR BGA MICROSTAR
JUNIOR
ZQL
SN74LVCH16244AZRDR BGA MICROSTAR
JUNIOR
ZRD
54
1000
333.2
345.9
28.6
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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