SN74LVCH245DWR [TI]
LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20;
| 型号： | SN74LVCH245DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20 总线收发器 输出元件 |
| 文件： | 总7页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES008 – JULY 1995
DB, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
V
CC
= 3.3 V, T = 25°C
CC
A
OE
B1
B2
B3
B4
B5
B6
B7
B8
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
OH
= 3.3 V, T = 25°C
CC
A
ESD Protection Exceeds 2000 V Per
MIL-STD-833C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
A5
A6
A7
A8
GND
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltages With
3.3-VV
)
CC
Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
Package Options Include Shrink
Small-Outline (DB), Plastic Small-Outline
(DW), and Thin Shrink Small-Outline (PW)
Packages
description
This octal bus transceiver is designed for 2.7-V to 3.6-V V
environment.
operation; it can interface to a 5-V system
CC
The SN74LVCH245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES008 – JULY 1995
†
logic symbol
logic diagram (positive logic)
19
1
DIR
G3
OE
1
DIR
3EN1[BA]
3EN2[AB]
19
18
OE
B1
2
18
A1
B1
1
2
A1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
To Seven Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
O
Voltage range applied to any output in the high
or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
O
Input clamp current, I (V < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . 0.6 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DW package . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES008 – JULY 1995
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
Data retention only
1.5
2
V
IH
V
IL
V
I
High-level input voltage
Low-level input voltage
Input voltage data inputs
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
V
V
V
CC
0.8
5.5
CC
0
0
0
High or low state
3 state
V
CC
5.5
V
O
Output voltage
V
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
I
I
High-level output current
Low-level output current
mA
mA
OH
= 2.7 V
= 3 V
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
= –100 µA
MIN to MAX
2.7 V
3 V
V
OH
CC
2.2
V
= – 12 mA
V
OH
OL
OH
2.4
2.2
I
I
I
I
= – 24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
MIN to MAX
2.7 V
3 V
0.2
0.4
V
V
0.55
±5
I
I
V = 5.5 V or GND
3.6 V
3 V
µA
µA
I
I
V = 0.8 V
75
I
V = 2 V
3 V
–75
I(hold)
I
V = 0 to 3.6 V
3.6 V
±500
±10
±50
10
I
V
= V
or GND
O
O
CC
= 3.6 V or 5.5 V
or GND,
§
MIN to MAX
µA
I
I
OZ
V
V = V
I
I = 0
O
3.6 V
2.7 V to 3.6 V
3.3 V
µA
µA
pF
pF
CC
CC
I
One input at V
– 0.6 V,
Other inputs at V or GND
CC
500
CC
CC
or GND
C
C
Control inputs
A or B ports
V = V
3.3
5.4
i
I
CC
= V or GND
CC
V
O
3.3 V
io
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are measured at V = 3.3 V, T = 25°C.
CC
A
For I/O ports, the parameter I
OZ
includes the input leakage current.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES008 – JULY 1995
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
1.5
1.5
1.5
MAX
MIN
MAX
8
t
t
t
t
A or B
OE
B or A
A or B
A or B
7
8.5
7.5
1
ns
ns
ns
ns
pd
9.5
8.5
en
OE
dis
†
sk(o)
†
Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
36
2
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES008 – JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
S1
500 Ω
t
Open
6 V
pd
/t
From Output
Under Test
t
GND
PLZ PZL
t
/t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
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Copyright 1998, Texas Instruments Incorporated
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