SN74LVT16245BDLG4 [TI]
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位总线，三态输出收发器
| 型号： | SN74LVT16245BDLG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总20页 (文件大小：604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
FEATURES
SN54LVT16245B . . . WD PACKAGE
SN74LVT16245B . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
1
48
47
46
45
44
43
42
41
40
39
38
37
2
3
•
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
4
5
3.3-V VCC
)
6
•
•
•
•
•
•
•
Support Unregulated Battery Operation Down
to 2.7 V
V
CC
V
CC
7
1B5
1B6
GND
1B7
1B8
1A5
1A6
GND
1A7
1A8
8
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
9
10
11
12
Ioff and Power-Up 3-State Support Hot
Insertion
2B1 13
36 2A1
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
14
15
16
17
18
19
20
21
22
23
24
35
34
33
32
31
30
29
28
27
26
25
2B2
GND
2B3
2A2
GND
2A3
2A4
Flow-Through Architecture Optimizes PCB
Layout
2B4
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
CC
V
CC
2B5
2B6
GND
2B7
2A5
2A6
GND
2A7
2A8
2OE
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
2B8
2DIR
1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVT16245BGRDR
SN74LVT16245BZRDR
SN74LVT16245BDL
TOP-SIDE MARKING
FBGA – GRD
Reel of 1000
Tube of 25
VD245B
FBGA – ZRD (Pb-free)
SN74LVT16245BDLG4
SN74LVT16245BDLR
74LVT16245BDLRG4
SN74LVT16245BDGGR
74LVT16245BDGGRE4
SN74LVT16245BDGVR
74LVT16245BDGVRE4
SN74LVT16245BGQLR
SN74LVT16245BZQLR
SNJ54LVT16245BWD
SSOP – DL
LVT16245B
Reel of 1000
Reel of 2000
Reel of 2000
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
LVT16245B
VD245B
VFBGA – GQL
Reel of 1000
Tube
VD245B
VFBGA – ZQL (Pb-free)
CFP – WD
–55°C to 125°C
SNJ54LVT16245BWD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2000–2006, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The 'LVT16245B devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between two data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ
.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
(1) NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
2DIR
2OE
(1) NC – No internal connection
2
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
FUNCTION TABLE(1)
(each 8-bit section)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
2OE
2B1
36
47
1A1
2A1
2
1B1
To Seven Other Channels
To Seven Other Channels
3
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
Absolute Maximum Ratings(1)
over recommended operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
4.6
7
V
V
V
V
VO
VO
7
–0.5 VCC + 0.5
SN54LVT16245B
96
128
48
IO
Current into any output in the low state
Current into any output in the high state(3)
mA
mA
SN74LVT16245B
SN54LVT16245B
SN74LVT16245B
VI < 0
IO
64
IIK
Input clamp current
Output clamp current
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DGV package
DL package
58
θJA
Package thermal impedance(4)
63 °C/W
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
4
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
Recommended Operating Conditions(1)
SN54LVT16245B(2) SN74LVT16245B
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
VIL
Supply voltage
3.6
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–24
48
0.8
5.5
–32
64
V
VI
V
IOH
IOL
High-level output current
Low-level output current
Input transition rise or fall rate
mA
mA
ns/V
µs/V
°C
∆t/∆v
Outputs enabled
10
10
∆t/∆VCC Power-up ramp rate
TA Operating free-air temperature
200
–55
200
–40
125
85
(1) All unused or undriven (floating) inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCC or GND) to ensure
proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
(2) Product preview
5
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVT16245B(1)
MIN TYP(2)
SN74LVT16245B
MIN TYP(2) MAX
PARAMETER
VIK
TEST CONDITIONS
UNIT
MAX
VCC = 2.7 V,
II = –18 mA
–1.2
–1.2
V
VCC = 2.7 to 3.6 V,
VCC = 2.7 V,
IOH = –100 µA
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
VCC – 0.2
VCC – 0.2
2.4
2
2.4
VOH
V
V
VCC = 3 V
2
0.2
0.5
0.2
0.5
0.4
0.5
VCC = 2.7 V
0.4
VOL
0.5
VCC = 3 V
0.55
0.55
±1
VCC = 3.6 V,
±1
10
20
5
Control
inputs
VCC = 0 or 3.6 V,
10
II
VI = 5.5 V
20
µA
A or B
port(3)
VCC = 3.6 V
VCC = 0,
VI = VCC
1
VI = 0
–5
–5
Ioff
VI or VO = 0 to 4.5 V
±100
µA
µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
±100(4)
±100(4)
±100
±100
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
IOZPD
µA
mA
mA
Outputs high
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
0.19
5
0.19
5
ICC
Outputs low
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(5)
∆ICC
0.2
0.2
Ci
VI = 3 V or 0
VO = 3 V or 0
4
4
pF
pF
Cio
10
10
(1) Product preview
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
(3) Unused pins at VCC or GND.
(4) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(5) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
6
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVT16245B(1)
SN74LVT16245B
VCC = 3.3 V
± 0.3 V
MAX MIN TYP(2) MAX MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
PARAMETER
VCC = 2.7 V
VCC = 2.7 V UNIT
± 0.3 V
MIN
0.5
0.5
0.5
0.5
1
MAX
4.5
4.4
6.5
5.4
6.8
6.2
MIN
tPLH
tPHL
4.6
3.9
6.6
6.2
7
1.5
1.3
1.5
1.6
2.3
2.2
2.3
2.1
2.8
2.9
3.7
3.5
3.3
3.3
4.5
4.6
5.1
5.1
0.5
0.5
3.7
3.5
5.3
5.2
5.5
5.4
A or B
OE
B or A
A or B
A or B
ns
ns
ns
ns
tPZH
tPZL
tPHZ
OE
tPLZ
1
6.3
tsk(LH)
tsk(HL)
(1) Product preview
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
7
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SN54LVT16245B, SN74LVT16245B
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS715E–FEBRUARY 2000–REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
GND
PLH PHL
t
t
/t
PLZ PZL
C = 50 pF
L
/t
PHZ PZH
500 Ω
(see Note A)
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
0 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74LVT16245BDGGRE4
74LVT16245BDGGRG4
74LVT16245BDGVRE4
74LVT16245BDGVRG4
74LVT16245BDLRG4
SN74LVT16245BDGGR
SN74LVT16245BDGVR
SN74LVT16245BDL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
SSOP
DGG
DGV
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT16245BDLG4
SN74LVT16245BDLR
SN74LVT16245BGQLR
SSOP
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SN74LVT16245BGRDR
SN74LVT16245BZQLR
SN74LVT16245BZRDR
ACTIVE
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
ZQL
ZRD
54
56
54
1000
TBD
SNPB
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
(mm)
24
SN74LVT16245BDGGR
SN74LVT16245BDGVR
SN74LVT16245BDLR
SN74LVT16245BGQLR
SN74LVT16245BGRDR
SN74LVT16245BZQLR
SN74LVT16245BZRDR
DGG
DGV
DL
48
48
48
56
54
56
54
SITE 41
SITE 41
SITE 41
SITE 32
SITE 32
SITE 32
SITE 32
8.6
6.8
15.8
10.1
16.2
7.3
1.8
1.6
12
12
16
8
24
24
32
16
16
16
16
Q1
Q1
Q1
Q1
Q1
Q1
Q1
24
32
11.35
4.8
3.1
GQL
GRD
ZQL
ZRD
16
1.45
1.55
1.45
1.55
16
5.8
8.3
8
16
4.8
7.3
8
16
5.8
8.3
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LVT16245BDGGR
SN74LVT16245BDGVR
SN74LVT16245BDLR
SN74LVT16245BGQLR
SN74LVT16245BGRDR
SN74LVT16245BZQLR
SN74LVT16245BZRDR
DGG
DGV
DL
48
48
48
56
54
56
54
SITE 41
SITE 41
SITE 41
SITE 32
SITE 32
SITE 32
SITE 32
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
49.0
33.0
33.0
33.0
33.0
GQL
GRD
ZQL
ZRD
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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