SN74LVT2952PWLE_技术文档

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SCBS152E − MAY 1992 − REVISED JULY 1995

SN54LVT2952 . . . JT PACKAGE

SN74LVT2952 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

D State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

B8

B7

V

CC

A8

1

24

23

D Support Mixed-Mode Signal Operation (5-V

2

Input and Output Voltages With 3.3-V V

)

CC

B6

B5

B4

3

22 A7

21 A6

20 A5

D Support Unregulated Battery Operation

4

Down to 2.7 V

5

6

19

18

17

16

15

14

13

B3

B2

B1

A4

A3

A2

A1

OEBA

CLKBA

CLKENBA

D Typical V

D ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(Output Ground Bounce)

OLP

7

< 0.8 V at V

= 3.3 V, T = 25°C

CC

A

8

9

OEAB

CLKAB

CLKENAB

GND

10

11

12

(C = 200 pF, R = 0)

D Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

SN54LVT2952 . . . FK PACKAGE

(TOP VIEW)

D Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

D Support Live Insertion

D Package Options Include Plastic

4

3

2

1

28 27 26

25

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK), and

Ceramic (JT) DIPs

5

B5

B4

B3

NC

B2

A6

6

24 A5

23 A4

22

21

20

19

7

8

NC

A3

A2

A1

9

description

10

11

B1

OEAB

These octal bus transceivers and registers are

designed specifically for low-voltage (3.3-V) V

12 13 14 15 16 17 18

CC

operation, but with the capability to provide a TTL

interface to a 5-V system environment.

The ’LVT2952 consist of two 8-bit back-to-back

registers that store data flowing in both directions

between two bidirectional buses. Data on the A or

B bus is stored in the registers on the low-to-high

NC − No internal connection

transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input

is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

The SN74LVT2952 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LVT2952 is characterized for operation over the full military temperature range of −55°C to 125°C.

The SN74LVT2952 is characterized for operation from −40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1995, Texas Instruments Incorporated

ꢒ ꢁ ꢄꢔꢀꢀ ꢐ ꢆꢙ ꢔꢓꢘ ꢕꢀ ꢔ ꢁ ꢐꢆꢔꢖ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢚꢓ ꢐ ꢖ ꢒ ꢑꢆ ꢕꢐ ꢁ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢂꢇ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢂ ꢇ

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ꢘꢕ ꢆ ꢙ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢐꢒꢆ ꢚꢒ ꢆꢀ

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SCBS152E − MAY 1992 − REVISED JULY 1995

†

FUNCTION TABLE

INPUTS

OUTPUT

B

CLKENAB CLKAB OEAB

A

‡

H

X

L

X

L

H

X

L

B

0

H or L

B

↑

X

L

H

Z

L

H

X

†

A-to-B data flow is shown; B-to-A data flow is similar

but uses CLKENBA, CLKBA, and OEBA.

Level of B before the indicated steady-state input

conditions were established

‡

§

logic symbol

15

EN3

13

OEBA

G1

CLKENBA

CLKBA

14

1 C5

9

EN4

11

OEAB

CLKENAB

CLKAB

G2

10

2 C6

8

16

B1

3

1

5D

A1

6D

4

17

18

19

20

21

22

23

7

6

5

4

3

2

1

A2

A3

A4

A5

A6

A7

A8

B2

B3

B4

B5

B6

B7

B8

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, and PW packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCBS152E − MAY 1992 − REVISED JULY 1995

logic diagram (positive logic)

11

CLKENAB

10

CLKAB

9

OEAB

13

CLKENBA

14

CLKBA

15

OEBA

C1

1D

16

8

B1

A1

C1

1D

To Seven Other Channels

Pin numbers shown are for the DB, DW, JT, and PW packages.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢂꢇ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢂ ꢇ

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ꢘꢕ ꢆ ꢙ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢐꢒꢆ ꢚꢒ ꢆꢀ

SCBS152E − MAY 1992 − REVISED JULY 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . −0.5 V to 7 V

O

Current into any output in the low state, I : SN54LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN74LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

SN74LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W

A

DW package . . . . . . . . . . . . . . . . . . . 1.7 W

PW package . . . . . . . . . . . . . . . . . . . 0.7 W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology

Data Book, literature number SCBD002B.

recommended operating conditions (see Note 4)

SN54LVT2952

SN74LVT2952

UNIT

MIN

2.7

2

MAX

MIN

2.7

2

MAX

V

Supply voltage

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−24

48

0.8

5.5

−32

64

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

mA

ns/V

°C

OH

OL

∆t/∆v

Outputs enabled

10

T

A

−55

125

−40

85

NOTE 4: Unused control inputs must be held high or low to prevent them from floating.

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4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢋꢌ ꢋ ꢍꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢏꢒꢀ ꢆ ꢓꢎꢁꢀ ꢑꢔꢕ ꢅꢔꢓꢀ ꢎꢁꢖ ꢓꢔꢗ ꢕ ꢀ ꢆꢔ ꢓ

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ꢘ ꢕꢆ ꢙ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢐ ꢒꢆ ꢚ ꢒꢆ

SCBS152E − MAY 1992 − REVISED JULY 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVT2952

SN74LVT2952

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 2.7 V,

I = −18 mA

−1.2

V

IK

CC

I

‡

= MIN to MAX ,

I

= −100 µA

= − 8 mA

= − 24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

V

−0.2

V

−0.2

OH

OL

CC

2.4

CC

2.4

= 2.7 V,

V

OH

V

2

V

= 3 V

CC

2

0.2

0.5

0.2

0.5

0.4

0.5

V

= 2.7 V

0.4

V

OL

0.5

V

CC

= 3 V

0.55

1

V

= 3.6 V,

V = V

I CC

or GND

1

10

CC

Control inputs

‡

= 0 or MAX ,

V = 5.5 V

I

10

CC

V = 5.5 V

I

20

I

µA

§

V = V

5

V

CC

= 3.6 V

A or B ports

I

CC

V = 0

−10

100

I

V

= 0,

V or V = 0 to 4.5 V

I

µA

off

CC

O

V = 0.8 V

75

I

= 3 V

A or B ports

I(hold)

CC

V = 2 V

I

−75

I

V

= 3.6 V,

V

= 3 V

1

−1

1

−1

µA

OZH

CC

O

V

= 0.5 V

OZL

CC

Outputs high

Outputs low

Outputs disabled

− 0.6 V,

0.13

8.8

0.19

12

0.13

8.8

0.19

12

V

= 3.6 V,

I

= 0,

CC

O

I

mA

CC

V = V

I

or GND

CC

0.13

0.19

0.13

0.19

V

= 3 V to 3.6 V,

One input at V

CC

or GND

CC

Other inputs at V

¶

∆I

CC

0.2

mA

CC

C

V = 3 V or 0

4.5

pF

i

I

V

O

= 3 V or 0

11.5

io

†

‡

§

¶

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

Unused terminals at V or GND

CC

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

or GND.

CC

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ꢡ ꢜꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢌ

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5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢂꢇ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢂ ꢇ

ꢋꢌ ꢋꢍꢅ ꢎ ꢏ ꢆ ꢐꢑ ꢆꢎꢄ ꢏꢒ ꢀ ꢆꢓ ꢎꢁ ꢀꢑ ꢔꢕ ꢅ ꢔꢓ ꢀ ꢎꢁꢖ ꢓꢔ ꢗꢕ ꢀꢆ ꢔꢓꢀ

ꢘꢕ ꢆ ꢙ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢐꢒꢆ ꢚꢒ ꢆꢀ

SCBS152E − MAY 1992 − REVISED JULY 1995

timing requirement over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

SN54LVT2952

= 3.3 V

SN74LVT2952

= 3.3 V

V

CC

0.3 V

CC

0.3 V

V

= 2.7 V

MAX

V

= 2.7 V

UNIT

CC

MIN

MAX

MIN

MAX

MIN

MAX

f

t

Clock frequency

Pulse duration

150

MHz

ns

clock

CLK high

CLK low

Data high

Data low

Data high

Data low

3.3

2.5

0.9

2.4

1.5

2.5

3.3

2.8

3

w

2.6

0.9

2.5

1.5

2.6

2.9

3.1

0.8

2.7

0.7

2.6

Setup time, A or B before CLK↑

Setup time, CE before CLK↑

t

ns

su

h

0.8

2.7

0.7

2.6

Hold time, A or B after CLK↑

Hold time, CE after CLK↑

t

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

SN54LVT2952

= 3.3 V

SN74LVT2952

= 3.3 V

V

FROM

(INPUT)

TO

(OUTPUT)

CC

0.3 V

CC

0.3 V

V

CC

= 2.7 V

MAX

V

= 2.7 V

MAX

PARAMETER

UNIT

CC

†

MIN

MAX

MIN

MIN TYP

MAX

MIN

150

2.7

2.6

2.9

2.7

1.8

f

t

150

MHz

ns

max

PLH

PHL

PZH

PZL

PHZ

PLZ

1.3

1.8

1

6.4

6.1

6.3

6.6

7

2.7

2.6

2.9

2.7

1.7

7.4

7

1.3

1.8

1

3.6

3.7

3.2

4.1

3.3

6.1

6

7.1

6.9

6.7

8

CLKBA or

CLKAB

A or B

7.3

8.2

7.6

6

5.6

6.5

6.3

5.1

OEBA or

OEAB

ns

1.1

1

1.2

1

6.9

5.3

OEBA or

OEAB

1.6

5.8

1.6

†

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

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ꢛ

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ꢩ

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ꢡ ꢜ ꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢌ

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6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢂ

ꢇ

ꢉ

ꢀ

ꢁ

ꢊ

ꢃ

ꢋꢌ ꢋ ꢍꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢏꢒꢀ ꢆ ꢓꢎꢁꢀ ꢑꢔꢕ ꢅꢔꢓꢀ ꢎꢁꢖ ꢓꢔꢗ ꢕ ꢀ ꢆꢔ ꢓ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢂ

ꢇ

ꢀ

ꢘ ꢕꢆ ꢙ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢐ ꢒꢆ ꢚ ꢒꢆ

SCBS152E − MAY 1992 − REVISED JULY 1995

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

S1

t

/t

PLH PHL

Open

6 V

500 Ω

Open

GND

From Output

Under Test

t

/t

PLZ PZL

t

/t

PHZ PZH

GND

C

= 50 pF

L

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT FOR OUTPUTS

1.5 V

Timing Input

Data Input

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

t

Input

1.5 V

t

PZL

t

PHL

PLH

PLZ

1.5 V

Output

Waveform 1

S1 at 6 V

V

3 V

OH

1.5 V

Output

V

+ 0.3 V

− 0.3 V

OL

V

OL

(see Note B)

t

PHZ

t

PLH

t

PZH

PHL

Output

Waveform 2

S1 at GND

V

OH

V

OH

1.5 V

Output

(see Note B)

[ 0 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	SN74LVT2952PWLE
厂家：	TEXAS INSTRUMENTS
描述：	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 输出元件
文件：	总11页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LVT2952PWLE [TI]

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