SN74LVTH162240-EP [TI]
3.3-V ABT 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74LVTH162240-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢊꢃꢋ ꢌꢍ ꢎ
ꢏ ꢐꢏ ꢌꢅ ꢑꢒꢆ ꢈ ꢉ ꢌꢒꢓ ꢆ ꢒꢔꢕ ꢕ ꢍ ꢖꢗ ꢘꢖ ꢓ ꢅꢍ ꢖ
ꢙ ꢓꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚ ꢔꢆ ꢎ ꢔꢆꢀ
SCBS780 − NOVEMBER 2003
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Enhanced Diminishing Manufacturing
Sources (DMS) Support
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Enhanced Product-Change Notification
†
Qualification Pedigree
Member of the Texas Instruments
Widebus Family
DGG PACKAGE
(TOP VIEW)
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
2
3
4
D
D
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
5
6
7
V
V
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
CC
CC
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
V
)
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
D
D
D
Supports Unregulated Battery Operation
Down To 2.7 V
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CC
CC
4Y1
4Y2
GND
4Y3
4Y4
4A1
4A2
GND
4A3
4A4
3OE
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
4OE
description/ordering information
The SN74LVTH162240 is a 16-bit buffer/driver designed specifically for low-voltage (3.3-V) V
operation and
CC
to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented
receivers and transmitters. It has the capability to provide a TTL interface to a 5-V system environment.
This device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting outputs
and symmetrical active-low output-enable (OE) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢋ ꢌꢍ ꢎ
ꢏꢐ ꢏꢌꢅ ꢑ ꢒ ꢆ ꢈ ꢉꢌ ꢒꢓ ꢆ ꢒꢔ ꢕꢕ ꢍꢖ ꢗꢘ ꢖꢓ ꢅ ꢍꢖ
ꢙꢓ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚꢔꢆ ꢎ ꢔꢆꢀ
SCBS780 − NOVEMBER 2003
description/ordering information (continued)
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
TSSOP − DGG
A
−40°C to 85°C
Tape and reel CLVTH162240IDGGREP
LH162240EP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢊꢃꢋ ꢌꢍ ꢎ
ꢏ ꢐꢏ ꢌꢅ ꢑꢒꢆ ꢈ ꢉ ꢌꢒꢓ ꢆ ꢒꢔꢕ ꢕ ꢍꢖ ꢗꢘ ꢖ ꢓꢅ ꢍ ꢖ
ꢙ ꢓꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚ ꢔꢆ ꢎꢔ ꢆꢀ
SCBS780 − NOVEMBER 2003
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
46
35
33
32
14
16
17
1A2
3A2
3A3
3A4
44
1A3
43
1A4
48
24
30
2OE
4OE
4A1
41
8
9
19
20
22
23
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
40
29
27
26
2A2
4A2
4A3
4A4
38
11
12
2A3
37
2A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢋ ꢌꢍ ꢎ
ꢏꢐ ꢏꢌꢅ ꢑ ꢒ ꢆ ꢈ ꢉꢌ ꢒꢓ ꢆ ꢒꢔ ꢕꢕ ꢍꢖ ꢗꢘ ꢖꢓ ꢅ ꢍꢖ
ꢙꢓ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚꢔꢆ ꢎ ꢔꢆꢀ
SCBS780 − NOVEMBER 2003
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−12
12
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
I = −18 mA
−1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= −12 mA
= 12 mA
2
OH
OL
OH
= 3 V,
0.8
10
1
OL
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
V = V
or GND
I
CC
I
I
I
µA
µA
µA
I
V = V
1
I
CC
V
= 3.6 V
= 0,
Data inputs
CC
CC
V = 0
I
−5
100
V
V or V = 0 to 4.5 V
off
I
O
V = 0.8 V
I
75
V
V
= 3 V
CC
V = 2 V
I
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
CC
I
I
I
V
CC
V
CC
V
CC
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
−5
µA
µA
µA
OZH
O
= 0.5 V
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care
O
100
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care
O
100
0.19
5
µA
I
CC
OZPD
Outputs high
Outputs low
I
V
= 3.6 V, I = 0, V = V
CC
or GND
mA
CC
§
CC
CC
O
I
Outputs disabled
0.19
0.2
V
= 3 V to 3.6 V, One input at V
CC
− 0.6 V, Other inputs at V
or GND
mA
pF
pF
∆I
CC
CC
C
C
V = 3 V or 0
I
4
9
i
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢊꢃꢋ ꢌꢍ ꢎ
ꢏ ꢐꢏ ꢌꢅ ꢑꢒꢆ ꢈ ꢉ ꢌꢒꢓ ꢆ ꢒꢔꢕ ꢕ ꢍꢖ ꢗꢘ ꢖ ꢓꢅ ꢍ ꢖ
ꢙ ꢓꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚ ꢔꢆ ꢎꢔ ꢆꢀ
SCBS780 − NOVEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
4
MIN
MAX
4.6
4.6
5.7
4.9
5.2
4.5
0.5
t
t
t
t
t
t
t
1
1
1
1
2
2
2.5
2.9
2.8
2.8
3.5
3.4
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
ns
ns
4
4.8
4.7
4.7
4.5
0.5
OE
OE
ns
ns
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢋ ꢌꢍ ꢎ
ꢏꢐ ꢏꢌꢅ ꢑ ꢒ ꢆ ꢈ ꢉꢌ ꢒꢓ ꢆ ꢒꢔ ꢕꢕ ꢍꢖ ꢗꢘ ꢖꢓ ꢅ ꢍꢖ
ꢙꢓ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢚꢔꢆ ꢎ ꢔꢆꢀ
SCBS780 − NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
S1
Open
TEST
S1
500 Ω
From Output
Under Test
t
/t
Open
6 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
L
t
/t
GND
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
V
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
3 V
OH
1.5 V
1.5 V
1.5 V
t
Output
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
− 0.3 V
1.5 V
OH
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVTH162240IDGGREP
V62/04707-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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OTHER QUALIFIED VERSIONS OF SN74LVTH162240-EP :
Catalog: SN74LVTH162240
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CLVTH162240IDGGREP TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CLVTH162240IDGGREP
2000
Pack Materials-Page 2
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