SN74LVTH16543-EP [TI]

3.3-V ABT 16-BIT REGISTERED TRANSCEIVER 3-STATE OUTPUTS; 3.3 -V ABT 16位寄存收发器3态输出
SN74LVTH16543-EP
型号: SN74LVTH16543-EP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3.3-V ABT 16-BIT REGISTERED TRANSCEIVER 3-STATE OUTPUTS
3.3 -V ABT 16位寄存收发器3态输出

输出元件
文件: 总12页 (文件大小:304K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OEAB  
1LEAB  
1CEAB  
GND  
1OEBA  
1LEBA  
1CEBA  
GND  
2
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
3
4
Enhanced Product-Change Notification  
5
1A1  
1A2  
1B1  
1B2  
(1)  
Qualification Pedigree  
6
Member of the Texas Instruments Widebus™  
Family  
7
V
CC  
V
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
9
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V Operation  
and Low Static-Power Dissipation  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Supports Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V VCC  
)
Supports Unregulated Battery Operation  
Down to 2.7 V  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
V
CC  
V
CC  
2A7  
2A8  
GND  
2CEAB  
2LEAB  
2OEAB  
2B7  
2B8  
GND  
2CEBA  
2LEBA  
2OEBA  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVTH16543 is a 16-bit registered transceiver designed for low-voltage (3.3-V) VCC operation, but with  
the capability to provide a TTL interface to a 5-V system environment. This device can be used as two 8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or  
OEBA) inputs are provided for each register to permit independent control in either direction of data flow.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
DESCRIPTION/ORDERING INFORMATION (CONTINUED)  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data  
present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and  
OEBA inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
Tape and reel  
Tape and reel  
ORDERABLE PART NUMBER  
CLVTH16543IDGGREP  
CLVTH16543MDLREP  
TOP-SIDE MARKING  
LH16543EP  
LH16543MEP  
–40°C to 85°C  
–55°C to 125°C  
TSSOP – DGG  
SSOP – DL  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE(1)  
(each 8-bit section)  
INPUTS  
OUTPUT  
B
CEAB  
LEAB  
OEAB  
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
(2)  
B0  
L
L
L
L
H
H
(1) A-to-B data flow is shown; B-to-A flow control is the same, except  
that it uses CEBA, LEBA, and OEBA.  
(2) Output level before the indicated steady-state input conditions were  
established  
2
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SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
LOGIC DIAGRAM (POSITIVE LOGIC)  
56  
54  
1OEBA  
1CEBA  
55  
1
1LEBA  
1OEAB  
3
2
1CEAB  
1LEAB  
C1  
1D  
5
1A1  
52  
1B1  
C1  
1D  
To Seven Other Channels  
29  
31  
2OEBA  
2CEBA  
30  
28  
2LEBA  
2OEAB  
26  
27  
2CEAB  
2LEAB  
C1  
1D  
15  
2A1  
42  
2B1  
C1  
1D  
To Seven Other Channels  
3
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SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
MAX  
4.6  
UNIT  
VCC Supply voltage range  
V
VI  
Input voltage range(2)  
7
7
V
VO  
VO  
IO  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Voltage range applied to any output in the high state(2)  
Current into any output in the low state  
V
VCC + 0.5  
128  
V
mA  
mA  
mA  
mA  
IO  
Current into any output in the high state(3)  
64  
IIK  
IOK  
Input clamp current  
Output clamp current  
VI < 0  
–50  
VO < 0  
–50  
DGG package  
DL package  
81  
θJA  
Package thermal impedance(4)  
Storage temperature range(5)  
°C/W  
°C  
73.5  
150  
Tstg  
–65  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
(3) This current flows only when the output is in the high state and VO > VCC  
.
(4) The package thermal impedance is calculated in accordance with JESD 51.  
(5) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of  
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.  
Recommended Operating Conditions(1)  
MIN  
2.7  
2
MAX UNIT  
VCC  
VIH  
Supply voltage  
3.6  
V
V
High-level input voltage  
Low-level input voltage  
Input voltage  
VIL  
0.8  
5.5  
–32  
64  
V
VI  
V
IOH  
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Power-up ramp rate  
mA  
mA  
IOL  
t/v  
t/VCC  
Outputs enabled  
10 ns/V  
200  
–40  
–55  
µs/V  
I temp  
85  
TA  
Operating free-air temperature  
°C  
M temp  
125  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
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SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
II = –18 mA  
MIN TYP(1)  
MAX  
UNIT  
VIK  
VCC = 2.7 V,  
–1.2  
V
VCC = 2.7 V to 3.6 V,  
VCC = 2.7 V,  
IOH = –100 µA  
IOH = –8 mA  
VCC – 0.2  
VOH  
2.4  
2
V
V
VCC = 3 V,  
IOH = –32 mA  
IOL = 100 µA  
0.2  
0.5  
0.4  
0.5  
0.55  
±1  
VCC = 2.7 V  
IOL = 24 mA  
VOL  
IOL = 16 mA  
VCC = 3 V  
IOL = 32 mA  
IOL = 64 mA (I temp)  
VI = VCC or GND  
VI = 5.5 V  
VCC = 3.6 V,  
Control  
inputs  
VCC = 0 or 3.6 V,  
10  
VI = 5.5 V (I temp)  
VI = 5.5 V (M temp)  
VI = VCC  
20  
II  
µA  
100  
1
A or B port(2) VCC = 3.6 V  
VI = 0  
–5  
VI or VO = 0 to 4.5 V (I temp)  
VI or VO = 0 to 4.5 V (M temp)  
VI = 0.8 V  
±100  
±550  
Ioff  
VCC = 0  
µA  
µA  
75  
VCC = 3 V  
II(hold) A or B port  
VI = 2 V  
–75  
VCC = 3.6 V,(3)  
VI = 0 to 3.6 V  
±500  
±100  
±100  
0.19  
5
IOZPU  
IOZPD  
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care  
VCC = 1.5 to 0 V, VO = 0.5 V to 3 V, OE = don't care  
Outputs high  
µA  
µA  
(4)  
ICC  
VCC = 3.6 V, IO = 0, VI = VCC or GND  
Outputs low  
mA  
Outputs disabled  
0.19  
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,  
Other inputs at VCC or GND  
ICC  
0.2  
mA  
Ci  
VI = 3 V or 0  
VO = 3 V or 0  
4
pF  
pF  
Cio  
10  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) Unused pins at VCC or GND  
(3) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.  
5
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SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
Timing Requirements  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
M TEMP  
I TEMP  
VCC = 3.3 V  
± 0.3 V  
MIN MAX MIN MAX  
VCC = 3.3 V  
± 0.3 V  
VCC = 2.7 V  
VCC = 2.7 V UNIT  
MIN MAX MIN MAX  
tw Pulse duration, LEAB or LEBA low  
A or B before LEABOR LEBA↑  
3.3  
0.7  
1.2  
0.5  
1.1  
1.5  
1.2  
1.7  
1.6  
3.3  
0.9  
1.9  
0.8  
1.9  
1.0  
1.5  
1.1  
1.9  
3.3  
0.5  
0.8  
0
3.3  
0.5  
1.3  
0
ns  
ns  
Data high  
Data low  
Data high  
Data low  
Data high  
Data low  
Data high  
Data low  
tsu Setup time  
A or B before CEABor CEBA↑  
A or B before LEABOR LEBA↑  
A or B before CEABor CEBA↑  
0.6  
1.5  
1.2  
1.7  
1.6  
1.1  
0.7  
1.3  
0.9  
1.8  
th Hold time  
ns  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)  
M TEMP  
VCC = 3.3 V  
± 0.3 V  
MIN  
I TEMP  
VCC = 3.3 V  
± 0.3 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
VCC = 2.7 V  
VCC = 2.7 V  
UNIT  
MAX  
4.7  
5.4  
7.3  
6.9  
6.5  
6.7  
5.7  
5.1  
6.5  
6.4  
5.3  
5.1  
MIN  
MAX  
MIN TYP(1)  
MAX  
3.2  
3.2  
3.9  
3.9  
4.3  
4.3  
4.7  
4.4  
4.5  
4.5  
4.9  
4.7  
MIN  
MAX  
tPLH  
tPHL  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
tPZH  
tPZL  
tPHZ  
tPLZ  
1.2  
1.2  
1.3  
1.3  
1.3  
1.3  
2
6.5  
6.5  
7.8  
7.8  
7.4  
7.4  
7.2  
6.9  
7.6  
7.6  
7.4  
6.9  
1.2  
1.2  
1.3  
1.3  
1.3  
1.3  
2
2.3  
2.1  
2.5  
2.3  
2.8  
2.8  
3.5  
3.3  
3
3.7  
3.7  
4.9  
4.9  
5.4  
5.4  
5.2  
4.5  
5.6  
5.6  
5.4  
4.9  
A or B  
LE  
B or A  
A or B  
A or B  
A or B  
A or B  
A or B  
ns  
ns  
ns  
ns  
ns  
ns  
OE  
OE  
2
2
1.3  
1.3  
2
1.3  
1.3  
2
CE  
3
3.6  
3.5  
CE  
2
2
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
6
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SN74LVTH16543-EP  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVER  
3-STATE OUTPUTS  
www.ti.com  
SCBS785BNOVEMBER 2003REVISED JUNE 2006  
PARAMETER MEASUREMENT INFORMATION  
6 V  
Open  
GND  
TEST  
/t  
S1  
S1  
500 Ω  
From Output  
Under Test  
t
Open  
6 V  
PLH PHL  
t
/t  
PLZ PZL  
C = 50 pF  
(see Note A)  
t
/t  
GND  
L
PHZ PZH  
500 Ω  
2.7 V  
0 V  
Timing Input  
Data Input  
1.5 V  
LOAD CIRCUIT  
t
w
t
t
h
su  
2.7 V  
2.7 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
2.7 V  
0 V  
2.7 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
t
t
PHL  
t
t
PLH  
PZL  
PLZ  
Output  
Waveform 1  
S1 at 6 V  
V
V
3 V  
OH  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
t
Output  
V
+ 0.3 V  
OL  
V
OL  
(see Note B)  
OL  
t
t
PZH  
PHZ  
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
V
V
OH  
OH  
V
− 0.3 V  
OH  
1.5 V  
1.5 V  
Output  
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
7
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PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
CLVTH16543IDGGREP  
CLVTH16543MDLREP  
V62/04715-01XE  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
DGG  
56  
56  
56  
56  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
TSSOP  
SSOP  
DL  
DGG  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
V62/04715-02YE  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN74LVTH16543-EP :  
Catalog: SN74LVTH16543  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Aug-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
CLVTH16543IDGGREP TSSOP  
CLVTH16543MDLREP SSOP  
DGG  
DL  
56  
56  
2000  
1000  
330.0  
330.0  
24.4  
32.4  
8.6  
15.6  
1.8  
3.1  
12.0  
16.0  
24.0  
32.0  
Q1  
Q1  
11.35  
18.67  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Aug-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CLVTH16543IDGGREP  
CLVTH16543MDLREP  
TSSOP  
SSOP  
DGG  
DL  
56  
56  
2000  
1000  
346.0  
346.0  
346.0  
346.0  
41.0  
49.0  
Pack Materials-Page 2  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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