SN74LXC1T14QDCKRQ1 [TI]
汽车类单通道定向反相 1.1V 至 5.5V 电压电平转换器 | DCK | 5 | -40 to 125;
| 型号： | SN74LXC1T14QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类单通道定向反相 1.1V 至 5.5V 电压电平转换器 | DCK | 5 | -40 to 125 转换器 电平转换器 |
| 文件： | 总24页 (文件大小：1340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
SN74LXC1T14-Q1 具有施密特触发输入的
汽车类双电源反相转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
• 完全可配置的双电源轨设计可允许各个端口在1.1V
至5.5V 范围内运行
• 稳健、无干扰供电时序
• 在3.3V 至5.0V 范围内，支持高达420Mbps 的速
率
SN74LXC1T14-Q1 是一款具有施密特触发输入的一位
双电源反相电压电平转换器件。输入引脚 A 以 VCCI 逻
辑电平为基准，输出引脚 Y 以 VCCO 逻辑电平为基
准。输入引脚 A 能够接受 1.1V 至 5.5V 的电压，并且
可以直接连接到VCCI 或GND。请参阅器件功能模式，
简要了解逻辑的运行方式。
• 施密特触发输入可实现慢速或高噪声输入
• 带有集成动态下拉电阻器的输入有助于减少外部元
件数量
• 高驱动强度（在5V 时最高达32 mA）
• 低功耗
该器件可确保低功耗，并且完全符合使用 Ioff 的部分断
电应用的规范要求。当器件断电时，Ioff 电路将会禁用
输出。这会抑制电流反流到器件中，从而防止损坏器
件。
封装信息(1)
– 最大值3 µA (25°C)
– 最大值6 µA（–40°C 至125°C）
• VCC 隔离和VCC 断开(Ioff-float) 特性
封装尺寸（标称值）
器件型号
封装
SN74LXC1T14-Q1 SC70 (5) (DCK)
2.00mm × 1.25mm
– 如果任何一个VCC 电源电压< 100 mV 或已断
开，则所有I/O 都被下拉，然后成为高阻抗状态
• 过压容差输入支持最高5.5V 的电压，而与电源电压
无关。
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VCCI
VCCO
• Ioff 支持局部断电模式运行
• 工作温度范围为–40°C 至+125°C
• 闩锁性能超过100 mA，符合JESD 78 II 类规范的
要求
Y
A
• ESD 保护性能超过JESD 22 规范要求
– 4000V 人体放电模型
– 1000V 充电器件模型
GND
2 应用
简图
• 消除缓慢或嘈杂输入信号
• 驱动指示LED 或蜂鸣器
• 机械开关去抖
• 通用I/O (GPIO) 电平转换
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES950
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................15
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................17
11 Layout...........................................................................17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Device Support....................................................... 18
12.2 Documentation Support.......................................... 18
12.3 接收文档更新通知................................................... 18
12.4 支持资源..................................................................18
12.5 Trademarks.............................................................18
12.6 Electrostatic Discharge Caution..............................18
12.7 术语表..................................................................... 18
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics: Tpd....................................8
6.7 Switching Characteristics: TMAX .................................9
6.8 Typical Characteristics..............................................10
7 Parameter Measurement Information.......................... 11
7.1 Load Circuit and Voltage Waveforms........................11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
August 2022
*
Initial Release
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
5 Pin Configuration and Functions
VCCI
A
1
2
3
5
4
VCCO
Y
GND
图5-1. DCK Package, 5-Pin SC70 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DCK
VCCI
A
1
2
3
4
Input supply voltage. 1.1 V ≤VCCI ≤5.5 V.
—
I
Input A. Referenced to VCCI
Ground.
GND
Y
—
O
Output Y. Referenced to VCCO.
VCCO
5
Output supply voltage. 1.1 V ≤VCCO ≤5.5 V.
—
(1) I = input, O = output
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX UNIT
VCCI
VCCO
VI
Input supply voltage A
6.5
6.5
V
V
Output supply voltage Y
Input Voltage(2)
6.5
V
VO
VO
IIK
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2) (3)
Input clamp current
6.5
V
VCCB + 0.5
V
VI < 0
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
50 mA
200 mA
150 °C
150 °C
–50
Continuous current through VCC or GND
Junction Temperature
–200
Tj
Tstg
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
1.1
MAX UNIT
VCCI
Input supply voltage
5.5
5.5
V
V
VCCO
Output Supply voltage
1.1
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
–0.1
–4
–8
–12
–24
–32
0.1
IOH
High-level output current
mA
VCCO = 4.5 V
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
4
8
IOL
Low-level output current
Input voltage (3)
mA
12
24
VCCO = 4.5 V
32
VI
0
0
5.5
V
V
Active State
Tri-State
Operating free-air temperature
VCCO
5.5
VO
TA
Output voltage
0
125 °C
–40
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) Input of this device has a weak pulldown to ensure the line is not floating when undefined external to the device. The input leakage
from these weak pulldowns is defined by the II specification indicated under Electrical Characteristics.
6.4 Thermal Information
SN74LXC1T14
THERMAL METRIC(1)
DCK (SC70)
5 PINS
222.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
132.9
109.5
YJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
48.4
YJB
108.9
RθJC(bottom)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
TEST
CONDITIONS
PARAMETER
VCCI
VCCO
UNIT
–40°C to 85°C
–40°C to 125°C
1.1 V
1.1 V
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.2
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.48 0.17
0.59 0.28
0.69 0.35
0.97 0.56
1.5 0.89
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.48
0.59
0.69
0.97
1.5
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Positive-
going input-
threshold
voltage
Data Input
(Referenced to
VT+
V
VCCI
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Negative-
going input-
threshold
voltage
Data Input
(Referenced to
VT-
V
VCCI
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
1.97 1.51
2.4 1.88
1.97
2.4
0.4
0.2
0.4
0.25
0.3
0.5 0.25
0.5
Input-
Data Input
(A)
(Referenced to
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
VCCO
0.55
0.65
0.72
0.93
1.06
threshold
hysteresis
(VT+ –VT-)
0.38
0.46
0.58
0.69
VCCO
V
ΔVT
VCCI
)
4.5 V
5.5 V
4.5 V
5.5 V
1.1 V –5.5 1.1 V –5.5
V
IOH = –100 µA
–
0.1
–
0.1
V
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
1
1.2
1.9
2.4
3.8
1
1.2
1.9
2.4
3.8
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
IOH = –24 mA
IOH = –32 mA
High-level
output
VOH
V
voltage (3)
4.5 V
4.5 V
1.1 V –5.5 1.1 V –5.5
IOL = 100 µA
0.1
0.1
V
V
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 24 mA
IOL = 32 mA
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
0.3
0.45
0.3
0.3
0.45
0.3
Low-level
output
VOL
V
voltage (4)
0.55
0.55
0.55
0.55
4.5 V
4.5 V
Input
leakage
current
Data Input (5)
VI = VCCI or GND
1.1 V –5.5 1.1 V –5.5
II
1
1
2
µA
µA
–0.3
–1
–2
V
V
Inputs
VI or VO = 0 V –
5.5 V
Partial
power down
current
0 V
1
1
2
2
2.5
2.5
0 V –5.5 V
–1
–1
–2
–2
–2.5
–2.5
Ioff
0 V
0 V –5.5 V
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
TEST
CONDITIONS
PARAMETER
VCCI
VCCO
UNIT
–40°C to 85°C
–40°C to 125°C
Floating (6)
1.5
2
2.5
Floating
supply
Ioff-float Partial
0 V –5.5 V –1.5
–2
–2.5
Inputs
VI or VO = GND
µA
Floating (6)
1.5
2
2.5
0 V –5.5 V
–1.5
–2
–2.5
power down
current
1.1 V –5.5 1.1 V –5.5
2
3
6
V
V
VI = VCCI or GND
IO = 0
0 V
5.5 V
5.5 V
0 V
–0.2
–0.5
–1
VCCI supply
current
ICCI
µA
1
2
2
3
4
6
VI = GND
IO = 0
5.5 V
Floating (6)
1.1 V –5.5 1.1 V –5.5
2
1
3
2
6
4
V
V
VI = VCCI or GND
IO = 0
ICCO
VCCO
supply
current
0 V
5.5 V
5.5 V
0 V
µA
µA
–0.2
–0.5
–1
VI = GND
IO = 0
ICCO
Floating (6)
5.5 V
2
3
3
4
6
6
Combined
supply
current
ICCI
+
VI = VCCI or GND
IO = 0
1.1 V –5.5 1.1 V –5.5
V
ICCO
V
Additional
input supply
current
3.0 V –5.5 3.0 V –5.5
50
10
75 µA
10 pF
ΔICCI
VI = VCCI –0.6 V
V
V
Input
Ci
Capacitanc VI = 3.3 V or GND 3.3 V
e
3.3 V
5
5
VCCO = 0V VO
=
Output
Capacitanc
e
1.65 V DC +1 MHz
-16 dBm sine
wave
Co
3.3 V
3.3 V
10
10 pF
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) Tested at VI = VT+(MAX)
(4) Tested at VI = VT-(MIN)
(5) For I/O ports, the parameter Il includes the IOZ current.
(6) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10 nA.
.
.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.6 Switching Characteristics: Tpd
Over operating free-air temperature range (TA). See Figure 7-1 and Table 7-1for test circuit and loading. See Figure 7-2 and Figure 7-3 for measurement waveforms.
Input Supply Voltage (VCCI
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Output Supply
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
Voltage (VCCO
)
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
10
9
83
36
32
29
29
28
10
8
70
28
23
18
16
15
10
7
66
26
21
15
13
12
9
7
6
5
4
3
59
22
18
13
11
10
9
7
6
4
3
2
58
21
17
12
10
9
9
7
6
4
3
2
54
20
16
11
9
8
7
6
Propagation
delay
tpd
A
Y
ns
7
6
5
7
6
4
7
5
4
8
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.7 Switching Characteristics: TMAX
over operating free-air temperature range (unless otherwise noted)
Operating free-air
temperature (TA)
PARAMETER
TEST CONDITIONS
VCCI
VCCO
UNIT
-40°C to 125°C
MIN TYP MAX
3.0 V - 3.6 V
2.25 V - 2.75 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.1 V - 1.3 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
3.0 V - 3.6 V
3.0 V - 3.6 V
1.65 V - 1.95 V
3.0 V - 3.6 V
2.25 V - 2.75 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.1 V - 1.3 V
200
150
100
20
420
300
200
40
Up Translation
100
10
210
20
50% Duty Cycle Input
TMAX - Maximum One channel switching
5
10
Mbps
Data Rate
20% of pulse > 0.7*VCCO
20% of pulse < 0.3*VCCO
100
75
210
140
75
50
Down Translation 4.5 V - 5.5 V
3.0 V - 3.6 V
15
30
40
75
3.0 V - 3.6 V
10
20
1.65 V - 1.95 V
5
10
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
6.8 Typical Characteristics
5
4.5
4
1.8
1.6
1.4
1.2
1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
3.5
3
2.5
2
0.8
0.6
0.4
VCC = 1.8 V
VCC = 1.5 V
VCC = 1.2 V
1.5
0
5
10
15
20
25
30
35
40
45
50
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOH Output High Current (mA)
IOH Output High Current (mA)
图6-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source
Current (IOH
图6-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source
Current (IOH
)
)
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
0.05
0
0
5
10
15
20
25
30
35
40
45
50
IOL Output Low Current (mA)
图6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
图6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
)
)
图6-6. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage
图6-5. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage
(VIN)
(VIN)
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• Δt/ΔV ≤1 ns/V
Measurement Point
2 x VCCO
RL
S1
Output Pin
Under Test
Open
(1)
GND
CL
RL
1. CL includes probe and jig capacitance.
图7-1. Load Circuit
表7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
tpd
Propagation (delay) time
15 pF
Open
N/A
1.1 V –5.5 V
2 kΩ
(1)
VCCI
(1)
VCCI
100 kHz
Input A, B
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 1 s/V
0 V
0 V
VOH
(2)
VOH
tpd
tpd
(2)
Ensure Monotonic
Rising and Falling Edge
Output B, A
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
图7-3. Input Transition Rise and Fall Rate
图7-2. Propagation Delay
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
8 Detailed Description
8.1 Overview
The SN74LXC1T14-Q1 is a single bit translating transceiver that uses two individually configurable power-supply
rails. The device is operational with both VCCI and VCCO supplies as low as 1.1 V and as high as 5.5 V. The A
input is designed to track VCCI, and the Y output is designed to track VCCO
.
The SN74LXC1T14-Q1 device is designed for asynchronous communication between devices, and transmits
data from A to Y. The input circuitry on the A pin is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ
.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry
ensures that no excessive current is drawn from or sourced into an input or output while the device is powered
down.
The VCC isolation or VCC disconnect feature ensures that if either VCC is less than 100 mV or disconnected with
the complementary supply within recommended operating conditions, the input is weakly pulled-down and then
set to the high-impedance state by disabling their outputs while the supply current is maintained. The Ioff-float
circuitry ensures that no excess current is drawn from or sourced into an input, or output while the supply is
floating.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing
robust power sequencing performance.
8.2 Functional Block Diagram
VCCI
VCCO
Y
A
8.3 Feature Description
8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase
dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, see
Understanding Schmitt Triggers.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
8.3.1.1 Input with Integrated Dynamic Pull-Down Resistors
Input circuitry is always active even when the device is disabled. It is recommended to keep a valid voltage level
at the input to avoid high current consumption. To help avoid a floating input during disabling, this device has
100-kΩ typical integrated weak dynamic pull-down at the input. When the device is disabled, the dynamic pull-
downs are activated for only a short period of time to help drive and keep the floating input low before the device
output becomes high impedance. If the input lines will be floated after the device is disabled, it is recommended
to keep them at a valid input voltage level using external pull-downs. This feature is ideal for loads of 30 pF or
less. If greater capactive loading is present then external pull-downs are recommended. If an external pull-up is
required, it should be no larger than 15 kΩto avoid contention with the 100 kΩinternal pull-down.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
8.3.4 VCC Isolation and VCC Disconnect (Ioff-float
)
This device has an Input with Integrated Dynamic Pull-Down Resistors. The input will get pulled down and then
enter a high-impedance state when either supply is < 100 mV or left floating (disconnected), while the other
supply is still connected to the device. It is recommended to not drive the input for this device, but to keep it at a
logic low state prior to floating (disconnecting) either supply.
The maximum supply current is specified by ICCx, while VCCx is floating, in the Electrical Characteristics. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff(float) in the Electrical
Characteristics.
VCCI
VCCO
ICCO maintained
Supply disconnected
VCCI
VCCO
Hi-Z
Hi-Z
Y
Disabled
A
Ioff(float)
Ioff(float)
图8-1. VCC Disconnect Feature
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-Free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the output (that is, where
the output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can
be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a
false device configuration of the peripheral, or even a false data initialization by the peripheral.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
8.3.7 Negative Clamping Diodes
As shown in 图8-2, the inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCCA VCCB
Device
Input or I/O
configured
as input
Level
Shifter
I/O configured
as output
-IIK
-IOK
GND
图8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCI and VCCO pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).
8.3.9 Supports High-Speed Translation
The SN74LXC1T14-Q1 device can support high data-rate applications. The translated signal data rate can be up
to 420 Mbps when the signal is translated from 3.3 V to 5.0 V.
8.4 Device Functional Modes
表8-1. Function Table
Input A
Output Y
H
L
L
H
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LXC1T14-Q1 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74LXC1T14-Q1 device is ideal for use in
applications where a push-pull driver is connected to the input. The maximum data rate can be up to 420 Mbps
when the device translates a signal from 3.3 V to 5.0 V.
9.2 Typical Application
VCCO
VCCI
LDO
PMIC
DC/DC
GPIO1
RESET
System
Controller
SN74LXC1T14-Q1
图9-1. LED Driver Application
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
1.1 V to 5.5 V
Input voltage range
Output voltage range
1.1 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LXC1T14-Q1 device to determine the input
voltage range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage
(Vt+) of the input port. For a valid logic low the value must be less than the negative-going input-threshold
voltage (Vt-) of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LXC1T14-Q1 device is driving to determine the output
voltage range.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices, as described in Glitch-Free Power Supply Sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions
should be considered to prevent ringing.
11.2 Layout Example
Legend
Via to VCCI
Via to VCCO
A
B
G
Via to GND
Copper Traces
SN74LXC1T14-Q1
0402
0.1µF
0402
0.1µF
A
VCCI
B
G
1
2
3
5
VCCO
Reset Flag
from LDO
A
Reset Flag
to Controller
G
G
4
Y
图11-1. Layout Example − SN74LXC1T14-Q1
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: SN74LXC1T14-Q1
SN74LXC1T14-Q1
ZHCSQV8 –AUGUST 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Device Support
12.1.1 Regulatory Requirements
No statutory or regulatory requirements apply to this device.
There are no special characteristics for this product.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Understanding Schmitt Triggers applicatin report
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: SN74LXC1T14-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LXC1T14QDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2OAT
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LXC1T14-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2022
Catalog : SN74LXC1T14
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SN74LXC1T45DBV
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
SN74LXC1T45DBVR
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
SN74LXC1T45DCK
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
SN74LXC1T45DRL
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
SN74LXC1T45DRY
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
SN74LXC1T45DTQ
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting
TI
©2020 ICPDF网 联系我们和版权申明