SN74LXCH1T45DTQR [TI]
具有可配置电压电平转换功能的 single-bit 双电源收发器 | DTQ | 6 | -40 to 125;
| 型号： | SN74LXCH1T45DTQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可配置电压电平转换功能的 single-bit 双电源收发器 | DTQ | 6 | -40 to 125 |
| 文件： | 总38页 (文件大小：2530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LXCH1T45
ZHCSOE9 –APRIL 2022
具有可配置电压转换、三态输出和总线保持输入的SN74LXCH1T45 1 位双电源
总线收发器
1 特性
3 说明
• 完全可配置的双电源轨设计允许各个端口在1.1V 至
5.5V 范围内运行
• 稳健、无干扰电源时序控制
• 在3.3V 至5.0V 范围内，支持高达420 Mbps 的速
率
• 总线保持数据输入消除了对外部上拉或下拉电阻器
的需求
• 施密特触发控制输入可实现慢速或高噪声输入
• 带集成静态下拉电阻器的控制输入允许浮动控制输
入
SN74LXCH1T45 是一款 1 位双电源同相双向电压电平
转换器件，具有总线保持电路。I/O 引脚 A 和控制引脚
(DIR) 以 VCCA 逻辑电平为基准，I/O 引脚 B 以 VCCB
逻辑电平为基准。A 端口能够接受 1.1V 至 5.5V 的 I/O
电压，而 B 端口可接受 1.1V 至 5.5V 的 I/O 电压。
DIR 上为高电平时允许数据从 A 传输到 B，而 DIR 上
为低电平时允许数据从 B 传输到 A。请参阅器件功能
模式，简要了解控制逻辑的运行。
器件信息(1)
• 高驱动强度（在5V 时最高达32 mA）
• 低功耗
封装尺寸（标称值）
器件型号
封装
SC70 (DCK) (6)
SON (DRY) (6)
X2SON (DTQ) (6)
2.00mm × 1.25mm
1.45mm × 1.00mm
1.00mm × 0.80mm
– 最大值3µA (25°C)
– 最大值6µA（–40°C 至125°C）
• VCC 隔离和VCC 断开特性
SN74LXCH1T45
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 如果任何一个VCC 电源低于100 mV，则所有
I/O 均变为高阻抗状态
– Ioff-float 支持VCC 断开操作
• Ioff 支持局部断电模式运行
VCCA
VCCB
• 兼容LVC 系列电平转换器
• 控制逻辑(DIR) 以VCCA 为基准
DIR
• 工作温度范围为–40°C 至+125°C
• 闩锁性能超过100 mA，符合JESD 78 II 类规范
• ESD 保护性能超过JESD 22 规范要求
– 4000V 人体放电模型
– 1000V 充电器件模型
Bus-Hold
Bus-Hold
B
A
2 应用
• 消除缓慢或嘈杂输入信号
• 驱动指示LED 或蜂鸣器
• 机械开关去抖
Note: Bus-hold circuits are only present for data inputs, not control inputs
功能方框图
• 通用I/O 电平转换
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES939
SN74LXCH1T45
ZHCSOE9 –APRIL 2022
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Table of Contents
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Enable Times............................................................ 23
9.3 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support ......................................... 26
12.2 接收文档更新通知................................................... 26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 术语表..................................................................... 26
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V............ 9
6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V.......... 10
6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V........ 11
6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V.......... 12
6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V........ 13
6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V........ 14
6.12 Switching Characteristics: Tsk, TMAX ......................15
6.13 Operating Characteristics....................................... 15
6.14 Typical Characteristics............................................16
7 Parameter Measurement Information..........................17
7.1 Load Circuit and Voltage Waveforms........................17
Information.................................................................... 26
4 Revision History
DATE
REVISION
NOTES
April 2022
*
Initial Release
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5 Pin Configuration and Functions
1
2
3
6
5
4
VCCA
GND
A
VCCB
VCCA
1
2
3
6
5
4
VCCB
DIR
B
DIR
B
GND
A
图5-2. DRY Package Preview, 6-Pin SON
(Top View)
图5-1. DCK Package, 6-Pin SC70
(Top View)
1
3
6
4
VCCA
GND
VCCB
DIR
B
2
5
A
图5-3. DTQ Package Preview, 6-Pin X2SON Transparent (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A
NO.
3
I/O
I/O
I
Input or output A. Referenced to VCCA
Input or output B. Referenced to VCCB
.
.
B
4
DIR
GND
DIR
VCCA
VCCB
5
Direction-control signal for all ports. Referenced to VCCA
Ground.
.
.
2
—
5
I
Direction-control signal for all ports. Referenced to VCCA
A-port supply voltage. 1.1 V ≤VCCA ≤5.5 V.
B-port supply voltage. 1.1 V ≤VCCB ≤5.5 V.
1
—
—
6
(1) I = input, O = output, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
6.5
6.5
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
6.5
VI
Input Voltage(2)
6.5
V
6.5
6.5
Voltage applied to any output in the high-impedance or power-off
state(2)
VO
VO
V
V
B Port
6.5
A Port
VCCA + 0.5
VCCB + 0.5
Voltage applied to any output in the high or low state(2) (3)
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
50 mA
200 mA
150 °C
150 °C
–50
–200
Tj
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure beyond the limits listed in Recommended Operating Conditions. may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
1.1
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
5.5
5.5
V
V
1.1
VCCI = 1.1 V - 1.3 V
VCCI = 1.4 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3.0 V - 3.6 V
VCCI = 4.5 V - 5.5 V
VCCI = 1.1 V - 1.3 V
VCCI = 1.4 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3.0 V - 3.6 V
VCCI = 4.5 V - 5.5 V
VCCO = 1.1 V
VCCI x 0.8
VCCI x 0.65
1.7
Data Inputs
(A,B)
(Referenced to VCCI
High-level input
voltage
VIH
V
V
)
)
2
VCCI x 0.7
VCCI x 0.2
VCCI x 0.35
0.7
Data Inputs
(A,B)
(Referenced to VCCI
Low-level input
voltage
VIL
0.8
VCCI x 0.3
–0.1
–4
VCCO = 1.4 V
VCCO = 1.65 V
–8
IOH
High-level output current
mA
VCCO = 2.3 V
–12
–24
–32
0.1
VCCO = 3 V
VCCO = 4.5 V
VCCO = 1.1 V
VCCO = 1.4 V
4
VCCO = 1.65 V
8
IOL
Low-level output current
Input voltage
mA
VCCO = 2.3 V
12
VCCO = 3 V
24
VCCO = 4.5 V
32
VI
0
0
5.5
V
V
Active State
Tri-State
Operating free-air temperature
VCCO
5.5
VO
TA
Output voltage
0
125 °C
–40
(1) VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port.
6.4 Thermal Information
SN74LXCH1T45
THERMAL METRIC(1)
DCK (SC70)
6 PINS
205.2
DRY (SON)
6 PINS
293.4
DTQ (X2SON)
6 PINS
285.0
UNIT
RθJA
RθJC(top)
RθJB
YJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
132.4
184.0
140.0
65.1
164.9
208.5
48.0
28.3
6.1
Junction-to-board characterization
parameter
YJB
64.9
N/A
164.0
N/A
207.8
N/A
°C/W
°C/W
Junction-to-case (bottom) thermal
resistance
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics app report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
–40°C to 85°C
–40°C to 125°C
1.1 V
1.1 V
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.2
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.48 0.17
0.59 0.28
0.69 0.35
0.97 0.56
1.5 0.89
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.48
0.59
0.69
0.97
1.5
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Positive-
going input-
threshold
voltage
Control Inputs
(DIR)
(Referenced to
VT+
V
VCCI
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Negative-
going input-
threshold
voltage
Control Inputs
(DIR)
(Referenced to
VT-
V
VCCI
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
1.97 1.51
2.4 1.88
1.97
2.4
0.4
0.2
0.4
0.25
0.3
0.5 0.25
0.5
Input-
threshold
Control Input
(DIR)
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
VCCO
0.55
0.65
0.72
0.93
1.06
0.38
0.46
0.58
0.69
VCCO
V
ΔVT
hysteresis
(Referenced to
VCCA
)
(VT+ –VT-)
4.5 V
5.5 V
4.5 V
5.5 V
1.1V –
5.5V
1.1V –
5.5V
IOH = –100 µA
–
0.1
–
0.1
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
1
1.2
1.9
2.4
3.8
1
1.2
1.9
2.4
3.8
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
IOH = –24 mA
IOH = –32 mA
High-level
output
VOH
V
voltage (3)
4.5 V
4.5 V
1.1V –
5.5V
1.1V –
5.5V
IOL = 100 µA
0.1
0.1
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 24 mA
IOL = 32 mA
VI = 0.39
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
0.3
0.45
0.3
0.55
0.55
4
0.3
0.45
0.3
Low-level
output
VOL
V
voltage (4)
0.55
0.55
4.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4
15
VI = 0.49
10
Bus-hold low
sustaining
current
VI = 0.58
25
20
IBHL
µA
VI = 0.70
45
45
Port A or Port
B (6)
VI = 0.80
75
75
VI = 1.35
4.5 V
4.5 V
100
100
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over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
–40°C to 85°C
–40°C to 125°C
VI = 0.71 V
VI = 0.91 V
VI = 1.07 V
VI = 1.70 V
VI = 2.00 V
1.1 V
1.1 V
–4
–15
–25
–45
–75
–4
–15
–25
–45
–75
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Bus-hold high
sustaining
current
IBHH
µA
Port A or Port
B (7)
–
100
–
100
VI = 3.15 V
4.5 V
4.5 V
1.3 V
1.6 V
1.95 V
2.7 V
3.6 V
5.5 V
1.3 V
1.3 V
1.6 V
1.95 V
2.7 V
3.6 V
5.5 V
1.3 V
75
125
200
300
500
900
75
125
200
300
500
900
Bus-hold low
Ramp input up
VI = 0 to VCCI
IBHLO overdrive
µA
current (8)
–75
–75
–
125
–
125
1.6 V
1.95 V
2.7 V
3.6 V
5.5 V
1.6 V
1.95 V
2.7 V
3.6 V
5.5 V
–
200
–
200
Bus-hold high
Ramp input down
VI = VCCI to 0
IBHHO overdrive
µA
–
300
–
300
current (9)
–
500
–
500
–
900
–
900
Control input
(DIR)
VI = VCCA or GND
1.1V –
5.5V
1.1V –
5.5V
-0.1
1
1
-0.1
2
1
-0.1
2
2
µA
µA
µA
Input leakage
current
II
Data Inputs (5)
(Ax, Bx)
VI = VCCI or GND
1.1V –
5.5V
1.1V –
5.5V
–0.3
–1
–2
A Port or B Port
VI or VO = 0 V - 5.5
V
0 V
0 V - 5.5 V
1
1
2
2
2
2.5
2.5
2.5
–1
–1
–2
–2
–2
–2.5
–2.5
–2.5
Partial power
down current
Ioff
0 V - 5.5 V 0 V
Floating (10) 0 V - 5.5 V
1.5
Floating
–1.5
supply Partial A Port or B Port
power down VI or VO = GND
current
Ioff-float
µA
µA
0 V - 5.5 V Floating (10)
1.5
2
2
2
2.5
4
–1.5
–0.2
–2
–2.5
1.1V –
1.1V –
5.5V
5.5V
VI = VCCI or GND
IO = 0
0 V
5.5 V
0 V
–0.5
–1
VCCA supply
ICCA
current
5.5 V
1
1
2
2
VI = GND
IO = 0
5.5 V
Floating (10)
1.5
1.5
1.1V –
5.5V
1.1V –
5.5V
2
1
2
1
4
2
VI = VCCI or GND
IO = 0
0 V
5.5 V
0 V
VCCB supply
current
ICCB
µA
5.5 V
–0.2
–0.5
–1
VI = GND
IO = 0
Floating (10) 5.5 V
1.5
1.5
2
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over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
–40°C to 85°C
–40°C to 125°C
Combined
supply
current
ICCA
ICCB
+
VI = VCCI or GND
IO = 0
1.1V –
5.5V
1.1V –
5.5V
3
4
6
µA
Control input (DIR):
VI = VCCA –0.6 V
A port = VCCA or
GND
3.0V - 5.5V 3.0V - 5.5V
3.0V - 5.5V 3.0V - 5.5V
3.0V - 5.5V 3.0V - 5.5V
50
75
VCCA
additional
supply
current per
input
B Port = open
µA
ΔICCA
A Port: VI = VCCA
0.6 V
–
50
50
75
DIR = VCCA, B Port
= open
VCCB
additional
supply
current per
input
B Port: VI = VCCB
0.6 V
-
75 µA
ΔICCB
DIR = GND, A Port
= open
Control Input
Capacitance
Ci
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
3.3 V
2.2
4.9
4
4
7
pF
pF
VCCO = 0V VO
=
Data I/O
Capacitance
Cio
1.65V DC +1 MHz
-16 dBm sine wave
10
(1) VCCI is the VCC associated with the input port
(2) VCCO is the VCC associated with the output port
(3) Tested at VI = VT+(MAX)
(4) Tested at VI = VT-(MIN)
(5) For I/O ports, the parameter Il includes the IOZ current
(6) IBHL should be measured after lowering VI to GND and then raising it to the defined input voltage
(7) IBHH should be measured after raising VI to VCCI and then lowering it to the defined input voltage
(8) An external driver must source at least IBHLO to switch this node from low-to-high
(9) An external driver must sink at least IBHHO to switch this node from high to low
(10) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA
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6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
6
8
85
55
4
6
41
37
71
47
53
47
47
48
110
89
89
79
3
5
36
33
67
43
53
47
41
41
99
80
84
73
1
3
33
30
60
38
53
47
34
34
86
68
81
68
1
3
34
30
57
37
53
47
33
33
83
65
82
67
1
2
44
33
58
36
53
47
32
32
85
63
92
70
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
6
85
5
4
3
3
3
B
8
55
6
6
5
4
4
5
53
5
5
5
5
4
DIR
DIR
DIR
DIR
7
47
7
7
7
7
7
Disable time
Enable time
ns
ns
10
14
21
27
16
19
85
7
6
5
5
4
71
11
17
23
14
18
10
16
21
13
17
8
8
6
150
121
118
97
13
17
12
16
13
17
11
15
12
15
11
14
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6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
1
1
70
46
1
1
29
29
29
29
29
29
45
46
69
70
53
54
1
1
24
24
26
26
29
29
38
40
59
61
48
49
1
1
20
21
23
23
29
29
31
32
49
51
43
44
1
1
19
19
21
21
29
29
30
31
46
48
41
42
1
1
19
20
21
21
29
29
28
29
44
45
41
42
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
39
1
1
1
1
1
B
1
36
1
1
1
1
1
3
29
3
3
3
3
3
DIR
DIR
DIR
DIR
5
29
5
5
5
5
5
Disable time
Enable time
ns
ns
11
15
19
27
12
16
78
8
7
5
5
4
70
14
15
23
10
14
11
13
21
9
10
11
18
8
9
8
113
101
91
11
17
8
9
15
7
71
13
12
12
11
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6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
1
1
66
43
35
32
22
23
73
64
103
90
80
61
1
1
26
27
24
24
22
31
40
42
59
61
44
45
1
1
21
22
21
22
23
23
34
36
50
53
39
40
1
1
17
18
18
19
23
23
27
28
40
43
34
36
1
1
16
17
17
18
22
23
25
27
38
39
33
34
1
1
15
16
17
17
22
23
23
25
35
37
32
35
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
1
1
1
1
1
B
1
1
1
1
1
1
2
2
2
2
2
2
DIR
DIR
DIR
DIR
4
4
4
4
4
4
Disable time
Enable time
ns
ns
9
7
6
4
4
3
15
17
23
11
14
13
13
21
9
11
12
19
8
6
8
6
9
9
7
16
7
12
6
12
6
12
11
10
10
9
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6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
1
1
59
38
32
29
16
16
63
56
91
76
67
49
1
1
23
23
20
21
23
16
35
37
49
51
33
34
1
1
19
19
17
18
16
16
29
31
41
44
33
30
1
1
15
15
15
15
16
25
23
25
33
35
25
27
1
1
13
14
14
14
20
16
22
23
30
32
24
27
1
1
12
13
13
14
16
16
19
20
27
29
23
24
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
1
1
1
1
1
B
1
1
1
1
1
1
1
1
1
1
1
1
DIR
DIR
DIR
DIR
2
2
2
2
2
2
Disable time
Enable time
ns
ns
8
6
5
3
3
2
13
14
21
8
10
11
18
6
10
10
16
5
8
7
5
8
7
6
14
4
13
4
10
4
11
9
8
7
7
6
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6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
1
1
57
36
33
29
14
34
59
52
86
71
64
46
1
1
21
22
19
19
14
15
32
33
44
46
30
31
1
1
17
18
16
17
14
15
27
29
37
39
27
28
1
1
14
14
13
14
14
15
21
23
30
32
23
24
1
1
12
13
12
13
20
15
20
22
28
29
22
23
1
1
11
12
12
12
14
17
18
19
25
26
22
22
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
1
1
1
1
1
B
1
1
1
1
1
1
1
1
1
1
1
1
DIR
DIR
DIR
DIR
1
1
1
1
1
1
Disable time
Enable time
ns
ns
7
5
5
3
3
2
12
13
19
8
9
9
7
7
5
10
16
6
9
7
7
5
14
5
12
4
12
4
10
3
10
9
8
7
6
6
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6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
See 图7-1 and 表7-1 for test circuit and loading. See 图7-2, 图7-3, and 图7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
1.8 ± 0.15 V
2.5 ± 0.2 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
1
1
57
36
47
33
12
12
57
50
98
73
62
43
1
1
21
21
19
20
12
12
30
31
42
44
28
28
1
1
17
17
15
16
21
20
25
27
34
36
24
25
1
1
13
14
12
13
12
12
20
21
27
29
20
21
1
1
12
12
11
12
15
12
19
20
25
27
19
20
1
1
1
1
1
1
2
4
5
9
2
4
11
11
11
11
12
12
17
18
23
24
18
19
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
1
1
1
1
B
1
1
1
1
1
1
1
1
1
1
DIR
DIR
DIR
DIR
1
1
1
1
1
Disable time
Enable time
ns
ns
1
1
4
3
3
11
8
9
8
6
6
6
8
7
7
18
6
15
4
13
3
11
3
11
2
9
7
6
5
4
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6.12 Switching Characteristics: Tsk, TMAX
over operating free-air temperature range (unless otherwise noted)
Operating free-air
temperature (TA)
PARAMETER
TEST CONDITIONS
VCCI
VCCO
UNIT
-40°C to 125°C
MIN TYP MAX
200
150
100
20
420
300
200
40
3.0 V –3.6 V
2.25 V - 2.75 V
1.65 V –1.95 V
1.1 V –1.3 V
1.65 V –1.95 V
1.1 V –1.3 V
1.1 V –1.3 V
4.5 V –5.5 V
4.5 V –5.5 V
4.5 V –5.5 V
4.5 V –5.5 V
3.0 V –3.6 V
3.0 V –3.6 V
1.65 V –1.95 V
3.0 V –3.6 V
1.65 V –1.95 V
1.1 V –1.3 V
1.65 V –1.95 V
1.1 V –1.3 V
1.1 V –1.3 V
4.5 V –5.5 V
4.5 V –5.5 V
4.5 V –5.5 V
3.0 V –3.6 V
3.0 V –3.6 V
1.65 V –1.95 V
4.5 V –5.5 V
4.5 V - 5.5 V
4.5 V –5.5 V
4.5 V –5.5 V
3.0 V –3.6 V
3.0 V –3.6 V
1.65 V –1.95 V
3.0 V –3.6 V
2.25 V - 2.75 V
Up Translation
100
10
210
20
50% Duty Cycle
Input
One channel
switching
20% of pulse >
0.7*VCCO
5
10
TMAX - Maximum
Data Rate
Mbps
100
75
210
140
75
20% of pulse <
0.3*VCCO
50
1.65 V –1.95 V
1.1 V –1.3 V
1.65 V –1.95 V
1.1 V –1.3 V
1.1 V –1.3 V
4.5 V –5.5 V
4.5 V –5.5 V
4.5 V –5.5 V
3.0 V –3.6 V
3.0 V –3.6 V
1.65 V –1.95 V
3.0 V –3.6 V
1.65 V –1.95 V
1.1 V –1.3 V
1.65 V –1.95 V
1.1 V –1.3 V
1.1 V –1.3 V
Down Translation
15
30
40
75
10
20
5
10
1
2
3
Up Translation
2.5
3.5
4.5
1
Timing skew
between any two
switching outputs
within the same
device
ns
tsk –Output skew
2
3
Down Translation
3
4
5
6.13 Operating Characteristics
TA = 25℃(1)
Supply Voltage (VCCB = VCCA
)
PARAMETER
Test Conditions 1.2 ± 0.1V 1.5 ± 0.1V 1.8 ± 0.15V 2.5 ± 0.2V 3.3 ± 0.3V 5.0 ± 0.5V UNIT
TYP
TYP
TYP
TYP
TYP
TYP
A to B
B to A
A to B
B to A
A Port
CL = 0, RL = Open
f = 10 MHz
3.5
3.7
3.9
4.2
4.5
5
(2)
(2)
CpdA
pF
pF
20.2
20.2
3.5
20.5
20.5
3.7
20.7
20.8
3.9
21.5
21.5
4.2
22.8
22.8
4.5
24.9
24.8
5.1
trise = tfall = 1 ns
B Port
CL = 0, RL = Open
f = 10 MHz
CpdB
trise = tfall = 1 ns
(1) See the CMOS Power Consumption and Cpd Calculation application report for more information about power dissipation capacitance.
(2) CpdA and CpdB are respectively A-Port and B-Port power dissipation capacitances per transceiver.
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6.14 Typical Characteristics
5
4.5
4
1.8
1.6
1.4
1.2
1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
3.5
3
2.5
2
0.8
0.6
0.4
VCC = 1.8 V
VCC = 1.5 V
VCC = 1.2 V
1.5
0
5
10
15
20
25
30
35
40
45
50
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOH Output High Current (mA)
IOH Output High Current (mA)
图6-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source
Current (IOH
图6-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source
Current (IOH
)
)
0.45
0.4
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
VCC = 1.2 V
0.05
0
0.05
0
0
5
10
15
20
25
30
35
40
45
50
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOL Output Low Current (mA)
IOL Output Low Current (mA)
图6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
图6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
)
)
2
1.8
1.6
1.4
1.2
1
0.22
0.2
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
VCC = 1.2 V
0.18
0.16
0.14
0.12
0.1
0.8
0.6
0.4
0.2
0
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VIN Input Voltage (V)
VIN Input Voltage (V)
图6-5. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage
图6-6. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage
(VIN)
(VIN)
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• Δt/ΔV ≤1 ns/V
Measurement Point
2 x VCCO
RL
S1
Output Pin
Under Test
Open
(1)
GND
CL
RL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
表7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
tpd
Propagation (delay) time
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
Open
1.1 V –5.5 V
1.1 V –1.6 V
1.65 V –2.7 V
3.0 V –5.5 V
1.1 V –1.6 V
1.65 V –2.7 V
3.0 V –5.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 × VCCO
2 × VCCO
2 × VCCO
GND
0.1 V
0.15 V
0.3 V
0.1 V
0.15 V
0.3 V
ten, tdis Enable time or disable time
ten, tdis Enable time or disable time
GND
GND
(1)
VCCI
(1)
VCCI
100 kHz
Input A, B
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 1 s/V
0 V
0 V
VOH
tpd
tpd
(2)
VOH
(2)
Ensure Monotonic
Rising and Falling Edge
Output B, A
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
(2)
VOL
1. VCCI is the supply pin associated with the input port.
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1.
图7-3. Input Transition Rise and Fall Rate
图7-2. Propagation Delay
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VCCA
GND
OE
VCCA / 2
VCCA / 2
tdis
ten
(3)
VCCO
Output(1)
VCCO / 2
VOL + VTP
(4)
VOL
(4)
VOH
VOH - VTP
Output(2)
VCCO / 2
GND
1. Output waveform on the condition that input is driven to a valid Logic Low.
2. Output waveform on the condition that input is driven to a valid Logic High.
3. VCCO is the supply pin associated with the output port.
4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
图7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74LXCH1T45 is a 1-bit translating transceiver that uses two individually configurable power-supply rails.
The device is operational with VCCA and VCCB supplies as low as 1.1 V and as high as 5.5 V. Additionally, the
device operates with VCCA = VCCB. The A port is designed to track VCCA, and the B port is designed to track
VCCB
.
The SN74LXCH1T45 device is designed for asynchronous communication between data buses and transmits
data from the A bus to the B bus or from the B bus to the A bus based on the logic level of the direction-control
input (DIR). The control pin of the SN74LXCH1T45 (DIR) is referenced to VCCA
.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry
ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the device is
powered down.
The VCC isolation and VCC disconnect feature ensures that if either VCC is less than 100 mV or floating with the
complementary supply within the recommended operating conditions, both I/O ports are set to the high-
impedance state by disabling their outputs and the supply current is maintained.
Glitch-free power supply sequencing allows either supply rail to power on or off in any order while providing
robust power sequencing performance.
8.2 Functional Block Diagram
VCCA
VCCB
DIR
A
Bus-Hold
Bus-Hold
B
Note: Bus-hold circuits are only present for data inputs, not control inputs
8.3 Feature Description
8.3.1 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase
dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information
regarding Schmitt-trigger inputs.
8.3.1.1 Control Inputs with Integrated Static Pull-Down Resistors
Similar to the data I/O's, floating control inputs can cause high current consumption. This device has integrated
weak static pull-downs of 5-MΩ typical on the control inputs (DIR and OE) to help avoid this concern. These
pull-downs are always present. For example, if the DIR pin is left floating, then the B port will be configured as an
input and the A port will be configured as an output.
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8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. Ioff in the Electrical Characteristics specifies the maximum leakage into or out of
any input or output pin on the device.
8.3.4 VCC Isolation and VCC Disconnect
The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV, requiring
one supply to connect to the device. Note: the bus-hold circuitry always remains active even when the device is
disabled and all outputs are in the high-impedance state.
Either supply can be disconnected (floated), while the other supply is still connected and the device will maitain
the maximum supply current specified by ICCx(floating), in the Electrical Characteristics. The I/O's will not enter a
high-impedance state unless the supply is disconnected after it is driven to <100 mV. Ioff(float) in the Electrical
Characteristics specifies the maximum leakage into or out of any input or output pin on the device.
VCCA
VCCB
ICCB maintained
Supply disconnected
VCCA
VCCB
DIR
OE
Disabled
Hi-Z
B1
Hi-Z
A1
Bus-Hold
Bus-Hold
Ioff(float)
Ioff(float)
Disabled
GND
图8-1. VCC Disconnect Feature
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage as long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-Free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the
output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can be
misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a
false device configuration of the peripheral, or even a false data initialization by the peripheral.
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8.3.7 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in 图8-2.
CAUTION
Voltages beyond the values specified in 节 6.1 table can cause damage to the device. The input
negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
VCCA VCCB
Device
Input or I/O
configured
as input
Level
Shifter
I/O configured
as output
-IIK
-IOK
GND
图8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
The VCCA and VCCB pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).
8.3.9 Supports High-Speed Translation
The SN74LXCH1T45 device can support high data-rate applications. The translated signal data rate can be up
to 420 Mbps when the signal is translated from 3.3 V to 5.0 V.
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8.3.10 Bus-Hold Data Inputs
Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of
these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low
state. After data is sent through a channel, the latch maintains the previous state on the input (if the line is left
floating). It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may
cause undefined inputs to occur which leads to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs
application report explains the problems associated with leaving the CMOS inputs floating. These latches remain
active at all times, independent of all control signals such as direction control or output enable. The latches also
remain active when the device is in the partial power down state, corresponding supply is still present, or when
the I/O's are floated. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Level
Bus-Hold
Bus-Hold
Ax
Bx
Shifter
图8-3. Schematic Description of Location of Bus-Hold Circuits
8.4 Device Functional Modes
表8-1. Function Table(1)
CONTROL INPUTS
PORT STATUS
OPERATION
OE
L
DIR
L
A PORT
Output (Enabled)
Input (Hi-Z)
B PORT
Input (Hi-Z)
B data to A bus
A data to B bus
Isolation
L
H
Output (Enabled)
Input (Hi-Z)
H
X
Input (Hi-Z)
(1) Input circuits of the data I/Os are always active.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LXCH1T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74LXCH1T45 device is ideal for use in
applications where a push-pull driver is connected to the data I/O. The maximum data rate can be up to 420
Mbps when the device translates a signal from 3.3 V to 5.0 V.
9.2 Enable Times
Calculate the enable times for the SN74LXCH1T45 using the following formulas:
tA_en (DIR to A) = tdis (DIR to B) + tpd (B to A)
tB_en (DIR to B) = tdis (DIR to A) + tpd (A to B)
(1)
(2)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74LXCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled (tdis) before presenting it with an input. After the
B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay (tpd). To avoid bus contention, care should be taken to not apply an input signal prior to the
output being disabled (tdis maximum).
9.3 Typical Application
5.0 V
1.5 V
0.1 µF
0.1 µF
System
Controller
LDO
VCCB
VCCA
RESET
SN74LXCH1T45
GND
GPIO1
B1
DIR
A1
图9-1. LED Driver Application
9.3.1 Design Requirements
Use the parameters listed in 表9-1 for this design example.
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
1.1 V to 5.5 V
Input voltage range
Output voltage range
1.1 V to 5.5 V
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9.3.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range:
– Use the supply voltage of the device that is driving the SN74LXCH1T45 device to determine the input
voltage range. The value must exceed the high-level input voltage (VIH) of the input port for a valid logic-
high. The value must be less than the low-level input voltage (VIL) of the input port for a valid logic low.
• Output voltage range:
– Use the device's supply voltage that the SN74LXCH1T45 device is driving to determine the output voltage
range.
9.3.3 Application Curve
图9-2. Up Translation at 2.5 MHz (1.2 V to 5 V)
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
节8.3.6 describes how this device was designed with various power supply sequencing methods in mind to help
prevent unintended triggering of downstream devices.
11 Layout
11.1 Layout Guidelines
Following common printed-circuit board layout guidelines are recommended to ensure reliability of the device,
which follows:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads; so routing and load conditions
should be considered to prevent ringing.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74LXCH1T45DTQ
B
VCCA
1
VCCB
6
A
01005
0.1µF
01005
0.1µF
4 mil
GND
DIR
2
5
G
G
G
A
B
4
Reset Flag
to Controller
Reset Flag
from LDO
3
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics appliction report
• Texas Instruments, System Considerations for Using Bus-Hold Curcuits to Avoid Floating Inputs application
report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LXCH1T45DCKR
SN74LXCH1T45DRYR
SN74LXCH1T45DTQR
ACTIVE
ACTIVE
ACTIVE
SC70
SON
DCK
DRY
DTQ
6
6
6
3000 RoHS & Green
5000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
2NNT
MJ
NIPDAU
NIPDAU
X2SON
MF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Apr-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DTQ0006A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
0.85
0.75
0.40 MAX
(0.1) TYP
C
SEATING PLANE
0.05 C
(0.1)
2X 0.6
0.4
0.05
0.00
(0.027) TYP
3
4
PKG
+0.05
-0.03
0.25
TYP
2
5
(0.08)
0.25
4X
0.17
1
6
PIN 1 ID
(OPTIONAL)
NOTE 5
PKG
0.30
4X
0.22
0.1
0.05
C A B
C
4224056/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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EXAMPLE BOARD LAYOUT
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.05 MIN
ALL AROUND
TYP
SOLDER MASK OPEING
TYP
SYMM
4X (0.25)
6
(0.25)
TYP
1
4X (0.4)
SYMM
(0.8)
2
5
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
3
4
(0.2)
TYP
(0.027) TYP
(R0.05) TYP
(0.4)
(0.6)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.25)
SYMM
(0.027) TYP
(0.279)
TYP
6
1
4X (0.4)
SYMM
(0.8)
5
2
(0.2) TYP
SOLDER MASK
EDGE, 2X
3
METAL UNDER
SOLDER MASK
TYP
4
(0.2)
TYP
(R0.05) TYP
(0.21)
(0.367)
4X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.07 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
0.4
0.3
0.1
C A B
C
0.05
PIN 1 ID
(OPTIONAL)
0.35
0.25
5X
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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