SN74S1051N [TI]
12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY; 12位肖特基势垒二极管总线端接阵列
| 型号： | SN74S1051N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY |
| 文件： | 总7页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
D OR N PACKAGE
(TOP VIEW)
Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200 mA
12-Bit Array Structure Suited for
Bus-Oriented Systems
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
CC
D12
D11
D10
D09
D08
D07
GND
D01
D02
D03
D04
D05
D06
GND
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of a 12-bit
high-speed Schottky diode array suitable for
clamping to V
and/or GND.
CC
The SN74S1051 is characterized for operation
from 0°C to 70°C.
schematic diagrams
D01 D02
D03 D04
D05 D06 D07 D08 D09
12
D10
13
D11
14
D12
15
V
CC
1
V
CC
16
2
3
4
5
6
7
8
9
8
9
GND GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Steady-state reverse voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
R
Continuous forward current, I : Any D terminal from GND or to V . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
F
CC
Total through all GND or V
terminals . . . . . . . . . . . . . . . . . . . . . . . 170 mA
CC
‡
Repetitive peak forward current , I
: Any D terminal from GND or V
Total through all GND or V
. . . . . . . . . . . . . . . . . . . . . 200 mA
FRM
CC
terminals . . . . . . . . . . . . . . . . . . . . 1 A
CC
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 1) . . . . . . . . . . 625 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These values apply for t ≤ 100 µs, duty cycle ≤ 20%.
w
NOTE 1: For operation above 25°C free-air temperature, derate linearly at the rate of 5 m/W/°C.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
single-diode operation (see Note 2)
§
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
1.05
1.3
UNIT
I
F
I
F
I
F
I
F
I
F
= 18 mA
= 50 mA
= 18 mA
= 50 mA
= 200 mA
0.85
1.05
0.75
0.95
1.45
To V
CC
V
V
Static forward voltage
V
F
0.95
1.2
From GND
Peak forward voltage
Static reverse current
V
FM
To V
5
5
CC
From GND
I
R
V
R
= 7 V
µA
V
= 0 V,
= 2 V,
f = 1 MHz
f = 1 MHz
8
4
16
8
R
R
C
Total capacitance
pF
t
V
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
NOTE 2: Test conditions and limits apply separately to each of the diodes. The diodes not under test are open-circuited during the measurement
of these characteristics.
multiple-diode operation
§
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
2
UNIT
Total I current = 1 A,
See Note 3
See Note 3
0.8
F
I
x
Internal crosstalk current
mA
Total I current = 198 mA,
0.02
0.2
F
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
NOTE 3: I is measured under the following conditions with one diode static, all others switching:
x
Switching diodes: t = 100 µs, duty cycle = 20%
w
Static diode: V = 5 V
The static diode input current is the internal crosstalk current I .
R
x
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
TEST CONDITIONS
= 10 mA,
MIN
TYP
MAX
UNIT
t
rr
Reverse recovery time
I
F
= 10 mA,
I
I
= 1 mA,
R = 100 Ω
L
8
16
ns
RM(REC)
R(REC)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
50 Ω
450 Ω
Pulse
Generator
Sampling
Oscilloscope
(See Note A)
(See Note B)
DUT
90%
V
FM
V
F
Output
Waveform
Input Pulse
(See Note A)
(See Note B)
10%
t
r
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: t = 20 ns, Z = 50 Ω, freq = 500 Hz,
r
O
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: t ≤ 350 ps, R = 50 Ω, C ≤ 5 pF.
r
i
i
Figure 1. Forward Recovery Voltage
DUT
Sampling
Oscilloscope
Pulse
Generator
I
F
(See Note B)
(See Note A)
t
rr
I
f
t
f
10%
0
Output
Waveform
(See Note B)
Input Pulse
(See Note A)
I
R(REC)
90%
I
RM(REC)
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: t = 0.5 ns, Z = 50 Ω, t ≥ 50 ns,
f
O
w
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: t ≤ 350 ps, R = 50 Ω, C ≤ 5 pF.
r
i
i
Figure 2. Reverse Recovery Time
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
APPLICATION INFORMATION
Large negative transients occurring at the inputs of memory devices (DRAMs, SRAMs, EPROMs, etc.) or on the
CLOCK lines of many clocked devices can result in improper operation of the devices. The SN74S1051 diode
termination array helps suppress negative transients caused by transmission-line reflections, crosstalk, and
switching noise.
Diode terminations have several advantages when compared to resistor termination schemes. Split resistor or
Thevenin equivalent termination can cause a substantial increase in power consumption. The use of a single resistor
togroundtoterminatealineusuallyresultsindegradationoftheoutputhighlevel, resultinginreducednoiseimmunity.
Series damping resistors placed on the outputs of the driver reduce negative transients, but they also can increase
propagation delays down the line, as a series resistor reduces the output drive capability of the driving device. Diode
terminations have none of these drawbacks.
The operation of the diode arrays in reducing negative transients is explained in the following figures. The diode
conducts current when the voltage reaches a negative value large enough for the diode to turn on. Suppression of
negative transients is tracked by the current-voltage characteristic curve for that diode. Typical
current-versus-voltage curves for the SN74S1051 are shown in Figures 3 and 4.
To illustrate how the diode arrays act to reduce negative transients at the end of a transmission line, the test setup
in Figure 5 was evaluated. The resulting waveforms with and without the diode are shown in Figure 6.
The maximum effectiveness of the diode arrays in suppressing negative transients occurs when the diode arrays are
placed at the end of a line and/or the end of a long stub branching off a main transmission line. The diodes also can
be used to reduce the negative transients that occur due to discontinuities in the middle of a line. An example of this
is a slot in a backplane that is provided for an add-on card.
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
–100
T
A
= 25°C
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Forward Voltage – V
I
Figure 3. Typical Input Current vs Input Voltage
(Lower Diode)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
100
90
80
70
60
50
40
30
T
A
= 25°C
20
10
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Forward Voltage – V
I
Figure 4. Typical Input Current vs Input Voltage
(Upper Diode)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018A – SEPTEMBER 1990 – REVISED AUGUST 1997
APPLICATION INFORMATION
Z
= 50 Ω
O
Length = 36 in.
Figure 5. Diode Test Setup
31.500 ns
56.500 ns
81.500 ns
End-of-
Line
Without
Diode
End-of-Line With Diode
Vmarker 1
Vmarker 2
Ch 2
= 1.880 V/div
Offset = 0.000 V
Timebase = 5.00 ns/V
Memory 1 = 1.880 V/div
Vmarker 1 = –1.353 V
Vmarker 2 = –3.647 V
Delay = 56.500 ns
Delta V = –2.293 V
Figure 6. Oscilloscope Display
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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