SN74SSTU32864ZKER [TI]
25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS; 25 - BIT与SSTL_18输入和输出的配置寄存缓冲器
| 型号： | SN74SSTU32864ZKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS |
| 文件： | 总18页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
Member of the Texas Instruments
Widebus+ Family
Supports LVCMOS Switching Levels on the
Control and RESET Inputs
Pinout Optimizes DDR-II DIMM PCB Layout
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
ESD Protection Exceeds JESD 22
– 5000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
– 1000-V Charged-Device Model (C101)
Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK) Inputs
description/ordering information
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V
operation. In the
CC
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low)
to14-bit1:2(whenhigh). C0andC1shouldnotbeswitchedduringnormaloperation. Theyshouldbehard-wired
to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,
the A6, D6, and H6 terminals are driven low and should not be used.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always
must be held at a valid logic high or low level.
The two V
pins (A3 and T3), are connected together internally by approximately 150 Ω. However, it is
REF
necessary to connect only one of the two V
should be terminated with a V
pins to the external V
power supply. An unused V
pin
REF
REF
REF
coupling capacitor.
REF
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
0°C to 70°C
LFBGA – GKE
Tape and reel SN74SSTU32864GKER
SU864
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
description/ordering information (continued)
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS
or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR
control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired
to ground, in which case, the setup-time requirement for DCS is the same as for the other D data inputs.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
GKE PACKAGE
(TOP VIEW)
terminal assignments for 1:1 register (C0 = 0, C1 = 0)
1
D1 (DCKE)
D2
2
NC
3
4
5
Q1 (QCKE)
Q2
6
1
2
3
4
5
6
A
B
C
D
E
F
V
V
DNU
Q15
Q16
DNU
Q17
Q18
C0
REF
CC
D15
GND
GND
A
B
C
D
D3
D16
V
V
Q3
CC
GND
CC
GND
D4 (DODT)
D5
NC
Q4 (QODT)
Q5
D17
V
CC
GND
V
CC
GND
D6
D18
Q6
E
F
G
H
J
G
H
J
NC
RESET
D7 (DCS)
CSR
D19
V
V
C1
CC
GND
CC
GND
CLK
CLK
D8
Q7 (QCS)
NC
DNU
NC
V
CC
V
CC
K
L
GND
GND
Q8
Q19
Q20
Q21
Q22
Q23
Q24
Q25
D9
D20
V
CC
V
CC
Q9
M
N
P
R
T
D10
D21
GND
GND
Q10
K
L
D11
D22
V
CC
GND
V
CC
GND
Q11
D12
D23
Q12
M
N
P
R
T
D13
D24
V
CC
V
V
Q13
CC
D14
D25
V
REF
Q14
CC
Each pin name in parentheses indicates the DDR-II DIMM signal name.
NC – No internal connection
DNU – Do not use
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
logic diagram for 1:1 register configuration (positive logic)
G2
RESET
H1
J1
CLK
CLK
A3, T3
A1
V
REF
D1 (DCKE)
D4 (DODT)
D7 (DCS)
CSR
D
R
A5
D5
Q1 (QCKE)
Q4 (QODT)
CLK
CLK
CLK
D1
H2
J2
D
R
D
R
H5
Q7 (QCS)
One of 22 Channels
B1
D2
CE
D
R
B5
Q2
CLK
To 21 Other Channels (D3, D5, D6, D8–D25)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
GKE PACKAGE
(TOP VIEW)
terminal assignments for 1:2 register A (C0 = 0, C1 = 1)
1
2
3
4
5
6
1
2
3
4
5
6
Q1A
(QCKEA)
Q1B
(QCKEB)
A
D1 (DCKE)
NC
V
REF
V
CC
A
B
C
D
B
C
D2
D3
DNU
DNU
GND
GND
Q2A
Q3A
Q2B
Q3B
V
V
CC
GND
CC
GND
Q4A
(QODTA)
Q4B
(QODTB)
D
D4 (DODT)
NC
E
F
G
H
J
E
F
D5
D6
NC
DNU
DNU
V
V
Q5A
Q6A
C1
Q5B
Q6B
C0
CC
CC
GND
GND
G
RESET
V
CC
V
CC
Q7A
(QCSA)
Q7B
(QCSB)
H
CLK
D7 (DCS)
GND
GND
J
K
L
CLK
D8
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
V
CC
GND
V
CC
GND
NC
NC
K
L
Q8A
Q8B
D9
V
CC
GND
V
CC
GND
Q9A
Q9B
M
N
P
R
T
M
N
P
R
T
D10
D11
D12
D13
D14
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
Q14B
V
CC
GND
V
CC
GND
V
CC
V
V
CC
V
REF
CC
Each pin name in parentheses indicates the DDR-II DIMM signal name.
NC – No internal connection
DNU – Do not use
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
logic diagram 1:2 register-A configuration (positive logic)
G2
RESET
H1
J1
CLK
CLK
A3, T3
A1
V
REF
D1 (DCKE)
D4 (DODT)
D7 (DCS)
CSR
A5
A6
Q1A (QCKEA)
Q1B (QCKEB)
D
R
CLK
CLK
CLK
D1
H2
J2
D5
D6
Q4A (QODTA)
Q4B (QODTB)
D
R
H5
H6
Q7A (QCSA)
Q7B (QCSB)
D
R
One of Eleven Channels
B1
D2
B5
B6
CE
Q2A
Q2B
D
R
CLK
To 10 Other Channels (D3, D5, D6, D8–D14)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
GKE PACKAGE
(TOP VIEW)
terminal assignments for 1:2 register B (C0 = 1, C1 = 1)
1
2
3
4
5
6
1
2
NC
3
4
5
6
A
B
C
D
E
F
D1
D2
D3
D4
D5
D6
NC
V
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
REF
CC
A
B
C
D
DNU
DNU
NC
GND
GND
V
V
CC
GND
CC
GND
DNU
DNU
RESET
V
V
CC
GND
CC
GND
E
F
G
H
J
G
V
V
CC
GND
CC
GND
Q7A
(QCSA)
Q7B
H
CLK
D7 (DCS)
(QCSB)
J
K
L
CLK
D8
CSR
DNU
DNU
DNU
V
V
NC
Q8A
Q9A
Q10A
NC
Q8B
Q9B
Q10B
CC
GND
CC
GND
K
L
D9
V
CC
GND
V
CC
GND
M
D10
M
N
P
R
T
D11
(DODT)
Q11A
(QODTA)
Q11B
(QODTB)
N
DNU
V
V
CC
CC
P
R
D12
D13
DNU
DNU
GND
GND
Q12A
Q13A
Q12B
Q13B
V
CC
V
CC
D14
(DCKE)
Q14A
(QCKEA)
Q14B
(QCKEB)
T
DNU
V
REF
V
CC
Each pin name in parentheses indicates the DDR-II DIMM signal name.
NC – No internal connection
DNU – Do not use
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
logic diagram 1:2 register-B configuration (positive logic)
G2
RESET
H1
J1
CLK
CLK
A3, T3
T1
V
REF
D14 (DCKE)
D11 (DODT)
D7 (DCS)
CSR
T5
T6
Q14A (QCKEA)
Q14B (QCKEB)
D
R
CLK
CLK
CLK
N1
H2
J2
N5
N6
Q11A (QODTA)
Q11B (QODTB)
D
R
H5
H6
Q7A (QCSA)
Q7B (QCSB)
D
R
One of Eleven Channels
D1
A1
A5
A6
CE
Q1A
Q1B
D
R
CLK
To 10 Other Channels (D2–D6, D8–D10, D12–D13)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
TERMINAL FUNCTIONS
ELECTRICAL
CHARACTERISTICS
TERMINAL NAME
DESCRIPTION
Ground
Ground input
GND
Power-supply voltage
Input reference voltage
Positive master clock input
Negative master clock input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
V
V
CC
REF
CLK
CLK
Configuration control inputs – Register A, Register B, 1:1, 1:2 select
C0, C1
Asynchronous reset input – resets registers and disables V
differential-input receivers
data and clock
REF
LVCMOS input
SSTL_18 inputs
RESET
Data inputs – clocked in on the crossing of the rising edge of CLK and the falling edge of
CLK
D1–D25
†
Chip select inputs – disables D1-D25 outputs switching when both inputs are high
SSTL_18 inputs
CSR, DCS
DODT
The outputs of this register bit will not be suspended by the DCS and CSR control.
The outputs of this register bit will not be suspended by the DCS and CSR control.
Data outputs that are suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
No internal connection
SSTL_18 input
SSTL_18 input
DCKE
‡
1.8 V CMOS outputs
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
Q1–Q25
QCS
QODT
QCKE
NC
Do not use – inputs are in standby-equivalent mode, and outputs are driven low.
DNU
†
‡
Data inputs = D2, D3, D5, D6, D8–D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3 D5, D6, D8–D14 when C0 = 0 and C1 = 1
Data inputs = D1–D6, D8–D10, D12, D13 when C0 = 1 and C1 = 1.
Data outputs = Q2, Q3, Q5, Q6, Q8–Q25 when C0 = 0 and C1 = 0
Data outputs = Q2, Q3 Q5, Q6, Q8–Q14 when C0 = 0 and C1 = 1
Data outputs = Q1–Q6, Q8–Q10, Q12, Q13 when C0 = 1 and C1 = 1.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
FUNCTION TABLES
INPUTS
OUTPUT
Qn
RESET
DCS
CSR
CLK
CLK
Dn
H
L
X
↑
↓
L
L
H
H
H
H
H
L
X
X
L
↑
↓
H
L
H
L
↑
↑
↓
↓
X
L
H
H
H
H
↑
↓
X
Q
Q
0
0
X
X
L or H
X or
L or H
X or
X
X or
X or
X or
L
L
floating floating floating floating floating
INPUTS
OUTPUTS
DCKE,
DCS,
QCKE,
QCS,
RESET
CLK
CLK
DODT
QODT
H
H
H
↑
↑
↓
↓
H
L
H
L
L or H
X or
L or H
X or
X
Q
0
X or
L
L
floating floating floating
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.5 V
CC
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 2.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
recommended operating conditions (see Note 4)
MIN
1.7
NOM
MAX
1.9
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
CC
REF
I
Reference voltage
0.49 × V
0
0.5 × V
0.51 × V
CC
V
CC
CC
Input voltage
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
Low-level output current
Operating free-air temperature
Data inputs, CSR
Data inputs, CSR
Data inputs, CSR
Data inputs, CSR
RESET, Cn
V
V
+250 mV
+125 mV
V
IH
REF
V
V
–250 mV
–125 mV
V
IL
REF
V
IH
REF
V
IL
REF
0.65 × V
V
IH
CC
RESET, Cn
0.35 × V
V
IL
CC
CLK, CLK
0.675
1.125
V
ICR
I(PP)
CLK, CLK
600
mV
I
I
–8
8
OH
mA
OL
T
A
0
70
C
NOTE 4: The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS
Inputs, literature number SCBA004.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
MIN TYP
–0.2
MAX
UNIT
CC
I
I
I
I
= –100 µA
= –6 mA
= 100 µA
= 6 mA
1.7 V to 1.9 V
1.7 V
V
OH
OH
OL
OL
CC
1.2
V
V
V
OH
1.7 V to 1.9 V
1.7 V
0.2
0.5
±5
V
OL
‡
I
I
All inputs
V = V
or GND
1.9 V
µA
µA
I
I
CC
RESET = GND
RESET = V , V = V
Static standby
100
40
I
I
= 0
= 0
1.9 V
CC
O
Static operating
or V
or V
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
IL(AC)
Dynamic operating – RESET = V , V = V
clock only
,
µA/
MHz
CC
I
28
18
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input,
1:1 configuration
µA/
clock
RESET = V , V = V
CC
or V
IL(AC)
,
I
IH(AC)
I
1.8 V
CCD
O
CLK and CLK switching 50% duty cycle,
MHz/
D input
One data input switching at one-half clock
frequency, 50% duty cycle
Dynamic operating –
per each data input,
1:2 configuration
36
27
Chip-select-enabled
low-power active
mode – clock only
RESET = V , V = V
CC
or V
,
µA/
MHz
I
IH(AC)
IL(AC)
CLK and CLK switching 50% duty cycle
Chip-select-enabled
low-power active
mode –
2
2
I
I
O
= 0
1.8 V
CCDLP
µA/
clock
MHz/
D input
RESET = V , V = V
CC
or V
IL(AC)
,
I
IH(AC)
1:1 configuration
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
Chip-select-enabled
low-power active
mode –
1:2 configuration
Data inputs, CSR
CLK, CLK
V = V
I
± 250 mV
2.5
2
3
3.5
3
REF
= 0.9 V, V
C
V
ICR
= 600 mV
pF
1.8 V
i
I(PP)
or GND
RESET
V = V
I
2.5
CC
†
‡
All typical values are at V
= 1.8 V, T = 25°C.
CC
A
Each V
REF
pin (A3 or T3) should be tested independently, with the other (untested) pin open.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1 and Note 5)
MIN
MAX
UNIT
MHz
ns
f
t
t
t
Clock frequency
500
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 6)
Differential inputs inactive time (see Note 7)
1
w
10
15
ns
act
ns
inact
0.7
0.5
0.5
0.5
DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
t
Setup time
Hold time
ns
ns
DCS before CLK↑, CLK↓, CSR low
su
h
DODT, DCKE, and Data before CLK↑, CLK↓
DCS, DODT, DCKE, and Data after CLK↑, CLK↓
t
NOTES: 5. All input slew rates are 1 V/ns ±20%.
6.
7.
V
V
low.
must be held at a valid input level and data inputs must be held low for a minimum time of t
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t
max, after RESET is taken high.
REF
REF
act
max, after RESET is taken
inact
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
CC
± 0.1 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
500
1.4
MAX
f
t
t
MHz
ns
max
†
CLK and CLK
CLK and CLK
RESET
Q
Q
Q
2.5
2.7
3
pdm
†
ns
pdmss
†
t
ns
RPHL
†
Includes 350-ps test-load transmission-line delay
output slew rates over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
V = 1.8 V
CC
± 0.1 V
PARAMETER
FROM
TO
UNIT
MIN
MAX
dV/dt_r
dV/dt_f
20%
80%
80%
20%
1.9
4.9
V/ns
V/ns
V/ns
1.9
4.9
1
§
dV/dt_∆
80% or 20%
20% or 80%
§
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Z
= 50 Ω,
= 350 ps
O
Test
Point
DUT
CLK
t
D
R
= 1 kΩ
L
Output
Test Point
Out
Clock Inputs
R
= 100 Ω
L
C
= 30 pF
L
Z
t
= 50 Ω,
= 350 ps
O
D
CLK
R = 1 kΩ
L
(see Note A)
Test
Point
Z
= 50 Ω,
= 350 ps
O
t
D
LOAD CIRCUIT
t
w
V
V
IH
V
REF
V
V
Input
REF
V
IL
LVCMOS
RESET
Input
CC
V
/2
V
/2
CC
CC
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
ICR
ICR
I
I
(operating)
I
CC
CC
90%
(see
Note B)
10%
(standby)
CC
t
t
PLH
PHL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
OL
Output
V
TT
V
TT
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Inputs
LVCMOS
RESET
Input
V
ICR
V
CC
/2
IL
t
PHL
t
t
h
su
V
V
V
OH
IH
V
REF
Input
V
REF
Output
V
TT
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V
L
I
or GND, and I = 0 mA.
CC
CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
I.
V
V
V
V
= V /2
REF
IH
IL
CC
= V
= V
+ 250 mV (ac voltage levels) for differential inputs. V = V
– 250 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
for LVCMOS input.
CC
REF
REF
IH
IL
= 600 mV
and t
I(PP)
t
are the same as t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
DUT
R
= 50 Ω
L
V
V
OH
Out
Test Point
80%
C
= 5 pF
Output
L
20%
(see Note A)
OL
dV_f
dt_f
VOLTAGE WAVEFORMS
LOAD CIRCUIT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
dt_r
dV_r
Test Point
= 50 Ω
V
OH
80%
C
= 5 pF
L
Output
R
L
(see Note A)
20%
V
OL
LOAD CIRCUIT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Z = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
O
Figure 2. Output Slew-Rate Measurement Information
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74SSTU32864GKER
SN74SSTU32864ZKER
ACTIVE
ACTIVE
LFBGA
LFBGA
GKE
96
96
1000
TBD
/
/
Level-3-220C-168 HR
Level-3-250C-1WEEK
ZKE
1000 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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