SN75110ADG4 [TI]
DUAL LINE DRIVERS;型号: | SN75110ADG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL LINE DRIVERS 驱动 光电二极管 接口集成电路 驱动器 |
文件: | 总16页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
SN55110A . . . J OR W PACKAGE
SN75110A . . . D, N, OR NS PACKAGE
SN75112 . . . D OR N PACKAGE
(TOP VIEW)
Improved Stability Over Supply Voltage and
Temperature Ranges
Constant-Current Outputs
High Speed
1A
1B
V
CC+
1Y
1Z
1
2
3
4
5
6
7
14
13
12
11
10
9
Standard Supply Voltages
High Output Impedance
1C
High Common-Mode Output Voltage Range
. . . –3 V to 10 V
2C
V
CC–
2A
D
2B
2Z
2Y
TTL-Input Compatibility
8
GND
Inhibitor Available for Driver Selection
Glitch Free During Power Up/Power Down
SN55110A . . . FK PACKAGE
(TOP VIEW)
SN75112 and External Circuit Meets or
Exceeds the Requirements of CCITT
Recommendation V.35
3
2
1 20 19
18
description/ordering information
1Z
NC
V
1C
NC
2C
NC
2A
4
5
6
7
8
17
16
15
14
The SN55110A, SN75110A, and SN75112 dual
line drivers have improved output current
regulation with supply-voltage and temperature
variations. In addition, the higher current of the
SN75112 (27 mA) allows data to be transmitted
over longer lines. These drivers offer optimum
performance when used with the SN55107A,
SN75107A, and SN75108A line receivers.
CC–
NC
D
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN75110AN
SN75112N
SN75110AN
SN75112N
PDIP (N)
SOIC (D)
Tube of 25
Tube of 50
SN75110AD
SN75110ADR
SN75112D
SN75110A
SN75112A
0°C to 70°C
Reel of 2500
Tube of 50
Reel of 2500
Reel of 2000
SN75112DR
SN75110ANSR
SN55110AJ
SOP (NS)
CDIP (J)
SN75110A
SN55110AJ
SNJ55110AJ
SNJ55110AW
SNJ55110AFK
Tube of 25
SNJ55110AJ
SNJ55110AW
SNJ55110AFK
–55°C to 125°C
CFP (W)
Tube of 150
Tube of 55
LCCC (FK)
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
description/ordering information (continued)
These drivers feature independent channels with common voltage supply and ground terminals. The significant
difference between the three drivers is in the output-current specification. The driver circuits feature a constant
output current that is switched to either of two output terminals by the appropriate logic levels at the input
terminals. The output current can be switched off (inhibited) by low logic levels on the enable inputs. The output
current is nominally 12 mA for the ’110A devices, and is 27 mA for the SN75112.
The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe
or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output
current in the inhibited mode, I
, is specified so that minimum line loading is induced when the driver is used
O(off)
in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high.
The output impedance of a transistor is biased to cutoff.
The driver outputs have a common-mode voltage range of –3 V to 10 V, allowing common-mode voltage on the
line without affecting driver performance.
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at
2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure
400-mV noise margin when interfaced with TTL Series 54/74 devices.
The SN55110A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75110A and SN75112 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each driver)
LOGIC
INPUTS
ENABLE
INPUTS
†
OUTPUTS
A
B
X
X
X
L
C
L
D
Y
Z
X
X
L
X
L
Off
Off
On
On
Off
Off
Off
Off
Off
On
X
H
H
H
H
H
H
X
H
H
H = high level, L = low level, X = irrelevant
†
When using only one channel of the line drivers,
the other channel should be inhibited and/or have
its outputs grounded.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
schematic (each driver)
14
V
CC+
2.2 kΩ
NOM
+
3, 4
10
C
D
To Other
Driver
–
–
+
2.2 kΩ
NOM
8, 13
Y
9, 12
Z
1, 5
2, 6
A
B
7
GND
–
Common to Both Drivers
+
11
V
CC–
–
+
. . . V
. . . V
Bus
CC+
–
Bus
CC–
–
To Other Driver
Pin numbers shown are for the D, J, N, NS, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: V
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
CC+
CC–
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 12 V
O
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Package thermal impedance, θ (see Notes 4 and 5): FK package . . . . . . . . . . . . . . . . . . . . . . . . 13.42°C/W
JC
J package . . . . . . . . . . . . . . . . . . . . . . . . . 15.05°C/W
W package . . . . . . . . . . . . . . . . . . . . . . . . 14.65°C/W
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or NS package . . . . . . . . . . . . 260°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) – T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. Maximumpower dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable case
J
J
JC
C
temperature is P = (T (max) – T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
5. The package thermal impedance is calculated in accordance with MIL-STD-883.
D
J
C
JC
J
recommended operating conditions (see Note 6)
SN75110A
SN75112
SN55110A
MIN NOM
UNIT
MAX
MIN NOM
MAX
V
V
+
Supply voltage
4.5
–4.5
0
5
5.5
4.75
5
5.25
V
V
CC
Supply voltage
–5
–5.5 –4.75
–5 –5.25
CC–
Positive common-mode output voltage
Negative common-mode output voltage
High-level input voltage
10
0
0
2
10
V
0
–3
–3
V
V
V
2
V
IH
Low-level output current
Operating free-air temperature
0.8
0.8
70
V
IL
T
A
–55
125
0
°C
NOTE 6: When using only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN55110A
SN75112
SN75110A
†
TEST CONDITIONS
PARAMETER
UNIT
‡
‡
MIN TYP
MAX
–1.5
15
MIN TYP
MAX
–1.5
40
V
IK
Input clamp voltage
V
V
= MIN,
I = –12 mA
L
–0.9
–0.9
V
CC±
= MAX,
V
O
= 10 V
12
27
CC±
V
V
= MIN to MAX,
CC
O
I
On-state output current
24
15
28
27
32
mA
O(on)
= –1 V to 1 V, T = 25°C
A
V
= MIN,
= MIN,
V
= –3 V
6.5
12
CC±
CC±
O
O
I
I
Off-state output current
V
V
= 10 V
100
1
100
1
µA
O(off)
Input current
at maximum
input voltage
A, B, or C inputs
D input
V
V
= MAX,
= MAX,
V = 5.5 V
mA
I
CC±
I
2
2
A, B, or C inputs
D input
40
80
–3
–6
40
80
–3
–6
High-level
input current
I
I
V = 2.4 V
I
µA
IH
CC±
A, B, or C inputs
D input
Low-level
input current
V
V
= MAX,
= MAX,
V = 0.4 V
I
mA
IL
CC±
CC±
Supply current from V
with driver enabled
CC
I
I
A and B inputs at 0.4 V,
C and D inputs at 2 V
23
35
25
40
mA
mA
CC+(on)
V
CC±
= MAX,
Supply current from V
with driver enabled
CC–
–34
–50
–65
–100
A and B inputs at 0.4 V,
C and D inputs at 2 V
CC–(on)
Supply current from V
with driver inhibited
V
= MAX,
CC–
CC±
A, B, C, and D inputs at 0.4 V
I
I
21
30
mA
mA
CC+(off)
Supply current from V
with driver inhibited
V
= MAX,
CC±
CC±
A, B, C, and D inputs at 0.4 V
–17
–32
CC–(off)
†
‡
For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, V = –5 V, T = 25°C.
CC+
CC–
A
switching characteristics, V
= ±5 V, T = 25°C (see Figure 1)
CC±
A
FROM
(INPUT)
TO
(OUTPUT)
§
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
t
t
t
t
9
9
15
15
25
25
PLH
PHL
PLH
PHL
A or B
C or D
Y or Z
C
C
= 40 pF,
= 40 pF,
R
R
= 50 Ω,
= 50 Ω,
ns
L
L
L
L
16
13
Y or Z
ns
§
t
t
= Propagation delay time, low- to high-level output
= Propagation delay time, high- to low-level output
PLH
PHL
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC+
V
CC–
Input A or B
50 Ω
Output Y
= 40 pF
890 Ω
890 Ω
C
L
R
R
= 50 Ω
L
L
(see Note A)
Pulse
Generator
(See Note B)
Output Z
Pulse
Generator
(See Note B)
C
= 40 pF
(see Note A)
L
= 50 Ω
To Other Driver
See Note C
Input C or D
50 Ω
TEST CIRCUIT
3 V
50%
t
50%
Input A or B
0 V
w1
t
w2
3 V
0 V
50%
t
50%
Enable C or D
t
t
t
PHL
PLH
PHL
PLH
Off
On
Output Y
Output Z
50%
50%
50%
50%
t
t
PLH
PHL
Off
On
50%
50%
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. Thepulsegeneratorshavethefollowingcharacteristics:Z =50Ω, t =t =10± 5ns, t =500ns, PRR≤ 1MHz, t =1µs, PRR ≤
O
r
f
w1 w2
500 kHz.
C. For simplicity, only one channel and the enable connections are shown.
Figure 1. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
TYPICAL CHARACTERISTICS
SN75112
ON-STATE OUTPUT CURRENT
vs
SN55110A, SN75110A
ON-STATE OUTPUT CURRENT
vs
NEGATIVE SUPPLY VOLTAGE
NEGATIVE SUPPLY VOLTAGE
35
30
25
20
15
10
5
14
12
10
8
V
V
T
= 4.5 V
= –3 V
= 25°C
V
V
T
= 4.5 V
= –3 V
= 25°C
CC+
O
A
CC+
O
A
6
4
2
0
0
–3
–4
–5
–6
–7
–3
–4
–5
–6
–7
V
CC–
– Negative Supply Voltage – V
V
CC–
– Negative Supply Voltage – V
Figure 2
Figure 3
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
APPLICATION INFORMATION
special pulse-control circuit
Figure 4 shows a circuit that can be used as a pulse-generator output or in many other testing applications.
OUTPUTS
INPUT
A
Z
Y
High
Low
Off On
On Off
5 V
3
2
1
3
4
4
6
2
5
V
Y
5
CC+
1
6
A
B
Input
2.5 V
Z
C
D
3
4
2
1/2 ’110A
or SN75112
5
V
CC–
6
GND
1
–5 V
To Other Logic and
Strobe Inputs
Output
Input Pulse
0 V
Switch
Position
1
2
3
4
5
6
Output Pulse
0 V
Figure 4. Pulse-Control Circuit
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55110A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106F – DECEMBER 1975 – REVISED JULY 2003
APPLICATION INFORMATION
using the SN75112 as a CCITT-recommended V.35 line driver
The SN75112 dual line driver, the SN75107A dual line receiver, and some external resistors can be used to
implement the data-interchange circuit of CCITT recommendation V.35 (1976) modem specification. The circuit
of one channel is shown in Figure 1 and meets the requirement of the interface as specified by Appendix 11
of CCITT V.35 and is summarized in Table 1 (V.35 has been replaced by ITU V.11).
Table 1. CCITT V.35 Electrical Requirements
GENERATOR
MIN
50
MAX
150
165
660
UNIT
Ω
Source impedance, Z
source
Resistance to ground, R
135
440
40
Ω
Differential output voltage, V
mV
ns
OD
10% to 90% rise time, t
or
r
†
0.01 × ui
Common-mode output voltage, V
–0.6
0.6
V
OC
LOAD (RECEIVER)
MIN
90
MAX
110
UNIT
Ω
Input impedance, Z
I
Resistance to ground, R
135
165
Ω
†
ui = unit interval or minimum signal-element pulse duration
5 V
5 V
5 V
R3
390 Ω
Strobe
100 pF
R1
R6
6
1/2 SN75112
1.3 kΩ
50 Ω
13 1Y
1
1
1A
1B
R8
1A
Data In
Data Out
1Y
4
R5
75 Ω
2
12
1Z
2
125 Ω
1B
10
3
R7
50 Ω
5 Enable
1G
Enable
1C
1/2 SN75107A
100 pF
R4
390 Ω
R2
1.3 kΩ
5 V
All resistors are 5%, 1/4 W.
Figure 5. CCITT-Recommended V.35 Interface Using the SN75112 and SN75107A
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002
W (R-GDFP-F14)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.260 (6,60)
0.235 (5,97)
0.045 (1,14)
0.026 (0,66)
0.008 (0,20)
0.004 (0,10)
0.080 (2,03)
0.045 (1,14)
0.280 (7,11) MAX
0.019 (0,48)
0.015 (0,38)
1
14
0.050 (1,27)
0.390 (9,91)
0.335 (8,51)
0.005 (0,13) MIN
4 Places
7
8
0.360 (9,14)
0.250 (6,35)
0.360 (9,14)
0.250 (6,35)
4040180-2/C 02/02
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
0.775
0.920
1.060
A MAX
A
(19,69) (19,69) (23,37) (26,92)
16
9
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21,59) (23,88)
MS-100
VARIATION
0.260 (6,60)
0.240 (6,10)
AA
BB
AC
AD
C
1
8
0.070 (1,78)
0.045 (1,14)
D
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
D
0.030 (0,76)
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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