SN75FC1000 [TI]
1-GIGABIT FIBRE CHANNEL TRANSCEIVER; 1千兆光纤通道收发器
| 型号： | SN75FC1000 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-GIGABIT FIBRE CHANNEL TRANSCEIVER |
| 文件： | 总20页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
1.0625 Gigabits Per Second (Gbps) Fibre
Channel Transceiver Compatible With ANSI
X3T11 (FC-PH-0)
Interfaces to Electrical Cables/Backplane or
with Optical Modules
PECL Voltage Differential Signaling Load,
Designed to Support X3T11 10-Bit I/F
Specification
1 V Typ with 50 Ω – 75 Ω
Receiver Differential Input Voltage
200 mV Minimum
Transmits Serial Data Up to 1.0625 Gbps
(100 Megabytes Per Second [MBps] of Data
Bandwidth)
64-Pin Quad Flat Pack With Thermally
Enhanced Package
Operates With 3.3-V Supply Voltage
5-V Tolerant I/O Terminals
description
The SN75FC1000 fibre channel transceiver provides for ultra high-speed bidirectional point-to-point data
transmission. This device supports the ANSI X3T11 Fibre Channel standard and the functional and timing
requirements of the proposed 10-bit interface specification generated by ANSI X3T11.
PHD OR PJD PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_CMOS
TD0
RC0
48
47
46
45
44
43
42
41
40
1
SYNC
GND_TTL
RD0
2
TD1
3
TD2
4
V
_CMOS
TD3
RD1
CC
CC
5
RD2
6
TD4
V
_TTL
CC
7
TD5
RD3
RD4
8
TD6
9
V
_CMOS
TD7
39 RD5
38 RD6
10
11
12
13
14
15
16
TD8
37
36
35
34
33
V
CC
_TTL
TD9
RD7
RD8
RD9
GND_CMOS
GND_TX
TC1
GND_TTL
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
description (continued)
The intended application of this device is to provide building blocks for developing point-to-point baseband data
transmission over controlled-impedance media of approximately 50 Ω to 75 Ω. The transmission media can be
printed circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75FC1000 performs the data serialization and deserialization (SERDES) functions for the fibre channel
physical layer interface. The transceiver operates at 1.0625 Gbps (typical), providing up to 100 MBps of
bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded
data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at
pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial
stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with
respect to two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel bytes in RBC
clock rising edges.
The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver
can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.
The SN75FC1000 provides an internal loopback capability for self-test purposes. Serial data from the serializer
ispasseddirectlytothedeserializerallowingtheprotocoldeviceafunctionalself-checkofthephysicalinterface.
The SN75FC1000 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
functional block diagram
LOOPEN
TX+
TX–
10
/
10
/
10-Bit
Register
Shift
Register
TD0 – TD9
REFCLK
Clock
Multiplier
106.25 MHz
SYNCEN
SYNC
Synchronous
Detect
10
/
10
/
10-Bit
Register
Shift
Register
RD0 – RD9
53 MHz
53 MHz
PLL Clock
2:1
RBC0
RBC1
Recovery and
MUX
÷ 2
Data Retiming
106.25 MHz
RX+
RX–
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
I/O structures
PECL inputs (DIN_RXP, DIN_RXN)
PECL outputs (DIN_TXP, DIN_TXN)
V
DD
V
DD
100 Ω
DIN_RXP
DOUT_TXP
DOUT_TXN
4 kΩ
+
_
V
DD
V
CM
V
DD
4 kΩ
DIN_RXN
CMOS inputs (TD0 – TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)
V
DD
V
DD
TERMINALS
R1
R2
P
R1
REFCLK, TD0 – TD9 Open Circuit Open Circuit
120 Ω
LOOPEN
Open Circuit
400 kΩ
Input
SYNCEN, LCKREFN
400 kΩ
Open Circuit
R2
N
CMOS outputs (RD0 – RD9, RBC0, RBC1, SYNC)
V
DD
P
Output
N
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
Terminal Functions
TERMINAL
NO.
DESCRIPTION
NAME
TYPE
I/O and DATA
DOUT_TXP
DOUT_TXN
62
61
Output
Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface
to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.0625 Gbps.
DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is
low .
DIN_RXP
DIN_RXN
54
52
Input
Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface
fromacopperoranopticalI/Fmodule. TheseterminalsreceiveNRZdataatarateof1.0625Gbpsand
are active when LOOPEN is held low.
LCKREFN
LOOPEN
27
19
Input
Input
Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied
REFCLK signal. LCKREFN prelocks or resets the receive PLL.
Loopenable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted
serial data is directly routed to the inputs of the receiver. This provides a self-test capability in
conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during
the loop-back test. LOOPEN is held low during standard operational state with external serial outputs
and inputs active.
RBC0
RBC1
31
30
Output
Receive byte clock. RBC0 and RBC1 are 53.125-MHz recovered clocks used for synchronizing the
10-bit output data on RD0 – RD9. The 10-bit output data words are valid on the rising edges of RBC0
and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
RC1,
RC0
49
48
Analog
Output
Receivecapacitor. RC0andRC1areexternalcapacitorconnectionsusedforthereceiverinternalPLL
filter. The recommend value for this external capacitor is 2 nF.
RD0 – RD9
REFCLK
SYNC
45,44,43,4
140,39,38,
3635,34
Receivedata. Theseoutputscarry10-bitparalleldataoutputfromthetransceivertotheprotocollayer.
The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the K28.5
character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.
22
47
24
Input
Output
Input
Reference clock. REFCLK is an external 106.25 MHz input clock that synchronizes the receiver and
transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for
serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.
Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data
path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is
activated (asserted high).
SYNCEN
Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function
is activated. When this function is enabled, the transceiver detects the K28.5 character (0011111010
negativebeginningdisparity)intheserialdatastreamandrealignsdataonbyteboundariesifrequired.
When SYNCEN is low, serial input data is unframed in RD0 – RD9.
TC1
TC0
16
17
Analog
Input
Transmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal
PLL filter. The recommended value of this external capacitor is 2 nF.
TD0 – TD9
2,3,4,6
7,8,9,11
12,13
Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver
for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising
edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
Terminal Functions (Continued)
TERMINAL
NO.
DESCRIPTION
NAME
TYPE
POWER
_A provides a supply reference voltage for the high-speed analog circuits.
V
CC
_A
20,28,29,53
55,57,59,60
63
Supply
Analog power. V
CC
V
V
_CMOS
_RX
5,10,23,
Supply
Supply
Digital PECL logic power. V
circuits.
_CMOS provides an isolated low-noise power supply for the logic
CC
CC
50
Receiverpower. V
analog circuits.
_RXprovidesalow-noisesupplyreferencevoltageforthereceiverhigh-speed
CC
CC
V
V
_TTL
_TX
42,37
18
Supply
Supply
TTL power. V
_TTL provides a supply reference voltage for the receiver TTL circuits.
CC
CC
Transmitter power. V
_TX provides a low-noise supply reference voltage for the transmitter
CC
CC
high-speed analog circuits.
GROUND
GND_A
21,32,56,64
Ground
Ground
Analog ground. GND_A provides a ground reference for the high-speed analog circuits.
GND_CMOS
1,14,
Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits.
25,58
GND_RX
GND_TTL
GND_TX
51
33,46
15
Ground
Ground
Ground
Receiver ground. GND_RX provides a ground reference for the receiver circuits.
TTL circuit ground. GND_TTL provides a ground for TTL interface circuits.
Transmitter ground. GND_TX provides a ground reference for the transmitter circuits.
MISCELLANEOUS
RESERVED
26
Reserved. Internally pulled to GND, leave open or assert low.
detailed description
data transmission
The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0 – TD9) on the rising edge
of REFCLK (106.25 MHz). The reference clock is also used by the serializer, which multiplies the clock by a
factor of 10 providing a 1.0625 Gbaud signal that is fed to the shift register. The data is then transmitted
differentially at PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9.
transmission latency
The data transmission latency of the SN75FC1000 is defined as the delay from the initial 10-bit word load to
the serial transmission of bit 9. The typical transmission latency is 13 ns.
data reception
The receiver of the SN75FC1000 deserializes 1.0625 Gbps differential serial data. The 8b/10b data (or
equivalent) is retimed based on an extracted clock from the serial data. The serial data is then aligned to the
10-bit word boundaries and presented to the protocol controller along with two receive byte clocks (RBC0,
RBC1). RBC0 and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered
1.0625 Gbps (531 MHz) clock by 10 providing for two 53-MHz signals. The receiver presents the protocol device
byte 0 of the received data valid on the rising edge of RBC1.
NOTE:
This allows the option of byte alignment without the use of the synchronous detection
(SYNC) function by the protocol device.
The receiver PLL can lock to the incoming 1.0625 GHz data without the need for a lock-to-reference preset. The
received serial data rate (RX+ and RX–) should be 1.0625 Gbps ±0.01% (100 ppm) for proper operation.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
data reception (continued)
During a bus error condition or word alignment, the receive byte clocks RBC0 and RBC1 are stretched (never
truncated), ensuring that their frequency never exceeds 60 MHz. When the incoming serial data does not meet
its frequency requirements, then the receive byte clock frequency is maintained and never exceeds 60 MHz.
receive PLL operation
The receive PLL provides automatic locking to the incoming data. At power-up, the maximum initial lock time
is500µs. ThePLLcanalsobeinitiatedorsettophaselocktotheexternallysuppliedreferenceclockbyenabling
lock-to-reference (LCKREFN). The lock-to-reference causes the receive PLL to lock to 10× the reference clock
(REFCLK) input providing a PLL preset and reset capability.
If during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data
and/or a frequency wander of up to 200 ppm, then the PLL recovers lock within 2.4 µs (2500 serial bit times).
Any condition exceeding these values is considered a power-up scenario and the PLL recovers lock within
500 µs.
receiver word alignment
The SN75FC1000 uses a 10-bit K28.5 character (comma character) word alignment scheme. The following
sections explain how this scheme works and how it realigns itself.
comma character on expected boundary
The SN75FC1000 provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment
is enabled by forcing SYCNEN high. This enables the function that examines and compares ten bits of serial
input data to the K28.5 synchronization character. The K28.5 character is defined in the fibre channel standard
as a pattern consisting of 0011111010 (a negative number beginning disparity) with the 7 MSBs (0011111)
referred to as the comma character. The K28.5 character was implemented specifically for aligning fibre
channel data words. As long as the K28.5 character falls within the expected 10-bit word boundary, the received
10-bit data is properly aligned and data realignment is not required. Figure 1 shows the timing characteristics
of RBC0, RBC1, SYNC and RD0 – RD9 while synchronized.
NOTE:
The K28.5 character is valid on the rising edge of RBC1.
RBC0
RBC1
SYNC
RD0 – RD9
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
Figure 1. Synchronous Timing Characteristics Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
comma character not on expected boundary
When synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then
word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character
following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown
in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched
or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra
10 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1
instead of the rising edge. Fibre channel compliant systems transmit a minimum of three consecutively ordered
K28.5 data sets between frames and ensure that the receiver sees at least two of K28.5 sets (the fabric is
allowed
to
drop
one).
Figure 2 shows the timing characteristics of the data realignment.
Systems that do not require framed data can disable byte alignment by tying SYNCEN low.
When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K28.5
character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK
period.
Typical Receive
Path Latency = 21 ns
Serial Rx Data Stream
DIN_RxP – DIN_RxN
K28.5
Dxx.x Dxx.x
K28.5
Dxx.x Dxx.x
Dxx.x
K28.5
Dxx.x Dxx.x
10 Bit Times
20 Bit Times
(MAX)
10 Bit Times
RBC0
RBC1
Corrupted Data
Worst Case
Misaligned K28.5
Misalignment
Corrected
RD0 – RD9
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x Dxx.x
K28.5
SYNC
Figure 2. Word Realignment Timing Characteristics Waveforms
data reception latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The receive latency is typically 21 ns.
loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loop-back path.
Enabling LOOPEN causes serially transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. The external differential output is
held in a static state during loop-back testing.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
†
absolute maximum ratings
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V
CC
Input voltage, V (TTL, PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V
I
Input voltage, V (I/O Terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 5.5 V
I
Output current I (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Output current I (PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Voltage range at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
+ 0.5 V
CC
Electrostatic discharge, 5-V tolerant terminals (see Note 2) . . . . . . . . . . . . . . . . . . . Class 1, A:1 kV, B:150 V
Electrostatic discharge, all other terminals (see Note 2) . . . . . . . . . . . . . . . . . . . . . . Class 1, A:2 kV, B:200 V
Characterized free-air operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.
2. This parameter is tested in accordance with MIL-PRF-38535.
recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
Supply voltage, V
3.14
3.3
3.47
250
V
CC
(static)
†
Supply current, I
Static pattern
160
mA
CC
Power dissipation, P (static)
Outputs open,
(static pattern)
530
230
760
875
310
1085
70
mW
mA
mW
°C
D
†
Supply current, I
(dynamic)
K28.5
CC
Outputs open,
(K28.5)
Power dissipation, P (dynamic)
D
Operating free-air temperature, T
0
A
†
Power (static pattern) = 106.25 MHz to receiver and 5 ones and 5 zeros to transmitter.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
reference clock (REFCLK) timing requirements over recommended operating conditions (unless
†
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
MHz
ppm
Frequency
Accuracy
Duty cycle
Jitter
106.25
–100
40%
100
60%
40
50%
Random and deterministic
ps
†
This clock should be crystal referenced to meet the requirements of the this table. The maximum rate of frequency change specified is valid after
10 seconds from power on.
electrical characteristics over recommended operating conditions (unless otherwise noted)
TTL Signals: TD0 – TD9, REFCLK, LOOPEN, SYNCEN, SYNC, RD0 – RD9, RBC0, RBC1, LCKREFN
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
TYP
3
MAX
UNIT
V
V
V
V
V
V
V
= MIN,
= MIN,
I
= –400 µA
2.4
OH
OL
IH
CC
OH
OL
Low-level output voltage
High-level input voltage
Low-level input voltage
I
= 1 mA
0.25
0.4
5.5
0.8
40
V
CC
2
V
V
IL
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.4 V
µA
µA
µA
µA
pF
I
I
IH
Input High current
REFCLK
REFCLK
= MAX, V = 2.4 V
900
I
= MAX, V = 0.4 V
–40
I
I
IL
Input Low current
Input capacitance
= MAX, V = 0.4 V
–900
I
c
4
i
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
TRANSMITTER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
1200
1200
TYP
MAX
2200
2200
UNIT
R
R
R
= 75 Ω,
= 50 Ω,
= 75 Ω
See Figure 3
See Figure 3
L
L
L
|V
|
Differential driver output voltage (peak-to-peak)
Driver common-mode output voltage
mV
OD
V
OC
2100
mV
differential switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
Serial data deterministic jitter (peak-to-peak)
Serial data total jitter (peak-to-peak)
Differential signal rise time (20% to 80%)
Differential signal fall time (20% to 80%)
TEST CONDITIONS
Differential output jitter
Differential output jitter
MIN
TYP
MAX
75
UNIT
ps
197
300
300
ps
t
t
ps
R
= 75 Ω,
C
= 5 pF,
L
r3
f3
L
See Figure 3
ps
80%
50%
20%
≈V
≈V
– 0.7 V
– 1.6 V
CC
TX+
CC
t
f
t
r
80%
50%
20%
≈V
≈V
– 0.7 V
– 1.6 V
CC
TX–
CC
t
r
t
f
80%
50%
20%
≈1 V
V
OD
≈–1 V
t
f3
t
r3
Figure 3. Differential and Common-mode Output Voltage Definitions
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
TRANSMITTER SECTION
transmitter timing requirements over recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS
See Figure 4
MIN
2
NOM
MAX
UNIT
ns
t
t
Setup time, TD0 – TD9 valid to REFCLK ↑
Hold time, REFCLK ↑ to TD0 – TD9 invalid
Parallel-to-serial data latency
su1
h1
See Figure 4
1.5
ns
13
ns
transmit interface timing
The transmit interface is defined in the 10 b specification as the 10-bit parallel data input to the physical layer
forserialtransmission. ThetimingvaluesarespecifiedfromREFCLKmidpointtovalidinputsignallevelsorfrom
valid input signal levels to REFCLK midpoint.
50%
REFCLK
t
su1
t
h1
TD0 – TD9
Valid
Valid
Valid
Figure 4. Transmit 10-Bit Interface Timing Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
RECEIVER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
Differential input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
|V
|
200
1300
mV
ID
receiver and phase-locked loop performance characteristics over recommended operating
conditions (unless otherwise noted)
†
MAX UNIT
PARAMETER
Jitter tolerance (input data eye closure)
TEST CONDITIONS
See FC-PH-0 specification
From power up
MIN
TYP
70%
500
UI
us
ns
Data acquisition lock time
Data relock time
From synchronization loss
2500
†
UI is the unit interval of a single bit (941 ps).
receive clock timing requirements over recommended operating condtions (unless otherwise
noted)
PARAMETER
Clock frequency, RCLK (0)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
f
53.125
MHz
clk
Clock frequency, RCLK (1)
(180 deg out of phase with RCLK (0))
53.125
MHz
ns
clk
Data rise time
See Figure 5
0.7
4
t
r4
See Figure 5
See Figure 5
See Figure 5
0.7
0.7
0.7
40%
8.9
3
4
2
ns
ns
ns
t
t
t
Data fall time
f4
r5
f5
Rise time, single-ended output signal on RCLK
Fall time, single-ended output signal on RCLK
Duty cycle, RCLK
2
60%
9.9
t
t
t
t
t
Skew time, RCLK(1) ↑ to RCLK(0) ↑
Setup time, RD0 – RD9 valid to RCLK(0) ↑
Setup time, RD0 – RD9 valid to RCLK(1) ↑
Setup time, RCLK(1) ↑ to RD0 – RD9 invalid
Setup time, RCLK(0) ↑ to RD0 – RD9 invalid
Serial-to-parallel data latency
See Figure 6
See Figure 6
See Figure 6
See Figure 6
See Figure 6
9.4
21
ns
ns
ns
ns
ns
ns
(skew)
su2
3
su3
1.5
1.5
su4
su5
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
RECEIVER SECTION
80%
50%
20%
Data
t
f4
t
r4
80%
50%
20%
Clock
t
f5
t
r5
Figure 5. Receiver Data Measurement Levels
t
(skew)
50%
50%
RCLK(0)
RCLK(1)
50%
50%
t
su2
t
t
su3
t
su5
su4
RD0 – RD9
Valid
Valid
Valid
Valid
Valid
Figure 6. Receiver Interface Timing Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
APPLICATION INFORMATION
Ferrite Bead
Ferrite Bead
3.3 V
3.3 V
50
18
5 Ω at 100 MHz
0.01 µF
V
CC
_RX
V
CC
_TX
0.01 µF
15
62
51
GND_RX
GND_TX
SN75FC1000
Controlled Impedance
Transmission Line
DOUT_TXP
DOUT_TXN
R
(pd)
(see Note A)
10
/
TD0 – TD9
61
54
Controlled Impedance
Transmission Line
22
27
19
24
47
REFCLK
LCKREFN
Host
Protocol
Device
LOOPEN
SYNCEN
SYNC
Controlled Impedance
Transmission Line
DOUT_RXP
10
/
RD0 – RD9
RBC0,RBC1
2
/
31,30
50 Ω – 75 Ω
V
t
(see Note B)
52
Controlled Impedance
Transmission Line
DOUT_RXN
49
48
16
17
RC1
RC0
TC1
TC0
PLL Filter
Capacitor
= 2 nF
PLL Filter
Capacitor
= 2 nF
NOTES: A. R(pd) – This value is set to match the falling edge to rising edge transistion times, typically 150 Ω.
B. V (termination voltage): for termination R = 50 Ω, V = V – 1.3 V; R = 75 Ω, V = GND
t
t
CC
t
Figure 7. Typical Application Circuit
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
The SN75FC1000 incorporates the latest development in TI’s package line. The new patent-pending design,
designated the PWP delivers thermal performance comparative to a heat-spreader design in a true low-profile
package. The PWP, for the SN75FC1000 is designed to maximize heat transfer away from the die through the
top of the chip. As seen in Figures 9 and 10 the bottom of the leadframe is deep downset towards the top of
the chip, providing a thermal path away from the die and board. All this has been accomplished without
exceeding the 1.15 mm height of the TQFP. This package in the 10mm × 10mm TQFP (PJD) provides a thermal
resistance R
of 40°C/W and the package in the 14mm × 14mm TQFP (PHD) provides a R
of 40°C/W.
θJA
θJA
Figure 8. Heat-Spreader Design
Figure 9. Leadframe Downset
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
PHD (S-PQFP-G64)
PowerPAD PLASTIC QUAD FLATPACK (DIE DOWN)
0,40
0,30
0,80
M
0,20
48
33
32
49
Thermal Pad
(see Note D)
0,13 NOM
64
17
Gage Plane
1
16
0,25
12,00 TYP
0,15
0°–7°
14,05
SQ
0,05
13,95
0,75
0,45
16,15
SQ
15,85
1,05
0,95
Seating Plane
0,10
1,20 MAX
4087742/A 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
PJD (S-PQFP-G64)
PowerPAD PLASTIC QUAD FLATPACK (DIE DOWN)
0,27
0,17
M
0,08
0,50
48
33
49
32
Thermal Pad
(See Note D)
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
0,25
11,80
0,15
0,05
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4147703/A 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN75FC1000PHD
SN75FC1000PJD
OBSOLETE HTQFP
OBSOLETE HTQFP
PHD
64
64
TBD
TBD
Call TI
Call TI
Call TI
Call TI
PJD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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