SN75LVCP601RTJT [TI]
Two-Channel SATA 6-Gb/s Redriver; 双通道SATA 6 Gb / s的转接驱动器
| 型号： | SN75LVCP601RTJT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Two-Channel SATA 6-Gb/s Redriver |
| 文件： | 总23页 (文件大小：2189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
Two-Channel SATA 6-Gb/s Redriver
Check for Samples: SN75LVCP601
1
FEATURES
•
•
•
1.5/3/6-Gbps Two-Channel Redriver
•
•
20-Pin 4-mm × 4-mm QFN Package
High Protection Against ESD Transient
Integrated Output Squelch
Programmable Rx/Tx Equalization and
De-Emphasis Width Control
–
–
–
HBM: 10,000 V
CDM: 1,500 V
MM: 200 V
•
•
Power-Save Feature Lowers Power by >80% in
Auto Low-Power Mode
•
Pin-Compatible to LVCP412A/MAX4951
Low Power
–
–
–
<220 mW Typ.
APPLICATIONS
<50 mW (in Auto Low-Power Mode)
<5m W (in Standby Mode)
•
Notebooks, Desktops, Docking Stations,
Servers, and Workstations
•
Excellent Jitter and Loss Compensation
Capability to Over 24-Inch (61-cm) FR4 Trace
DESCRIPTION
The SN75LVCP601 is a dual-channel, single-lane SATA redriver and signal conditioner supporting data rates up
to 6 Gbps. The device complies with SATA physical link 2m and 3i specifications. The SN75LVCP601 operates
from a single 3.3-V supply and has 100-Ω line termination with a self-biasing feature, making the device suitable
for ac coupling. The inputs incorporate an out-of-band (OOB) detector, which automatically squelches the output
while maintaining a stable common-mode voltage compliant to the SATA link. The device is also designed to
handle spread-spectrum clocking (SSC) transmission per the SATA specification.
The SN75LVCP601 handles interconnect losses at both its input and output. The input stage of each channel
offers selectable equalization settings that can be programmed to match the loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the distortion that the SATA signal is expected to
experience. The level of equalization and de-emphasis settings depends on the length of interconnect and its
characteristics. Both equalization and de-emphasis levels are controlled by the setting of signal control pins EQ1,
EQ2, DE1, and DE2.
The device is hot-plug capable (requires the use of ac-coupling capacitors at differential inputs and outputs),
preventing device damage under device hot-insertion, such as async signal plug/removal, unpowered
plug/removal, powered plug/removal, or surprise plug/removal.
ORDERING INFORMATION(1)
PART NUMBER
SN75LVCP601RTJR
SN75LVCP601RTJT
PART MARKING
PACKAGE
LVC601
20-pin RTJ, reel (large)
20-pin RTJ, reel (small)
LVC601
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN75LVCP601
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PC/WS MB
ICH
HDD
R
PC/Workstation
Motherboard
eSATA
connector
eSATA
Cable
R = SN75LVCP601
HDD
ICH
eSATA
connector
R
eSATA Cable
(2m)
Notebook
Dock
Notebook Dock
iSATA
connector
HDD
SATA 6G Host
R
DT MB
Desktop Main Board
Figure 1. Typical Application
2
Copyright © 2010–2012, Texas Instruments Incorporated
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
GND[3,13,18]
VBB = 1.7 V TYP
RT
RX1P [1]
RX1N [2]
TX1P [15]
TX1N [14]
RT
VBB
SN75LVCP601
RT
RX2N [12]
RX2P [11]
TX2N [4]
TX2P [5]
RT
DEW1 [16]
DEW2 [6]
CTRL
EQ1[17]
DE1[9]
VCC[10,20]
EQ2[19]
DE2[8]
EN[7]
Figure 2. Data Flow Block Diagram
PIN TABLE
NAME
RX1P
RX1N
GND
PIN DESCRIPTION
NAME
RX2P
RX2N
GND
PIN
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
1
2
3
4
5
6
7
8
9
Input 1, non-inverting
Input 2, non-inverting
Input 2, inverting
Ground
Input 1, inverting
Ground
TX2N
TX2P
DEW2(1)
EN(1)
DE2(2)
DE1(2)
Vcc
Output 2, inverting
Output 2, non-inverting
De-emphasis width cntrl.-CH 2
Enable
TX1N
TX1P
DEW1(1)
EQ1(2)
GND
Output 1, inverting
Output 1, non-inverting
De-emphasis width cntrl.-CH 1
EQ control CH 1
Ground
De-emphasis CH2
De-emphasis CH1
EQ2(2)
EQ control CH 2
3.3-V supply
10 3.3-V supply
Vcc
(1) DEW1/2, EN tied to Vcc via internal PU resistor
(2) DE1, DE2, EQ1, EQ2 are tied to Vcc/2 via internal resistor
Copyright © 2010–2012, Texas Instruments Incorporated
3
SN75LVCP601
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
PACKAGE PINOUT
www.ti.com
Bottom View
Top View
20
6
7
16
17
18
19
20
10
9
VCC
DEW 1
EQ 1
VCC
DEW 2
LVCP601RTJ
19
EQ 2
EN
DE 1
DE 2
EN
Thermal Pad must
be soldered to PCB
18
8
8
GND
GND
LVCP601RTJ
DE 2
GND plane for
efficient thermal
performance
17
16
9
7
EQ 1
EQ 2
VCC
DE 1
VCC
10
6
DEW 1
DEW 2
PIN FUNCTIONS
PIN
PIN TYPE
DESCRIPTION
NO.
NAME
HIGH-SPEED DIFFERENTIAL I/O
2
RX1N
RX1P
RX2N
RX2P
TX1N
TX1P
TX2N
TX2P
I, CML
1
I, CML
I, CML
I, CML
O, VML
O, VML
O, VML
O, VML
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are
tied to an internal voltage bias by a dual-termination resistor circuit.
12
11
14
15
4
Non-inverting and inverting VML differential output for CH 1 and CH 2. These pins are
internally tied to voltage bias by termination resistors.
5
CONTROL PINS
7
EN
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Device enable/disable pin, internally pulled to VCC. See Table 2.
8, 9
DE1, DE2(1)
EQ1, EQ2(1)
DEW1, DEW2
Selects de-emphasis settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
Selects equalization settings for CH 1 and CH 2 per Table 1. Internally tied to VCC/2
De-emphasis width control for CH 1 and CH 2. See Table 2.
17, 19
16, 6
POWER
10, 20
3, 13, 18
Vcc
Power
Power
Positive supply should be 3.3 V ± 10%.
GND
Supply ground
(1) Internally biased to Vcc/2 with >200-kΩ pullup/pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA;
otherwise, drive to Vcc/2 to assert mid-level state.
4
Copyright © 2010–2012, Texas Instruments Incorporated
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
Table 1. Tx/Rx EQ and DE Pulse-Duration Settings
CH1/CH2De-Emphasis
dB (at 6Gbps)
CH1/CH2Equalization
dB (at 6Gbps)
DE1/DE2
EQ1/EQ2
NC (default)
–4
0
NC (default)
0
7
0
1
0
1
–2
14
DEW1/DEW2
Device Function → DE Width for CH1/CH2
0
De-emphasis pulse duration, short (recommended setting when link operates at SATA
1.5/3/6 Gbps)
1 (default)
De-emphasis pulse duration, long (recommended setting when link operates at SATA
1.5/3 Gbps speed only)
Table 2. Control Pin Settings
EN
Device Function → Standby Mode
Device in standby mode
0
1 (default) Device enabled
24 in. (61 cm)
Redriver
SATA Host
SATA
Connector
16 in. (40.6 cm)
8 in.
(20.3 cm)
Redriver on Motherboard
24 in. (61 cm)
SATA Host
Redriver
Main Board
SATA
Connector
Dock Board
8 in.
(20.3 cm)
16 in. (40.6 cm)
Redriver on Dock Board
NOTE: *Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ and
output de-emphasis) to meet SATA loss and jitter spec.
Actual trace length supported by the LVCP601 may be more or less than suggested values and depends on board
layout, trace widths, and number of connectors used in the SATA signal path.
Figure 3. Trace Length Example* for LVCP601
Copyright © 2010–2012, Texas Instruments Incorporated
5
SN75LVCP601
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
www.ti.com
3.3V
10nF
10nF
1
2
3
4
5
15
RX1P
RX1N
TX1P
TX1N 14
10nF
10nF
10nF
10nF
13
LVCP601 RTJ
RX2N
RX2P
12
11
TX2N
TX2P
10nF
10nF
(1) Place supply capacitors close to device pin.
(2) EN can be left open or tied to supply when no external control is implemented.
(3) Output de-emphasis selection is set at –2 dB, EQ at 7 dB, and DE duration for SATA I/II/III operation for both
channels.
(4) Actual EQ/DE duration settings depend on device placement relative to host and SATA connector.
Figure 4. Typical Device Implementation
OPERATION DESCRIPTION
INPUT EQUALIZATION
Each differential input of the SN75LVCP601 has programmable equalization in its front stage. The equalization
setting is shown in Table 1. The input equalizer is designed to recover a signal even when no eye is present at
the receiver, and effectively supports FR4 trace at the input anywhere from 4 in. (10.2 cm) to 20 in. (50.8 cm) at
SATA 6G speed.
OUTPUT DE-EMPHASIS
The SN75LVCP601 provides the de-emphasis settings shown in Table 1. De-emphasis is controlled
independently for each channel, and is set by the control pins DE1 and DE2 as shown in Table 1. There are two
de-emphasis duration settings available in the device. DEW1 and DEW2 control the DE durations for channels
one and two, respectively. The recommended settings for these control pins are listed Table 1. Output
de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1 cm) to 12 in. (30.5 cm) at
SATA 3G/6G speed.
LOW-POWER MODE
Two low-power modes are supported by the SN75LVCP601, listed as follows:
1. Standby mode (triggered by the EN pin, EN = 0 V)
–
Low-power mode is controlled by the enable (EN) pin. In its default state, this pin is internally pulled high.
Pulling this pin LOW puts the device in standby mode within 2 µs (max). In this mode, all active
components of the device are driven to their quiescent level, and differential outputs are driven to Hi-Z
(open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode to normal operation
requires a maximum latency of 5 µs.
6
Copyright © 2010–2012, Texas Instruments Incorporated
SN75LVCP601
www.ti.com
SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs
and EN = Vcc)
–
The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p < 50 mV and stays in this state for >100 µs, the associated channel(s) enters
into the low-power state. In this state, output of the associated channel(s) is driven to VCM and the
device selectively shuts off some circuitry to lower power by >80% of its normal operating power. Exit
time from the auto low-power mode is <50 ns.
Out-of-Band (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. Differential signal amplitude at the receiver input of 50 mVpp or less is not detected as an activity
and hence not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity
and therefore passed to the output, indicating activity. Squelch circuit ON/OFF time is 5 ns, maximum. While in
squelch mode, outputs are held to VCM.
DEVICE POWER
The SN75LVCP601 is designed to operate from a single 3.3 V supply. Always practice proper power-supply
sequencing procedure. Apply Vcc first, before any input signals are applied to the device. The power-down
sequence is in reverse order.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.5 to 4
UNIT
V
Supply voltage range(2)
Voltage range
VCC
Differential I/O
Control I/O
Human-body model(3)
Charged-device model(4)
Machine model(5)
–0.5 to 4
V
–0.5 to Vcc + 0.5
±10,000
V
V
Electrostatic discharge
±1500
V
±200
V
Continuous power dissipation
See Thermal Table
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
THERMAL INFORMATION
SN75LVCP601
THERMAL METRIC(1)
QFN
20 PINS
38
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
°C/W
°C/W
°C/W
θJCtop
θJB
40
10
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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UNITS
THERMAL INFORMATION (continued)
SN75LVCP601
THERMAL METRIC(1)
QFN
20 PINS
0.5
ψJT
Junction-to-top characterization parameter(5)
°C/W
°C/W
°C/W
mW
ψJB
θJCbot
PD
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
Device power dissipation in active mode
0.9
15.2
215 to 288
5
PSD
Device power dissipation under standby mode
mW
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
(Typical values for all parameters are at VCC = 3.3V and TA = 25°C. All temp limits are specified by design)
PARAMETER
Supply voltage
CONDITIONS
MIN
TYP
3.3
12
MAX UNITS
VCC
3
3.6
V
CCOUPLING
Coupling capacitor
nF
°C
Operating free-air temperature
0
85
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DEVICE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEWx = EN = Vcc, EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID = 700 mVp-p
PD
Power dissipation in active mode
215
288
5
mW
mW
mA
mA
Power dissipation in standby
mode
EN = 0 V, DEWx = EQx = DEx = NC, K28.5
pattern at 6 Gbps, VID = 700 mVp-p
PSD
ICC
EN = 3.3 V, DEWx= 0 V, EQx/DEx = NC,
K28.5 pattern at 6 Gbps, VID = 700 mVp-p
Active-mode supply current
Acive power-save mode ICC
65
80
10
When device is enabled and auto low-power
conditions are met
ICC_ALP
6.5
ICC_STDBY
Standby mode supply current
Maximum data rate
EN = 0 V
1
6
mA
Gbps
ps
1
323
105
42
tPDelay
Propagation delay
Measured using K28.5 pattern. See Figure 8.
Electrical idle at input; see Figure 9.
After first signal activity; see Figure 9.
EN 0→1
400
130
50
5
AutoLPENTRY
AutoLPEXIT
tENB
Auto low-power entry time
Auto low-power exit time
Device enable time
80
µs
ns
µs
tDIS
Device disable time
EN 1→0
2
µs
8
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
OUT-OF-BAND (OOB)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOOB
Input OOB threshold
OOB differential delta
OOB common-mode delta
OOB mode enter
f = 750 MHz
50
78
150
25
50
5
mVpp
mV
mV
ns
DVdiffOOB
DVCMOOB
tOOB1
See Figure 9.
For all control pins
3
3
tOOB2
OOB mode exit
5
ns
CONTROL LOGIC
VIH
Input high voltage
Input low voltage
Input hysteresis
1.4
V
V
VIL
0.5
VINHYS
115
mV
EQx, DEx = Vcc
EN, DEWx = Vcc
EQx, DEx = GND
EN, DEWx = GND
30
1
IIH
High-level input current
Low-level input current
µA
µA
–30
–10
IIL
RECEIVER AC/DC
ZDIFFRX
Differential-input impedance
Single-ended input impedance
Common-mode voltage
85
40
100
115
Ω
Ω
V
ZSERX
VCMRX
1.8
28
17
12
9
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
18
14
10
8
RLDiffRX
RXDiffRLSlope
RLCMRX
VdiffRX
Differential-mode return loss (RL) f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
dB
f = 2.4 GHz–3 GHz
3
9
Differential-mode RL slope
Common-mode return loss
Differential input voltage PP
f = 300 MHz–6 GHz (See Figure 5.)
–13
10
17
23
16
12
dB/dec
dB
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
f = 2.4 GHz–3 GHz
f = 1.5 GHz and 3 GHz
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
f = 2.4 GHz–3 GHz
f = 3 GHz–5 GHz
5
5
2
1
1
120
30
30
20
10
10
4
1600
mVppd
41
38
32
26
25
20
17
IBRX
Impedance balance
dB
f = 5 GHz–6.5 GHz
4
Rise times and fall times measured between
20% and 80% of the signal. SATA 6-Gbps
speed measured 1 in, (2.5 cm) from device
pin
t20-80RX
Rise/fall time
62
75
30
ps
ps
Difference between the single-ended
midpoint of the RX+ signal rising/falling edge,
and the single-ended midpoint of the RX–
signal falling/rising edge
tskewRX
Differential skew
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TRANSMITTER AC/DC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ZdiffTX
ZSETX
Pair differential impedance
Single-ended impedance
85
40
100
122
Ω
Ω
Transient voltages on the serial data bus
during power sequencing (lab load)
VTXtrans
Sequencing transient voltage
–1.2
1.2
V
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
f = 2.4 GHz–3 GHz
14
8
24
19
14
10
10
–13
20
19
17
12
11
41
38
33
24
26
22
21
RLDiffTX
Differential-mode return loss
Differential-mode RL slope
Common-mode return loss
6
dB
dB/dec
dB
6
3
TXDiffRLSlope
f = 300 MHz–3 GHz (SeeFigure 5.)
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
f = 2.4 GHz–3.0 GHz
f = 150 MHz–300 MHz
f = 300 MHz–600 MHz
f = 600 MHz–1.2 GHz
f = 1.2 GHz–2.4 GHz
f = 2.4 GHz–3 GHz
5
5
RLCMTX
2
1
1
30
30
20
10
10
4
IBTX
Impedance balance
dB
f = 3 GHz–5 GHz
f = 5 GHz–6.5 GHz
4
f = 3 GHz, DE1/DE2 = 0, DEWx = NC,
(under no interconnect loss)
DiffVppTX
Differential output-voltage swing
Output de-emphasis
550
mVppd
dB
f = 3 GHz, DE1/DE2 = 0
f = 3 GHz, DE1/DE2 = 1
f = 3 GHz, DE1/DE2 = NC
DEWx = 0
0
–2
DE
–4
94
tDE
De-emphasis duration
TX AC CM voltage
ps
DEWx = 1
215
20
At 1.5 GHz
50
26
30
mVppd
VCMAC_TX
At 3 GHz
12
dBmV
(rms)
At 6 GHz
13
VCMTX
t20-80TX
Common-mode voltage
Rise/fall time
1.8
V
Rise times and fall times measured between
20% and 80% of the signal. At 6Gbps under
no load conditions
42
55
6
75
20
ps
Difference between the single-ended
mid-point of the TX+ signal rising/falling
edge, and the single-ended mid-point of the
TX- signal falling/rising edge.
tskewTX
Differential skew
ps
TxR/FImb
TX rise-fall imbalance
At 3 Gbps
6%
2%
20%
10%
TxAmpImb
TX amplitude imbalance
10
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSMITTER JITTER
Deterministic jitter(1) at CP in
Figure 6
VID = 500 mVpp, UI = 333 ps,
K28.5 control character
DJTX
RJTX
DJTX
RJTX
0.06
0.01
0.08
0.09
0.19
2
UIp-p
ps-rms
UIp-p
VID = 500 mVpp, UI = 333 ps,
K28.7 control character
Residual random jitter(1)
Deterministic jitter(1) at CP in
Figure 6
VID = 500 mVpp, UI = 167 ps,
K28.5 control character
0.34
2
VID = 500 mVpp, UI = 167 ps,
K28.7 control character
Residual random jitter(1)
ps-rms
(1) TJ = (14.1 × RJSD + DJ), where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the SATA
connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown
in Figure 6.
Figure 5. TX, RX Differential Return Loss Limits
Jitter
Measurement
CP
8" 6 mil Stripline
12" 6mil
Stripline
1
AWG*
2
CP
AWG*
CP = Compliance point
Jitter
Measurement
Figure 6. Jitter Measurement Test Condition
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IN
tPDelay
tPDelay
OUT
Figure 7. Propagation Delay Timing Diagram
IN+
50 mV
Vcm
IN-
tOOB2
tOOB1
OUT+
Vcm
OUT-
Figure 8. OOB Enter and Exit Timing
RX1,2P
RX1,2N
TX1,2P
TX1,2N
VCM
RX
t
OOB1
AutoLP
EXIT
VCM
TX
AutoLP
Power Saving
Mode
ENTRY
Figure 9. Auto Low-Power Mode Enter and Exit Timing
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SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
1-bit
1 to N bits
1 to N bits
1-bit
tDE
0 dB
-2 dB
-4 dB
DiffVppTX_DE
DiffVppTX
tDE
Figure 10. TX Differential Output De-Emphasis
SN75LVCP601 TYPICAL PERFORMANCE CURVE
•
•
Input signal characteristics
–
–
–
Data rate = 6 Gbps, 3 Gbps, 1.5 Gbps
Amplitude = 500 mVp-p
Data pattern = K28.5
SN75LVCP601 device setup
–
–
–
–
Temperature = 25°C
Voltage = 3.3 V
De-emphasis duration = 117 ps (short)
Equalization and de-emphasis set to optimize performance at 6 Gbps
With LVCP601
16-in., 4-mil (40.6-cm, 0.101-mm)
8-in., 4-mil (20.3-cm, 0.101-mm)
FR4 Trace +
FR4 Trace +
2-in., 9.5-mil (5.05-cm, 0.241-mm)
FR4 Trace
2-in., 9.5-mil (5.05-cm, 0.241-mm)
FR4 Trace
Agilent
DCA -J
Agilent
ParBERT
LVCP601
TP3
TP4
TP2
TP1
EQ = 14 dB
DE = –2 dB
Without LVCP601
16-in., 4-mil (40.6-cm, 0.101-mm) FR4 Trace +
4-in., 9.5-mil (10.1-cm, 0.241-mm) FR4 Trace +
8-in., 4-mil (20.3-cm, 0.101-mm) FR4 Trace
Agilent
DCA -J
Agilent
ParBERT
TP1
TP4
Figure 11. Performance Curve Measurement Setup
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SN75LVCP601 TYPICAL PERFORMANCE CURVE (continued)
TJ
(1e-12)
ps
DJ
(δ-δ)
ps
RJ
(rms)
ps
Eye
Amplitude
mV
Eye
Width
ps
Eye
Opening
mV
Eye
Diagram
Test Point
TP1
29.0
91.8
42.0
39.0
56.7
3.3
1.88
1.93
1.91
1.92
2.00
412.4
159.2
350.52
TP2
65.4
15.9
12.7
29.8
240
28.9
81.24
TP3
788.8
557.1
165.4
141.3
149.7
101
623.02
459.62
13.24
TP4
With
LVCP601
TP4
Without
LVCP601
Figure 12. Jitter and VOD Results: Case 1 at 6 Gbps
TJ
(1e-12)
ps
DJ
(δ-δ)
ps
RJ
(rms)
ps
Eye
Amplitude
mV
Eye
Width
ps
Eye
Opening
mV
Eye
Diagram
Test Point
TP1
29.7
72.7
39.6
47.9
128.6
3.8
46.8
12.8
20.3
101.8
1.89
1.89
1.96
1.99
1.96
430.9
314.9
714.5
615.3
258.8
326
392.84
222.36
611.62
463.42
122.26
TP2
237
TP3
321
TP4
305.0
118
With
LVCP601
TP4
Without
LVCP601
Figure 13. Jitter and VOD Results: Case 2 at 3 Gbps
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SN75LVCP601
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SLLSE41B –JUNE 2010–REVISED FEBRUARY 2012
SN75LVCP601 TYPICAL PERFORMANCE CURVE (continued)
TJ
(1e-12)
ps
DJ
(δ-δ)
ps
RJ
(rms)
ps
Eye
Amplitude
mV
Eye
Width
ps
Eye
Opening
mV
Eye
Diagram
Test Point
TP1
34.3
67.5
44.9
57.3
113.3
3.4
2.26
2.11
2.31
2.62
2.30
448
659
417.28
318.48
604.02
442.42
217.46
TP2
38.6
13.2
21.5
81.9
363.4
753.1
672.8
322.8
589
TP3
649
TP4
632.0
493
With
LVCP601
TP4
Without
LVCP601
Figure 14. Jitter and VOD Results: Case 3 at 1.5 Gbps
TYPICAL CHARACTERISTICS
RESIDUAL DJ AND EYE OPENING
vs
INPUT TRACE LENGTH
14
12
10
8
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
G001
6
4
Residual DJ 3Gbps
Residual DJ 6Gbps
Eye Opening 3Gbps
Eye Opening 6Gbps
2
0
2
4
6
8
10
12
14
16
18
20
22
Input Trace Length (in)
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
RESIDUAL DJ AND EYE OPENING
vs
OUTPUT TRACE LENGTH
40
35
30
25
20
15
10
5
0.8
Residual DJ 3Gbps
Residual DJ 6Gbps
Eye Opening 3Gbps
Eye Opening 6Gbps
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10
12
14
16
18
20
22
Output Trace Length (in)
G002
Figure 16.
SPACER
REVISION HISTORY
Changes from Revision A (October 2011) to Revision B
Page
•
Changed pin type from CML to VML for pins 4, 5, 14, 15 .................................................................................................... 4
Changes from Original (June 2010) to Revision A
Page
•
Changed pin EN number From: 4 To: 7 ............................................................................................................................... 4
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN75LVCP601RTJR
SN75LVCP601RTJT
ACTIVE
ACTIVE
QFN
QFN
RTJ
RTJ
20
20
3000
250
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVCP601RTJR
SN75LVCP601RTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75LVCP601RTJR
SN75LVCP601RTJT
QFN
QFN
RTJ
RTJ
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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