SN75LVDM976CDGGR [TI]
9 LINE TRANSCEIVER, PDSO56;
| 型号： | SN75LVDM976CDGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9 LINE TRANSCEIVER, PDSO56 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总30页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDM976
SN75LVDM977
www.ti.com
SLLS292B–APRIL 1998–REVISED JANUARY 2000
9-CHANNEL DUAL-MODE TRANSCEIVERS
FEATURES
DGG PACKAGE
(TOP VIEW)
•
•
•
9 Channels for the Data and Control Paths of
the Small Computer Systems Interface (SCSI)
INV/NON
GND
CDE2
CDE1
CDE0
9B+
1
56
55
54
53
52
51
50
49
48
47
46
45
Supports Single-Ended and Low-Voltage
Differential (LVD) SCSI
2
GND
3
CMOS Input Levels ('LVDM976) or TTL Input
Levels ('LVDM977) Available
1A
4
1DE/RE
2A
9B–
5
•
•
Includes DIFFSENS Comparators on CDE0
8B+
6
Single-Ended Receivers Include Noise Pulse
Rejection Circuitry
2DE/RE
3A
8B–
7B+
7
8
•
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
3DE/RE
4A
7B–
6B+
9
10
11
12
•
•
•
•
Low Disabled Supply Current 7 mA Maximum
Power-Up/Down Glitch Protection
4DE/RE
6B–
V
V
CC
CC
GND 13
44 GND
Bus is High-Impedance With VCC = 1.5 V
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
GND
GND
GND
GND
GND
GND
Pin-Compatible With the SN75976ADGG
High-Voltage Differential Transceiver
DESCRIPTION
V
CC
V
CC
The SN75LVDM976 and SN75LVDM977 have nine
transceivers for transmitting or receiving the signals
to or from a SCSI data bus. They offer electrical
compatibility to both the single-ended signaling of
X3.277:1996-SCSI-3 Parallel Interface (Fast-20) and
the new low-voltage differential signaling method of
proposed standard 1142-D SCSI Parallel Interface –
2 (SPI-2).
5A
5DE/RE
6A
5B+
5B–
4B+
4B–
3B+
3B–
2B+
2B–
1B+
1B–
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
The differential drivers are nonsymmetrical. The SCSI
bus uses a dc bias on the line to allow terminated fail
safe and wired-OR signaling. This bias can be as
high as 125 mV and induces a difference in the
high-to-low and low-to-high transition times of a
symmetrical driver. In order to reduce pulse skew, an
LVD SCSI driver's output characteristics become
nonsymmetrical. In other words, there is more
assertion current than negation current to or from the
driver. This allows the actual differential signal
voltage on the bus to be symmetrical about 0 V. Even
though the driver output characteristics are
nonsymmetrical, the design of the 'LVDM976 drivers
maintains balanced signaling. Balanced means that
the current that flows in each signal line is nearly
equal but opposite in direction and is one of the keys
to the low-noise performance of a differential bus.
AVAILABLE OPTIONS
PACKAGE
TSSOP (DGG)
TTL INPUTS
LEVELS
TA
TSSOP (DGG)
CMOS INPUT LEVELS
0°C to
70°C
SN75LVDM976DGG
SN75LVDM977DGG
SN75LVDM976DGGR(1) SN75LVDM977DGGR(1)
(1) The R suffix designates a taped and reeled package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2000, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN75LVDM976
SN75LVDM977
www.ti.com
SLLS292B–APRIL 1998–REVISED JANUARY 2000
DESCRIPTION (CONTINUED)
The signal symmetry requirements of the LVD-SCSI bus mean you can no longer obtain logical inversion of a
signal by simply reversing the differential signal connections. This requires the ability to invert the logic
convention through the INV/NON terminal. This input would be a low for SCSI controllers with active-high data
and high for active-low data. In either case, the B+ signals of the transceiver must be connected to the SIGNAL+
line of the SCSI bus and the B- of the transceiver to the SIGNAL- line.
The CDE0 input incorporates a window comparator to detect the status of the DIFFSENS line of a SCSI bus.
This line is below 0.5 V, if using single-ended signals, between 1.7 V and 1.9 V if low-voltage differential, and
between 2.4 V and 5.5 V if high-voltage differential. The outputs assume the characteristics of single-ended or
LVD accordingly or place the outputs into high-impedance, when HVD is detected. This, and the INV/NON input,
are the only differences to the trade-standard function of the SN75976A HVD transceiver.
Two options are offered to minimize the signal noise margins on the interface between the communications
controller and the transceiver. The SN75LVDM976 has logic input voltage thresholds of about 0.5 VCC. The
SN75LVDM977 has a fixed logic input voltage threshold of about 1.5 V. The input voltage threshold should be
selected to be near the middle of the output voltage swing of the corresponding driver circuit.
The SN75LVDM976 and SN75LVDM977 are characterized for operation over an free-air temperature range of TA
= 0°C to 70°C.
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SN75LVDM977
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
LOGIC DIAGRAM (POSITIVE LOGIC)
2.4 V
A
CDE1
(Internal)
+
–
LVD
CDE0
B
–
+
0.5 V
(Internal)
SE
INV/NON
1DEb
1REb
1DE/RE
1DEb
1DEa
1B–
1A
1B+
1DEa
1REa
1REb
1REa
2A
2DE/RE
3A
3DE/RE
4A
2B–
2B+
3B–
3B+
4B–
4B+
Channel 2
Channel 3
Channel 4
4DE/RE
INV/NON
CDE2
SE
LVD
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
5B–
5B+
6B–
6B+
7B–
7B+
8B–
8B+
Channel 5
Channel 6
Channel 7
Channel 8
INV/NON
SE
LVD
9DEb
9REb
9DE/RE
9DEb
9DEa
9B–
9B+
9A
9DEa
9REa
9REb
9REa
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SN75LVDM977
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
LOGIC DIAGRAMS AND FUNCTION TABLES
FUNCTION TABLE
B−
V
ID
A
INPUTS
OUTPUTS
B+
(B+ – B–)
ID ≥ 30 mV
DE/RE
A
B+
Z
B–
Z
A
L
?
DE/RE
V
L
L
NA
NA
–30 mV < VID < 30
mV
Z
Z
VID– 30 mV
Open circuit
NA
L
L
NA
NA
L
Z
Z
H
L
Z
Z
L
H
?
Figure 1. Inverting LVD Transceiver
H
H
Z
Z
NA
H
H
A
B−
FUNCTION TABLE
DE/RE
INPUTS
OUTPUTS
B–
DE/RE
A
NA
NA
NA
L
B+
L
B–
Z
A
H
L
L
L
H
?
B+
L
Open circuit
NA
L
Z
L
L
Z
Figure 2. Inverting Single-Ended Transceiver
H
H
L
H
L
Z
Z
NA
H
L
A
FUNCTION TABLE
B−
INPUT
OUTPUTS
A
L
B+
L
B–
H
B+
H
L
L
Figure 3. Inverting Single-Ended Driver
FUNCTION TABLE
INPUT
OUTPUTS
B−
A
L
B+
H
B–
L
A
B+
H
L
H
Figure 4. Inverting LVD Driver
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
FUNCTION TABLE
B−
B+
INPUT
OUTPUTS
A
A
L
B+
L
B–
H
Figure 5. Noninverting LVD Driver
H
H
L
FUNCTION TABLE
B−
ID
V
A
INPUTS
OUTPUTS
B+
(B+ – B–)
DE/RE
A
B+
Z
B–
Z
A
H
?
DE/RE
VID ≥ 30 mV
L
L
NA
NA
–30 mV < VID < 30
mV
Z
Z
V
ID≤– 30 mV
L
L
NA
NA
L
Z
Z
L
Z
Z
H
L
L
?
Z
Z
Figure 6. Noninverting LVD Transceiver
Open circuit
NA
NA
H
H
H
H
A
B−
FUNCTION TABLE
DE/RE
INPUTS
OUTPUTS
B–
DE/RE
A
NA
NA
NA
L
B+
L
B–
Z
A
H
L
L
H
L
?
Z
Z
B+
L
Open circuit
NA
L
Z
L
L
Z
Figure 7. Noninverting Single-Ended Transceiver
H
H
L
L
NA
H
L
H
B−
B+
A
FUNCTION TABLE
INPUT
OUTPUTS
A
L
B+
L
B–
L
H
L
H
Figure 8. Noninverting Single-Ended Driver
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SN75LVDM977
www.ti.com
SLLS292B–APRIL 1998–REVISED JANUARY 2000
1B−
1B+
1B−
1B+
1B−
1A
1A
1A
2A
3A
4A
1B+
1DE/RE
1DE/RE
2B−
2B+
2B−
2B+
2B−
2A
2A
2B+
2DE/RE
2DE/RE
3B−
3B+
3B−
3B+
3B−
3A
3A
3B+
3DE/RE
3DE/RE
4B−
4B+
4B−
4B+
4B−
4A
4A
4B+
4DE/RE
4DE/RE
5B−
5B+
5B−
5B+
5B−
5A
5A
5A
5B+
5DE/RE
5DE/RE
6B−
6B+
6B−
6B+
6B−
6A
6A
6A
7A
6B+
6DE/RE
6DE/RE
7B−
7B+
7B−
7B+
7B−
7A
7A
7B+
7DE/RE
7DE/RE
8B−
8B+
8B−
8B+
8B−
8A
8A
8A
8B+
8DE/RE
8DE/RE
9B−
9B+
9B−
9B+
9B−
9A
9A
9A
9B+
9DE/RE
9DE/RE
9DE/RE
Control Inputs
Control Inputs
Control Inputs
CDE0 0.7 V < V < 1.9 V
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
I
L
L
L
L
L
H
INV/NON
CDE1
L
H
L
CDE2
CDE2
CDE2
(a)
(b)
(c)
Figure 9. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
1B−
1B+
1B−
1A
1B−
1B+
1A
1A
1B+
1DE/RE
1DE/RE
2B−
2B+
2B−
2A
2B−
2B+
2A
2A
3A
4A
5A
6A
7A
8A
2B+
2DE/RE
2DE/RE
3B−
3B+
3B−
3A
3B−
3B+
3A
3B+
3DE/RE
3DE/RE
4B−
4B+
4B−
4A
4B−
4B+
4A
4B+
4DE/RE
4DE/RE
5B−
5B+
5B−
5A
5B−
5B+
5A
5B+
5DE/RE
6B−
6B+
6B−
6A
6A
6B−
6B+
6B+
6DE/RE
7B−
7B+
7B−
7A
7B−
7B+
7A
7B+
7DE/RE
8B−
8B+
8B−
8A
8B−
8B+
8A
8B+
8DE/RE
9B−
9B+
9B−
9B+
9A
9B−
9A
9A
9DE/RE
9B+
9DE/RE
9DE/RE
Control Inputs
Control Inputs
Control Inputs
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
L
H
H
H
L
L
H
L
CDE2
CDE2
CDE2
H
(a)
(C)
(b)
Figure 10. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
1A
1B−
1A
1B−
1B−
1A
1DE/RE
1DE/RE
1B+
1B+
2B−
1B+
2B−
2A
2A
2B−
2A
2DE/RE
2DE/RE
2B+
2B+
3B−
2B+
3B−
3A
3A
3B−
3A
3DE/RE
3DE/RE
3B+
3B+
4B−
3B+
4B−
4A
4A
4B−
4A
4DE/RE
4DE/RE
4B+
4B+
5B−
4B+
5B−
5A
5A
6A
7A
8A
5B−
5A
5DE/RE
5B+
5B+
5B+
6B−
6A
6B−
6B+
6B−
6A
6DE/RE
6B+
6B+
7B−
7A
7B−
7B+
7B−
7A
7DE/RE
7B+
7B+
8B−
8A
8B−
8B+
8B−
8A
8DE/RE
8B+
8B+
9B−
9A
9A
9B−
9B+
9B−
9A
9DE/RE
9DE/RE
9B+
9DE/RE
9B+
Control Inputs
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
I
I
H
H
H
L
L
L
L
L
H
CDE1
CDE2
CDE1
CDE2
CDE2
(a)
(b)
(c)
Figure 11. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
1A
1B−
1B+
1A
2A
1A
1B−
1B−
1B+
1DE/RE
1B+
2B−
2A
2B−
2B+
2A
2B−
2B+
2DE/RE
2B+
3B−
3A
4A
3B−
3B+
3B−
3B+
3A
4A
5A
6A
3A
3DE/RE
3B+
4B−
4B−
4B+
4A
4B−
4B+
4DE/RE
4B+
5B−
5A
5B−
5A
5B−
5B+
5DE/RE
5DE/RE
5B+
6B−
5B+
6B−
6A
6A
6B−
6B+
6DE/RE
6DE/RE
6B+
7B−
6B+
7B−
7A
7A
8A
7A
7B−
7B+
7DE/RE
7DE/RE
7B+
8B−
7B+
8B−
8A
8A
8B−
8B+
8DE/RE
8DE/RE
8B+
9B−
8B+
9B−
9A
9A
9A
9B−
9B+
9DE/RE
9DE/RE
9DE/RE
9B+
9B+
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
Control Inputs
CDE0 V < 0.5 V
INV/NON
CDE0
INV/NON
CDE1
V < 0.5 V
I
I
I
H
L
L
L
H
L
L
CDE1
CDE2
CDE1
CDE2
H
H
CDE2
(c)
(a)
(b)
Figure 12. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
1B−
1B+
1A
2A
1A
1B−
1B−
1B+
1A
2A
1DE/RE
1B+
2B−
2B−
2B+
2A
2B−
2B+
2DE/RE
2B+
3B−
3B−
3B+
3A
4A
3A
3B−
3B+
3A
4A
5A
6A
3DE/RE
3B+
4B−
4B−
4B+
4A
4B−
4B+
4DE/RE
4B+
5B−
5B−
5A
5A
6A
7A
8A
5B−
5B+
5DE/RE
5B+
5B+
6B−
6A
6B−
6B+
6B−
6B+
6DE/RE
6B+
7B−
7A
7B−
7B+
7B−
7B+
7A
8A
7DE/RE
7B+
8B−
8A
8B−
8B+
8B−
8B+
9B−
8DE/RE
8B+
9B−
9A
9A
9A
9DE/RE
9B−
9B+
9DE/RE
9DE/RE
9B+
9B+
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
I
I
I
H
H
L
H
H
H
H
L
CDE1
CDE2
CDE1
CDE2
CDE1
CDE2
H
(b)
(a)
(c)
Figure 13. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
1A
1B–
1B+
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
2A
2B–
2B+
High Z
High Z
3B–
3B+
3A
High Z
High Z
4A
4B–
4B+
High Z
High Z
5A
5B–
5B+
High Z
High Z
6A
6B–
6B+
High Z
High Z
7A
7B–
7B+
High Z
High Z
8A
8B–
8B+
High Z
High Z
9A
9B–
9B+
High Z
High Z
Control Inputs
CDE0
INV/NON
CDE1
V > 2.5 V
I
X
X
X
CDE2
Figure 14. Logic Diagrams
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
INPUT AND OUTPUT EQUIVALENT SCHEMATIC DIAGRAMS
CDE1, CDE2, DE/RE Inputs
A and INV/NON Inputs
V
CC
V
CC
10uA
Input
10uA
Input
CDE0 Input
A Output
V
CC
V
CC
Input
A
B+ Input
B– Input
I
ref
I
ref
37 Ω
37 Ω
BP
BN
I
ref
I
ref
113 Ω
15 Ω
113 Ω
V
CC
V
CC
V
CC
15 Ω
15 Ω
113 Ω
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SLLS292B–APRIL 1998–REVISED JANUARY 2000
Terminal Functions
'LVDM977
Logic
Level
Terminat
ion
'LVDM976
Logic
Level
TERMINAL
I/O
DESCRIPTION
NAME
1A - 9A
NO.
4,6,8,10,
19,21,23,
25,27
CMOS
TTL
I/O
I/O
Pullup
None
1A - 9A carry data to and from the communication controller.
1B–– 9B– 29,31,33,
35,37,46,
LVD or
TTL
LVD or
TTL
1B- to 9B- are the signals to and from the data bus. When INV/NON
is low, the logic sense is the opposite that of the A input (inverted).
When INV/NON is high, the logic sense is the same as the A input
(noninverted).
48,50,52
1B+ - 9B+ 30,32,34,
36,38,47,
LVD or
GND
LVD or
GND
I/O
None
None
When in the LVD mode, 1B+ - 9B+ are signals to or from the data
bus and follow the same logic sense as the A input when INV/NON
is low (noninverted). The logic sense is opposite that of the A input
(inverted) when INV/NON is high. When in single-ended mode,
these terminals become a ground connection through a transistor
and do not switch.
49,51,53
CDE0
54
Trinary
Trinary
Input
CDE0 is the common driver enable 0. With the driver enabled and
the CDE0 input less than 0.5 V, the driver output is single-ended
mode. With the driver enabled and the CDE0 input between 0.7 V
and 1.9 V the driver output is LVD mode. All drivers are disabled
when the input is greater than 2.4 V.
CDE1
CDE2
55
56
CMOS
CMOS
CMOS
TTL
TTL
TTL
Input Pulldown CDE1 is the common driver enable 1. When CDE1 is high, drivers
1–4 are enabled
Input Pulldown CDE2 is the common driver enable 2. When CDE2 is high, drivers 5
to 8 are enabled.
1DE/RE - 5,7,9,11,
9DE/RE
Input Pulldown 1DE/RE–9DE/RE are direction controls that transmit data to the bus
when it is high and CDE0 is below 2.2 V. Data is received from the
bus when 1DE/RE- 9DE/RE, CDE1, and CDE2 are low.
20,22,24,
26,28
GND
2,3,13,14,
15,16,17,
40,41,42,
43,44
NA
NA
Power
NA
GND is the circuit ground.
INV/NON
VCC
1
CMOS
NA
CMOS
NA
Input
Pullup
NA
A high-level input to INV/NON inverts the logic to and from the A
terminals. (i.e., the voltage at A terminal and the corresponding B-
terminal are in phase.)
12,18,39,
45
Power
Supply voltage
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.5 V to 7 V
VCC
VI
Supply voltage range(2)
Input voltage range
(A, INV/NON)
–0.5 V to VCC + 0.5 V
–0.5 V to 5.25 V
See Dissipation Rating Table
–65°C to 150°C
260°C
(DE/RE, B+, B-, CDE0, CDE1, CDE2)
Continuous total power dissipation
Tstg
Storage temperature range,
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND unless otherwise noted.
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DISSIPATION RATING TABLE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
PACKAGE
DGG
978 mW
10.8 mW/°C
492 mW
RECOMMENDED OPERATING CONDITIONS (see Figure 15)
MIN NOM
MAX UNIT
VCC
VIH
Supply voltage
4.75
0.7 VCC
2
5
5.25
V
SN75LVDM976
SN75LVDM977
SN75LVDM976
SN75LVDM977
Differential receiver
High-level input voltage
V
0.3 VCC
0.8
VIL
Low-level input voltage
V
|VID
|
Differential input voltage
0.03
0.7
3.6
V
V
VIC
Common-mode input voltage
1.8
Differential output voltage
bias
VOD(bias)
IOH
Differential
100
125
mV
mA
Single-ended driver
Receiver
7
2
High-level output current
Low-level output current
Single-ended driver
Receiver
48
2
IOL
mA
ZL
TA
Differential load impedance
40
0
65
70
Ω
Operating free-air temperature
°C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CDE1 and CDE2
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
50
µA
50
IIH High-level input current
INV/NON
CDE1 and CDE2
INV/NON
50
µA
50
IIL
Low-level input current
Disabled
7
LVD drivers enabled,
No load
No load
No load
26
ICC Supply current
Single-ended drivers enabled,
LVD receivers enabled,
10
26
7
mA
pF
Singled-ended receivers enabled, No load
CI
Input capacitance
Bus terminal
VI = 0.2 sin (2 π (1E06)t) + 0.5 ± 0.01 V
9.5
∆CI Difference in input capacitance between B+ and B–
0.2
(1) All typical values are at VCC = 5 V, TA = 25°C.
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DIFFSENS (CDE0) RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TYP(
PARAMETER
Input threshold voltage
TEST CONDITIONS
MIN
MAX UNIT
1)
VIT1
VIT2
II
0.5
1.9
0.6
2.1
0.7
V
Input threshold voltage
Input current
2.4
0 V ≤ VI ≤ 2.7 V
±1
±1
µA
µA
II(OFF)
Power-off input current
VCC = 0, 0 V ≤ VI ≤ 2.7 V
(1) All typical values are at VCC = 5 V, TA = 25°C.
LVD DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
270
TYP(1)
MAX
UNIT
460
780
VI(1) = 0.96 V, VI(2) = 0.53 V,
See Figure 16
0.69|VOD(L) |+50
270
1.45|VOD(L) |–65
780
Driver differential high-level output
voltage
VOD(H)
mV
500
VI(1) = 1.96 V, VI(2) = 1.53 V,
See Figure 16
0.69|VOD(L) |+50
1.45|VOD(L) |–65
VI(1) = 0.96 V, VI(2) = 0.53 V,
See Figure 16
260
260
1.1
400
400
1.2
640
640
1.5
Driver differential low-level output
voltage
VOD(L)
mV
VI(1) = 1.96 V, VI(2) = 1.53 V,
See Figure 16
Steady-state common-mode output
voltage
VOC(SS)
V
Change in steady-state
∆VOC(SS) common-mode output voltage
VI(1) = 1.41 V, VI(2) = 0.99 V,
See Figure 17
±50
80
±120
150
mV
between logic states
Peak-to-peak common-mode
output voltage
VOC(PP)
mV
µA
A
7
8
IIH
High-level input current
VIH = 3.3 V ('976) VIH = 2 V ('977)
VIL = 1.6 V ('976)VIL = 0.8 V ('977)
DE/RE
A
50
30
IIL
Low-level input current
Power-off output current
µA
DE/RE
IO(OFF)
IOS
VCC = 0, 0 V ≤ VO ≤ 2.5 V
0 V ≤ VO ≤ 2.5 V
±1
±24
±1
µA
mA
µA
Short-circuit output current
IOZ
High-impedance output current
VO = 0 or 2.5 V
(1) All typical values are at VCC = 5 V, TA = 25°C.
LVD DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted) (See Figure 16)
TYP(
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1)
tPLH
tPHL
tr
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Differential output signal rise time
2.9
2.9
1
8.8
8.8
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5 V,
VI2 = 0.99 V,
VI1 = 1.41 V,
TA = 25°C
3
3
6
6
tf
Differential output signal fall time
1
tsk(p)
Pulse skew (|tPHL– tPLH|)
3.7
5.9
50
33
tsk(lim) Skew limit(2)
tPHZ Propagation delay time, high-level to high-impedance output
ten Enable time, receiver to driver
(1) All typical values are at VCC = 5 V, TA = 25°C.
VI1 = 1.41 V,
See Figure 18
VI2 = 0.99 V,
(2) tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the
same ambient temperature.
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SINGLE-ENDED DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
IOH = –7 mA,
IOH = 0 mA
VCC = 5 V,
See Figure 19
2
3.24
3.7
V
V
V
VOH
High-level output voltage
B– output
B– output
B+
IOL = 48 mA
0.5
VOL
Low-level output voltage
IOL = –25 mA
IOL = 25 mA
–0.5
0.5
V
A
–7
8
IIH
High-level input current
Low-level input current
VIH = 3.3 V ('976), VIH = 2 V ('977)
VIL = 1.6 V ('976), VIL = 0.8 V ('977)
µA
µA
DE/RE
A
50
–30
IIL
DE/RE
B–
IO(OFF)
IOZ
Power-off output current
VCC = 0,
0 V ≤ VO ≤ 5.25 V
±1
±1
µA
µA
High-impedance output current
VO = 0 or VCC
SINGLE-ENDED DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
MI TYP(
N
PARAMETER
TEST CONDITIONS
MAX UNIT
1)
tPLH
tPHL
tr
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Differential output signal rise time
2.7
2.7
0.5
0.5
8.2
8.2
4
ns
ns
ns
ns
ns
ns
ns
VCC = 5 V, TA = 25°C, See Figure 19
tf
Differential output signal fall time
4
tsk(p)
Pulse skew (|tPHL– tPLH|)
3.4
5.5
50
tsk(lim) Skew limit(2)
ten
Enable time, receiver to driver
See Figure 20
Propagation delay time, low-level to high-impedance
output
tPLZ
30
ns
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the
same ambient temperature.
LVD RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
mV
mV
V
VIT+ Positive-going differential input voltage threshold
30
See Figure 21
VIT-
Negative-going differential input voltage threshold
–30
VOH High-level output voltage
IOH = –2 mA
IOL = 2 mA
3.7
0.5
±1
VOL
II
Low-level output voltage
Input current, B+ or B–
V
VI = 0 V to 2.5 V
µA
II(OFF
Power-off Input current, B+ or B–
VCC = 0,
VI = 0 V to 2.5 V
±1
µA
)
IIH
High-level input current, DE/RE
Low-level input current, DE/RE
High-impedance output current
VIH = 3.3 V ('976), VIH = 2 V ('977)
VIL = 1.6 V ('976), VIL = 0.8 V ('977)
VO = 0 or VCC
50
µA
µA
µA
IIL
8
IOZ
±30
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LVD RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TYP(
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
1)
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Pulse skew (|tPHL– tPLH|)
4.5
4.5
10
10
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5 V, TA = 25°C, See
Figure 21
Output signal rise time
8
tf
Output signal fall time
8
tsk(lim) Skew limit(2)
5.5
42
20
26
tPHZ
tPLZ
ten
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output See Figure 18
Enable time, driver to receiver
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the
same ambient temperature.
SINGLE-ENDED RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+ Positive-going input voltage threshold B–
Negative-going input voltage
TEST CONDITIONS
MIN TYP
MAX UNIT
1.6
1.9
V
VIT–
B–
1
1.1
V
threshold
VOH High-level output voltage
VOL Low-level output voltage
IOH = –2 mA
3.7
4.6
0.3
V
V
IOL = 2 mA
0.5
±1
II
Input current
B–
B–
VI = 0 to VCC
µA
II(OFF
Power-off Input current
VCC = 0 V, VI = 0 to 5.25 V
±1
50
µA
)
IIH
High-level input current
DE/RE
DE/RE
VIH = 3.3 V ('976), VIH = 2 V ('977)
VIL = 1.6 V ('976), VIL = 0.8 V ('977)
VO = 0 or VCC
µA
µA
µA
IIL
Low-level input current
8
IOZ
High-impedance output current
-30
SINGLE-ENDED RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Pulse skew (|tPHL– tPLH|)
TEST CONDITIONS
MIN TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tr
7
7
12.5
12.5
3.5
8
ns
ns
ns
ns
ns
ns
VCC = 5 V, TA = 25°C, See
Figure 22
Output signal rise time
tf
Output signal fall time
tsk(lim) Skew limit(1)
8
5.5
Propagation delay time, high-level to high-impedance
output
tPHZ
20
ns
Propagation delay time, low-level to high-impedance
output
See Figure 20
tPLZ
ten
30
48
ns
ns
Enable time, driver to receiver
(1) tsk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the
same ambient temperature.
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PARAMETER MEASUREMENT INFORMATION
I +
OB
B+
I
I
A
I –
OB
V
OD
V
) V
OB)
OB*
2
V
OB+
B–
V
OC
V
I
V
OB–
Figure 15. Voltage and Current Definitions
50 Ω
100 Ω
Input
5 V
A
B–
V1
V2
DE/RE
CDE0
C
C
= 10 pF
= 10 pF
+
–
L
1.3 V
V
OD
75 Ω
Open
CDE1
Open
CDE2
B+
0 V or 5 V
INV/NON
100 Ω
+
–
L
0.7 V (’976)
CC
2 V (’977)
INPUT
Solid line is INV/NON at 0 V.
Dashed line is INV/NON at 5 V.
0.3 V (’976)
CC
0.8 V (’977)
t
t
PHL
PLH
100%
80%
V
OD(H)
OUTPUT
0 V
V
OD(L)
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate
(PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 16. Differential Output Signal Test Circuit, Timing, and Voltage Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
V1
50 Ω
100 Ω
Input
5 V
A
V
L
OC
B–
B+
37.5 Ω
DE/RE
CDE0
1.3 V
Open
CDE1
C
= 50 pF
Open
CDE2
37.5 Ω
100 Ω
0 V or 5 V
INV/NON
V2
0.7 V (’976)
CC
Input
2 V (’977)
0.3 V (’976)
CC
0.8 V (’977)
V
OC(PP)
V
OC(SS)
Output
A. NOTES: . All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse
repetition rate (PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 17. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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PARAMETER MEASUREMENT INFORMATION (continued)
V1
100 Ω
C
L
= 50 pF
C
L
= 50 pF
A
B–
37.5 Ω
37.5 Ω
620 Ω
V
V
OD
Input
1.3 V
DE/RE
CDE0
B+
C
L
= 50 pF
Open
CDE1
Open
CDE2
0 V or 5 V
INV/NON
100 Ω
V2
TEST CIRCUIT
V at 5 V, INV/NON at 0 V
V at 0 V, INV/NON at 5 V
0.7 V (’976)
0.7 V (’976)
CC
CC
2 V (’977)
2 V (’977)
50%
Input
50%
0.3 V (’976)
CC
0.3 V (’976)
CC
0.8 V (’977)
0.8 V (’977)
t
t
t
t
PHZ(d)
en(d)
PHZ(d)
en(d)
≈ 0.4 V
≈ 0.4 V
V
OD
0 V
0 V
≈ –0.12 V
≈ –0.12 V
t
t
en(d)
t
t
en(r)
en(d)
en(r)
5 V
5 V
V
A
1.4 V
1.4 V
≈ 0.2 V
≈ 0.2 V
VOLTAGE WAVEFORMS
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulsewidth = 500 ns ±50 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 18. LVD Transceiver Enable and Disable Time Test Circuit and Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
Input
0 V
A
I
O
DE/RE
CDE0
CDE1
CDE2
INV/NON
47 Ω
B–
0 V
Open
C
L
= 10 pF
+
–
Open
2.5 V
V
O
0 V or 5 V
0.7 V (’976)
CC
2 V (’977)
Solid line is INV/NON
at a high-level input.
INPUT
0.3 V (’976)
CC
Dashed line is INV/NON
at a low-level input.
0.8 V (’977)
t
t
PHL
PLH
100%
80%
OUTPUT
1.4 V
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate
(PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 19. Single-Ended Driver Switching Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
C
L
= 50 pF
V
A
47 Ω
B–
V
A
620 Ω
Input
0 V
DE/RE
CDE0
CDE1
CDE2
INV/NON
C
L
= 10 pF
+
–
2.5 V
V
B
Open
Open
0 V or 5 V
TEST CIRCUIT
V and INV/NON at 5 V
V and INV/NON at 0 V
0.7 V
50%
0.3 V
0.7 V
50%
0.3 V
CC
CC
Input
CC
CC
t
PHZ(r)
t
en(r)
t
t
en(r)
PLZ(r)
V
OL
V
A
0.5 V
V
OL
0.5 V
t
t
t
t
PLZ(d)
PLZ(d)
en(d)
en(d)
V
B
V
OL
V
OL
0.5 V
0.5 V
VOLTAGE WAVEFORMS
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulsewidth = 500 ns ±50 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 20. Single-Ended Transceiver Enable and Disable Timing Measurements
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PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
I
IB+
I
O
V
ID
V
IB
C
L
= 15 pF
50 Ω
V
O
I
IB–
V
IB–
0 V
DE/RE
CDE0
1.3 V
Open
CDE1
Open
CDE2
0 or 5 V
INV/NON
TEST CIRCUIT
V
1.4 V
1 V
IB
V
IB–
0.4 V
0 V
V
ID
–0.4 V
t
t
PLH
PHL
Solid line is INV/NON
at a high-level input.
V
OH
80%
20%
50%
V
O
V
OL
Dashed line is INV/NON
at a low-level input.
t
f
t
r
VOLTAGE WAVEFORMS
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns, Zo = 50 Ω.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 21. LVD Receiver Switching Characteristic Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
Input
B–
I
O
GND
GND
DE/RE
CDE0
A
Open
Open
CDE1
C
L
= 15 pF
CDE2
V
O
GND or V
INV/NON
CC
2 V
1.4 V
0.8 V
Solid line is INV/NON at a high-level input.
Dashed line is INV/NONat a low-level input.
INPUT
t
t
PHL
PLH
V
OH
100%
80%
OUTPUT
–1.4 V
20%
0%
V
OL
t
r
t
f
A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate
(PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns.
B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 22. Single-Ended Receiver Timing Test Circuit
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APPLICATION INFORMATION
U1
‘LVDM976
8.2 kΩ, 1/8 W, 5%
0.022 µF, 6 V, 10%
CDE0
DIFFSENS
U2
‘LVDM976
CDE0
U3
‘LVDM976
CDE0
Figure 23. Low-Pass Filter for Connecting DIFFSENS to CDE0
25
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
SN75LVDM976DGG
SN75LVDM976DGGG4
SN75LVDM976DGGR
SN75LVDM976DGGRG4
SN75LVDM976DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
56
56
56
56
56
35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
TSSOP
SSOP
DGG
DGG
DGG
DL
35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN75LVDM976DLG4
SN75LVDM977DGG
SN75LVDM977DGGG4
SN75LVDM977DGGR
SN75LVDM977DGGRG4
SN75LVDM977DL
SSOP
DL
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SSOP
DGG
DGG
DGG
DGG
DL
35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN75LVDM977DLG4
SSOP
DL
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN75LVDM976DGGR
SN75LVDM977DGGR
TSSOP
TSSOP
DGG
DGG
56
56
2000
2000
330.0
330.0
24.4
24.4
8.6
8.6
15.6
15.6
1.8
1.8
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75LVDM976DGGR
SN75LVDM977DGGR
TSSOP
TSSOP
DGG
DGG
56
56
2000
2000
346.0
346.0
346.0
346.0
41.0
41.0
Pack Materials-Page 2
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