SN75LVDS83DGGR-P [TI]
FlatLink(TM) Transmitter 56-TSSOP;
| 型号： | SN75LVDS83DGGR-P |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FlatLink(TM) Transmitter 56-TSSOP |
| 文件： | 总15页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
DGG PACKAGE
(TOP VIEW)
28:4 Data Channel Compression at up to
227.5 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
V
D4
1
56
55
54
53
52
51
50
49
48
47
46
CC
D5
D3
2
D6
D7
D2
3
28 Data Channels and Clock-In Low-Voltage
TTL
GND
D1
4
GND
D8
5
D0
6
4 Data Channels and Clock-Out
Low-Voltage Differential
D9
D27
LVDSGND
Y0M
Y0P
Y1M
7
D10
8
Operates From a Single 3.3-V Supply With
250 mW (Typ)
V
9
CC
D11
D12
10
11
ESD Protection Exceeds 6 kV
5-V Tolerant Data Inputs
D13 12
GND 13
D14 14
45 Y1P
Selectable Rising or Falling Edge-Triggered
Inputs
44 LVDSV
CC
43 LVDSGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D15
D16
Y2M
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
Y2P
CLKSEL
D17
CLKOUTM
CLKOUTP
Y3M
Consumes Less Than 1 mW When Disabled
Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
D18
D19
Y3P
No External Components Required for PLL
GND
D20
LVDSGND
PLLGND
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D21
PLLV
CC
Improved Replacement for the DS90C581
D22
PLLGND
SHTDN
CLKIN
D26
D23
description
V
CC
D24
D25
The SN75LVDS83 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
7× clock synthesizer, and five low-voltage
GND
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-endedlow-voltageTTL(LVTTL)datatobesynchronouslytransmittedoverfivebalanced-pairconductors
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit
links with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in
7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all
internal registers to a low level.
The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0 C to 70 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
functional block diagram
Parallel-Load 7-Bit
Shift Register
7
Y0P
Y0M
D0, D1, D2, D3,
A,B, ...G
SHIFT/LOAD
CLK
D4, D6, D7
Parallel-Load 7-Bit
Shift Register
7
D8, D9, D12, D13,
Y1P
Y1M
A,B, ...G
SHIFT/LOAD
CLK
D14, D15, D18
Parallel-Load 7-Bit
Shift Register
7
D19, D20, D21, D22,
Y2P
Y2M
A,B, ...G
SHIFT/LOAD
CLK
D24, D25, D26
Parallel-Load 7-Bit
Shift Register
7
D5, D10, D11, D16,
D17, D23, D27
Y3P
Y3M
A,B, ...G
SHIFT/LOAD
CLK
Control Logic
SHTDN
7× Clock/PLL
7×CLK
CLKOUTP
CLKOUTM
CLK
CLKIN
CLKINH
RISING/FALLING EDGE
CLKSEL
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
D0
CLKIN
or
CLKIN
CLKOUT
Next
Cycle
Previous Cycle
Current Cycle
D0–1
D8–1
D7
D6
D4
D3
D2
D1
D9
D0
D8
D7+1
Y0
Y1
D18
D15
D14
D13
D12
D18+1
D19–1
D27–1
D26
D23
D25
D17
D24
D16
D22
D11
D21
D10
D20
D5
D19
D27
D26+1
D23+1
Y2
Y3
Figure 1. SN75LVDS83 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
V
CC
V
CC
5 Ω
YnP or YnM
10 kΩ
Dn or
SHTDN
50 Ω
7 V
7 V
300 kΩ
INPUT
OUTPUT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Output voltage range, V (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input voltage range, V (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
‡
T
A
T = 70°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DGG
1377 mW
11.0 mW/°C
822 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
V
Low-level input voltage, V
0.8
132
70
V
IL
Differential load impedance, Z
90
0
Ω
L
Operating free-air temperature, T
°C
A
timing requirements
MIN NOM
MAX
UNIT
ns
t
t
t
t
t
Cycle time, input clock
14.7
32.4
c
Pulse duration, high-level input clock
0.4t
0.6t
c
ns
w
t
c
Transition time, input signal
5
ns
Setup time, data, D0 – D27 valid before CLKIN↑ or CLKIN↓ (See Figure 2)
Hold time, data, D0 – D27 valid after CLKIN↑ or CLKIN↓ (See Figure 2)
3
ns
su
h
1.5
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
Input threshold voltage
1.4
IT
|V
|
Differential steady-state output voltage magnitude
247
454
50
mV
OD
R
= 100 Ω,
L
Change in the steady-state differential output
voltage magnitude between opposite binary states
See Figure 3
∆|V
|
mV
OD
V
V
Steady-state common-mode output voltage
Peak-to-peak common-mode output voltage
High-level input current
1.125
1.375
150
25
V
OC(SS)
See Figure 3
mV
µA
µA
mA
mA
µA
OC(PP)
I
I
V
V
V
V
V
= V
= 0
IH
IH
CC
= 0
Low-level input current
±10
±24
±12
±10
IL
IL
O(Yn)
I
Short-circuit output current
OS
OZ
= 0
OD
= 0 to V
I
High-impedance state output current
O
CC
Disabled,
All inputs at GND
280
µA
Enabled,
R
= 100 Ω,
L
Gray-scale pattern (see Figure 4),
V = 3.3 V,
CC
c
72
90
mA
I
Quiescent supply current
CC
t = 15.38 ns
Enabled,
R
= 100 Ω,
L
85
3
110
mA
pF
Worst-case pattern (see Figure 5),
t = 15.38 ns
c
C
Input capacitance
I
†
All typical values are at V = 3.3 V, T = 25°C.
CC
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Delay time, CLKOUT↑ to serial bit
position 0
t
t
t
t
t
t
–0.2
0
0.2
ns
d0
d1
d2
d3
d4
d5
Delay time, CLKOUT↑ to serial bit
position 1
1
7
1
7
ns
ns
ns
ns
ns
t
t
t
t
t
t
0.2
0.2
0.2
0.2
0.2
t
t
t
0.2
0.2
0.2
c
c
c
c
c
c
c
c
c
Delay time, CLKOUT↑ to serial bit
position 2
2
7
2
7
t = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps ,
See Figure 6
c
Delay time, CLKOUT↑ to serial bit
position 3
3
7
3
7
‡
Delay time, CLKOUT↑ to serial bit
position 4
4
7
4
7
t
t
0.2
0.2
c
c
Delay time, CLKOUT↑ to serial bit
position 5
5
7
5
7
Delay time, CLKOUT↑ to serial bit
position 6
6
7
6
7
t
t
ns
ns
0.2
t
0.2
0.2
d6
c
n
7
–0.2
Output skew,
t
t
c
sk(o)
n
t = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps ,
See Figure 6
c
‡
t
d7
Delay time, CLKIN↓ to CLKOUT↑
4.2
ns
t = 15.38 ± 0.75 sin (2π500E3t) + 0.05 ns,
See Figure 7
c
±70
ps
ps
ns
ps
ms
ns
§
∆t
c(o)
Cycle time, output clock jitter
t = 15.38 ± 0.75 sin (2π3E6t) + 0.05 ns,
c
±187
See Figure 7
4
7
t
c
t
Pulse duration, high-level output clock
Transition time, differential output
w
t
t
t
See Figure 3
See Figure 8
See Figure 9
260
700
1
1500
t
(t or t )
r
f
Enable time, SHTDN↑ to phase lock (Yn
valid)
en
Disable time, SHTDN↓ to off state
(CLKOUT low)
250
dis
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
|Input clock jitter| is the magnitude of the change in the input clock period.
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
t
t
h
su
Dn
CLKSEL LOW
CLKSEL HIGH
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Waveforms
49.9 Ω ± 1% (2 Places)
YP
V
OD
V
OC
YM
C
= 10 pF Max
L
(2 Places)
NOTE A: The lumped instrumentation capacitance for any
single-endedvoltage measurement is less than or equal
to 10 pF. When making measurements at YP or YM, the
complementary output is similarly loaded.
(a) SCHEMATIC
100%
80%
V
OD(H)
0 V
V
OD(L)
20%
0%
t
f
t
r
V
OC(PP)
V
V
OC(SS)
OC(SS)
0 V
(b) WAVEFORMS
Figure 3. Test Load and Voltage Waveforms for LVDS Outputs
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4–7, 12–15, 20–23
D24–27
NOTE A: The16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown.
Figure 4. 16-Grayscale Test-Pattern Waveforms
t
c
CLKIN
Even Dn
Odd Dn
NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with
CLKSEL low shown.
Figure 5. Worst-Case Test-Pattern Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
t
d7
CLKIN
(see Note A)
CLKIN
(see Note B)
CLKOUT
t
d0
Yn
t
d1
t
d2
t
d3
t
d4
t
d5
t
d6
≈ 2.5 V
1.4 V
V
OD(H)
CLKOUT
CLKIN
or
0.00 V
Yn
≈ 0.5 V
V
OD(L)
t
d7
t
– t
d0 d6
NOTES: A. This wave form is valid when CLKSEL is low.
B. This wave form is valid when CLKSEL is high.
Figure 6. SN75LVDS83 Timing Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Device
Under
Test
+
Reference
VCO
∑
+
Modulation
V(t) = A sin (2 π f
t)
(mod)
HP8656B
Signal Generator
0.1 MHz – 990 MHz
HP8665A
Synthesized Signal
Generator
Device Under Test
DTS2070C
Digital Time Scope
0.1 MHz – 4200 MHz
OUTPUT
CLKIN
CLKOUT
Input
RF Output
Modulation Input
Figure 7. Output Clock Jitter Testing
CLKIN
Dn
t
en
SHTDN
Yn
Invalid
Valid
Figure 8. Enable Time Waveforms
CLKIN
t
dis
SHTDN
CLKOUT
Figure 9. Disable Time Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
CLOCK FREQUENCY
80
V
CC
= 3.6 V
70
60
50
V
CC
= 3.3 V
V
CC
= 3 V
40
30
Grayscale Data Pattern
R
= 100 Ω
= 25°C
L
T
A
30
40
50
60
70
f
– Clock Frequency – MHz
clk
Figure 10
ZERO-TO-PEAK OUTPUT JITTER
vs
MODULATION FREQUENCY
200
180
160
140
120
100
80
60
40
Input jitter = 750 sin (6.28 f
t) ps
(mod)
V
T
A
= 3.3 V
= 25°C
20
0
CC
0
0.5
1
1.5
2
2.5
3
f
– Modulation Frequency – MHz
(mod)
Figure 11
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
Graphic Controller
SN75LVDS83
SN75LVDS82
12-BIT
RED0
RED1
RED2
RED3
RSVD
RSVD
NA
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
NA
24-BIT
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
48
9
51
52
54
55
56
3
D0
Y0M
A0M
D1
100 Ω
100 Ω
100 Ω
100 Ω
D2
47
46
10
11
D3
Y0P
Y1M
A0P
A1M
D4
D6
50
2
D27
D5
NA
NA
4
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
D7
6
45
42
12
15
D8
Y1P
Y2M
A1P
A2M
7
D9
11
12
14
8
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL
RSVD
RSVD
NA
GREEN4 GREEN4
GREEN5 GREEN5
NA
GREEN6
GREEN7
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17
41
38
16
19
NA
NA
Y2P
Y3M
A2P
A3M
BLUE0
BLUE1
BLUE2
BLUE3
RSVD
RSVD
NA
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
NA
37
20
Y3P
A3P
NA
NA
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
40
39
17
18
CLKOUTM
CLKOUTP
CLKINM
CLKINP
NA
NA
RSVD
100 Ω
CLOCK
CLOCK
CLOCK
See Note A
NOTES: A. Connect this terminal to V
for triggering to the rising edge of the input clock and to GND for the falling edge.
CC
B. The five 100-Ω terminating resistors are recommended to be 0603 types.
Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
Graphic Controller
SN75LVDS83
SN75LVDS86
12-BIT
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
NA
24-BIT
48
8
51
52
54
55
56
3
RED0
RED1
RED2
RED3
RSVD
RSVD
NA
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
D0
Y0M
A0M
D1
100 Ω
100 Ω
100 Ω
D2
47
46
9
D3
Y0P
Y1M
A0P
A1M
D4
D6
50
2
10
D27
D5
NA
NA
4
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
D7
6
45
42
11
14
D8
Y1P
Y2M
A1P
A2M
7
D9
11
12
14
8
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL
RSVD
RSVD
NA
GREEN4 GREEN4
GREEN5 GREEN5
NA
GREEN6
GREEN7
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17
41
38
15
NA
NA
Y2P
Y3M
A2P
BLUE0
BLUE1
BLUE2
BLUE3
RSVD
RSVD
NA
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
NA
37
Y3P
NA
NA
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
40
39
16
17
CLKOUTM
CLKOUTP
CLKINM
CLKINP
NA
NA
RSVD
100 Ω
CLOCK
CLOCK
CLOCK
See Note A
NOTES: A. Connect this terminal to V
for triggering to the rising edge of the input clock and to GND for the falling edge.
CC
B. The four 100-Ω terminating resistors are recommended to be 0603 types.
Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS83
FLATLINK TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
14
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