SN75LVPE801DRFT [TI]
8.0Gbps SATA Express 转接驱动器 | DRF | 8 | 0 to 85;
| 型号： | SN75LVPE801DRFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8.0Gbps SATA Express 转接驱动器 | DRF | 8 | 0 to 85 驱动 光电二极管 商用集成电路 驱动器 |
| 文件： | 总33页 (文件大小：3249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
SN75LVPE801 8.0Gbps SATA Express 均衡器和转接驱动器
1 特性
3 说明
1
•
SATA Express 支持
可选均衡和去加重功能
SN75LVPE801 是一款通用型单通道 SATA Express
信号调节器，最高可支持 8Gbps 的数据速率。此器件
支持 SATA Gen 1、2 和 3 规范以及 PCIe 1.0、2.0 和
3.0。SN75LVPE801 由 3.3V 单电源供电运行，并且
配有带自偏置特性的 100Ω 线路端接电阻，适用于交
流耦合。输入端包含一个带外 (OOB) 检测器，可在输
入差分电压低于阈值时自动抑制输出端噪声，同时保持
一个稳定的共模电压。此外，该器件还被设计成依据
SATA 标准处理扩频时钟 (SSC) 传输。
•
•
•
•
支持热插拔功能
接收器检测与带外 (OOB) 支持
多速率运行
–
–
SATA：1.5Gpbs、3.0Gpbs、6.0Gpbs
PCIe：2.5Gbps、5.0Gbps、8.0Gbps
•
•
适用于为长达 40 英寸（1.0 米）的各种尺寸 FR4
PC 电路板接收 8.0Gbps 数据
在 3GHz 频率下，可补偿接收端高达 14dB 的损
耗，以及发送端 1.2dB 的损耗
75SNLVPE801 通过可选均衡设置来处理其输入端的
互连损耗，能够通过编程来匹配通道中的损耗。对于
8Gbps 及以下的数据传输速率，75SNLVPE801 可为
长达 50 英寸的 FR4 电路板材料提供信号均衡。对于
8Gbps 数据传输速率而言，该器件可针对长达 40 英寸
的 FR4 材料进行补偿。均衡级别可通过设置信号控制
引脚 EQ 来控制。
•
•
•
集成输出噪声抑制
温度范围：0°C 至 85°C
自动低功耗特性，可使功耗降低 90% 以上
–
–
< 100mW（工作模式，典型值）
< 11mW（自动低功耗模式，典型值）
•
•
3.3V 单电源
针对静电放电 (ESD) 瞬态的高度保护功能
器件信息(1)
器件型号
封装
WSON (8)
封装尺寸（标称值）
–
–
人体放电模式 (HBM)：6kV
组件充电模式 (CDM)：1.5kV
SN75LVPE801
2.00mm x 2.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
超小型尺寸：2mm × 2mm WSON 封装
2 应用
•
•
•
•
•
笔记本电脑
台式机
扩展坞
服务器
工作站
SATA Express 参考原理图
Connector
Host Controller
Device
VCC
1
2
3
4
8
7
6
5
VCC
RX+
RX-
EQ
DE
TX+
220nF
220nF
200nF
TX-
200nF
GND
SN75LVPE801
330
330
VCC
8
7
6
5
1
2
3
4
DE
VCC
RX+
RX-
EQ
220nF
470nF
200nF
200nF
TX+
TX-
220nF
470nF
GND
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEW8
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 13
10 Applications and Implementation...................... 14
10.1 Application Information.......................................... 14
10.2 Typical SATA Applications.................................... 14
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Example .................................................... 24
13 器件和文档支持 ..................................................... 26
13.1 器件支持................................................................ 26
13.2 接收文档更新通知 ................................................. 26
13.3 社区资源................................................................ 26
13.4 商标....................................................................... 26
13.5 静电放电警告......................................................... 26
13.6 Glossary................................................................ 26
14 机械、封装和可订购信息....................................... 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 7
7.7 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9.1 Overview ................................................................. 10
8
9
4 修订历史记录
日期
修订版本
注释
2016 年 9 月
*
最初发布版本。
2
版权 © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
5 说明 （续）
发送侧有两个去加重级别可供选择，用于为输出端提供 0dB 或 1.2dB 的附加高频损耗补偿。
该器件支持热插拔(1)，能够防止器件在热插入（例如，异步信号插/拔、不带电插/拔、带电插/拔或意外插/拔）情况
下遭到损坏。
(1) 需要在差分输入和输出端使用交流耦合电容。
6 Pin Configuration and Functions
DRF Package
8-Pin WSON
Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
HIGH SPEED DIFFERENTIAL I/O
RX+
RX–
TX+
TX–
2
3
7
6
I
Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual
termination resistor circuit.
I
O
O
Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by
dual termination resistor circuit.
CONTROL PINS
EQ
4
8
I
I
Selects equalization settings per Table 1. Internally tied to GND.
Selects de-emphasis settings per Table 1. Internally tied to GND.
DE
POWER
VCC
1
5
P
Positive supply must be 3.3 V ±10%
Supply ground
GND
G
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2016, Texas Instruments Incorporated
3
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–65
MAX
UNIT
V
(2)
Supply voltage, VCC
4
4
Differential I/O
V
Voltage
Control I/O
VCC + 0.5
150
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground pin.
7.2 ESD Ratings
VALUE
±6000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
MIN
3
TYP
3.3
MAX
3.6
UNIT
V
VCC
Supply voltage
Coupling capacitor
75
0
100
200
85
nF
TA
Operating free-air temperature
°C
7.4 Thermal Information
SN75LVPE801
DRF (WSON)
8 PINS
97.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
81.9
65.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJB
65.6
RθJCbot
19.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
7.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
DEVICE PARAMETERS
TEST CONDITIONS
MIN TYP MAX
UNIT
ICCMax-s
ICCPS
Active mode supply current
Auto power save mode ICC
Maximum data rate
EQ/DE = NC, K28.5 pattern at 8 Gbps, VID = 700 mVpp
When auto low power conditions are met
29
40
5.9
8
mA
mA
3.3
Gbps
OOB
VOOB
Input OOB threshold
F = 750 MHz
50
1.4
10
70
90
25
50
mVpp
mV
DVdiffOOB
DVCMOOB
OOB differential delta
OOB common-mode delta
mV
CONTROL LOGIC
VIH
High-level input voltage
For all control pins
V
V
VIL
Low-level input voltage
Input hysteresis
0.5
20
VINHYS
IIH
115
mV
μA
μA
High-level input current
Low-level input current
VIH = VCC (DE/EQ)
VIL = 0V (DE/EQ)
IIL
RECEIVER AC/DC
ZDIFFRX Differential input impedance
ZSERX
85 100 115
Ω
Ω
V
Single-ended input impedance
Common-mode voltage
40
VCMRX
1.7
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
20
18
14
10
8
26
22
17
12
12
11
–13
9
Differential mode return loss
(RL)
RLDiffRX
dB
dB/dec
dB
f = 3 GHz to 5 GHz
6
RXDiffRLSlope Differential mode RL slope
f = 300 MHz to 6 GHz (see Figure 6)
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
8
14
12
8
17
18
10
8
RLCMRX
Common-mode return loss
Differential input voltage PP
6
f = 3 GHz to 5 GHz
6
8.5
VdiffRX
f = 1.5 GHz and 3 GHz
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
120
30
34
24
14
12
6
1600
mVpp
41
41
33
24
26
18
18
IBRX
Impedance balance
dB
f = 3 GHz to 5 GHz
f = 5 GHz to 6.5 GHz
5
TRANSMITTER AC/DC
ZdiffTX Pair differential impedance
ZSETX
85 100 122
40
Ω
Ω
Single-ended input impedance
Sequencing transient voltage
Transient voltages on the serial data bus during power
sequencing (lab load)
VTXtrans
–1.2
0.3
1.2
V
Copyright © 2016, Texas Instruments Incorporated
5
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
dB
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
14
12
11
10
10
8
22
21
18
14
14
14
–13
20
16
13.5
8.5
8
RLDiffTX
Differential mode return loss
Differential mode RL slope
Common-mode return loss
f = 3 GHz to 5 GHz
TXDiffRLSlope
f = 300 MHz to 3 GHz (see Figure 6)
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
dB/dec
dB
10
9
8
RLCMTX
6
5
f = 3 GHz to 5 GHz
4
7
f = 150 MHz to 300 MHz
f = 300 MHz to 600 MHz
f = 600 MHz to 1.2 GHz
f = 1.2 GHz to 2.4 GHz
f = 2.4 GHz to 3 GHz
34
32
24
18
18
12
8
38
38
33
25
25
21
21
IBTX
Impedance balance
dB
f = 3 GHz to 5 GHz
f = 5 GHz to 6.5 GHz
Differential output voltage
swing
DiffVppTX
f = 3 GHz (under no interconnect loss)
400 650 900
mVpp
mVpp
At 1.5 GHz
At 3 GHz
15
10
50
26
dBmV
(rms)
VCMAC_TX
TX AC CM voltage
dBmV
(rms)
At 6 GHz
12
30
VCMTX
Common-mode voltage
1.70
V
TRANSMITTER JITTER 3 Gbps
VID = 500 mVpp, UI = 333 ps, K28.5 control character,
see Figure 7
DJTX
RJTX
Residual deterministic jitter
Random jitter
0.12 0.19
UIpp
VID = 500 mVpp, UI = 333 ps, K28.7 control character,
see Figure 7
1
2
ps-rms
TRANSMITTER JITTER 6 Gbps
VID = 500 mVpp, UI = 167 ps, K28.5 control character,
see Figure 7
DJTX
RJTX
Residual deterministic jitter
Random jitter
0.12 0.34
UIpp
VID = 500 mVpp, UI = 167 ps, K28.7 control character,
see Figure 7
0.95
2
ps-rms
TRANSMITTER JITTER 8 Gbps
VID = 500 mVpp, UI = 125 ps, K28.5 control character,
see Figure 7
DJTX
RJTX
DJTX
RJTX
Residual deterministic jitter
4.7 5.76
8.7 (ps) (DD)
ps-rms
2.7 (ps) (DD)
0.9 0.92 0.93 ps-rms
VID = 500 mVpp, UI = 125 ps, K28.5 control character,
see Figure 7
Random jitter
0.93 0.94 0.95
0.8 1.24
VID = 500 mVpp, UI = 125 ps, K28.7 control character,
see Figure 7
Residual deterministic jitter
Random jitter
VID = 500 mVpp, UI = 125 ps, K28.7 control character,
see Figure 7
6
Copyright © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
7.6 Timing Requirements
MIN TYP MAX
UNIT
DEVICE PARAMETERS
tPDelay
Propagation delay
Measured using K28.5 pattern (see Figure 1)
Electrical idle at input (see Figure 3)
After first signal activity (see Figure 3)
275 350
11
ps
μs
ns
AutoLPENTRY Auto low power entry time
AutoLPEXIT
OOB
Auto low power exit time
33
50
tOOB1
OOB mode enter
OOB mode exit
See Figure 2
See Figure 2
1
1
5
5
ns
ns
tOOB2
RECEIVER AC/DC
Rise times and fall times measured between 20% and
80% of the signal. SATA 8 Gbps speed measured 1" from
device pin.
t20-80RX Rise and fall time
62
44
75
30
ps
ps
Difference between the single-ended mid-point of the RX+
signal rising and falling edge, and the single-ended mid-
point of the RX– signal falling and rising edge.
tskewRX
TRANSMITTER AC/DC
t20-80TX Rise and fall time
Differential skew
Rise times and fall times measured between 20% and
80% of the signal. At 8 Gbps under no load conditions
measured at the pin.
58
2
85
15
ps
ps
Difference between the single-ended mid-point of the TX+
signal rising edge and falling edge, and the single-ended
mid-point of the TX– signal falling edge and rising edge,
D1, D0 = VCC
tskewTX
Differential skew
txR/Flmb
TX rise and fall imbalance
TX amplitude imbalance
At 8 Gbps
6% 20%
1% 10%
txAmplmb
TRANSMITTER JITTER
46.5 47.5 48.3
Rise and Fall time
%
%
%
Rise and Fall mismatch
1.5%
3%
IN
t
t
PDelay
PDelay
OUT
Figure 1. Propagation Delay Timing Diagram
IN+
Vcm
IN-
50 mV
t
t
OOB2
OOB1
OUT+
Vcm
OUT-
Figure 2. OOB Enter and Exit Timing
Copyright © 2016, Texas Instruments Incorporated
7
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
RX1,2P
RX1,2N
TX1,2P
TX1,2N
VCM
RX
t
OOB1
AutoLP
EXIT
VCM
TX
Power Saving
Mode
AutoLP
ENTRY
Figure 3. Auto Low Power Mode Entry and Exit Timing
7.7 Typical Characteristics
50
45
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
8" EQ = 1, DE = 0
16" EQ = 1, DE = 0
24" EQ = 1, DE = 0
32" EQ = 1, DE = 1
36" EQ = 1, DE = 1
1.5 Gbps
3.0 Gbps
6.0 Gbps
8.0 Gpbs
0
0
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
Input Voltage (mV)
Data Rate (Gbps)
D002
D001
Function of data rate after equalizing for 32" of input
FR = 4 trace, EQ = 1, DE = 1
A function of input trace length of 4 mil FR-4
xx
Figure 5. Deterministic Jitter vs Launch Amplitude
Figure 4. Deterministic Jitter vs Data Rate
8
Copyright © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
8 Parameter Measurement Information
-RL
dB
Rx0.
TX
0.3
4
Log Frequency - GHz
6
Figure 6. TX, RX Differential Return Loss Limits
Jitter
Measurement
CP
40" 4mil
Stripline
AWG
4" 4mil Stripline
Figure 7. Jitter Measurement Test Condition
Copyright © 2016, Texas Instruments Incorporated
9
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
9 Detailed Description
9.1 Overview
The SN75LVPE801 is a single channel equalizer and redriver. The device operates over a wide range of
signaling rates, supporting operation from DC to 8 Gbps. The wide operating range supports SATA Gen 1,2,3
(1.5 Gbps, 3.0 Gbps, and 6.0 Gbps respectively) as well as PCI Express 1.0, 2.0, 3.0 (2.5 Gbps, 5.0 Gbps, and
8.0 Gbps). The device also supports SATA Express (SATA 3.2) which is a form factor specification that allows
for SATA and PCI Express signaling over a single connector.
9.2 Functional Block Diagram
VCC[1]
GND[5]
VBB = 1.7 V TYP
RT
LVPE801
RX+ [2]
RX– [3]
TX+ [7]
TX– [6]
Equalizer
Driver
RT
OOB
Detect
CTRL
EQ
[4]
DE
[8]
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 SATA Express
SATA Express (sometimes SATAe) is an electro-mechanical standard that supports both SATA and PCI Express
storage devices. SATAe is standardized in the SATA 3.2 standard. The standard is concerned with providing a
smooth transition from SATA to PCIe storage devices. The standard provides for standardized cables and
connectors, and muxes the PCIe and SATA lanes at the host side so that either SATA compliant or PCIe
compliant devices may operate with a host.
SATAe provides support for SATA1, SATA2 and SATA3 devices (operating from 1.5 Gbps to 6.0 Gbps), as well
as PCIe1, PCIe2 and PCIe3 devices (operating from 2.5 Gbps to 8.0 Gbps).
The SN75LVPE801 provides for equalization and re-drive of a single channel input signal complying with any of
the SATA or PCIe standards available with SATAe.
The SATAe standard provides for a mechanism for a host to recognize and detect whether a SATA or PCIe
device is plugged into the host. See the Typical SATA Applications section for the details of the SATA Express
Interface Detect operation.
9.3.2 Receiver Termination
The receiver has integrated terminations to an internal bias voltage. The receiver differential input impedance is
nominally 100 Ω, with a ±15% variation.
For PCI Express compatibility it is necessary to include 330 Ω pull-down resistors between the connector and the
AC capacitors, refer to Figure 24 for more information.
9.3.3 Receiver Internal Bias
The SN75LVPE801 receiver is internally biased to 1.7 V, providing support for AC coupled inputs.
10
Copyright © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
Feature Description (continued)
9.3.4 Receiver Equalization
The SN75LVPE801 incorporates programmable equalization. The EQ input controls the level of equalization that
is used to open the eye of the received input signal. If the EQ input is left open, or pulled LO, 8 dB (at 4 GHz) of
equalization is applied. When the EQ input is HIGH, the equalization is set to 16 dB (again at 4 GHz).Table 1
shows the equalization values discussed.
Table 1. EQ and DE Settings
EQUALIZATION
dB (at 8 Gbps)
EQ
DE
DE-EMPHASIS
0 (default)
1
8
0 (default)
1
0
16
–1.2
9.3.5 OOB/Squelch
The SN75LVPE801 receiver incorporates an Out-Of-Band (OOB) detection circuit in addition to the main signal
chain receiver. The OOB detector continuously monitors the differential input signal to the device. The OOB
detector has a 50-mVpp entry threshold. If the differential signal at the receiver input is less than the OOB entry
threshold, the device transmitter transitions to squelch. The SN75LVPE801 enters squelch within 5 ns of the
input signal falling below the OOB entry threshold. The SN75LVPE801 continues to monitor the input signal while
in squelch. While in squelch, if the OOB detector determines that the input signal now exceeds the 90 mVpp exit
threshold, the SN75LVPE801 exits squelch within 5 ns. See Figure 8.
IN+
Vcm
IN-
50 mV
t
t
OOB2
OOB1
OUT+
Vcm
OUT-
Figure 8. OOB Enter and Exit Timing
Receiver Input Termination is Disabled
When the SN75LVPE801 enters squelch state the transmitter output is squelched. The transmitter non-inverting
(TX+) output and the transmitter inverting output (TX-) are both driven to the transmitter nominal common mode
voltage which is 1.7 V .
9.3.6 Auto Low Power
The SN75LVPE801 also includes an Auto Low Power Mode (ALP). ALP is entered when the differential input
signal has been less than 50 mV for > 10 µs. The device enters and exits Low Power Mode by actively
monitoring the input signal level. In this state the device selectively shuts off internal circuitry to lower power by >
90% of its normal operating power. While in ALP mode the device continues to actively monitor input signal
levels. When the input signal exceeds the OOB exit threshold level, the device reverts to the active state. Exit
time from Auto Low Power Mode is < 50 ns (max). See Figure 9.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSFI1 –SEPTEMBER 2016
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RX1,2P
RX1,2N
TX1,2P
TX1,2N
VCM
RX
t
OOB1
AutoLP
EXIT
VCM
TX
Power Saving
Mode
AutoLP
ENTRY
Figure 9. Auto Low Power Mode Entry and Exit Timing
9.3.7 Transmitter Output Signal
The SN75LVPE801 differential output signal is 650 mVpp when de-emphasis is disabled (DE input is open or
pulled low).
9.3.8 Transmitter Common Mode
The SN75LVPE801 transmitter common mode output is set to 1.7 V.
9.3.9 De-Emphasis
The SN75LVPE801 transmitter incorporates programmable de-emphasis to provide signal conditioning to offset
the anticipated channel losses based on expected use cases for the device. Figure 10 shows an example of a
SATA host communicating with a SATA device through a backplane. In such a use case, an SN75LVPE801
would be located at the end of the interconnect channels (i.e. at the device end for the host TX channel, and at
the host end for the host RX channel. These locations are selected based on the signal conditioning that is
incorporated into the SN75LVPE801. The SN75LVPE801 provides up to 16 dB of equalization, while supporting
up to 1.2 dB of de-emphasis. The optimum location would therefore be at the end of the interconnect, allowing
the receiver equalization to address the majority of the channel loss, while the de-emphasis would be employed
to overcome the much shorter interconnect length.
The DE input controls the amount of de-emphasis that is applied at the transmitter output. The de-emphasis
selections are shown in Table 1. When DE is left open, or pulled low, de-emphasis shall be off. When DE is
pulled HIGH, 1.2 dB of de-emphasis is used at the transmitter output.
Figure 10. Trace Length Example
12
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SN75LVPE801
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ZHCSFI1 –SEPTEMBER 2016
9.3.10 Transmitter Termination
The SN75LVPE801 transmitter includes integrated terminations. The receiver differential output impedance is
nominally 100 Ω, with a ≤ 22% variation.
9.4 Device Functional Modes
9.4.1 Active
Active mode is the normal operating mode. When power is applied to the device, and the differential input signal
to the receiver is greater than 90 mVpp, the device is in active mode and meets all the specifications in the data
sheet.
9.4.2 Squelch
When the device is powered, and the differential input signal to the receiver is less than 50 mVpp, the device is in
squelch mode. In squelch mode the transmitter outputs are both set to VCMTX or 1.7 V.
9.4.3 Auto Low Power
When the device is powered and the differential input signal to the receiver has been less than 50 mVpp for
greater than 10 ns, the device transitions to Auto Low Power (ALP) mode. In ALP, the transmitter outputs are
both set to VCMTX. In addition, while in ALP, the device shuts off internal circuitry to lower power to less than
10% of the power in the Active mode.
Copyright © 2016, Texas Instruments Incorporated
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SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN75LVPE801 can be used for SATA applications as well as SATA Express applications. The device
supports SATA Gen1, Gen2, and Gen3 applications with data rates from 1.5 to 8 Gbps. The built-in equalization
circuits provide up to 16 dB of equalization at 4 GHz. This equalization can support SATA GEN2 (3 Gbps)
applications over up to 50 inches of FR-4 material. The same 16 dB equalizer is suited to SATA Gen3 (8 Gbps)
applications up to 40 inches of FR4.
In addition to SATA applications, the SN75LVPE801 can support SATA Express applications. SATA Express
provides a standardized interface to support both SATA (Gen1, Gen2, and Gen3) and PCI Express (PCIe 1.0,
2.0 and 3.0).
All applications of the SN75LVPE801 share some common applications issues. For example, power supply
filtering, board layout, and equalization performance with varying interconnect losses. Other applications issues
are specific, such as implementing receiver detection for SATA Express applications. The Typical Application
examples demonstrate common implementations of the SN75LVPE801 supporting SATA, as well as SATA
Express applications.
10.2 Typical SATA Applications
Copyright © 2016, Texas Instruments Incorporated
(1) Place supply caps close to the device pin
(2) EQ and DE selection at 8 dB and 0 dB respectively
(3) Actual EQ and DE settings depend on the device placement relative to the host and SATA connector
Figure 11. Typical Device Implementation
14
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SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
Typical SATA Applications (continued)
10.2.1 Design Requirements
DESIGN PARAMETERS
SATA Signaling Rate
VALUE
1.5 - 6.0 Gbps
10 nF
AC Coupling Capacitance
Interconnect Characteristic Impedance
100 Ohms
Up to 50" FR4 for SATA Gen2
Up to 40" FR4 for SATA Gen3
Interconnect Length
Termination Resistance
100 Ohms differential integrated into TX and RX
10.2.2 Detailed Design Procedure
Figure 11 shows a typical SATA Application. The SATA host, which may be a notebook or desktop,
communicates with a SATA sink, which could be a SSD mass storage device. The SATA host and sink
communicate over a backplane differential pair, or a SATA cable. When using the SN75LVPE801 as an
equalizer/redriver, the designer would optimally place the SN75LVPE801 close to the end of the interconnect.
The SN75LVPE801 provides up to 16 dB of equalization, and up to 1.2 dB of de-emphasis. Placing the
SN75LVPE801 close to the end of the interconnect allows the device equalizer to address the majority of the
high frequency losses introduced in the channel.
Ensure that the channel loss for the interconnect material and length is matched reasonably well to the
selectable equalization and de-emphasis settings available on the SN75LVPE801. The table above provides an
estimate of the amount of FR4 material that could be used as a function of the signal rate. In any case, channel
modeling would be prudent to ensure that the SATA host, interconnect, SATA equalizer/re-driver, and SATA Sink
can establish and maintain a low BER link.
The AC coupling capacitors of 10 nF are chosen to comply with the SATA standard (< 12 nF)
Often a designer may not be sure whether a signal conditioning device like the SN75LVPE801 is needed in their
specific application. The SN75LVPE801 allows the user to take the guess work of using a signal conditioning
device in a SATA link. With the SN75LVPE801 the designer has the option to use or remove the device based
on signal conditioning needs. Figure 12 shows guidelines that could be used to allow in situ testing when a board
is available. The designer would start with 0 Ω resistors in place to determine if the eye quality at the end of the
link is satisfactory. If the eye opening is not sufficient, the 0 Ω resistors could be replaced with the
SN75LVPE801.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSFI1 –SEPTEMBER 2016
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Figure 12. Implementation Guideline
To demonstrate the effectiveness of the SN75LVPE801 signal conditioning for varied configurations that may be
encountered, Figure 13 is used as a reference. A Gen3, 6 Gbps SATA host communicates with a sink located at
point B. The host and sink are separated by “X+Y” inches, where X represents the distance between the host
and the SN75LVPE801, while Y represents the distance between the SN75LVPE801 and the sink. The
Application Curves are for a 6-Gbps K28.5 pattern, with VCC = 3.3 V and at an ambient temperature of 25°C.
DE
EQ
A
B
X
Y
SATA 6G
Host
801
(4 mil)
(4 mil)
Figure 13. Test Points
16
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SN75LVPE801
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ZHCSFI1 –SEPTEMBER 2016
10.2.3 Application Curves
All graphs at 6 Gbps
DE = 1
EQ = 0
DE = 1
EQ = 0
Figure 14. Eye Pattern at A → X = 8”; Y = 2”
Figure 15. Eye Pattern at B → X = 8”; Y = 2”
DE = 1
EQ = 0
DE = 1
EQ = 0
Figure 16. Eye Pattern at A → X = 16”; Y = 2”
Figure 17. Eye Pattern at B → X = 16”; Y = 2”
DE = 1
EQ = 0
DE = 1
EQ = 0
Figure 18. Eye Pattern at A → X = 24”; Y = 2”
Figure 19. Eye Pattern at B→ X = 24”; Y = 2”
Copyright © 2016, Texas Instruments Incorporated
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SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
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DE = 1
EQ = 1
DE = 1
EQ = 1
Figure 20. Eye Pattern at A → X = 32”; Y = 2”
Figure 21. Eye Pattern at B → X = 32”; Y = 2”
DE = 1
EQ = 1
DE = 1
EQ = 1
Figure 22. Eye Pattern at A → X = 40”; Y = 2”
Figure 23. Eye Pattern at B → X = 40”; Y = 2”
18
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SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
10.2.4 SATA Express Applications
Connector
Host Controller
Device
VCC
1
2
3
4
8
7
6
5
VCC
RX+
RX-
EQ
DE
TX+
220nF
220nF
200nF
TX-
200nF
GND
SN75LVPE801
330
330
VCC
8
7
6
5
1
2
3
4
DE
VCC
RX+
RX-
EQ
220nF
470nF
200nF
200nF
TX+
TX-
220nF
470nF
GND
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
Figure 24. SN75LVPE801 SATA Express Reference Schematic
EQ: 8 dB when Floated, DE: 0 dB when Floated
10.2.4.1 Design Requirements
DESIGN PARAMETERS
VALUE
1.5 - 8.0 Gbps
200 - 220 nF
100 Ω
SATA Express Signaling Rate
AC Coupling Capacitance
Interconnect Characteristic Impedance
Up to 50" FR4 for SATA Gen2
Up to 40" FR4 for SATA Gen3
Interconnect Length
Receiver pull-down terminations
Termination Resistance
330 Ω
100 Ohms differential integrated into TX and RX
Copyright © 2016, Texas Instruments Incorporated
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SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
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10.2.4.2 Detailed Design Procedure
Figure 24 is a reference schematic of a SATAe implementation using the SN75LVPE801. With a SATAe design,
both SATA and PCI Express must be supported. SATAe supports both cabled and direct connections. Using a
cabled application as an example, the SATAe power connector includes an Interface Detect (IFDet, power
connector pin P4) signal that indicates whether a SATA client or a PCIe client is connected.
When the SATAe host determines that a PCIe client is connected, the SATAe host performs receiver detection.
Receiver detection determines the presence of a client by detecting the load impedance. The transmitter
performs a common mode voltage shift, and measures the rate at which the voltage at the transmitter output
changes. The rate of change indicates if a client is present (fast charging when a low impedance load is present,
or slow charging when the load is open or high impedance). With the implementation in Figure 24, 330-Ω
pulldowns have been inserted between the host and the SN75LVPE801. The pulldown resistors indicate to the
host that a client is present. While an actual client would be expected to have an active load of 50 Ω single
ended, the 330 Ω is chosen here to meet two requirements. The 330 Ω is low enough to force the SATAe host to
decide that a receiver is present, while also high enough to only marginally affect the load when the
SN75LVPE801 is active, and presenting a 50-Ω load. With the 50 Ω and 330 Ω are both present, the parallel
combination of 43 Ω is satisfactory for most applications.
Assuming that the SATAe host has detected (via IFDet) that a SATA client is present, the SATAe host
communicates with the client via the SN75LVPE801. The SATA standard does not have a receiver detection
mode as is present in PCIe. A SATA host does use OOB signaling to communicate identification information. The
SN75LVPE801 incorporates an OOB detector in order to support OOB signaling through the device. The OOB
detector drives a squelch circuit on the SN75LVPE801 output transmitter. (See OOB/Squelch for more details on
the OOB/Squelch circuitry.)
Returning again to Figure 24, we see 200-nF AC coupling capacitors on the device or client side of the interface.
These capacitors allow interfacing to both SATA and PCIe clients. In the case of a PCIe client, the 200 nF is
within the acceptable range for all PCIe devices. When a SATA client is present, the 200 nF capacitor has little
effect on the overall link, as it appears in series with the 12-nF (max) AC coupling capacitor incorporated into the
SATA client. The 200 nF in series with the 12 nF presents an effective capacitance of 11.3 nF, as expected less
than the 12-nF maximum permitted.
The physical placement of the resistors on the high-speed transmission lines can be made as not to create a
stub on the transmission line by using resistors with the 0201 package size, an example is provided in Figure 25.
SN75LVPE801
0201 Package Size
300-W Resistor
Rx +/-
TRACE
VIA to GND
Figure 25. Resistor Placement to Avoid Stub (All Dimensions in mm)
20
Copyright © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
10.2.4.3 Application Curve
Eye-diagrams were taken on the SN75LVPE801 configured as in Figure 24 above. Testing was performed at a
PCIe 3.0 speed of 8Gbps.
Figure 26. SN75LVPE801 8-Gbps Eye-Diagram
10.2.5 PCIe Applications
PCIe-only applications are implemented in a manner very similar to SATA Express applications as covered in
Detailed Design Procedure. Looking at Figure 27, and comparing it to the SATA Express application in Figure 24,
a single change is noted. For PCIe applications the 220 nF AC-coupling capacitors on the Host-to-Device link are
relocated from the Device side of the connector to the Host side. No other changes are required.
Connector
VCC
Host Controller
Device
1
2
3
4
8
7
6
5
VCC
RX+
RX-
EQ
DE
TX+
220nF
220nF
220nF
220nF
TX-
GND
SN75LVPE801
330
330
VCC
8
7
6
5
1
2
3
4
DE
VCC
RX+
RX-
EQ
220nF
470nF
200nF
200nF
TX+
TX-
220nF
470nF
GND
SN75LVPE801
330
330
Copyright © 2016, Texas Instruments Incorporated
Figure 27. SN75LVPE801 PCI-Express Reference Schematic
EQ: 7 dB when Floated, DE: 0 dB when Floated
11 Power Supply Recommendations
The SN75LVPE801DRF is designed to operate from a single 3.3-V supply. Always practice proper power-supply
sequencing procedure. Apply VCC first before any input signals are applied to the device. The power-down
sequence is in reverse order.
Copyright © 2016, Texas Instruments Incorporated
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12 Layout
12.1 Layout Guidelines
12.1.1 Return Current and Plane References
High frequency return signal/current is defined as the path that a signal follows back to its original source as all
signals flow in a closed loop. Minimizing the loop area of the closed loop is beneficial for both EMI (Electro-
Magnetic Interference) reduction and signal integrity.
The best way to minimize loop area is to always have a signal reference their nearest solid ground or power
plane. Obstructions to the return signal causes signal integrity problems like reflections, crosstalk, undershoot
and overshoot.
Signals can reference either power or ground planes, but ground is preferred. Without solid plane references,
single ended and differential impedance control is very hard to accomplish; crosstalk to other signals may
happen as the return signals have no other path. This type of crosstalk is difficult to troubleshoot.
Symmetric pairing of solid planes in the layer stackup can significantly reduce warping of the PCB during the
manufacturing process. Warping of the PCB is crucial to minimize on boards that uses BGA components.
12.1.2 Split Planes – What to Avoid
Never route signals over splits in their perspective reference planes.
Figure 28. Overlapping Analog and Digital Planes
22
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SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
Layout Guidelines (continued)
Figure 29. Incorrect Routing
Figure 30. Proper Routing
Copyright © 2016, Texas Instruments Incorporated
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SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
Layout Guidelines (continued)
12.1.3 Avoiding Crosstalk
Crosstalk is defined as interference from one trace to another by either or both inductive and capacitive coupling.
Best ways to avoid crosstalk are:
•
•
Provide stable reference planes for all high speed signals (as noted in previous sections).
Use the 3W rule (3 times the width of trace for separation) where applicable on all signals, but absolutely use
on clock signals.
•
•
Use ground traces/guards around either victim or aggressor signals prone to crosstalk.
When space is constrained and limited on areas of the PCB to route parallel buses, series or end termination
resistors can be used to route traces closer than what is normally recommended. However, calculations and
simulations must be done to validate the use of series or end termination resistors to eliminate crosstalk.
Figure 31. Ways to Avoid Crosstalk
12.2 Layout Example
Figure 32. Printed-Circuit Board Stackup (FR-4 Example)
24
版权 © 2016, Texas Instruments Incorporated
SN75LVPE801
www.ti.com.cn
ZHCSFI1 –SEPTEMBER 2016
Layout Example (接下页)
PCB layer configuration suggestions for stackup symmetry and signal integrity.
Figure 33. PCB Layer Configuration Suggestions
版权 © 2016, Texas Instruments Incorporated
25
SN75LVPE801
ZHCSFI1 –SEPTEMBER 2016
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
26
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都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN75LVPE801DRFR
SN75LVPE801DRFT
ACTIVE
ACTIVE
WSON
WSON
DRF
DRF
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 85
0 to 85
801
801
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
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