SNJ54ALS996JT [TI]
8 位 D 类边沿触发读回锁存器 | JT | 24 | -55 to 125;
| 型号： | SNJ54ALS996JT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位 D 类边沿触发读回锁存器 | JT | 24 | -55 to 125 驱动 锁存器 总线驱动器 总线收发器 |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
SN54ALS996 . . . JT PACKAGE
SN74ALS996 . . . DW OR NT PACKAGE
(TOP VIEW)
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• T/C Determines True or Complementary
Data at Q Outputs
1D
2D
3D
4D
5D
6D
7D
8D
EN
V
CC
1
2
3
4
5
6
7
8
9
24
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 OE
14 T/C
13 CLR
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.
RD 10
CLK 11
GND 12
The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN) input is low. Data can be
read back onto the data inputs by taking the read
(RD) input low, in addition to having EN low. When
EN is high, both the read-back and write modes
are disabled. Transitions on EN should only be
made with CLK high to prevent false clocking.
SN54ALS996 . . . FK PACKAGE
(TOP VIEW)
4
3
2
1
28 27 26
25
4D
5D
6D
NC
7D
8D
EN
3Q
4Q
5Q
NC
6Q
7Q
8Q
5
24
23
22
21
20
19
6
7
The polarity of the Q outputs can be controlled by
the polarity (T/C) input. When T/C is high, Q is the
same as is stored in the flip-flops. When T/Cis low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (OE) input high. OE does not affect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.
8
9
10
11
12 13 14 15 16 17 18
NC – No internal connection
A low level at the clear (CLR) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum
for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
I
OL
The SN54ALS996 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
†
logic symbol
15
EN4
N3
OE
14
13
10
9
T/C
R
&
CLR
RD
EN2
EN
≥ 1
C1
11
1
CLK
1D
1D
2
23
3,4
1Q
2
3
4
5
6
7
8
22
21
20
19
18
17
16
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
15
OE
14
T/C
13
CLR
10
RD
9
EN
11
CLK
1
1D
C1
1D
23
1Q
R
To Seven Other Channels
Pin numbers shown are for the DW, JT, and NT packages.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
timing diagram
(T/C = H)
CLR
D
Input Data
Read-Back Data
t
su
t
h
t
w
CLK
EN
t
en
t
dis
t
su
†
t
h
t
t
en
dis
RD
Q
t
p
Output
Output Data
t
t
en
dis
OE
Async
Clear
Write
Read
Back
†
This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
recommended operating conditions
SN54ALS996
SN74ALS996
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
5
5.5
4.5
2
5
5.5
V
CC
All inputs
High-level input voltage
All inputs except OE, RD
OE, RD
2
V
IH
2.2
Low-level input voltage
High-level output current
0.8
–1
0.8
–2.6
–0.4
24
V
IL
Q
D
I
mA
OH
–0.4
12
Q
D
†
48
I
f
t
Low-level output current
Clock frequency
mA
MHZ
ns
OL
clock
w
8
8
0
10
35
0
10
14.5
14.5
15
10
15
10
0
35
CLR low
Pulse duration
CLK low
14.5
14.5
15
CLK high
Data before CLK↑
EN low before CLK↑
10
t
t
Setup time
ns
su
‡
CLK high before EN↑
15
CLR high (inactive) before CLK↑
Data after CLK↑
10
1
Hold time
EN low after CLK↑
5
5
ns
h
§
RD high after CLK↑
5
5
T
A
Operating free-air temperature
–55
125
0
70
°C
†
‡
§
Applies only to the -1 version and only if V
CC
This setup time ensures that EN will not false clock the data register.
This hold time ensures that there will be no conflict on the input data bus.
is maintained between 4.75 V and 5.25 V
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS996
SN74ALS996
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
All outputs
Q
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
I
= – 0.4 mA
= – 1 mA
= – 2.6 mA
= 4 mA
V
–2
V
CC
–2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
3.2
0.25
0.25
V
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.2
0.4
0.4
D
Q
V
= 8 mA
0.35
0.25
0.35
0.35
0.5
0.4
0.5
0.5
20
V
OL
= 12 mA
= 24 mA
V
CC
= 4.5 V
‡
= 48 mA
= 2.7 V
= 0.4 V
I
I
Q
V
V
= 5.5 V,
= 5.5 V,
V
V
20
–20
0.1
µA
µA
OZH
CC
O
Q
–20
0.1
0.1
20
OZL
CC
O
D inputs
All others
V = 5.5 V
I
I
I
V
V
= 5.5 V
= 5.5 V,
mA
CC
V = 7 V
I
0.1
§
D inputs
All others
20
V = 2.7 V
I
µA
I
CC
IH
IL
20
20
§
D inputs
All others
–0.1
–0.1
–0.1
–0.1
V
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
I
mA
mA
I
CC
V
= 2.25 V
CC
O
¶
–20
–112
–30
–112
I
O
CLR = 2.5 V
Outputs high
Outputs low
35
55
42
55
85
65
35
55
42
55
85
65
V
= 5.5 V,
CC
EN, RD low
I
mA
CC
Outputs disabled
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
‡
§
¶
Applies only to the -1 version and only if V
is maintained between 4.75 V and 5.25 V
CC
For I/O ports (Q thru Q ), the parameters I and I include the off-state output current.
A
H
IH IL
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
T
A
= 4.5 V to 5.5 V,
= 50 pF,
= MIN to MAX
CC
L
†
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
SN54ALS996 SN74ALS996
MIN
35
5
MAX
MIN
35
5
MAX
f
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PHL
30
24
27
23
23
23
30
18
19
17
19
15
11
28
28
27
23
23
23
30
16
19
16
19
15
10
CLK
(T/C = H or L)
Q
Q
5
5
CLR (T/C = L)
CLR (T/C = H)
5
7
ns
5
7
4
5
ns
ns
ns
T/C
Q
D
5
5
CLR
5
8
‡
2
3
t
t
t
t
t
t
en
RD
EN
OE
D
D
Q
§
1
3
dis
‡
2
3
en
ns
ns
§
1
3
dis
‡
2
4
en
§
1
1
dis
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t = t
en PZH
or t
PZL
or t
t = t
dis PHZ
PLZ
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
7 V
7 V
S1
S1
500 Ω
1 kΩ
Test
Point
Test
Point
From Output
Under Test
From Output
Under Test
C
C
L
L
1 kΩ
500 Ω
(see Note A)
(see Note A)
LOAD CIRCUIT FOR Q OUTPUTS
LOAD CIRCUIT FOR D OUTPUTS
3.5 V
0.3 V
3.5 V
Timing
Input
High-Level
Pulse
1.3 V
1.3 V
1.3 V
0.3 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
1.3 V
1.3 V
(low-level
enabling)
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note C)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
OH
OL
Waveform 2
S1 Open
(see Note C)
Out-of-Phase
Output
1.3 V
1.3 V
0.3 V
V
(see Note B)
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
Figure 1. Load Circuits and Voltage Waveforms
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–8
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明