SNJ54AS574B [TI]
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS; 八D型边沿触发触发器具有三态输出
| 型号： | SNJ54AS574B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总25页 (文件大小：1247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
SN54ALS574B, SN54AS574 . . . J OR W PACKAGE
SN74ALS574B, SN74AS574 . . . DW OR N PACKAGE
(TOP VIEW)
• 3-State Buffer-Type Noninverting Outputs
Drive Bus Lines Directly
• Bus-Structured Pinout
• Buffered Control Inputs
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19 1Q
18 2Q
17
16
15
14
13
12
11
• SN74ALS575A and ′AS575 Have
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Synchronous Clear
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N, NT)
and Ceramic (J, JT) 300-mil DIPs, and
Ceramic Flat (W) Packages
GND
SN54ALS574B, SN54AS574 . . . FK PACKAGE
(TOP VIEW)
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
3
9
2
1 20 19
18 2Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
3Q
4Q
5Q
6Q
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input. The
SN74ALS575A, SN54AS575, and SN74AS575
may be synchronously cleared by taking the clear
(CLR) input low.
10 11 1213
SN54AS575 . . . JT OR W PACKAGE
SN74ALS575A, SN74AS575 . . . DW OR NT PACKAGE
(TOP VIEW)
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLR
OE
1D
V
CC
NC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
NC
2D
3D
4D
5D
6D
7D
8D
The
SN54ALS574B,
SN54AS574,
and
SN54AS575 are characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74ALS574B, SN74ALS575A,
SN74AS574, and SN74AS575 are characterized
for operation from 0°C to 70°C.
9
10
11
12
NC
GND
SN54AS575 . . . FK PACKAGE
(TOP VIEW)
4
3
2
1 28 27 26
5
6
7
8
9
25
24
23
22
21
20
19
2D
3D
4D
NC
5D
6D
7D
2Q
3Q
4Q
NC
5Q
6Q
7Q
10
11
1213
18
14 15 16 17
NC – No internal connection
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
Function Tables
SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q
0
H
Z
SN74ALS575A, SN54AS575, SN74AS575
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLR
CLK
D
X
H
L
L
H
H
H
X
↑
↑
L
H
L
L
L
↑
L
L
H
X
X
Q
0
H
Z
†
logic symbols
SN54ALS574B, SN74ALS574B,
SN54AS574, SN74AS574
SN74ALS575A, SN54AS575,
SN74AS575
1
2
EN
C1
OE
EN
C1
1R
OE
11
14
1
CLK
CLK
CLR
2
3
4
5
6
7
8
9
19
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
18
17
16
15
14
13
12
3
22
21
20
19
18
17
16
15
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
5
6
7
8
9
10
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, J, JT, N, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
logic diagrams (positive logic)
SN54ALS574B, SN74ALS574B,
SN54AS574, SN74AS574
SN74ALS575A, SN54AS575,
SN74AS575
1
2
OE
OE
14
1
11
2
CLK
CLK
CLR
1D
C1
1D
19
1Q
1D
C1
1D
22
1Q
3
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DW, J, JT, N, and NT packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS574B . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS574B, SN74ALS575A . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS574B
SN74ALS575A
SN54ALS574B
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
IH
0.7
–1
12
28
0.8
–2.6
24
V
IL
I
mA
mA
OH
OL
I
′ALS574B
0
16.5
15
0
0
35
f
t
t
t
Clock frequency
MHz
ns
clock
SN74ALS575A
30
′ALS574B, CLK high or low
SN74ALS575A, CLK high or low
Data
14
16.5
15
15
0
Pulse duration
w
ns
Setup time before CLK↑
su
h
SN74ALS575A, CLR
Data
4
ns
Hold time after CLK↑
SN74ALS575A, CLR
0
T
A
Operating free-air temperature
–55
125
0
70
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS574B
SN54ALS574B
SN74ALS575A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –0.4 mA
= –1 mA
= –2.6 mA
= 12 mA
= 24 mA
= 2.7 V
V
–2
V
CC
–2
CC
OH
OH
OH
OL
OL
CC
2.4
3.3
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.2
0.25
0.35
0.25
0.4
0.4
0.5
20
V
OL
V
V
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
20
–20
0.1
20
µA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–20
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
IH
V = 0.4 V
I
–0.2
–112
18
–0.2
–112
18
mA
mA
IL
‡
V
O
= 2.25 V
–20
–30
O
Outputs high
Outputs low
11
17
17
10
15
16
11
17
17
10
15
16
′ALS574B
V
= 5.5 V
= 5.5 V
27
27
CC
CC
Outputs disabled
Outputs high
Outputs low
28
28
I
mA
CC
17
17
SN74ALS575A
V
24
24
Outputs disabled
30
30
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
§
= MIN to MAX
SN54ALS574B SN74ALS574B SN74ALS575A
MIN
28
4
MAX
MIN
35
3
MAX
MIN
30
4
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
22
17
21
26
16
25
14
14
18
18
10
12
14
14
18
18
10
13
CLK
Q
Q
Q
4
4
4
4
3
4
ns
ns
OE
OE
4
4
4
2
1
2
2
2
3
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54AS574, SN54AS575 . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS574, SN74AS575 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS574
SN54AS575
SN74AS574
SN74AS575
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–12
32
0.8
–15
48
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
*
0
5
100
0
5.5
5.5
5.5
6.5
3
90
CLK high
t *
w
Pulse duration
ns
ns
CLK low
4
Data
3
t
su
*
Setup time before CLK↑
′AS575, CLR high or low
Data
6.5
3
t *
h
ns
Hold time after CLK↑
′AS575, CLR
0
0
T
A
Operating free-air temperature
–55
125
0
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS574
SN54AS575
SN74AS574
SN74AS575
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –2 mA
= –12 mA
= –15 mA
= 32 mA
= 48 mA
= 2.7 V
V
–2
CC
2.4
V
–2
CC
OH
OH
OH
OL
OL
CC
3.2
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.3
0.29
0.5
V
OL
V
V
0.34
0.5
50
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
50
–50
0.1
µA
µA
mA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–50
0.1
V = 7 V
I
V = 2.7 V
I
20
20
IH
OE, CLK, CLR
–0.5
–3
–0.5
–2
I
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
mA
mA
IL
CC
CC
I
D
‡
I
O
V
V
O
= 2.25 V
–30
–112
116
134
134
126
142
142
–30
–112
116
134
134
126
142
142
Outputs high
Outputs low
73
85
84
78
89
88
73
85
84
78
89
88
′AS574
′AS575
V
= 5.5 V
= 5.5 V
CC
CC
Outputs disabled
Outputs high
Outputs low
I
mA
CC
V
Outputs disabled
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
§
= MIN to MAX
PARAMETER
(INPUT)
UNIT
SN54AS574
SN54AS575
SN74AS574
SN74AS575
MIN
100
3
MAX
MIN
90
3
MAX
f
t
t
t
t
t
t
*
MHz
ns
max
11
11
7
8
9
PLH
PHL
PZH
PZL
PHZ
PLZ
CLK
Any Q
Any Q
Any Q
4
4
2
2
6
ns
ns
OE
OE
3
11
7
3
10
6
2
2
2
7
2
6
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS574B, SN54AS574, SN54AS575
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS165B – JUNE 1982 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
84001012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84001012A
SNJ54ALS
574BFK
8400101RA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
FK
J
20
20
20
20
20
20
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
A42
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8400101RA
SNJ54ALS574BJ
8400101SA
8400101SA
SNJ54ALS574BW
JM38510/37104B2A
JM38510/37104BRA
M38510/37104B2A
M38510/37104BRA
LCCC
CDIP
LCCC
CDIP
POST-PLATE
A42
JM38510/
37104B2A
JM38510/
37104BRA
FK
J
POST-PLATE
A42
JM38510/
37104B2A
JM38510/
37104BRA
SN54ALS574BJ
SN54AS574J
ACTIVE
ACTIVE
CDIP
CDIP
J
J
20
20
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
SN54ALS574BJ
SN54AS574J
SN54AS575JT
OBSOLETE
ACTIVE
CDIP
SOIC
JT
24
20
Call TI
Call TI
-55 to 125
0 to 70
SN74ALS574BDW
DW
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALS574B
SN74ALS574BDWE4
SN74ALS574BDWG4
SN74ALS574BDWR
SN74ALS574BDWRE4
SN74ALS574BDWRG4
SN74ALS574BN
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
N
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Call TI
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
ALS574B
25
Green (RoHS
& no Sb/Br)
ALS574B
ACTIVE
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
ALS574B
ACTIVE
Green (RoHS
& no Sb/Br)
ALS574B
ACTIVE
Green (RoHS
& no Sb/Br)
ALS574B
ACTIVE
Pb-Free
(RoHS)
SN74ALS574BN
SN74ALS574BN3
OBSOLETE
N
TBD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74ALS574BNE4
SN74ALS574BNSR
SN74ALS574BNSRE4
SN74ALS574BNSRG4
SN74ALS575ADW
SN74ALS575ADWE4
SN74ALS575ADWG4
SN74ALS575ANT
SN74ALS575ANTE4
SN74AS574DW
ACTIVE
PDIP
SO
N
20
20
20
20
24
24
24
24
24
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74ALS574BN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NS
NS
NS
DW
DW
DW
NT
NT
DW
DW
DW
DW
DW
DW
N
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
ALS574B
ALS574B
ALS574B
ALS575A
ALS575A
ALS575A
SN74ALS575ANT
SN74ALS575ANT
AS574
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
15
Pb-Free
(RoHS)
15
Pb-Free
(RoHS)
N / A for Pkg Type
25
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74AS574DWE4
SN74AS574DWG4
SN74AS574DWR
SN74AS574DWRE4
SN74AS574DWRG4
SN74AS574N
25
Green (RoHS
& no Sb/Br)
AS574
25
Green (RoHS
& no Sb/Br)
AS574
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
AS574
Green (RoHS
& no Sb/Br)
AS574
Green (RoHS
& no Sb/Br)
AS574
Pb-Free
(RoHS)
SN74AS574N
SN74AS574N
SN74AS574NE4
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
SN74AS575DW
OBSOLETE
OBSOLETE
SOIC
SOIC
DW
DW
24
24
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
SN74AS575DWR
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74AS575NT
OBSOLETE
ACTIVE
PDIP
NT
24
20
TBD
TBD
Call TI
Call TI
0 to 70
SNJ54ALS574BFK
LCCC
FK
1
POST-PLATE
N / A for Pkg Type
-55 to 125
84001012A
SNJ54ALS
574BFK
SNJ54ALS574BJ
SNJ54ALS574BW
SNJ54AS574FK
SNJ54AS574J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
FK
J
20
20
20
20
1
1
1
1
TBD
TBD
TBD
TBD
A42
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8400101RA
SNJ54ALS574BJ
8400101SA
SNJ54ALS574BW
LCCC
CDIP
POST-PLATE
A42
SNJ54AS
574FK
SNJ54AS574J
SNJ54AS575FK
SNJ54AS575JT
SNJ54AS575W
OBSOLETE
OBSOLETE
OBSOLETE
LCCC
CDIP
CFP
FK
JT
W
28
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS574B, SN54AS574, SN54AS575, SN74ALS574B, SN74AS574, SN74AS575 :
Catalog: SN74ALS574B, SN74AS574, SN74AS575
•
Military: SN54ALS574B, SN54AS574, SN54AS575
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS574BDWR
SN74ALS574BNSR
SN74AS574DWR
SOIC
SO
DW
NS
20
20
20
2000
2000
2000
330.0
330.0
330.0
24.4
24.4
24.4
10.8
8.2
13.0
13.0
13.0
2.7
2.5
2.7
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
SOIC
DW
10.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS574BDWR
SN74ALS574BNSR
SN74AS574DWR
SOIC
SO
DW
NS
20
20
20
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
SOIC
DW
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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