SNLV1023ARHBTG4 [TI]
10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER; 10 MHz至66 MHz的10 ： 1 LVDS串行器/解串器
| 型号： | SNLV1023ARHBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER |
| 文件： | 总29页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LV1023A
SN65LV1224B
www.ti.com
SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
FEATURES
•
•
•
Lock Indicator
•
100-Mbps to 660-Mbps Serial LVDS Data
Payload Bandwidth at 10-MHz to 66-MHz
System Clock
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN
Packages Available
•
•
•
Pin-Compatible Superset of
DS92LV1023/DS92LV1224
•
Industrial Temperature Qualified, TA = –40°C
to 85°C
Chipset (Serializer/Deserializer) Power
Consumption <450 mW (Typ) at 66 MHz
•
•
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
Synchronization Mode for Faster Lock
DESCRIPTION
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz
to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload
encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC
patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,
the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is
available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to
85°C.
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SYNC1
SYNC2
DV
DV
AV
AGND
PWRDN
AGND
CC
CC
CC
2
3
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
32 31 30 29 28 27 26 25
4
D
D
1
24
23
22
21
20
19
18
17
AGND
IN1
5
2
3
4
5
6
7
8
2
PWRDN
AGND
6
IN
IN
DB Package
SN65LV1023A
Serializer
7
D +
D
3
O
RHB Package
SN65LV1023A
Serializer
8
D −
O
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
O+
D
O−
9
AGND
DEN
AGND
10
11
12
13
14
(Top View)
AGND
DEN
AV
CC
TCLK_R/F
TCLK
DGND
DGND
AGND
9
10 11 12 13 14 15 16
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LV1023A
SN65LV1224B
www.ti.com
SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
RCLK_R/F
REFCLK
R
R
R
R
R
OUT0
OUT1
OUT2
OUT3
OUT4
2
3
4
AV
CC
5
R +
I
32 31 30 29 28 27 26 25
6
R −
DV
CC
DGND
DV
I
AV
1
24
23
22
21
20
19
18
17
R
R
CC
OUT3
DB Package
SN65LV1224B
Deserializer
7
PWRDN
REN
RCLK
LOCK
2
3
4
5
6
7
8
R
I+
I−
OUT4
8
CC
R
DV
CC
9
DGND
RHB Package
SN65LV1224B
Deserializer
(Top View)
10
11
12
13
14
R
OUT5
PWRDN
REN
DGND
DV
AV
R
OUT6
R
OUT7
R
OUT8
R
OUT9
CC
CC
AGND
AGND
DGND
RCLK
LOCK
DGND
R
OUT5
AV
R
OUT6
CC
9
10 11 12 13 14 15 16
BLOCK DIAGRAMS
SN65LV1023A
SN65LV1224B
LVDS
10
10
A+ Y+
D
IN
D
OUT
A− Y−
TCLK_R/F
TCLK
(10 MHz to
66 MHz)
REFCLK
REN
Timing /
Control
Timing /
Control
PLL
DEN
PLL
LOCK
Clock
Recovery
SYNC1
SYNC2
RCLK_R/F
RCLK
(10 MHz to
66 MHz)
2
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SN65LV1224B
www.ti.com
SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
FUNCTIONAL DESCRIPTION
The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over
differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset
has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down
mode, and high-impedance mode. The following sections describe each state of operation.
INITIALIZATION MODE
Initialization of both devices must occur before data transmission can commence. Initialization refers to
synchronization of the serializer and deserializer PLLs to local clocks.
When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,
while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device
begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an
external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs
remain in the high-impedance state, while the PLL locks to the TCLK.
SYNCHRONIZATION MODE
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be
accomplished in one of two ways:
•
Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six
ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the
deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC
patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or
SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock
information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC
patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes
low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the
deserializer LOCK output directly to SYNC1 or SYNC2.
•
Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the
serializer to send special SYNC patterns. This allows the SN65LV1224B to operate in open-loop
applications. Equally important is the deserializer’s ability to support hot insertion into a running backplane. In
the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because
lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary
constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK
when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT); see Figure 1 for RMT examples. This occurs when more than one low-high transition takes
place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data
pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists.
Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern
changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock,
the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle.
The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start
bits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive
cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event
of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a
high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted.
3
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SN65LV1224B
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
FUNCTIONAL DESCRIPTION (continued)
D
IN0
Held Low and D
Held High
IN1
Stop Start
Bit Bit
Stop Start
Bit Bit
D
IN0
D
IN1
D
IN4
Held Low and D
Held High
IN5
Stop Start
Bit Bit
Stop Start
Bit Bit
D
IN4
D
IN5
D
IN8
Held Low and D
Held High
IN9
Stop Start
Bit Bit
Stop Start
Bit Bit
D
IN8
D
IN9
Figure 1. RMT Pattern Examples
DATA TRANSMISSION MODE
After initialization and synchronization, the serializer accepts parallel data from inputs DIN0–DIN9. The serializer
uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to
strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0–DIN9 is ignored
regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.
After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±) at
12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mbps. Because
only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz,
the useful data rate is 66 × 10 = 660 Mbps. The data source, which provides TCLK, must be in the range of 10
MHz to 66 MHz.
The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.
The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the serializer output pins enter the high-impedance state.
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SN65LV1224B
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
FUNCTIONAL DESCRIPTION (continued)
Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to
the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise
ROUT0–ROUT9 is invalid. The ROUT0–ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be
used is selected by the RCLK_R/F input. The ROUT0–ROUT9, LOCK and RCLK outputs can drive a maximum of
three CMOS input gates (15-pF load. total for all three) with a 66-MHz clock.
POWER DOWN
When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the
power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down
when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power
down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces
supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.
Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and
resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer
initialize and drives LOCK high until lock to the LVDS clock occurs.
HIGH-IMPEDANCE MODE
The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins
(DO+ and DO–) into a high-impedance state. When you drive DEN high, the serializer returns to the previous
state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin
is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting
the state of the PLL.
Deserializer Truth Table
INPUTS
OUTPUTS
(2)
PWRDN
REB
H
ROUT(0:9)(1)
LOCK
RCLK(3)(1)
H
H
L
Z
Active
Z
H
L
Z
Active
Z
H
X
Z
H
L
Z
Active
Z
(1) ROUT and RCLK are 3-stated when LOCK is asserted high.
(2) LOCK output reflects the state of the deserializer with regard to the selected data stream.
(3) RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by
RCLK_R/F.
FAILSAFE BIASING FOR THE SN65LV1224B
The SN65LV1224B has an input threshold sensitivity of ±50 mV. This allows for greater differential noise margin
in the SN65LV1224B. However, in cases where the receiver input is not being actively driven, the increased
sensitivity of the SN65LV1224B can pickup noise as a signal and cause unintentional locking. This may occur
when the input cable is disconnected. The SN65LV1224B has an on-chip fail-safe circuit that drives the serial
input and LOCK signal high. The response time of the fail-safe circuit depends on interconnect characteristics.
5
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SN65LV1224B
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
TERMINAL FUNCTIONS
PIN
I/O
DESCRIPTION
DB PACKAGE
SERIALIZER
18, 20, 23, 25
17, 26
RHB PACKAGE
17, 19, 22, 24
16, 25
AGND
AVCC
Analog circuit ground (PLL and analog circuits)
Analog circuit power supply (PLL and analog circuits)
LVTTL logic input. Low puts the LVDS serial output into the high-impedance state.
High enables serial data output.
19
18
DEN
15, 16
3–12
21
12, 13, 14, 15
32, 1–9
20
DGND
DIN0 – DIN9
DO–
Digital circuit ground
Parallel LVTTL data inputs
Inverting LVDS differential output
Noninverting LVDS differential output
Digital circuit power supply
22
21
DO+
27, 28
26, 27, 28, 29
DVCC
LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs
into the high-impedance state, putting the device into a low-power mode.
24
23
PWRDN
LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of
the two pins is asserted high for 6 cycles of TCLK, the serializer initiates
transmission of a minimum 1026 SYNC patterns. If after completion of the
transmission of 1026 patterns SYNC continues to be asserted, then the
transmission continues until SYNC is driven low and if the time SYNC holds > 6
cycles, another 1026 SYNC pattern tranmission initiates.
SYNC1,
SYNC2
1, 2
30, 31
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a
TCLK rising-edge data strobe.
13
14
10
11
TCLK_R/F
TCLK
LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to
66-MHz clock. TCLK strobes parallel data into the input latch and provides a
reference frequency to the PLL.
DESERIALIZER
1, 12, 13
4, 11
10, 11, 28, 29, 30
1, 8, 9
AGND
AVCC
Analog circuit ground (PLL and analog circuits)
Analog circuit power supply (PLL and analog circuits)
Digital circuit ground
14, 20, 22
21, 23
12, 13, 19, 21
20, 22
DGND
DVCC
Digital circuit power supply
LVTTL level output. LOCK goes low when the deserializer PLL locks onto the
embedded clock edge.
10
7
LOCK
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a
high-impedance state, putting the device into a low-power mode. To initiate power
down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low,
the device is in the power down state.
7
4
PWRDN
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an
RCLK rising-edge data strobe.
2
9
3
31
6
RCLK_R/F
RCLK
LVTTL level output recovered clock. Use RCLK to strobe ROUTx.
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL
frequency.
32
REFCLK
LVTTL logic input. Low places ROUT0–ROUT9 and RCLK in the high-impedance
state.
8
5
REN
5
2
RI+
RI–
Serial data input. Noninverting LVDS differential input
Serial data input. Inverting LVDS differential input
6
3
28–24, 19–15
27–23, 18–14
ROUT0–ROUT9 Parallel LVTTL data outputs
6
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SN65LV1224B
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.3 V to 4 V
–0.3 V to (VCC + 0.3 V)
–0.3 V to (VCC + 0.3 V)
–0.3 V to 3.9 V
–0.3 V to 3.9 V
10 ms
VCC to GND
LVTTL input voltage
LVTTL output voltage
LVDS receiver input voltage
LVDS driver output voltage
LVDS output short circuit duration
Electrostatic discharge:
HBM
MM
up to 6 kV
up to 200 V
Junction temperature
Storage temperature
150°C
–65°C to 150°C
260°C
Lead temperature (soldering, 4 seconds)
DB package maximum package
power dissipation
TA = 25°C
1.27 W
RHB package maximum package TA = 25°C
2.85 W
power dissipation
DB package derating
RHB package derating
10.3 mW/°C above 25°C
23.6 mW/°C above 25°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
(1)
VCC
Supply voltage
3.3
V
V
V
Receiver input voltage range
Receiver input common mode range
0
2.4
V
VCM
V
ID
2.4 * ǒ Ǔ
2
ID
2
Supply noise voltage
100
mVp-p
TA
Operating free-air temperature
–40
25
°C
(1) By design, DVCC and AVCC are separated internally and does not matter what the difference is for |DVCC–AVCC|, as long as both are
within 3 V to 3.6 V.
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SN65LV1224B
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ELECTRICAL CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS(1)
VIH
VIL
VCL
IIN
High-level input voltage
Low-level input voltage
Input clamp voltage
2
VCC
V
GND
0.8
–1.5
200
V
V
ICL = –18 mA
VIN = 0 V or 3.6 V
-0.86
(2)
Input current,
–200
±100
µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS(3)
VIH
VIL
VCL
IIN
High-level input voltage
Low-level input voltage
Input clamp voltage
2
VCC
0.8
V
V
GND
ICL = –18 mA
-0.62
–1.5
200
V
Input current (pull-up and
VIN = 0 V or 3.6 V
–200
µA
pull-down resistors on inputs)
VOH
VOL
IOS
High-level output voltage
Low-level output voltage
Output short-circuit current
High-impedance output current
IOH = –5 mA
2.2
GND
–15
3
0.25
–47
±1
VCC
0.5
–85
10
V
V
IOL = 5 mA
VOUT = 0 V
mA
µA
IOZ
PWRDN or REN = 0.8 V, VOUT = 0 V or VCC
–10
SERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins DO+ and DO–)
VOD
Output differential voltage
(DO+)–(DO–)
RL = 27 Ω, See Figure 19
350
1.1
450
mV
mV
∆VOD
Output differential voltage
unbalance
35
VOS
∆VOS
IOS
Offset voltage
1.2
4.8
-10
1.3
35
V
Offset voltage unbalance
Output short circuit current
mV
mA
D0 = 0 V, DINx = high,
-90
PWRDN and DEN = 2.4 V
IOZ
High-impedance output current
PWRDN or DEN = 0.8 V,
DO = 0 V or VCC
–10
-20
±1
±1
10
µA
IOX
CO
Power-off output current
VCC = 0 V, DO = 0 V or 3.6 V
25
µA
Output single-ended capacitance
1±20%
pF
DESERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins RI+ and RI–)
VTH
VTL
Differential threshold high voltage
Differential threshold low voltage
VCM = 1.1 V
50
mV
mV
–50
–10
–10
VIN = 2.4 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
±1
15
10
IIN
CI
Input current
µA
±0.05
Input single-ended capacitance
0.5±20
pF
%
SERIALIZER SUPPLY CURRENT (Applies to Pins DVCC and AVCC)
f = 10 MHz
f = 66 MHz
20
55
25
70
Serializer supply current worst
case
ICCD
RL = 27 Ω, See Figure 4
mA
ICCXD
Serializer supply current
PWRDN = 0.8 V
200
500
µA
DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 10 MHz
f = 66 MHz
15
80
35
95
1
Deserializer supply current, worst
case
ICCR
CL = 15 pF, See Figure 4
mA
mA
ICCXR
Deserializer supply current, power PWRDN = 0.8 V, REN = 0.8 V
down
0.36
(1) Apply to DIN0–DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, and DEN
(2) High IIN values are due to pullup and pulldown resistors on the inputs.
(3) Apply to pins PWRDN, RCLK_R/F, REN, and REFCLK = inputs; apply to pins ROUTx, RCLK, and LOCK = outputs
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SN65LV1224B
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SERIALIZER TIMING REQUIREMENTS FOR TCLK
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
15.15
0.4T
TYP
T
MAX
100
0.6T
0.6T
6
UNIT
ns
tTCP
tTCIH
tTCIL
tt(CLK)
tJIT
Transmit clock period
Transmit clock high time
Transmit clock low time
TCLK input transition time
TCLK input jitter
0.5T
0.5T
3
ns
0.4T
ns
ns
See Figure 18
150 ps (RMS)
Frequency tolerance
-100
+100
ppm
SERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.2
MAX
0.4
UNIT
ns
tTLH(L)
tLTHL(L)
tsu(DI)
tsu(DI)
td(HZ)
LVDS low-to-high transition time
LVDS high-to-low transition time
DIN0–DIN9 setup to TCLK
DIN0–DIN9 hold from TCLK
RL = 27 Ω, CL = 10 pF to GND, See
Figure 5
0.25
0.4
ns
RL = 27 Ω, CL = 10 pF to GND, See
Figure 8
0.5
4
ns
ns
DO± high-to-high impedance state
delay
RL = 27 Ω, CL = 10 pF to GND, See
Figure 9
2.5
2.5
5
5
5
td(LZ)
td(ZH)
td(ZL)
DO± low-to-high impedance state
delay
ns
DO± high-to-high impedance
state-tohigh delay
10
10
DO± high-to-high impedance
state-to-low delay
6.5
tw(SPW)
t(PLD)
td(S)
SYNC pulse duration
Serializer PLL lock time
Serializer delay
RL = 27 Ω, See Figure 11
6×tTCP
1026×tTCP
tTCP+1
ns
ns
ns
RL = 27 Ω, See Figure 12
tTCP+2
tTCP+3
230
tDJIT
Deterministic jitter
RL = 27 Ω, CL = 10 pF to GND
ps
150
tRJIT
Random jitter
RL = 2.7 Ω, CL = 10 pF to GND
10
19 ps (RMS)
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
REFCLK period
TEST CONDITIONS
MIN
15.15
30%
TYP
T
MAX
UNIT
tRFCP
tRFDC
tt(RF)
100
70%
6
ns
REFCLK duty cycle
REFCLK transition time
Frequency tolerance
50%
3
ns
-100
+100
ppm
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DESERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER
TEST
PIN/FREQ
MIN
TYP
MAX UNIT
CONDITIONS
t(RCP)
Receiver out clock period
t(RCP) = t(TCP), See RCLK
Figure 12
15.15
100
2.5
2.5
ns
tTLH(C)
tTHL(C)
CMOS/TTL low-to-high
transition time
ROUT0–ROUT9
1.2
1.1
CL = 15 pF,CL =
15 pF, See
Figure 6
,
ns
LOCK, RCLK
CMOS/TTL high-to-low
transition time
(1)
td(D)
Deserializer delay, See
Figure 13
Room temperature, 10 MHz
3.3 V
1.75×t(RCP)
+4.2
1.75×t(RCP)
+12.6
ns
ns
66 MHz
1.75×t(RCP)
+7.4
1.75×t(RCP)
+9.7
t(ROS)
ROUTx data valid before RCLK
ROUTx data valid after RCLK
RCLK duty cycle
RCLK 10 MHz
0.4×t(RCP)
0.4×t(RCP)
0.5×t(RCP)
0.5×t(RCP)
RCLK 66 MHz
10 MHz
See Figure 14
ns
t(ROH)
–0.4×t(RCP) –0.5×t(RCP)
–0.4×t(RCP) –0.5×t(RCP)
66 MHz
t(RDC)
td(HZ)
40%
50%
6.5
60%
8
ns
ns
High-to-high impedance state
delay
td(LZ)
Low-to-high impedance state
delay
4.7
5.3
4.7
8
8
8
ns
ns
ns
See Figure 15
ROUT0–ROUT9
td(HR)
td(ZL)
High-impedance state to high
delay
High-impedance state to low
delay
t(DSR1)
Deserializer PLL lock time from
PWRDN (with SYNCPAT)
10 MHz
66 MHz
10 MHz
66 MHz
850 x tRFCP
850 x tRFCP
2
µs
See Figure 16,
Figure 17,
and
t(DSR2)
Deserializer PLL lock time from
SYNCPAT
0.303
(2)
td(ZHLK)
High-impedance state to high
delay (power up)
LOCK
3
ns
ps
10 MHz
66 MHz
3680
540
See Figure 18 and
tRNM
Deserializer noise margin
(3)
(1) The deserializer delay time for all frequencies does not exceed two serial bit times.
(2) t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the
powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer
when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify
deserializer PLL performance, tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs.
(3) tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
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TIMING DIAGRAMS AND TEST CIRCUITS
TCLK
ODD D
IN
EVEN D
IN
Figure 2. Worst-Case Serializer ICC Test Pattern
SUPPLY CURRENT
vs
TCLK FREQUENCY
60
66 mA, 48.880 MHz
50
40
I
CC
30
20
10 mA, 14.732 MHz
10
0
0
20
40
60
80
TCLK Frequency − MHz
Figure 3.
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
RCLK
ODD R
OUT
EVEN R
OUT
Figure 4. Worst-Case Deserializer ICC Test Pattern
10 pF
t
t
THL(L)
TLH(L)
R
L
D +
O
80%
20%
80%
20%
V
diff
D −
O
10 pF
V
diff
= (D +) − (D −)
O O
Figure 5. Serializer LVDS Output Load and Transition Times
CMOS/TTL Output
t
Deserializer
t
THL(C)
TLH(C)
80%
20%
80%
20%
15 pF
Figure 6. Deserializer CMOS/TTL Output Load and Transition Times
t
t
t(CLK)
t(CLK)
3 V
0 V
90%
10%
90%
10%
TCLK
Figure 7. Serializer Input Clock Transition Time
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
t
TCP
1.5 V
su(DI)
1.5 V
1.5 V
TCLK
For TCLK_R/F = Low
t
h(DI)
t
D
IN
[9:0]
1.5 V
Setup
Hold
1.5 V
Figure 8. Serializer Setup/Hold Times
Parasitic Package and
Trace Capacitance
3 V
0 V
DEN
1.5 V
1.5 V
t
d(ZH)
t
d(HZ)
V
V
OH
13.5 Ω
13.5 Ω
50%
50%
D +
O
1.1 V
1.1 V
t
d(ZL)
D ±
O
t
d(LZ)
D −
O
1.1 V
DEN
50%
50%
OL
Figure 9. Serializer High-Impedance State Test Circuit and Timing
2 V
PWRDN
TCLK
0.8 V
1026 Cycles
t
or t
d(LZ)
d(HZ)
t
or t
d(ZL)
d(ZH)
t
PLD
D ±
O
3-State
Output Active
3-State
Figure 10. Serializer PLL Lock Time and PWRDN High-Impedance State Delays
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
REN
PWRDN
TCLK
t
w(SP)
SYNC1
or
SYNC2
D ±
O
DATA
SYNC Pattern
TCLK
SYNC1
or
SYNC2
t
Min. Timing Met
SYNC Pattern
w(SP)
D ±
O
DATA
Figure 11. SYNC Timing Delays
D
IN
D
IN0
− D
SYMBOL N
D
IN0
− D SYMBOL N+1
IN9
IN9
t
d(S)
TCLK
Timing for TCLK_R/F = High
Stop Start
Bit Bit
Stop
Bit
Start
Bit
D
00
− D SYMBOL N
09
D
00
− D SYMBOL N−1
09
D
O
Figure 12. Serializer Delay
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
Start
Bit
Stop Start
Bit Bit
Stop Start
Bit Bit
Stop
Bit
D
00
− D SYMBOL N
D
00
− D SYMBOL N+1
D − D SYMBOL N+2
00 09
09
09
1.2 V
1 V
R
I
t
DD
RCLK
Timing for TCLK_R/F = High
R
OUT0
− R
SYMBOL N−1
R
OUT0
− R
SYMBOL N
R
OUT0
− R SYMBOL N+1
OUT9
R
OUT
OUT9
OUT9
Figure 13. Deserializer Delay
t
t
Low
t
High
RCLK
RCLK_R/F = Low
High
t
Low
RCLK
RCLK_R/F = High
t
ROH
t
ROS
Data Valid
Data Valid
R
OUT
[9:0]
1.5 V
1.5 V
Before RCLK
After RCLK
Figure 14. Deserializer Data Valid Out Times
7 V x (LZ/ZL), Open (HZ/ZH)
V
OH
REN
1.5 V
1.5 V
V
OL
500 Ω
Scope
450 Ω
t
d(ZL)
t
d(LZ)
V
+ 0.5 V
V
+ 0.5 V
OL
OL
50 Ω
V
V
OL
t
d(ZH)
R [9:0]
OUT
t
d(HZ)
OH
V
OH
− 0.5 V
V
OH
− 0.5 V
Figure 15. Deserializer High-Impedance State Test Circuit and Timing
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
2 V
PWRDN
REFCLK
0.8 V
1.5 V
t
(DSR1)
DATA
Not Important
R ±
I
t
d(ZHL)
SYNC Patterns
LOCK
[9:0]
3-State
3-State
3-State
3-State
t
or t
d(LZ)
t
or t
d(ZL)
d(HZ)
d(ZH)
R
OUT
3-State
SYNC Symbol or D [9:0]
IN
RCLK
REN
3-State
RCLK_R/F = Low
Figure 16. Deserializer PLL Lock Times and PWRDN 3-State Delays
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
TIMING DIAGRAMS AND TEST CIRCUITS (continued)
3.6 V
3 V
V
CC
0 V
PWRDN
REFCLK
0.8 V
t
(DSR2)
DATA
1.2 V
1 V
Not Important
3-State
R ±
I
SYNC Patterns
LOCK
[9:0]
t
or t
d(ZL)
t
or t
d(LZ)
d(ZH)
d(HZ)
R
3-State
3-State
3-State
3-State
OUT
SYNC Symbol or D [9:0]
IN
RCLK
REN
Figure 17. Deserializer PLL Lock Time From SyncPAT
1.2 V
V
V
TH
R ±
I
TL
1 V
t
t
DJIT
DJIT
t
t
RNM
RNM
t
SW
Ideal Sampling Position
t
t
t
: Setup and Hold Time (Internal Data Sampling Window)
SW
: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
DJIT
RNM
: Receiver Noise Margin Time
Figure 18. Receiver LVDS Input Skew Margin
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TIMING DIAGRAMS AND TEST CIRCUITS (continued)
D +
O
R
L
10
Parallel-to-Serial
D
IN
D −
O
> TCLK
V
OD
= (D +) − (D −)
O O
Differential Output Signal Is Shown as (D +) − (D −)
O
O
Figure 19. VOD Diagram
DEVICE STARTUP PROCEDURE
It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a
logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 20.
3.0 V
V
DD
PWRDNB
Figure 20. Device Startup
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
APPLICATION INFORMATION
DIFFERENTIAL TRACES AND TERMINATION
The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission
medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the
media’s characteristics impedance.
Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable
picks up noise together and appears to the receiver as common mode. Differential receivers reject
common-mode noise. Keep cables or traces matched in length to help reduce skew.
Running the differential traces close together helps cancel the external magnetic field, as well as maintain a
constant impedance. Avoiding sharp turns and reducing the number of vias also helps.
TOPOLOGIES
There are several topologies that the serializers can operate. Three common examples are shown below.
Figure 21 shows an example of a single-terminated point-to-point connection. Here a single termination resistor
is located at the deserializer end. The resistor value should match that of the characteristic impedance of the
cable or PC board traces. The total load seen by the serializer is 100 Ω. Double termination can be used and
typically reduces reflections compared with single termination. However, it also reduces the differential output
voltage swing.
AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data
stream. Otherwise the ac-capicitors can induce common mode voltage drift due to the dc-unbalanced data
stream.
Serialized Data
Parallel Data In
100 Ω
Parallel Data Out
Figure 21. Single-Terminated Point-to-Point Connection
Figure 22 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to
multiple receivers. A 50-kΩ resistor at the far end terminates the bus.
ASIC
ASIC
ASIC
ASIC
50 Ω
Figure 22. Multidrop Configuration
Figure 23 shows an example of multiple serializers and deserializers on the same differential bus, such as in a
backplane. This is a multipoint configuration. In this situation, the characteristic impedance of the bus can be
significantly less due to loading. Termination resistors that match the loaded characteristic impedance are
required at each end of the bus. The total load seen by the serializer in this example is 27 Ω.
19
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SLLS621C–SEPTEMBER 2004–REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
ASIC
ASIC
ASIC
ASIC
54 Ω
54 Ω
Figure 23. Multiple Serializers and Deserializers on the Same Differential Bus
20
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN65LV1023ADB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
32
32
32
28
28
28
28
32
32
32
32
32
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LV1023ADBG4
SN65LV1023ADBR
SN65LV1023ADBRG4
SN65LV1023ARHBR
SN65LV1023ARHBRG4
SN65LV1023ARHBT
SN65LV1224BDB
SSOP
SSOP
SSOP
QFN
DB
DB
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RHB
RHB
RHB
DB
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
SSOP
SSOP
QFN
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LV1224BDBG4
SN65LV1224BDBR
SN65LV1224BDBRG4
SN65LV1224BRHBR
SN65LV1224BRHBRG4
SN65LV1224BRHBT
SN65LV1224BRHBTG4
SNLV1023ARHBTG4
DB
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RHB
RHB
RHB
RHB
RHB
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
(mm)
16
SN65LV1023ADBR
SN65LV1023ARHBR
SN65LV1023ARHBT
SN65LV1224BDBR
SN65LV1224BRHBR
SN65LV1224BRHBT
DB
28
32
32
28
32
32
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
8.1
5.3
5.3
8.1
5.3
5.3
10.4
5.3
2.5
1.5
1.5
2.5
1.5
1.5
12
8
16
12
12
16
12
12
Q1
Q2
Q2
Q1
Q2
Q2
RHB
RHB
DB
12
12
5.3
8
16
10.4
5.3
12
8
RHB
RHB
12
12
5.3
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LV1023ADBR
SN65LV1023ARHBR
SN65LV1023ARHBT
SN65LV1224BDBR
SN65LV1224BRHBR
SN65LV1224BRHBT
DB
28
32
32
28
32
32
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
SITE 60
346.0
342.9
342.9
346.0
342.9
342.9
346.0
336.6
336.6
346.0
336.6
336.6
33.0
20.64
20.64
33.0
RHB
RHB
DB
RHB
RHB
20.64
20.64
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
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Digital Control
Military
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interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
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Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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