SRC4382IPFB [TI]
集成器件采样速率转换器 | PFB | 48 | -40 to 85;型号: | SRC4382IPFB |
厂家: | TEXAS INSTRUMENTS |
描述: | 集成器件采样速率转换器 | PFB | 48 | -40 to 85 商用集成电路 转换器 |
文件: | 总84页 (文件大小:1192K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SRC4382
SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
Two-Channel, Asynchronous Sample Rate Converter with
Integrated Digital Audio Interface Receiver and Transmitter
1
FEATURES
•
Digital Audio Interface Receiver (DIR)
234
•
Two-Channel Asynchronous Sample Rate
Converter (SRC)
–
–
–
–
–
PLL Lock Range Includes Sampling Rates
from 20kHz to 216kHz
–
Dynamic Range with –60dB Input
(A-Weighted): 128dB typical
Includes Four Differential Input Line
Receivers and an Input Multiplexer
–
Total Harmonic Distortion and Noise
(THD+N) with Full-Scale Input: –125dB
typical
Bypass Multiplexer Routes Line Receiver
Outputs to Line Driver and Buffer Outputs
Block-Sized Data Buffers for Both Channel
Status and User Data
–
–
–
–
Supports Audio Input and Output Data
Word Lengths Up to 24 Bits
Automatic Detection of Non-PCM Audio
Streams (DTS CD/LD and IEC 61937
formats)
Supports Input and Output Sampling
Frequencies Up to 216kHz
Automatic Detection of the Input-to-Output
Sampling Ratio
–
–
–
Audio CD Q-Channel Sub-Code Decoding
and Data Buffer
Wide Input-to-Output Conversion Range:
16:1 to 1:16 Continuous
Status Registers and Interrupt Generation
for Flag and Error Conditions
–
–
Excellent Jitter Attenuation Characteristics
Low Jitter Recovered Clock Output
Digital De-Emphasis Filtering for 32kHz,
44.1kHz, and 48kHz Input Sampling Rates
•
Two Audio Serial Ports (Ports A and B)
–
Synchronous Serial Interface to External
Signal Processors, Data Converters, and
Logic
–
Digital Output Attenuation and Mute
Functions
–
–
Output Word Length Reduction
–
–
–
Slave or Master Mode Operation with
Sampling Rates up to 216kHz
Status Registers and Interrupt Generation
for Sampling Ratio and Ready Flags
Supports Left-Justified, Right-Justified, and
Philips I2S™ Data Formats
•
Digital Audio Interface Transmitter (DIT)
Supports Audio Data Word Lengths Up to
24 Bits
–
–
Supports Sampling Rates Up to 216kHz
Includes Differential Line Driver and
CMOS Buffered Outputs
•
•
Four General-Purpose Digital Outputs
–
Multifunction Programmable Via Control
Registers
–
–
Block-Sized Data Buffers for Both Channel
Status and User Data
Extensive Power-Down Support
Status Registers and Interrupt Generation
for Flag and Error Conditions
–
Functional Blocks May Be Disabled
Individually When Not In Use
•
User-Selectable Serial Host Interface: SPI or
Philips I2C™
•
•
Operates From +1.8V Core and +3.3V I/O
Power Supplies
–
Provides Access to On-Chip Registers and
Data Buffers
Small TQFP-48 Package, Compatible with the
SRC4392 and DIX4192
U.S. Patent No. 7,262,716
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
Dolby is a registered trademark of Dolby Laboratories.
I2C, I2S are trademarks of Koninklijke Philips Electronics N.V.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
SRC4382
www.ti.com
SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
APPLICATIONS
DESCRIPTION
•
•
•
DIGITAL AUDIO RECORDERS AND
MIXING DESKS
DIGITAL AUDIO INTERFACES FOR
COMPUTERS
DIGITAL AUDIO ROUTERS AND
DISTRIBUTION SYSTEMS
BROADCAST STUDIO EQUIPMENT
DVD/CD RECORDERS
SURROUND SOUND DECODERS AND
A/V RECEIVERS
The SRC4382 is a highly-integrated CMOS device
designed for use in professional and broadcast digital
audio systems. The SRC4382 combines
a
high-performance, two-channel, asynchronous
sample rate converter (SRC) with a digital audio
interface receiver (DIR) and transmitter (DIT), two
audio serial ports, and flexible distribution logic for
interconnection of the function block data and clocks.
•
•
•
The DIR and DIT are compatible with the AES3,
S/PDIF, IEC 60958, and EIAJ CP-1201 interface
standards. The audio serial ports, DIT, and SRC may
be operated at sampling rates up to 216kHz. The DIR
lock range includes sampling rates from 20kHz to
216kHz.
•
CAR AUDIO SYSTEMS
The SRC4382 is configured using on-chip control
registers and data buffers, which are accessed
through either a 4-wire serial peripheral interface
(SPI) port, or a 2-wire Philips I2C bus interface.
Status registers provide access to a variety of flag
and error bits, which are derived from the various
function blocks. An open drain interrupt output pin is
provided, and is supported by flexible interrupt
reporting and mask options via control register
settings. A master reset input pin is provided for
initialization by a host processor or supervisory
functions.
The SRC4382 requires a +1.8V core logic supply, in
addition to a +3.3V supply for powering portions of
the DIR, DIT, and line driver and receiver functions. A
separate logic I/O supply supports operation from
+1.65V to +3.6V, providing compatibility with low
voltage logic interfaces typically found on digital
signal processors and programmable logic devices.
The SRC4382 is available in a lead-free, TQFP-48
package, and is pin- and register-compatible with the
Texas Instruments SRC4392 and DIX4192 products.
2
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Product Folder Link(s): SRC4382
SRC4382
www.ti.com
SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
OPERATING
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE
SRC4382IPFBT
SRC4382IPFBR
Tape and Reel, 250
Tape and Reel, 2000
SRC4382
TQFP-48
PFB
–40C to +85C
SRC4382I
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supplies
VDD18
–0.3V to +2.0V
–0.3V to +4.0V
–0.3V to +4.0V
–0.3V to +4.0V
VDD33
VIO
VCC
Digital Input Voltage: Digital Logic
RXCKI, MUTE, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA,
BCKB, LRCKA, LRCKB, SDINA, SDINB
–0.3V to (VIO + 0.3V)
Line Receiver Input Voltage (per pin)
RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–
Input Current (all pins except power and ground)
Ambient Operating Temperature
(VDD33 + 0.3) VPP
10mA
–40C to +85C
–65C to +150C
Storage Temperature
(1) These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolute
maximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured.
Copyright © 2006–2007, Texas Instruments Incorporated
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SRC4382
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL I/O CHARACTERISTICS
(All I/O Pins Except Line Receivers and Line Driver)
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
High-Level Input Current, IIH
Low-Level Input Current, VIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
Input Capacitance, CIN
0.7
נ
VIO VIO
0.3
נ
VIO 10
V
V
0
0.5
0.5
μA
μA
V
10
IO = –4mA
IO = +4mA
0.8
נ
VIO VIO
0
0.2
נ
VIO V
3
pF
LINE RECEIVER INPUTS
(RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)
Voltage across a given
differential input pair
Differential Input Sensitivity, VTH
Input Hysteresis, VHY
150
200
mV
mV
150
5.4
LINE DRIVER OUTPUTS
(TX+, TX–)
Differential Output Voltage, VTXO
RL = 110Ω Across TX+ and TX–
VPP
MASTER CLOCK INPUT
Master Clock Input (MCLK) Frequency, fMCLK
Master Clock Input (MCLK) Duty Cycle, fMCLKD
ASYNCHRONOUS SAMPLE RATE CONVERTER (SRC)
Input or Output Sampling Rate, fSIN or fSOUT
Input-to-Output Sampling Ratio
1
27.7
55
MHz
%
45
4
216
kHz
1:16
16:1
Interchannel Gain Mismatch
0
0
dB
Interchannel Phase Mismatch
Degrees
Dynamic Range (no weighting filter applied)(1)
BW = 22Hz to fSOUT/2,
f = 997Hz at –60dBFS
fSIN:fSOUT = 12kHz:192kHz
fSIN:fSOUT = 44.1kHz:44.1kHz
fSIN:fSOUT = 44.1kHz:48kHz
fSIN:fSOUT = 44.1kHz:96kHz
fSIN:fSOUT = 44.1kHz:192kHz
fSIN:fSOUT = 48kHz:44.1kHz
fSIN:fSOUT = 48kHz:48kHz
fSIN:fSOUT = 48kHz:96kHz
fSIN:fSOUT = 48kHz:192kHz
fSIN:fSOUT = 96kHz:44.1kHz
fSIN:fSOUT = 96kHz:48kHz
fSIN:fSOUT = 96kHz:96kHz
fSIN:fSOUT = 96kHz:192kHz
fSIN:fSOUT = 192kHz:12kHz
fSIN:fSOUT = 192kHz:44.1kHz
fSIN:fSOUT = 192kHz:48kHz
fSIN:fSOUT = 192kHz:96kHz
fSIN:fSOUT = 192kHz:192kHz
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
(1) Measured with an Audio Precision SYS-2722 192kHz test system with the input and output sampling frequencies asynchronous to one
another. A-weighted dynamic range specifications will be improved by approximately 2dB to 3dB when compared to the results without
A-weighting applied.
4
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Total Harmonic Distortion + Noise (THD+N)(2)
BW = 22Hz to fSOUT/2,
f = 997Hz at 0dBFS
fSIN:fSOUT = 12kHz:192kHz
fSIN:fSOUT = 44.1kHz:44.1kHz
fSIN:fSOUT = 44.1kHz:48kHz
fSIN:fSOUT = 44.1kHz:96kHz
fSIN:fSOUT = 44.1kHz:192kHz
fSIN:fSOUT = 48kHz:44.1kHz
fSIN:fSOUT = 48kHz:48kHz
fSIN:fSOUT = 48kHz:96kHz
fSIN:fSOUT = 48kHz:192kHz
fSIN:fSOUT = 96kHz:44.1kHz
fSIN:fSOUT = 96kHz:48kHz
fSIN:fSOUT = 96kHz:96kHz
fSIN:fSOUT = 96kHz:192kHz
fSIN:fSOUT = 192kHz:12kHz
fSIN:fSOUT = 192kHz:44.1kHz
fSIN:fSOUT = 192kHz:48kHz
fSIN:fSOUT = 192kHz:96kHz
fSIN:fSOUT = 192kHz:192kHz
Digital Interpolation Filter Characteristics
Passband
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
–125
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.4535
נ
fSIN 0.007
Hz
Passband Ripple
dB
Transition Band
0.4535
נ
fSIN 0.5465
נ
fSIN –125
0.5465
נ
fSIN Hz
Stop Band
Hz
Stop Band Attenuation
dB
Group Delay (64 samples pre-buffered)
Group Delay (64 samples pre-buffered)
Group Delay (32 samples pre-buffered)
Group Delay (32 samples pre-buffered)
Group Delay (16 samples pre-buffered)
Group Delay (16 samples pre-buffered)
Group Delay (8 samples pre-buffered)
Group Delay (8 samples pre-buffered)
Digital Decimation Filter Characteristics
Passband
Decimation filter enabled
Direct down-sampling enabled
Decimation filter enabled
102.53125/fSIN
102/fSIN
Seconds
Seconds
Seconds
Seconds
Seconds
Seconds
Seconds
Seconds
70.53125/fSIN
70/fSIN
Direct down-sampling enabled
Decimation filter enabled
54.53125/fSIN
54/fSIN
Direct down-sampling enabled
Decimation filter enabled
46.53125/fSIN
46/fSIN
Direct down-sampling enabled
0.4535
נ
fSOUT 0.008
Hz
dB
Passband Ripple
Transition Band
0.4535
נ
fSOUT 0.5465
נ
fSOUT –125
0.5465
נ
fSOUT Hz
Stop Band
Hz
Stop Band Attenuation
dB
Group Delay
Decimation filter enabled
36.46875/fSOUT
0
Seconds
Seconds
Group Delay
Direct down-sampling enabled
Digital De-Emphasis Filter Characteristics
Filter Error for All Settings
De-emphasis filter enabled
0.001
dB
(2) Measured with an Audio Precision SYS-2722 192kHz test system with the input and output sampling frequencies asynchronous to one
another.
Copyright © 2006–2007, Texas Instruments Incorporated
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
PLL Lock Range
20
3.5
45
216
27.7
55
kHz
MHz
%
Reference Clock Input (RXCKI) Frequency, fRXCKI
Reference Clock Input (RXCKI) Duty Cycle, fRXCKID
Recovered Clock Output (RXCKO) Frequency, fRXCKO
Recovered Clock Output (RXCKO) Duty Cycle, fRXCKOD
Recovered Clock Output (RXCKO) Intrinsic Jitter
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic Output Jitter
3.5
45
27.7
55
MHz
%
Measured cycle-to-cycle
Measured cycle-to-cycle
250
200
ps RMS
ps RMS
ELECTRICAL CHARACTERISTICS: Audio Serial Ports
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
AUDIO SERIAL PORTS (Port A and Port B)
LRCK Clock Frequency, fLRCK
CONDITIONS
MIN
TYP
MAX
216
UNITS
0
kHz
%
LRCK Clock Duty Cycle, tLRCKD
50
BCK Clock Frequency, fBCK
0
13.824
MHz
ns
BCK High Pulse Width, tBCKH
10
10
10
10
BCK Low Pulse Width, tBCKL
ns
Audio Data Input (SDIN) Setup Time, tAIS
Audio Data Input (SDIN) Hold Time, tAISH
Audio Data Output (SDOUT) Delay, tADD
ns
ns
10
ns
ELECTRICAL CHARACTERISTICS: SPI Interface
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
HOST INTERFACE: SPI Mode
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock (CCLK) Frequency, fCCLK
CS Falling to CCLK Rising, tCSCR
CCLK Falling to CS Rising, tCFCS
CDIN Data Setup Time, tCDS
0
8
7
7
6
40
MHz
ns
ns
ns
CDIN Data Hold Time, tCDH
ns
CCLK Falling to CDOUT Data Valid, tCFDO
CS Rising to CDOUT High-Impedance, tCSZ
3
3
ns
ns
6
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: I2C Standard and Fast Modes
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
HOST INTERFACE: I2C Standard Mode(1)
SCL Clock Frequency, fSCL
CONDITIONS
MIN
TYP
MAX
UNITS
0
4
100
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
V
Hold Time Repeated START Condition, tHDSTA
Low Period of SCL Clock, tLOW
4.7
4
High Period of SCL Clock, tHIGH
Setup Time Repeated START Condition, tSUSTA
Data Hold Time, tHDDAT
4.7
0(2)
250
3.45(3)
Data Setup Time, tSUDAT
Rise Time for Both SDA and SDL, tR
Fall Time for Both SDA and SDL, tF
Setup Time for STOP Condition, tSUSTO
Bus Free Time Between START and STOP, tBUF
Capacitive Load for Each Bus Line, CB
Noise Margin at Low Level (including hysteresis), VNL
Noise Margin at High Level (including hysteresis), VNH
HOST INTERFACE: I2C Fast Mode(1)
SCL Clock Frequency, fSCL
1000
300
4
4.7
400
400
0.1
נ
VIO 0.2
נ
VIO V
0
0.6
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns
pF
V
Hold Time Repeated START Condition, tHDSTA
Low Period of SCL Clock, tLOW
1.3
High Period of SCL Clock, tHIGH
0.6
Setup Time Repeated START Condition, tSUSTA
Data Hold Time, tHDDAT
0.6
0(2)
100(4)
20 + 0.2CB
20 + 0.2CB
0.6
0.9(3)
Data Setup Time, tSUDAT
(5)
(5)
Rise Time for Both SDA and SDL, tR
Fall Time for Both SDA and SDL, tF
Setup Time for STOP Condition, tSUSTO
Bus Free Time Between START and STOP, tBUF
Spike Pulse Width Suppressed by Input Filter, tSP
Capacitive Load for Each Bus Line, CB
Noise Margin at Low Level (including hysteresis), VNL
Noise Margin at High Level (including hysteresis), VNH
300
300
1.3
0
50
400
0.1
נ
VIO 0.2
נ
VIO V
(1) All values referred to the VIH minimum and VIL maximum levels listed in the Digital I/O Characteristics section of the Electrical
Characteristics: General, SRC, DIR, and DIT table.
(2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH minimum input level) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum tHDDAT has only to be met if the device does not stretch the Low period (tLOW) of the SCL signal.
(4) A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement that tSUDAT be 250ns minimum must
then be met. For the SRC4382, this is automatically the case, since the device does not stretch the Low period of the SCL signal.
(5) CB is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are
allowed.
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ELECTRICAL CHARACTERISTICS: Power Supplies
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER
POWER SUPPLIES
CONDITIONS
MIN
TYP
MAX
UNITS
Recommended Supply Voltage Range
VDD18
+1.65
+3.0
+1.8
+3.3
+3.3
+3.3
+1.95
+3.6
+3.6
+3.6
V
V
V
V
VDD33
VIO
+1.65
+3.0
VCC
Supply Current: Initial Startup
All Blocks Powered Down by Default
VDD18 = +1.8V
IDD18S
90
1
μA
μA
μA
μA
IDD33S
VDD33 = +3.3V
IIOS
VIO = +3.3V
270
1
ICCS
VCC = +3.3V
Supply Current: Quiescent
All Blocks Powered Up with No Clocks Applied
VDD18 = +1.8V
IDD18Q
3.1
0.5
mA
mA
mA
mA
IDD33Q
VDD33 = +3.3V
IIOQ
VIO = +3.3V
0.27
6.6
ICCQ
VCC = +3.3V
Supply Current: Dynamic
All Blocks Powered Up, fS = 48kHz
VDD18 = +1.8V
IDD18D
23
14
43
8
mA
mA
mA
mA
IDD33D
IIOD(1)
VDD33 = +3.3V
VIO = +3.3V
ICCD
VCC = +3.3V
Supply Current: High Sampling Rate
IDD18H
All Blocks Powered Up, fS = 192kHz
VDD18 = +1.8V
58
15
44
8
mA
mA
IDD33H
IIOH(1)
VDD33 = +3.3V
VIO = +3.3V
mA
ICCH
VCC = +3.3V
mA
Total Power Dissipation: Initial Startup
Total Power Dissipation: Quiescent
Total Power Dissipation: Dynamic
Total Power Dissipation: High Sampling Rate
All Blocks Powered Down by Default
All Blocks Powered Up with No Clocks Applied
All Blocks Powered Up, fS = 48kHz
All Blocks Powered Up, fS = 192kHz
1
mW
mW
mW
mW
30
256
326
(1) The typical VIO supply current is measured using the SRC4382EVM evaluation module with loading from the DAIMB mother-board
circuitry. VIO supply current will be dependent upon the loading on the logic output pins.
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TIMING DIAGRAMS
LRCK
tBCKH
BCK
tAIS
tBCKL
SDIN
tAIH
tAOD
SDOUT
Figure 1. Audio Serial Port Timing
tCFCS
CS
tCSCR
tCDS
CCLK
CDIN
tCDH
Hi Z
Hi Z
tCSZ
CDOUT
tCFDO
Figure 2. SPI Interface Timing
tF
SDA
tSUDAT
tHDSTA
tSP
tR
tBUF
tLOW
tR
tF
SCL
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tHIGH
S
R
P
S
S = Start Condition
R = Repeated Start Condition
P = Stop Condition
Figure 3. I2C Standard and Fast Mode Timing
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
PIN CONFIGURATION
Top View
TQFP
48 47 46 45 44 43 42 41 40 39 38 37
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
1
2
3
4
5
6
7
8
9
36 SYNC
35 BLS
34 AESOUT
33 VDD33
32 TX+
31 TX-
SRC4382
30 DGND2
29 GPO4
28 GPO3
27 GPO2
26 GPO1
25 MCLK
AGND 10
LOCK 11
RXCKO 12
13 14 15 16 17 18 19 20 21 22 23 24
NC = No Connection
PIN DESCRIPTIONS
NAME
RX1+
PIN NUMBER
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Power
Ground
Output
Output
Input
Input
Output
Ground
Power
Input
Input
Input
Input
I/O
DESCRIPTION
1
2
Line Receiver 1, Noninverting Input
Line Receiver 1, Inverting Input
Line Receiver 2, Noninverting Input
Line Receiver 2, Inverting Input
Line Receiver 3, Noninverting Input
Line Receiver 3, Inverting Input
Line Receiver 4, Noninverting Input
Line Receiver 4, Inverting Input
RX1–
RX2+
3
RX2–
4
RX3+
5
RX3–
6
RX4+
7
RX4–
8
VCC
9
DIR Comparator and PLL Power Supply, +3.3V Nominal
DIR Comparator and PLL Power-Supply Ground
DIR PLL Lock Flag (active Low)
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
LOCK
RXCKO
RXCKI
MUTE
DIR Recovered Master Clock (tri-state output)
DIR Reference Clock
SRC Output Mute (active High)
RDY
SRC Ready Flag (active Low)
DGND1
VDD18
CPM
Digital Core Ground
Digital Core Supply, +1.8V Nominal
Control Port Mode, 0 = SPI Mode, 1 = I2C Mode
Chip Select (active Low) for SPI Mode or Programmable Slave Address for I2C Mode
Serial Data Clock for SPI Mode or I2C Mode
CS or A0
CCLK or SCL
CDIN orA1
CDOUT or SDA
SPI Port Serial Data input or Programmable Slave Address for I2C Mode
SPI Port Serial Data Output (tri-state output) or Serial Data I/O for I2C Mode
10
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
PIN DESCRIPTIONS (continued)
NAME
INT
PIN NUMBER
I/O
Output
Input
DESCRIPTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Interrupt Flag (open-drain, active Low)
Reset (active Low)
RST
MCLK
GPO1
GPO2
GPO3
GPO4
DGND2
TX–
Input
Master Clock
Output
Output
Output
Output
Ground
Output
Output
Power
Output
I/O
General-Purpose Output 1
General-Purpose Output 2
General-Purpose Output 3
General-Purpose Output 4
DIR Line Receiver Bias and DIT Line Driver Digital Ground
DIT Line Driver Inverting Output
DIT Line Driver Noninverting Output
DIR Line Receiver Bias and DIT Line Driver Supply, +3.3V Nominal
DIT Buffered AES3-Encoded Data
DIT Block Start Clock
TX+
VDD33
AESOUT
BLS
SYNC
BCKA
LRCKA
SDINA
SDOUTA
NC
Output
I/O
DIT internal Sync Clock
Audio Serial Port A Bit Clock
I/O
Audio Serial Port A Left/Right Clock
Audio Serial Port A Data Input
Audio Serial Port A Data Output
No Internal Signal Connection, Internally Bonded to ESD Pad
Logic I/O Supply, +1.65V to +3.6V
Logic I/O Ground
Input
Output
—
VIO
Power
Ground
Ground
Output
Input
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
Substrate Ground, Connect to AGND (pin 10)
Audio Serial Port B Data Output
Audio Serial Port B Data Input
Audio Serial Port B Left/Right Clock
Audio Serial Port B Bit Clock
I/O
I/O
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT SAMPLING RATE
(fSOUT = 44.1kHz and fIN = 997Hz at 0dBFS)
THD+N vs INPUT SAMPLING RATE
(fSOUT = 48kHz and fIN = 997Hz at 0dBFS)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
32
52
72
92
112
132
152
172
192
32
52
72
92
112
132
152
172
192
Sampling Rate (kHz)
Sampling Rate (kHz)
Figure 4.
Figure 5.
THD+N vs INPUT SAMPLING RATE
(fSOUT = 96kHz and fIN = 997Hz at 0dBFS)
THD+N vs INPUT SAMPLING RATE
(fSOUT = 192kHz and fIN = 997Hz at 0dBFS)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
32
52
72
92
112
132
152
172
192
32
52
72
92
112
132
152
172
192
Sampling Rate (kHz)
Sampling Rate (kHz)
Figure 6.
Figure 7.
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 44.1kHz:44.1kHz and
Input Amplitude = 0dBFS)
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 44.1kHz:48kHz and
Input Amplitude = 0dBFS)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 8.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 9.
10k 20k
12
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 44.1kHz:96kHz and
Input Amplitude = 0dBFS)
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 44.1kHz:192kHz and
Input Amplitude = 0dBFS)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 10.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 11.
10k 20k
THD+N vs INPUT FREQUENCY
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 48kHz:48kHz and Input Amplitude = 0dBFS)
-115
(fSIN:fSOUT = 48kHz:44.1kHz and Input Amplitude = 0dBFS)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 12.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 13.
10k 20k
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 48kHz:96kHz and Input Amplitude = 0dBFS)
-115
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 48kHz:192kHz and Input Amplitude = 0dBFS)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 14.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 15.
10k 20k
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT FREQUENCY
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 96kHz:48kHz and Input Amplitude = 0dBFS)
-115
(fSIN:fSOUT = 96kHz:44.1kHz and Input Amplitude = 0dBFS)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 16.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 17.
10k 20k
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 96kHz:96kHz and Input Amplitude = 0dBFS)
-115
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 96kHz:192kHz and Input Amplitude = 0dBFS)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
10k
40k
20
100
1k
10k
40k
Input Frequency (Hz)
Figure 18.
Input Frequency (Hz)
Figure 19.
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 192kHz:44.1kHz and
Input Amplitude = 0dBFS)
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 192kHz:48kHz and
Input Amplitude = 0dBFS)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
Input Frequency (Hz)
Figure 20.
10k 20k
20
100
1k
Input Frequency (Hz)
Figure 21.
10k 20k
14
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SRC4382
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 192kHz:96kHz and Input Amplitude = 0dBFS)
-115
THD+N vs INPUT FREQUENCY
(fSIN:fSOUT = 192kHz:192kHz and Input Amplitude = 0dBFS)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
20
100
1k
10k
40k
20
100
1k
10k
80k
Input Frequency (Hz)
Figure 22.
Input Frequency (Hz)
Figure 23.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 44.1kHz:44.1kHz and
Input Frequency = 997Hz)
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 44.1kHz:48kHz and
Input Frequency = 997Hz)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 24.
Figure 25.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 44.1kHz:96kHz and Input Frequency = 997Hz)
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 44.1kHz:192kHz and Input Frequency = 997Hz)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 26.
Figure 27.
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 48kHz:44.1kHz and Input Frequency = 997Hz)
-115
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 48kHz:48kHz and Input Frequency = 997Hz)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 28.
Figure 29.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 48kHz:96kHz and Input Frequency = 997Hz)
-115
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 48kHz:192kHz and Input Frequency = 997Hz)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 30.
Figure 31.
THD+N vs INPUT AMPLITUDE
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 96kHz:48kHz and Input Frequency = 997Hz)
-115
(fSIN:fSOUT = 96kHz:44.1kHz and Input Frequency = 997Hz)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 32.
Figure 33.
16
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SRC4382
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 96kHz:96kHz and Input Frequency = 997Hz)
-115
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 96kHz:192kHz and Input Frequency = 997Hz)
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 34.
Figure 35.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 192kHz:44.1kHz and Input Frequency = 997Hz)
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 192kHz:48kHz and Input Frequency = 997Hz)
-115
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 36.
Figure 37.
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 192kHz:96kHz and Input Frequency = 997Hz)
-115
THD+N vs INPUT AMPLITUDE
(fSIN:fSOUT = 192kHz:192kHz and Input Frequency = 997Hz)
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-115
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
-125
-100
-75
-50
-25
0
-125
-100
-75
-50
-25
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 38.
Figure 39.
Copyright © 2006–2007, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
FFT PLOT
(fSIN:fSOUT = 44.1kHz:44.1kHz and
Input Frequency = 997Hz at 0dBFS)
FFT PLOT
(fSIN:fSOUT = 44.1kHz:48kHz and
Input Frequency = 997Hz at 0dBFS)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
100
1k
Frequency (Hz)
Figure 40.
10k 22k
10
20
10
100
1k
Frequency (Hz)
Figure 41.
10k
24k
96k
24k
FFT PLOT
FFT PLOT
(fSIN:fSOUT = 44.1kHz:96kHz and
Input Frequency = 997Hz at 0dBFS)
(fSIN:fSOUT = 44.1kHz:192kHz and
Input Frequency = 997Hz at 0dBFS)
-0
-20
-0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
100
1k
48k
100
1k
10k
10k
Frequency (Hz)
Figure 42.
Frequency (Hz)
Figure 43.
FFT PLOT
FFT PLOT
(fSIN:fSOUT = 48kHz:44.1kHz and
Input Frequency = 997Hz at 0dBFS)
(fSIN:fSOUT = 48kHz:48kHz and
Input Frequency = 997Hz at 0dBFS)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
100
1k
10k 22k
100
1k
Frequency (Hz)
Figure 45.
10k
Frequency (Hz)
Figure 44.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
FFT PLOT
(fSIN:fSOUT = 48kHz:96kHz and
Input Frequency = 997Hz at 0dBFS)
FFT PLOT
(fSIN:fSOUT = 48kHz:192kHz and
Input Frequency = 997Hz at 0dBFS)
-0
-20
-0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
10
10
100
1k
48k
10k 22k
48k
20
10
20
100
1k
96k
24k
96k
10k
10k
Frequency (Hz)
Figure 46.
Frequency (Hz)
Figure 47.
FFT PLOT
FFT PLOT
(fSIN:fSOUT = 96kHz:44.1kHz and
Input Frequency = 997Hz at 0dBFS)
(fSIN:fSOUT = 96kHz:48kHz and
Input Frequency = 997Hz at 0dBFS)
-0
-20
-0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
100
1k
Frequency (Hz)
Figure 48.
100
1k
Frequency (Hz)
Figure 49.
10k
FFT PLOT
FFT PLOT
(fSIN:fSOUT = 96kHz:96kHz and
Input Frequency = 997Hz at 0dBFS)
(fSIN:fSOUT = 96kHz:192kHz and
Input Frequency = 997Hz at 0dBFS)
-0
-20
-0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
100
1k
100
1k
10k
10k
Frequency (Hz)
Figure 50.
Frequency (Hz)
Figure 51.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
FFT PLOT
(fSIN:fSOUT = 192kHz:44.1kHz and
Input Frequency = 997Hz at 0dBFS)
FFT PLOT
(fSIN:fSOUT = 192kHz:48kHz and
Input Frequency = 997Hz at 0dBFS)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
100
1k
10k
24k
10
100
1k
Frequency (Hz)
Figure 52.
10k 22k
Frequency (Hz)
Figure 53.
FFT PLOT
FFT PLOT
(fSIN:fSOUT = 192kHz:96kHz and
(fSIN:fSOUT = 192kHz:192kHz and
Input Frequency = 997Hz at 0dBFS)
Input Frequency = 997Hz at 0dBFS)
-0
-20
-0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
10
100
1k
48k
20
100
1k
96k
10k
10k
Frequency (Hz)
Figure 54.
Frequency (Hz)
Figure 55.
IMD
IMD
(fSIN:fSOUT = 44.1kHz:48kHz, SMPTE/DIN 1:1, 10kHz and
(fSIN:fSOUT = 48kHz:44.1kHz, SMPTE/DIN 1:1, 10kHz and
11kHz, and –0.1dB Input Amplitude)
11kHz, and –0.1dB Input Amplitude)
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
0
2
4
6
8
10 12 14 16 18 20 22 24
Frequency (kHz)
0
2
4
6
8
10 12 14 16 18 20
22
Frequency (kHz)
Figure 56.
Figure 57.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise
noted.
IMD
(fSIN:fSOUT = 96kHz:48kHz, SMPTE/DIN 1:1, 10kHz and 11kHz,
and –0.1dB Input Amplitude)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
2
4
6
8
10 12 14 16 18 20 22 24
Frequency (kHz)
Figure 58.
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PRODUCT OVERVIEW
The SRC4382 is a two-channel asynchronous sample rate converter (SRC) with an integrated digital audio
interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port B, support input and
output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic
provides for flexible interconnection between the five functional blocks. The audio serial ports, DIT, and SRC may
be operated at sampling rates up to 216kHz. The DIR is specified for a PLL lock range that includes sampling
rates from 20kHz to 216kHz. All function blocks support audio data word lengths up to 24 bits.
The SRC4382 requires an external host processor or logic for configuration control. The SRC4382 includes a
user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a
2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40MHz. The I2C bus interface may be
operated in standard or fast modes, supporting operation at 100kbps and 400kbps, respectively. The SPI and I2C
interfaces provide access to internal control and status registers, as well as the buffers utilized for the DIR and
DIT channel status and user data.
The asynchronous SRC is based upon the successful SRC4192 core from Texas Instruments. The SRC in the
SRC4382 has been further enhanced to provide exceptional jitter attenuation characteristics, helping to improve
overall application performance. The SRC operates over a wide input-to-output sampling ratio range, from 1:16
to 16:1 continuous. The input-to-output sampling ratio is determined automatically by the SRC rate estimation
circuitry, with the digital re-sampler parameters being updated in real-time without the need for programming.
Interpolation and decimation filter delay are user-selectable. Additional SRC features include de-emphasis
filtering, output word length reduction, output attenuation and muting, and input-to-output sampling ratio readback
via status registers.
The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or
unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported.
The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input
multiplexer, which is utilized to select one of the four line receiver outputs for processing by the DIR core. The
outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be
used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This
configuration provides a bypass signal path for AES3-encoded input data streams.
The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and
parity data. Channel status and user data is stored in block-sized buffers, which may be accessed via the SPI or
I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The validity
and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock, which
may be utilized to generate word and bit clocks using on-chip or external logic circuitry.
The digital interface transmitter (DIT) encodes digital audio input data into an AES3 formatted output data
stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line
driver and buffer include 1-of-2 input data selectors, which are utilized to choose either the output of the DIT
AES3 encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or
unbalanced cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules
and external logic or line drivers. The DIT includes block-sized data buffers for both channel status and user
data. These buffers are accessed via either the SPI or I2C host interface, or may be loaded directly from the DIR
channel status and user data buffers.
The SRC4382 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured as
simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may be
connected to one of 14 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs. The
GPO pins provide added utility in applications where hardware access to selected internal logic signals may be
necessary.
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Figure 59 shows a simplified functional block diagram for the SRC4382. Additional details for each function block
will be covered in respective sections of this datasheet.
SRC4382
CPM
SDINA
CS or A0
Host
CCLK or SCL
CDIN or A1
CDOUT or SDA
INT
SDOUTA
LRCKA
BCKA
Audio Serial
Port A
Interface
(SPI or I2C)
and
General-
Purpose
Outputs
RST
GPO1
GPO2
GPO3
SDINB
SDOUTB
LRCKB
BCKB
GPO4
Audio Serial
Port B
Control and Status
Registers
RXCKO
LOCK
DIR C and U
Data Buffers
RX1+
RX1-
RX2+
DIT C and U
Data Buffers
Digital
Interface
Receiver (DIR)
RX2-
MCLK
Master
Clock
RX3+
RXCKI
RX3-
Distribution
From RXCKO
RX4+
RX4-
TX+
Digital
Interface
Transmitter
(DIT)
TX-
AESOUT
VDD18
DGND1
VDD33
DGND2
VIO
BLS
SYNC
Power
Asynchronous
Sample Rate
Converter
(SRC)
RDY
DGND3
VCC
MUTE
AGND
Internally Tied
to Substrate
BGND
Figure 59. Functional Block Diagram
RESET OPERATION
The SRC4382 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the
internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset
low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation
using either the SPI or I2C port for at least 500μs after the rising edge of RST. See Figure 60 for the reset timing
sequence of the SRC4382.
In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby
all registers and buffers are forced to their default settings. Refer to the Control Registers section for details
regarding the RESET bit function.
Upon reset initialization, all functional blocks of the SRC4382 default to the powered-down state, with the
exception of the SPI or I2C host interface and the corresponding control registers. The user may then program
the SRC4382 to the desired configuration, and then release the desired function blocks from the power-down
state utilizing the corresponding bits in control register 0x01.
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Write or Read
via
2
SPI or I C
1
RST
0
500ns (min)
500ms (min)
Figure 60. Reset Sequence Timing
MASTER AND REFERENCE CLOCKS
The SRC4382 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically
used as the master clock source for the audio serial ports, the DIT, and/or the SRC. The MCLK may also be
utilized as the reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock
source, although it may also be used as the master or reference clock source for the audio serial ports and/or the
SRC.
In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the
AES3-encoded input data stream. This clock is suitable for use as a master or system clock source in many
applications. The recovered master clock output, RXCKO (pin 12), may be utilized as the master or reference
clock source for the audio serial ports, the DIT, and/or the SRC, as well as external audio devices.
The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode
configuration of the port. In Slave mode, the ports do not require a master clock, as the left/right word and bit
clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master
mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source,
MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using
one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to the Audio Serial Port Operation
section for additional details.
The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock
output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock
using one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to the Digital Interface Transmitter
(DIT) Operation section for additional details.
The DIR reference clock may be any frequency that meets the PLL1 setup requirements, described in the
Control Registers section. Typically, a common audio system clock rate, such as 11.2896MHz, 12.288MHz,
22.5792MHz, or 24.576MHz, may be used for this clock.
The SRC reference clock rate may be any frequency up to 27.7MHz, and does not have to be related to or
synchronous with the input or output sampling rates. The MCLK, RXCKI, or RXCKO clocks may be utilized as
the reference clock source for the SRC. Refer to the Asynchronous Sample Rate Converter (SRC) Operation
section for additional details.
It is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators
for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they
are designed and/or specified for low clock jitter.
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AUDIO SERIAL PORT OPERATION
The SRC4382 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial
interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right
word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in
Figure 61.
The audio serial ports may be operated at sampling rates up to 216kHz, and support audio data word lengths up
to 24 bits. Philips I2S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 62.
The left/right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either
Master or Slave mode operation. In Master mode these clocks are outputs, derived from the selected master
clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio
input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave
mode the left/right word and bit clocks are inputs, being sourced from an external audio device acting as the
serial bus master.
The LRCKA or LRCKB clocks operate at the input/output sampling rate, fS. The BCKA and BCKB clock rates are
fixed at 64 times the left/right word clock rate in Master mode. For Slave mode, the minimum BCKA and BCKB
clock rate is determined by the audio data word length multiplied by two, since there are two audio data channels
per left/right word clock period. For example, if the audio data word length is 24 bits, the bit clock rate must be at
least 48 times the left/right word clock rate, allowing one bit clock period for each data bit in the serial bit stream.
Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port
on the falling edge of the bit clock. Refer to the Electrical Characteristics: Audio Serial Ports table for parametric
information and Figure 1 for a timing diagram related to audio serial port operation.
The audio serial ports are configured using control registers 0x03 through 0x06. Refer to the Control Registers
section for descriptions of the control register bits.
CLK[1:0]
M/S
DIV[1:0]
MCLK
RXCKI
Master
Mode
Clock
Master
Clock
Source
RXCKO
Generation
SDINA (pin 39) or SDINB (pin 46)
LRCKA (pin 38) or LRCKB (pin 47)
BCKA (pin 37) or BCKB (pin 48)
Audio Data
Serial
Input
Internal Clocks
Port A
Data
Source
Port B
DIR
Serial
Output
SDOUTA (pin 40) or SDOUTB (pin 45)
SRC
OUTS[1:0]
MUTE
FMT[1:0]
Figure 61. Audio Serial Port Block Diagram
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Channel 1 (Left Channel)
Channel 2 (Right Channel)
LRCKA
LRCKB
BCKA
BCKB
Audio
MSB
LSB
MSB
LSB
Data
(a) Left-Justified Data Format
LRCKA
LRCKB
BCKA
BCKB
Audio
Data
MSB
LSB
MSB
LSB
(b) Right-Justified Data Format
LRCKA
LRCKB
BCKA
BCKB
Audio
Data
MSB
LSB
MSB
LSB
2
(c) I S Data Format
1/fs
Figure 62. Audio Data Formats
OVERVIEW OF THE AES3 DIGITAL AUDIO INTERFACE PROTOCOL
This section introduces the basics of digital audio interface protocols pertaining to the transmitter (DIT) and
receiver (DIR) blocks of the SRC4382. Emphasis is placed upon defining the basic terminology and
characteristics associated with the AES3-2003 standard protocol, the principles of which may also be applied to
a number of consumer-interface variations, including S/PDIF, IEC-60958, and EIAJ CP-1201. It is assumed that
the reader is familiar with the AES3 and S/PDIF interface formats. Additional information is available from the
sources listed in the Reference Documents section.
The AES3-2003 standard defines a technique for two-channel linear PCM data transmission over 110Ω shielded
twisted-pair cable. The AES-3id document extends the AES3 interface to applications employing 75Ω coaxial
cable connections. In addition, consumer transmission variants, such as those defined by the S/PDIF, IEC
60958, and CP-1201 standards, utilize the same encoding techniques but with different physical interfaces or
transmission media. Channel status data definitions also vary between professional and consumer interface
implementations.
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For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and
status data, corresponding to audio Channels 1 and 2 (or Left and Right, respectively, for stereophonic audio).
Figure 63 shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble,
up to 24 bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data
(C), one bit for user data (U), and one bit for setting parity (P).
The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble
codes are used to identify the start of the Channel 1 and Channel 2 subframes, as shown in Figure 63. However,
the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the
start of a new block of channel status and user data.
Block Start
Frame 191
Frame 0
Y
Frame 1
Y
X
Channel 1
Y
Channel 2
Z
Channel 1
Channel 2
X
Channel 1
Channel 2
One Sub Frame
Bits: 0
3 4
7 8
27 28 29 30 31
MSB
Audio or
Aux Data
Preamble
Audio Data
V U C P
Validity Bit
User Data
Channel Status Data
Parity Bit
Figure 63. AES3 Frame and Subframe Encoding
One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and
user data for each channel. The 192 bits are organized into 24 data bytes, which are defined by the AES3-2003
and consumer standards documents. The AES18 standard defines recommended usage and formatting of the
user data bits, while consumer applications may utilize the user data for other purposes. The SRC4382 also
includes block-sized transmitter and receiver channel status and user data buffers, which have 24 bytes each for
the channel status and user data assigned to audio Channels 1 and 2. Refer to the Channel Status and User
Data Buffer Maps section for the organization of the buffered channel status and user data for the receiver and
transmitter functions.
The audio data for Channel 1 and Channel 2 may be up to 24 bits in length, and occupies bits 4 through 27 of
the corresponding subframe. Bit 4 is the LSB while bit 27 is the MSB. If only 20 bits are required for audio data,
then bits 8 through 27 are utilized for audio data, while bits 4 though 7 are utilized for auxiliary data bits.
The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for
digital-to-analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity
bit is 0, then the audio sample is suitable for conversion or additional processing. If the validity bit is 1, then the
audio sample is not suitable for conversion or additional processing.
The parity (P) bit is set to either a 0 or 1, such that bits 4 through 31 carry an even number of ones and zeros for
even parity. The DIT block in the SRC4382 automatically manages the parity bit, setting it to a 0 or 1 as needed.
The DIR block checks the parity of bits 4 though 31 and generates a parity error if odd parity is detected.
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The binary non-return to zero (NRZ) formatted audio and status source data for bits 4 through 31 of each
subframe are encoded utilizing a Biphase Mark format for transmission. This format allows for clock recovery at
the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections.
The preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting,
making their detection by the receiver reliable, as well as avoiding the possibility of audio and status data
imitating the preambles. Figure 64 shows the Biphase Mark and preamble encoding.
Although the AES3 standard originally defined transmission for sampling rates up to 48kHz, the interface is
capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching.
Equalization at the receiver may also be required, depending on the cable and matching factors. It is also
possible to transmit and decode more than two channels of audio data utilizing the AES3 or related consumer
interfaces. Special encoding and/or compression algorithms are utilized to support multiple channels, including
the Dolby® AC-3, DTS, MPEG-1/2, and other data reduced audio formats.
Clock
(2x Source Bit Rate)
Source Data
1
Coding
Insert Preamble
Code Below
0
(NRZ)
AES3 Channel
Coding
1
0
(Biphase Mark)
Preamble Z (Block Start)
Preceding State, from the Parity bit of the previous Frame.
Preamble Coding
Preceding State:
0
1
Preamble:
Channel Coding:
11100010
Channel Coding: Description:
X
Y
Z
00011101
00011011
00010111
Channel 1 Subframe
Channel 2 Subframe
Channel 1 Subframe and Block Start
11100100
11101000
Figure 64. Biphase Mark Encoding
DIGITAL INTERFACE TRANSMITTER (DIT) OPERATION
The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream.
In addition to the encoding function, the DIT includes differential line driver and CMOS buffered output functions.
The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS buffered output is
designed to drive external logic or line drivers, as well as optical transmitter modules. Figure 65 illustrates the
functional block diagram for the DIT.
The input of the DIT receives the audio data for Channels 1 and 2 from one of four possible sources: Port A, Port
B, the DIR, or the SRC. By default, Port A is selected as the source. The DIT also requires a master clock
source, which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock
output). A master clock divider is utilized to select the frame rate for the AES3-encoded output data. The
TXDIV[1:0] bits in control register 0x07 are utilized to select divide by 128, 256, 384, or 512 operation.
Channel status and user data for Channels 1 and 2 are input to the AES3 encoder via the corresponding
Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers,
which are programmed via the SPI or I2C host interface, or loaded from the DIR Receiver Access (RA) data
buffers. The source of the channel status and user data is selected utilizing the TXCUS[1:0] bits in control
register 0x09. When the DIR is selected as the input source, the channel status and user data output from the
DIT is delayed by one block in relation to the audio data.
The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is
utilized to select the validity data source for the DIT block. The default source is the VALID bit in control register
0x07, which is written via the SPI or I2C host interface. The validity bit may also be transferred from the AES3
decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by frame.
The parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits 4
through 31 of the AES3-encoded subframe are even parity.
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The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown
in Figure 65, the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from
the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line
receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be
routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and
CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When
the outputs are disabled, they are forced to a low logic state.
The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and
auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute
function is controlled using the TXMUTE bit in control register 0x08.
TXDIV[1:0]
TXCLK
Master
Clock
MCLK
AESMUX
AESOFF
RXCKO
Source
AESOUT
(pin 34)
TXIS[1:0]
Port A
Port B
DIR
LDMUX
TXOFF
Data
Source
SRC
TX+ (pin 32)
AES3
Encoder
User Access
(UA) Buffers
Transmitter Access
(TA) Buffers
TX- (pin 31)
From Receiver
From
Bypass
Multiplexer
Output
Access (RA) Buffer
2
To/From SPI or I C
Channel
Status
Channel
Status
Host Interface
From Receiver
BLS (pin 35)
SYNC (pin 36)
Access (RA) Buffer
2
To/From SPI or I C
User
Data
User
Data
Host Interface
TXCUS[1:0] TXBTD
TXMUTE
BLSM
Figure 65. Digital Interface Transmitter (DIT) Functional Block Diagram
The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an
input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07.
By default, the BLS pin is configured as an input.
As an input, the BLS pin may be utilized to force a block start condition, whereby the start of a new block of
channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input
must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock
rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 66
illustrates the format required for an external block start signal, as well as indicating the format when the BLS pin
is configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon
the internal SYNC clock.
For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to
the Control Registers and Channel Status and User Data Buffer Maps sections.
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Block Start
(Frame 0 starts here)
SYNC
BLS
(input)
BLS
(output)
Figure 66. DIT Block Start Timing
DIGITAL INTERFACE RECEIVER (DIR) OPERATION
The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The
lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 67 shows the functional block
diagram for the DIR.
Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers
can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with
CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 68 for a simplified schematic
for the line receiver. External connections are discussed in the Receiver Input Interfacing section.
2
To SPI or I C Host Interface
Reference
MCLK
Clock
Source
Channel
Status
User
Data
User Access
(UA) Buffers
PLL1
RXCKI
To
DIT
To
RXCLK
DIT
RX1+ (pin 1)
RXMUX[1:0]
Channel
Status
User
Data
AES3
RX1- (pin 2)
Decoder
Receiver
Access
RX2+ (pin 3)
RX2- (pin 4)
(RA) Buffers
RX3+ (pin 5)
RX3- (pin 6)
Pulse
Data Stream
De-Mux
Error and
Generator
RX4+ (pin 7)
Status Outputs
RX4- (pin 8)
To DIT Buffer
BYPMUX[1:0]
PLL2
128fS
256fS
512fS
Ch.1
(Left) (Right)
Audio Audio
Ch.2
and Line Driver
LOCK
(pin 11)
Clock
Receiver
Sync
RXCKO
(pin 12)
Divider
Divide by
1, 2, 4, or 8
RXCKOF[1:0]
RCV_SYNC
Generator
RXCKO
Figure 67. Digital Interface Receiver (DIR) Functional Block Diagram
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VDD33
24kW
24kW
3kW
RX+
To Receiver
Input and Bypass
Multiplexers
RX-
3kW
24kW
24kW
DGND2
Figure 68. Differential Line Receiver Circuit
The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer
and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for
the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is utilized to route a
line receiver output to either the DIT line driver or CMOS buffered outputs, thereby bypassing all other internal
circuitry. The bypass function is useful for simple signal distribution and routing applications.
The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK
(pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is utilized as the oversampling
clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the
audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are
separated for further processing and buffering. The pulse generator circuitry samples the encoded input data
stream and generates a clock that is 16 times the frame/sampling rate (or fS). The 16fS clock is then processed
by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available
PLL2 output clock rates include 512fS, 256fS, and 128fS. The maximum available PLL2 output clock rate for a
given input sampling rate is estimated by internal logic and made available for readback via status register 0x13.
The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered
master clock output, RXCKO (pin 12). The RXCKO clock is also be routed internally to other function blocks,
where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and
forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be
tied to the same external circuit node, if needed. By default, the RXCKO output (pin 12) is disabled and forced to
a high-impedance state.
Figure 69 illustrates the frequency response of PLL2. Jitter attenuation starts at approximately 50kHz. Peaking is
nominally 1dB, which is within the 2dB maximum allowed by the AES3 standard. The receiver jitter tolerance plot
for the DIR is illustrated in Figure 70, along with the required AES3 jitter tolerance template. The DIR jitter
tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification.
Figure 70 was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame
rate.
The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks,
including Port A, Port B, the SRC, and/or the DIT. The decoded channel status and user data is buffered in the
corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data
buffers, where it may be read back through either the SPI or I2C serial host interface. The contents of the RA
buffers may also be transferred to the DIT UA data buffers; see Figure 65. The channel status and user data bits
may also be output serially through the general-purpose output pins, GPO[4:1]. Figure 71 illustrates the output
format for the GPO pins when used for this purpose, along with the DIR block start (BLS) and frame
synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with the start of each
frame for the received AES3 data.
The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock
output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags
may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the SPI or
I2C host interface. Refer to the General-Purpose Digital Outputs and Control Registers sections for additional
information regarding the DIR status functions.
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2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0
1
2
3
4
5
6
10
10
10
10
10
10
10
Jitter Frequency (Hz)
Figure 69. DIR Jitter Attenuation Characteristics
-10
-20
5
2
Input Jitter Amplitude
-30
1
-40
Output Jitter Amplitude
500m
200m
100m
50m
20m
10m
5m
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
THD+N
2m
1m
20
100
1k
10k
100k
Sinusoidal Jitter Frequency (Hz)
Figure 70. DIR Jitter Tolerance Plot
Block Start
(Frame 0 Starts Here)
BLS
(output)
SYNC
(output)
C or U data
(output)
Ch. 1 Ch. 2 Ch. 1 Ch. 2 Ch. 1 Ch. 2 Ch. 1 Ch. 2
Bit 0
Bit 1
Bit 2
Bit 4
¼
Figure 71. DIR Channel Status and User Data Serial Output Format Via the GPO Pins
ASYNCHRONOUS SAMPLE RATE CONVERTER (SRC) OPERATION
The asynchronous SRC provides conversion from an arbitrary input sampling rate to a desired output sampling
rate. The input and output sampling rates may be equal or different, within the bounds of a 1:16 to 16:1
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input-to-output sampling ratio range. The input and output data sources may be completely asynchronous to one
another; synchronous operation is also supported. The input-to-output sampling ratio is determined automatically
using internal rate estimation logic, with the re-sampler being updated in real time without the need for
programming. The SRC supports input and output sampling rates up to 216kHz, with audio data word lengths up
to 24 bits. A functional block diagram for the SRC is shown in Figure 72.
MUTE (pin 14)
DDN
TRACK
AL[7:0]
DEM[1:0]
IGRP[1:0]
SRCIS[1:0]
AUTODEM
AR[7:0]
OWL[1:0]
Audio Data Output
Port A
Port B
DIR
De-Emphasis
Filter
Interpolation
Filter
Decimation
Filter
Re-Sampler
INT_SYNC
From Port A, Port B, or DIT
fSIN
fSOUT
Rate
MCLK
RXCKI
Estimator
Reference Clock
RXCKO
SRI[4:0]
SRF[10:0]
RATIO
SRCCLK[1:0]
RDY (pin 15)
Figure 72. Asynchronous Sample Rate Converter (SRC) Functional Block Diagram
The SRC receives a digital audio input from one of three data sources: Port A, Port B, or the DIR. By default,
Port A is selected as the input source for the SRC. The output of the SRC may be connected to Port A, Port B,
and/or the DIT.
The SRC requires a reference clock, which may be sourced from either the MCLK (pin 25) or RXCKI (pin 13)
clock inputs, or from the RXCKO recovered master clock output from the DIR block. The reference clock is
utilized by the rate estimator to determine the input-to-output sampling ratio. By default, MCLK is selected as the
reference clock source for the SRC.
As part of the SRC rate estimation and re-sampling functions, two digital servo loops are employed, one for the
input side and one for the output side. The servo loops operate in two modes: Fast and Slow. When a change in
one or both of the sampling rates occurs, the servo loop(s) enter(s) Fast mode operation. When a servo loop has
settled in Fast mode, it will then switch to Slow mode. When both the input and output servo loops have switched
to Slow mode, the RDY output (pin 15) is forced low, indicating that the SRC has completed the rate estimation
process.
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The input and output servo-loop frequency responses are shown in Figure 73 and Figure 74, respectively. The
filter response for each servo loop rolls off at 80dB per decade. The servo loop corner frequencies scale
proportionally with input or output sampling rates. The low corner frequency and sharp roll-off provide excellent
jitter attenuation for the SRC block.
0
-50
Fast Mode
-100
Slow Mode
-150
fS = 192kHz
-200
-1
0
1
2
3
4
5
10
10
10
10
10
10
10
Frequency (Hz)
Figure 73. Input Digital Servo-Loop Frequency Response
0
-50
Fast Mode
Slow Mode
-100
-150
fS = 192kHz
-200
-2
-1
0
1
2
3
4
5
10
10
10
10
10
10
10
10
Frequency (Hz)
Figure 74. Output Digital Servo-Loop Frequency Response
The SRC includes output soft muting and digital attenuation functions, providing artifact-free muting and output
level control for the SRC output data. The mute function forces the SRC output data low by stepping the output
attenuation from the current setting to an all-zero data output state. The mute function may be controlled by the
MUTE input (pin 14), or the MUTE bit in control register 0x2D. Both the pin and control bit are active high, with
the signals being combined by a logic OR function internally to generate the SRC output mute control signal. The
MUTE control bit in control register 0x2D is disabled by default.
The digital attenuation is programmable over a 0dB to –127.5dB range in 0.5dB steps, and may be controlled
independently for the Left and Right channels. The attenuation level is set using control registers; by default, the
level is 0dB. A tracking function is available, allowing the Left and Right channel attenuation data to be set to the
same value by simply programming the Left channel attenuation register. The tracking mode is enabled or
disabled using a control register bit. The tracking function is disabled by default.
The SRC includes digital de-emphasis filtering for the audio input data. The de-emphasis filter provides
normalization for 50/15μs pre-emphasized audio data. The de-emphasis filter supports 32kHz, 44.1kHz, and
48kHz input sampling rates. The filter is controlled by the DEM0, DEM1, and AUTODEM bits in control register
0x2E. The DEM0 and DEM1 bits allow the user to manually configure the de-emphasis filter operation. By
default, the de-emphasis filtering is disabled. The AUTODEM bit, when enabled, overrides the setting of the
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DEM0 and DEM1 bits. The AUTODEM function automatically enables and disables the de-emphasis filter for the
required sampling rate based upon the setting of the pre-emphasis and sampling frequency channel status bits in
the AES3 or S/PDIF input data stream, which are decoded by the DIR block. The AUTODEM feature functions
only when both 50/15μs pre-emphasis and one of the three supported sampling rates (32kHz, 44.1kHz, or
48kHz) are decoded by the DIR. By default, the de-emphasis filter, including the AUTODEM function, is disabled.
The group delay of the SRC interpolation function can be programmed to one of four settings. The actual length
of the interpolation filter is unaltered, but the number of samples pre-buffered in the FIFO prior to the re-sampler
function can be set to 64, 32, 16, or 8. The FIFO length directly impacts the latency and group delay. By default,
the number of samples pre-buffered is set to 64.
The decimation filter includes a direct down-sampling option. This option should only be used in cases where the
output sampling rate is higher than the input sampling rate. The advantage of using the direct down-sampling
option is that it results in zero latency operation, as it simply selects one out of every 16 samples from the
re-sampler output without applying low-pass anti-aliasing filtering. By contrast, the decimation filter response
adds 36.46875 samples of group delay. The disadvantage of the direct down-sampling option is that it cannot be
used in cases where the output sampling rate is equal to or lower than the input sampling rate, since the lack of
low-pass filtering results in aliasing. By default, the decimation filter is enabled, as the initial values of the input
and output sampling rates may be unknown.
The SRC includes two status registers that contain the integer and fractional parts of the input-to-output sampling
ratio, which is derived by the SRC rate estimator circuitry. These registers can be read back any time the RDY
output is low. When either the input or output sampling rate is known, the unknown sampling rate can be
calculated using the contents of these status registers.
The SRC provides a simple word length reduction mechanism for reducing 24-bit audio data to 20-, 18-, or 16-bit
output word lengths. Word length reduction is performed utilizing triangular probability density function (or TPDF)
dither. The OWL0 and OWL1 bits in control register 0x2F are utilized to set the SRC output word length.
One note concerning the SRC output word length setting: when using the SRC output as the data source for
either the Port A or Port B serial data outputs, and the audio serial port data format is set to Right-Justified, the
word length set for the audio serial port format must match the word length set for the SRC output data.
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GENERAL-PURPOSE DIGITAL OUTPUTS
The SRC4382 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29,
respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be
connected to one of 14 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal.
Control registers 0x1B through 0x1E are utilized to select the function of the GPO pins. For details regarding
GPO output configuration, refer to the Control Registers section. Table 1 summarizes the available output
options for the GPO pins.
Table 1. General-Purpose Output Pin Configurations
GPOn3
GPOn2
GPOn1
GPOn0
GPOn FUNCTION
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPOn is forced Low (default).
GPOn is forced High.
SRC Interrupt Flag; Active Low
DIT Interrupt Flag; Active Low
DIR Interrupt Flag; Active Low
DIR 50/15μs Emphasis Flag; Active Low
DIR Non-Audio Data Flag; Active High
DIR Non-Valid Data Flag; Active High
DIR Channel Status Data Serial Output
DIR User Data Serial Output
DIR Block Start Clock Output
DIR COPY Bit Output
(0 = Copyright Asserted, 1 = Copyright Not Asserted)
1
0
1
1
DIR L (or Origination) Bit Output
(0 = 1st Generation or Higher,1 = Original)
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
DIR Parity Error Flag; Active High
DIR Internal Sync Clock Output; may be used as the data clock for the Channel
Status and User Data serial outputs.
DIT Internal Sync Clock
HOST INTERFACE OPERATION:
SERIAL PERIPHERAL INTERFACE (SPI) MODE
The SRC4382 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI
port supports high-speed serial data transfers up to 40Mbps. Register and data buffer write and read operations
are supported.
The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in
order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is
ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial
data input for the port; the CDOUT output serves as the serial data output.
The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the
CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of
CCLK.
Figure 75 illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant
bit (or MSB) is the read/write bit. For the R/W bit, a '0' indicates a write operation, while a '1' indicates a read
operation. The remaining seven bits of the command byte are utilized for the register address targeted by the
write or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to
retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter
products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices.
The SPI port supports write and read operations for multiple sequential register addresses through the
implementation of an auto-increment mode. As shown in Figure 75, the auto-increment mode is invoked by
simply holding the CS input low for multiple data bytes. The register address is automatically incremented after
each data byte transferred, starting with the address specified by the command byte.
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Refer to the Electrical Characteristics: SPI Interface table and Figure 2 for specifications and a timing diagram
that highlight the key parameters for SPI interface operation.
Set CS = 1 here to write/read one register location.
Hold CS = 0 to enable auto-increment mode.
CS
Header
Register Data
Byte N
Byte 0
Hi Z
Byte 1
Hi Z
Byte 2
Byte 3
CDIN
Register Data
Data for A[6:0] Data for A[6:0]+1
Data for A[2:0]+N
CDOUT
CCLK
Byte Definition
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
Byte 0:
Register Address
Set to 0 for Write; Set to 1 for Read.
Byte 1: Don’t Care
Byte 2 through Byte N: Register Data
Figure 75. Serial Peripheral Interface (SPI) Protocol for the SRC4382
HOST INTERFACE OPERATION: PHILIPS I2C MODE
The SRC4382 supports a 2-wire Philips I2C bus interface when CPM (pin 18) is forced high or pulled up to the
VIO supply rail. The SRC4382 functions as a Slave-only device on the bus. Standard and Fast modes of
operation are supported. Standard mode supports data rates up to 100kbps, while Fast mode supports data
rates up to 400kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes
referred to as Fast/Standard, or F/S mode. The I2C Bus Specification (Version 2.1, January 2000), available from
Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the
reader is familiar with this specification. Refer to the Electrical Characteristics: I2C Standard and Fast Modes
table and Figure 3 for specifications and a timing diagram that highlight the key parameters for I2C interface
operation.
When the I2C mode is invoked, pin 20 becomes SCL (which serves as the bus clock) and pin 22 becomes SDA
(which carries the bi-directional serial data for the bus). Pins 19 and 21 become A0 and A1, respectively, and
function as the hardware configurable portion of the 7-bit slave address.
The SRC4382 utilizes a 7-bit Slave address, see Figure 76(a). Bits A2 through A6 are fixed and bits A0 and A1
are hardware programmable using pins 19 and 21, respectively. The programmable bits allow for up to four
SRC4382 devices to be connected to the same bus. The slave address is followed by the Register Address Byte,
which points to a specific register or data buffer location in the SRC4382 register map. The register address byte
is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation, see
Figure 76(b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a
single operation, and is especially useful for block write and read operations.
Figure 77 illustrates the protocol for Standard and Fast mode Write operations. When writing a single register
address, or multiple non-sequential register addresses, the single register write operation of Figure 77(a) may be
used one or more times. When writing multiple sequential register addresses, the auto-increment mode of
Figure 77(b) improves efficiency. The register address is automatically incremented by one for each successive
byte of data transferred.
Figure 78 illustrates the protocol for Standard and Fast mode Read operations. The current address read
operation of Figure 78(a) assumes the value of the register address from the previously executed write or read
operation, and is useful for polling a register address for status changes. Figure 78(b) and Figure 78(c) illustrate
read operations for one or more random register addresses, with or without auto-increment mode enabled.
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First Byte After the START/RESTART Condition
Slave Address
MSB
LSB
A6
1
A5
1
A4
1
A3
0
A2 A1
A1
A0
A0 R/W
0
Set by Pin 19
Set by Pin 21
(a) SRC4382 Slave Address
MSB
LSB
A0
INC A6
A5
A4
A3
A2
A1
Auto-Increment
0 = Disabled
1 = Enabled
(b) Register Address Byte
Figure 76. SRC4382 Slave Address and Register Address Byte Definitions
Byte 1
Byte 2
Byte 3
Register
Data
Slave Address
with R/W = 0
Register Address Byte
with INC = 0
S
A
A
A P
(a) Writing a Single Register
Byte 1
Byte 2
Register Address Byte
with INC = 1
Byte 4
Byte N
Slave Address
with R/W = 0
Register Data
For Address + 1
Register Data
For Address + N
Byte 3
Register Data
S
A
A
A
A
A P
(b) Writing Multiple Sequential Registers Using Auto-Increment Operation
Legend
S = START Condition
Transfer from Master to Slave
A = Acknowledge
Transfer from Slave to Master
P = STOP Condition
Figure 77. Fast/Standard Mode Write Operations
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Byte 1
Byte 2
Slave Address
with R/W = 1
Register Address Byte
with INC = 0
S
A
A P
(a) Current Address Read, Assumes the Register Address of the Previous
Byte 1
Byte 2
Byte 3
Byte 4
Register Data
Slave Address
with R/W = 0
Register Address Byte
with INC = 0
Slave Address
with R/W = 1
A
A P
S
A
A R
(b) Random Read Operation, Auto-Increment Disabled
Byte 1
Byte 2
Byte 3
Byte N
Slave Address
with R/W = 0
Register Address Byte
with INC = 1
Slave Address
with R/W = 1
Byte 4
Register Data
For Address + N
Register Data
S
A
A R
A
A
A P
(c) Random Read Operation, Auto-Increment Enabled
Legend
S = START Condition
Transfer from Master to Slave
Transfer from Slave to Master
A = Acknowledge
A = Not Acknowledge
R = Repeated START
P = STOP Condition
Figure 78. Fast/Standard Mode Read Operations
INTERRUPT OUTPUT
The SRC4382 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The
interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pull-up
resistor to the VIO supply rail. The value of the pull-up is not critical, but a 10kΩ device should be sufficient for
most applications. Figure 79 shows the interrupt output pin connection. The open-drain output allows interrupt
pins from multiple SRC4382 devices to be connected in a wired OR configuration.
SRC4382
MCU, DSP,
or Logic
VIO
Interrupt
Logic
10kW
INT 23
Interrupt
Input
To the INT outputs for
additional SRC4382 devices
Figure 79. Interrupt Output Pin Connections
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APPLICATIONS INFORMATION
Typical application diagrams and power-supply connections are presented in this section to aid the customer in
hardware designs employing the SRC4382 device.
Figure 80 illustrates typical application connections for the SRC4382 using an SPI host interface. The SPI host
will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to
providing the SPI bus master, the host may be utilized to process interrupt and flag outputs from the SRC4382.
The audio serial ports are connected to external digital audio devices, which may include data converters, digital
signal processors, digital audio interface receivers/transmitters, or other logic devices. The DIR inputs and DIT
outputs are connected to line, optical, or logic interfaces (see the Receiver Input Interfacing and Transmitter
Output Interfacing sections). Master and DIR reference clock sources are also shown.
Figure 81 illustrates typical application connections for the SRC4382 using an I2C bus interface. The I2C bus
master will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to
providing the I2C bus master, the host may be used to process interrupt and flag outputs from the SRC4382.
Pull-up resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These pull-up
resistors are required for the open drain outputs of the I2C interface. All other connections to the SRC4382 are
the same as the SPI host case discussed previously.
Figure 82 illustrates the recommended power-supply connections and bypassing for the SRC4382. In this case, it
is assumed that the VIO, VDD33, and VCC supplies are powered from the same +3.3V power source. The
VDD18 core supply is powered from a separate supply, or derived from the +3.3V supply using a linear voltage
regulator, as illustrated with the optional regulator circuitry of Figure 82.
The 0.1μF bypass capacitors are surface-mount X7R ceramic, and should be located as close to the device as
possible. These capacitors should be connected directly between the supply and corresponding ground pins of
the SRC4382. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB).
The larger value capacitors, shown connected in parallel to the 0.1μF capacitors, are recommended. At a
minimum, there should at least be footprints on the PCB for installation of these larger capacitors, so that
experiments can be run with and without the capacitors installed, in order to determine the effect on the
measured performance of the SRC4382. The larger value capacitors can be surface-mount X7R multilayer
ceramic or tantalum chip.
The substrate ground, BGND (pin 44), should be connected by a PCB trace to AGND (pin 10). The AGND pin is
then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the
device, aiding the overall jitter and noise tolerance for the receiver.
A series resistor is shown between the +3.3V supply and VCC (pin 9) connection. This resistor combines with the
bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply. The
series resistor should be a metal film type for best filtering characteristics. As a substitute for the resistor, a ferrite
bead can be utilized, although it may have to be physically large in order to contribute to the filtering.
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SRC4382IPFB
BCKA
37
38
39
40
41
42
43
44
45
46
47
48
36
35
34
33
32
31
30
29
28
27
26
25
SYNC
BLS
Audio
I/O
To Host or External Logic
LRCKA
SDINA
SDOUTA
NC
AESOUT
VDD33
TX+
Device
To Digital Outputs
(Line, Optical, Logic)
VIO
TX-
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
Audio
I/O
To Host or External Logic
Device
1
2
24
23
22
21
20
19
18
17
16
15
14
13
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
RST
INT
3
CDOUT
CDIN
CCLK
CS
4
From Digital Inputs
(Line, Optical, Logic)
5
SPI
Host
6
7
CPM
8
Controller
VDD18
DGND1
RDY
9
10
11
12
AGND
LOCK
RXCKO
MUTE
RXCKI
DIR Recovered Clock
Master
Clock
10kW
VIO
DIR
Ref Clock
NOTE: See Figure 82 for power-supply connections. Dashed lines denote optional connections to the host.
Figure 80. Typical Application Diagram Using SPI Host Interface
SRC4382IPFB
37
38
39
40
41
42
43
44
45
46
47
48
36
35
34
33
32
31
30
29
28
27
26
25
BCKA
SYNC
BLS
Audio
I/O
To Host or External Logic
LRCKA
SDINA
SDOUTA
NC
AESOUT
VDD33
TX+
Device
To Digital Outputs
(Line, Optical, Logic)
VIO
TX-
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
Audio
I/O
To Host or External Logic
Device
1
2
24
23
22
21
20
19
18
17
16
15
14
13
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
RST
INT
3
SDA
4
From Digital Inputs
A1
5
2
I C
(Line, Optical, Logic)
SCL
6
A0
7
Host
CPM
VDD18
DGND1
RDY
MUTE
RXCKI
8
Controller
Tie
9
LO or HI
10
11
12
AGND
LOCK
RXCKO
DIR Recovered Clock
Master
Clock
10kW
2.7kW
VIO
DIR
Ref Clock
NOTE: See Figure 82 for power-supply connections. Dashed lines denote optional connections to the host.
Figure 81. Typical Application Diagram Using I2C Host Interface
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+3.3V
10mF
+
44
0.1mF
R
43
42
SRC4382IPFB
9
33
30
+
+
0.1mF
10mF
10mF
0.1mF
10
Connect pin 44 to pin 10.
Pin 10 is then connected to
the ground plane.
+3.3V
TPS79318DBVR
16
17
0.1mF
1
5
IN
OUT
NR
4
3
EN
GND
2
C
+
0.1mF
0.01mF
2.2mF
+1.8V
Optional Regulator Circuit
R may be set from 2W to 10W, or replaced by a ferrite bead.
C may be set to 10mF, or not installed when using the optional regulator circuit.
Figure 82. Recommended Power-Supply Connections
DIGITAL AUDIO TRANSFORMER VENDORS
Transformers are shown in this data sheet for both receiver and transmitter balanced and unbalanced line
interface implementations. For the Texas Instruments Pro Audio evaluation modules, transformers from Scientific
Conversion are utilized. In addition to Scientific Conversion, there are other vendors that offer transformer
products for digital audio interface applications. Please refer to the following manufacturer web sites for details
regarding their products and services. Other transformer vendors may also be available by searching catalog
and/or Internet resources.
•
•
•
Scientific Conversion: http://scientificonversion.com
Schott Corporation: http://schottcorp.com
Pulse Engineering: http://pulseeng.com
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RECEIVER INPUT INTERFACING
This section details the recommended interfaces for the SRC4382 line receiver inputs. Balanced and unbalanced
line interfaces, in addition to optical receiver and external logic interfacing, will be discussed.
For professional digital audio interfaces, 110Ω balanced line interfaces are either required or preferred.
Transformer coupling is commonly employed to provide isolation and to improve common-mode noise rejection.
Figure 83 shows the recommended transformer-coupled balanced line receiver interface for the SRC4382. The
transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for best
performance. Due to the DC bias on the line receiver inputs, 0.1μF capacitors are utilized for AC-coupling the
transformer to the line receiver inputs. On the line side of the transformer, an optional 0.1μF capacitor is shown
for cases where a DC bias may be applied at the transmitter side of the connection. The coupling capacitors
should be surface-mount ceramic chip type with an X7R or C0G dielectric.
(1)
1:1
C
0.1mF
To RX+
3
2
Digital Input
1
110W
110W Balanced
To RX-
XLR
0.1mF
(1) Insert a 0.1mF capacitor when blocking common-mode DC voltage.
Figure 83. Transformer-Coupled Balanced Input Interface
Unbalanced 75Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio
applications. Designs with and without transformer line coupling may be utilized. Figure 84(a) shows the
recommended 75Ω transformer-coupled line interface, which shares many similarities to the balanced design
shown in Figure 83. Once again, the transformer provides isolation and improved noise rejection. Figure 84(b)
shows the transformer-free interface, which is commonly used for S/PDIF consumer connections.
(1)
1:1
C
0.1mF
To RX+
Digital Input
75W Unbalanced
75W
(RCA or BNC connector)
To RX-
0.1mF
(a) Transformer-Coupled Unbalanced Line Interface
0.1mF
To RX+
Digital Input
75W Unbalanced
75W
(RCA or BNC connector)
To RX-
0.1mF
(b) Unbalanced Line Interface Without Transformer
(1) Insert a 0.1mF capacitor when blocking common-mode DC components.
Figure 84. Unbalanced Line Input Interfaces
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Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where
interconnections are less than 10m in length. Optical receiver modules utilized for a digital audio interface
operate from either a single +3.3V or +5V supply and have a TTL-, CMOS-, or low-voltage CMOS-compatible
logic output. Interfacing to +3.3V optical receivers is straightforward when the optical receiver supply is powered
from the SRC4382 VDD33 power source, as shown in Figure 85. For the +5V optical receivers, the output high
logic level may exceed the SRC4382 line receiver absolute maximum input voltage. A level translator is required,
placed between the optical receiver output and the SRC4382 line receiver input. Figure 86 shows the
recommended input circuit when interfacing a +5V optical receiver to the SRC4382 line receiver inputs. The
Texas Instruments SN74LVC1G125 single buffer IC is operated from the same +3.3V supply used for SRC4382
VDD33 supply. This buffer includes a +5V tolerant digital input, and provides the logic level translation required
for the interface.
VDD33
All-Plastic
(5 or 10 meters maximum)
Optical
(1)
To RX+
Receiver
To RX-
0.1mF
(1) Toshiba TORX141 or equivalent.
Figure 85. Interfacing to a +3.3V Optical Receiver Module
SN74LVC1G125
or Equivalent
+5V
VDD33
5
2
4
All-Plastic
(5 or 10 meters maximum)
Optical
(1)
To RX+
Receiver
To RX-
1
3
0.1mF
(1) Toshiba TORX173, TORX176, TORX179, or equivalent.
Figure 86. Interfacing to a +5V Optical Receiver Module
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The SRC4382 line receivers may also be driven directly from external logic or line receiver devices with TTL or
CMOS outputs. If the logic driving the line receiver is operated from +3.3V, then logic level translation is not be
required. However, if the external logic is operated from a power-supply voltage that exceeds the maximum
VDD33 supply voltage of the SRC4382, or operates from a supply voltage lower than +3.3V, then level
translation is required. Figure 87 shows the recommended logic level translation methods, utilizing buffers and
level translators available from Texas Instruments.
SN74LVC1G125
or Equivalent
VDD33
5
2
4
From +5V Logic
(TTL or CMOS)
To RX+
To RX-
1
3
0.1mF
SN74AVC1T45
or Equivalent
+1.8V or +2.5V
VDD33
1
5
6
3
4
From +1.8V or +2.5V
CMOS Logic
To RX+
To RX-
2
0.1mF
Figure 87. CMOS/TTL Input Logic Interface
TRANSMITTER OUTPUT INTERFACING
This section details the recommended interfaces for the SRC4382 transmitter line driver and CMOS buffered
outputs. Balanced and unbalanced line interfaces, in addition to optical transmitter and external logic interfacing,
will be discussed.
For professional digital audio interfaces, 110Ω balanced line interfaces are either required or preferred.
Transformer coupling is commonly employed to provide isolation and to improve common-mode noise
performance. Figure 88 shows the recommended transformer-coupled balanced line driver interface for the
SRC4382. The transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for
best performance. To eliminate residual DC bias, a 0.1μF capacitor is utilized for AC-coupling the transformer to
the line driver outputs. The coupling capacitor should be a surface-mount ceramic chip type with an X7R or C0G
dielectric.
1:1
110W
TX+
3
2
Digital Output
1
110W Balanced
TX-
XLR
0.1mF
Figure 88. Transformer-Coupled Balanced Output Interface
Unbalanced 75Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio
applications. Designs with and without transformer line coupling may be utilized. Figure 89(a) illustrates the
recommended 75Ω transformer-coupled line driver interface, which shares many similarities to the balanced
design shown in Figure 88. Figure 89(b) illustrates the transformer-free line driver interface, which is commonly
used for S/PDIF consumer connections.
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1:1
0.1mF
R1
TX+
Digital Output
R2
75W Unbalanced
(RCA or BNC connector)
(a) Transformer-Coupled Unbalanced Output
0.1mF
R1
TX+
Digital Output
R2
75W Unbalanced
(RCA or BNC connector)
(b) Unbalanced Output Without Transformer
R1 and R2 are selected to achieve the desired output voltage level while maintaining the required 75W transmitter output impedance.
The TX+ output impedance is negligible.
Figure 89. Unbalanced Line Output Interfaces
Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where
interconnections are less than 10m in length. Most optical transmitter modules utilized for a digital audio interface
operate from a single +3.3V or +5V supply and have a TTL-compatible logic input. The CMOS buffered
transmitter output of the SRC4382, AESOUT (pin 34), is capable of driving the optical transmitter with VIO supply
voltages down to +3.0V. If the VIO supply voltage is less than +3.0V, then level translation logic is required to
drive the optical transmitter input. A good choice for this application is the Texas Instruments SN74AVC1T45
single bus transceiver. This device features two power-supply rails, one for the input side and one for the output
side. For this application, the input side supply is powered from the VIO supply, while the output side is powered
from a +3.3V supply. This will boost the logic high level to a voltage suitable for driving the TTL compatible input
configuration. Figure 90 shows the recommended optical transmitter interface circuits.
Optical
All-Plastic Fiber
(5 or 10 meters maximum)
(1)
AESOUT
Transmitter
VIO
1
+3.3V
6
5
If VIO < +3.0V.
3
4
2
SN74AVC1T45
or Equivalent
(1) Toshiba TOTX141, TOTX173, TOTX176, TOTX179, or equivalent.
Figure 90. Interfacing to an Optical Transmitter Module
The AESOUT output may also be used to drive external logic or line driver devices directly. Figure 91 illustrates
the recommended logic interface techniques, including connections with and without level translation. Figure 92
illustrates an external line driver interface utilizing the Texas Instruments SN75ALS191 dual differential line
driver. If the VIO supply of the SRC4382 is set from +3.0V to +3.3V, no logic level translation is required between
the AESOUT output and the line driver input. If the VIO supply voltage is below this range, then the optional logic
level translation logic of Figure 92 is required. The SN75ALS191 dual line driver is especially useful in
applications where simultaneous 75Ω and 110Ω line interfaces are required.
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Direct to external logic
AESOUT
operating from the VIO supply.
+5V
5
2
4
To +5V Logic
(VIO supply = +3.0V to +3.3V)
3
1
SN74AHCT1G125
or Equivalent
Figure 91. CMOS/TTL Output Logic Interface
+5V
SN75ALS191
1
8
2
To Balanced or Unbalanced
Line Interface
AESOUT
7
VIO
+3.3V
6
1
6
5
5
If VIO < +3.0V.
3
To Balanced or Unbalanced
Line Interface
3
4
2
SN74AVC1T45
or Equivalent
1
Figure 92. External Line Driver Interface
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REGISTER AND DATA BUFFER ORGANIZATION
The SRC4382 organizes the on-chip registers and data buffers into four pages. The currently active page is
chosen by programming the Page Selection Register to the desired page number. The Page Selection Register
is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates
the page selection corresponding to the Page Selection Register value.
Table 2. Register Page Selection
Page Selection Register Value (Hex)
Selected Register Page
00
01
02
03
Page 0, Control and Status Registers
Page 1, DIR Channel Status and User Data Buffers
Page 2, DIT Channel Status and User Data Buffers
Page 3, Reserved
Register Page 0 contains the control registers utilized to configure the various function blocks within the
SRC4382. In addition, status registers are provided for flag and error conditions, with many of the status bits
capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map.
Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These
buffers correspond to the data contained in the C and U bits of the previously received block of the
AES3-encoded data stream. The contents of these buffers may be read through the SPI or I2C serial host
interface and processed as needed by the host system. See Table 5 for the DIR channel status buffer map, and
Table 6 for the DIR user data buffer map.
Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These
buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The
contents of these buffers may be written through the SPI or I2C serial host interface to configure the C and U bits
of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See
Table 7 for the DIT channel status buffer map, and Table 8 for the DIT user data buffer map.
Register Page 3 is reserved for factory test and verification purposes, and cannot be accessed without an unlock
code. The unlock code remains private; the test modes disable normal operation of the device, and are not
useful in customer applications.
CONTROL REGISTERS
See Table 3 for the control and status register map of the SRC4382. Register addresses 0x00 and 0x34 through
0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The
following pages provide detailed descriptions for each control and status register.
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Table 3. Control and Status Register Map (Register Page 0)
ADDRESS
D7
(Hex)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
7F
(MSB)
D6
D5
D4
PDPA
0
D3
PDPB
0
D2
PDTX
TX
D1
PDRX
RX
D0
PDSRC
SRC
REGISTER GROUP
Power-Down and Reset
Global Interrupt Status
Port A Control
RESET
0
PDALL
0
0
0
0
AMUTE
AOUTS1
AOUTS0
0
AM/S
ACLK1
BM/S
BCLK1
TXIS0
TXBTD
0
AFMT2
ACLK0
BFMT2
BCLK0
BLSM
AESOFF
VALSEL
0
AFMT1
ADIV1
BFMT1
BDIV1
VALID
TXMUTE
TXCUS1
TSLIP
MTSLIP
TBTIM1
RXMUX1
RXCKOD0
J3
AFMT0
ADIV0
BFMT0
BDIV0
BSSL
TXOFF
TXCUS0
TBTI
0
0
0
Port A Control
0
BMUTE
BOUTS1
BOUTS0
0
Port B Control
0
0
0
Port B Control
TXCLK
TXDIV1
TXDIV0
TXIS1
LDMUX
0
Transmitter Control
BYPMUX1
BYPMUX0
AESMUX
Transmitter Control
0
0
0
Transmitter Control
0
0
RATIO
READY
MREADY
READYM0
RXBTD
LOL
0
SRC and DIT Status
0
0
MRATIO
0
0
MTBTI
TBTIM0
RXMUX
RXCKOE
J2
SRC and DIT Interrupt Mask
SRC and DIT Interrupt Mode
Receiver Control
RATIOM1
RATIOM0
READYM1
TSLIPM1
RXCLK
RXAMLL
J5
TSLIPM0
0
0
0
0
0
0
P3
0
RXCKOD1
J4
Receiver Control
P2
P1
P0
Receiver PLL Configuration
Receiver PLL Configuration
Receiver PLL Configuration
Non-PCM Audio Detection
Receiver Status
J1
J0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
DTS CD/LD
RXCKR1
QCRC
0
IEC61937
RXCKR0
RBTI
0
0
0
0
0
0
CSCRC
0
PARITY
0
VBIT
BPERR
0
QCHG
0
UNLOCK
0
Receiver Status
0
OSLIP
MRBTI
MOSLIP
RBTIM0
BPERRM0
OSLIPM0
GPO10
GPO20
GPO30
GPO40
Q7
Receiver Status
MCSCRC
0
MPARITY
0
MVBIT
MBPERR
0
MQCHG
0
MUNLOCK
0
MQCRC
0
Receiver Interrupt Mask
Receiver Interrupt Mask
Receiver Interrupt Mode
Receiver Interrupt Mode
Receiver Interrupt Mode
General-Purpose Out (GPO1)
General-Purpose Out (GPO2)
General-Purpose Out (GPO3)
General-Purpose Out (GPO4)
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
Audio CD Q-Channel Sub-Code
PC Burst Preamble, High Byte
PC Burst Preamble, Low Byte
PD Burst Preamble, High Byte
PD Burst Preamble, Low Byte
SRC Control
0
UNLOCKM1
PARITYM1
0
QCHGM1
CSCRCM1
0
QCHGM0
CSCRCM0
0
UNLOCKM0
PARITYM0
0
QCRCM1
VBITM1
0
QCRCM0
VBITM0
0
RBTIM1
BPERRM1
OSLIPM1
GPO11
GPO21
GPO31
GPO41
Q6
0
0
0
0
GPO13
GPO23
GPO33
GPO43
Q4
GPO12
GPO22
GPO32
GPO42
Q5
0
0
0
0
0
0
0
0
0
0
0
0
Q0
Q1
Q2
Q3
Q8
Q9
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
PC13
PC05
PD13
PD05
0
Q11
Q12
Q13
Q14
Q15
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
PC15
PC07
PD15
PD07
0
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
PC14
PC06
PD14
PD06
TRACK
0
Q19
Q20
Q21
Q22
Q23
Q27
Q28
Q29
Q30
Q31
Q35
Q36
Q37
Q38
Q39
Q43
Q44
Q45
Q46
Q47
Q51
Q52
Q53
Q54
Q55
Q59
Q60
Q61
Q62
Q63
Q67
Q68
Q69
Q70
Q71
Q75
Q76
Q77
Q78
Q79
PC12
PC04
PD12
PD04
MUTE
DEM1
0
PC11
PC03
PD11
PD03
SRCCLK1
DEM0
0
PC10
PC02
PD10
PD02
SRCCLK0
DDN
0
PC09
PC01
PD09
PD01
SRCIS1
IGRP1
0
PC08
PC00
PD08
PD00
SRCIS0
IGRP0
0
0
AUTODEM
0
SRC Control
OWL1
AL7
AR7
SRI4
SRF7
0
OWL0
AL6
AR6
SRI3
SRF6
0
SRC Control
AL5
AL4
AL3
AL2
AL1
AL0
SRC Control
AR5
SRI2
SRF5
0
AR4
SRI1
SRF4
0
AR3
AR2
AR1
AR0
SRC Control
SRI0
SRF3
0
SRF10
SRF2
0
SRF9
SRF1
PAGE1
SRF8
SRF0
PAGE0
SRC Input: Output Ratio
SRC Input: Output Ratio
Page Selection
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Register 01: Power-Down and Reset
Bit 7 (MSB)
RESET
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PDSRC
PDALL
PDPA
PDPB
PDTX
PDRX
PDSRC
Power-Down for the SRC Function Block
This bit is utilized to power-down the SRC and associated functions.
PDSRC
SRC Power-Down Mode
0
Enabled (Default)
Disabled; the SRC function block will operate normally based upon the applicable control
register settings.
1
PDRX
Power-Down for the Receiver Function Block
This bit is utilized to power-down the DIR and associated functions. All receiver outputs are forced low.
PDRX
Receiver Power-Down Mode
0
Enabled (Default)
Disabled; the Receiver function block will operate normally based upon the applicable
control register settings.
1
PDTX
Power-Down for the Transmitter Function Block
This bit is utilized to power-down the DIT and associated functions. All transmitter outputs are forced low.
PDTX
Transmitter Power-Down Mode
0
Enabled (Default)
Disabled; the Transmitter function block will operate normally based upon the applicable
control register settings.
1
PDPB
PDPA
PDALL
Power-Down for Serial Port B
This bit is utilized to power-down the audio serial I/O Port B. All port outputs are forced low.
PDPB
Port B Power-Down Mode
0
1
Enabled (Default)
Disabled; Port B will operate normally based upon the applicable control register settings.
Power-Down for Serial Port A
This bit is utilized to power-down the audio serial I/O Port A. All port outputs are forced low.
PDPA
Port A Power-Down Mode
0
1
Enabled (Default)
Disabled; Port A will operate normally based upon the applicable control register settings.
Power-Down for All Functions
This bit is utilized to power-down all function blocks except the host interface port and the control and status registers.
PDALL
All Function Power-Down Mode
0
Enabled (Default)
Disabled; all function blocks will operate normally based upon the applicable control register
settings.
1
RESET
Software Reset
This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset via the RST input (pin 24).
RESET
Reset Function
0
1
Disabled (Default)
Enabled; all control registers will be reset to the default state.
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Register 02: Global Interrupt Status (Read-Only)
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RX
Bit 0 (LSB)
SRC
0
0
0
TX
SRC
SRC Function Block Interrupt Status (Active High)
When set to 1, this bit indicates an active interrupt from the SRC function block. This bit is active high. The user should then read status
register 0x0A in order to determine which of the sources has generated an interrupt.
RX
TX
Receiver Function Block Interrupt Status (Active High)
When set to 1, this bit indicates an active interrupt from the DIR function block. This bit is active high. The user should then read status
registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt.
Transmitter Function Block Interrupt Status (Active High)
When set to 1, this bit indicates an active interrupt from the DIT function block. This bit is active high. The user should then read status
register 0x0A in order to determine which of the sources has generated an interrupt.
Register 03: Port A Control Register 1
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
AFMT0
0
AMUTE
AOUTS1
AOUTS0
AM/S
AFMT2
AFMT1
AFMT[2:0]
Port A Audio Data Format
These bits are used to set the audio input and output data format for Port A. Refer to the Audio Serial Port Operation section for
illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable
timing diagram and parameters.
AFMT2
AFMT1
AFMT0
Audio Data Format
24-Bit Left-Justified (Default)
24-Bit Philips I2S
Unused
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Unused
16-Bit Right-Justified
18-Bit Right-Justified
20-Bit Right-Justified
24-Bit Right-Justified
Note: When the SRC is selected as the output data source for Port A and the data format for the port is set to Right-Justified, the proper
word length must be selected in the Port A control registers such that it matches the corresponding SRC output data word length. Refer to
control register 0x2F for the SRC output word length selection.
AM/S
Port A Slave/Master Mode
This bit is used to set the audio clock mode for Port A to either Slave or Master.
AM/S
Slave/Master Mode
0
1
Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (Default)
Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source.
AOUTS[1:0]
Port A Output Data Source
These bits are used to select the output data source for Port A. The data is output at SDOUTA (pin 40).
AOUTS1
AOUTS0
Output Data Source
0
0
1
1
0
1
0
1
Port A Input, for data loop back. (Default)
Port B Input
DIR
SRC
AMUTE
Port A Output Mute
This bit is used to mute the Port A audio data output.
AMUTE
Output Mute
0
1
Disabled; SDOUTA is driven by the output data source. (Default)
Enabled; SDOUTA is forced low.
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Register 04: Port A Control Register 2
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
ADIV0
0
0
ACLK1
ACLK0
ADIV1
ADIV[1:0]
Port A Master Clock Divider
These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation.
BCKA is always set to 64 times the LRCKA clock rate in Master mode.
ADIV1
ADIV0
Master Mode Clock Divider
Divide By 128 (Default)
Divide By 256
0
0
1
1
0
1
0
1
Divide By 384
Divide By 512
ACLK[1:0]
Port A Master Clock Source
These bits are used to set the master clock source for Port A when configured for Master mode operation.
ACLK1
ACLK0
Master Clock Source
MCLK (Default)
RXCKI
0
0
1
1
0
1
0
1
RXCKO
Reserved
Register 05: Port B Control Register 1
Bit 7 (MSB)
0
Bit 6
BMUTE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
BFMT0
BOUTS1
BOUTS0
BM/S
BFMT2
BFMT1
BFMT[2:0]
Port B Audio Data Format
These bits are used to set the audio input and output data format for Port B. Refer to the Audio Serial Port Operation section for
illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure 1 for an applicable
timing diagram and parameters.
BFMT2
BFMT1
BFMT0
Audio Data Format
24-Bit Left-Justified (Default)
24-Bit Philips I2S
Unused
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Unused
16-Bit Right-Justified
18-Bit Right-Justified
20-Bit Right-Justified
24-Bit Right-Justified
Note: When the SRC is selected as the output data source for Port B and the data format for the port is set to Right-Justified, the proper
word length must be selected in the Port B control registers such that it matches the corresponding SRC output data word length. Refer to
control register 0x2F for the SRC output word length selection.
BM/S
Port B Slave/Master Mode
This bit is used to set the audio clock mode for Port B to either Slave or Master.
BM/S
Slave/Master Mode
0
1
Slave mode; the LRCK and BCK clocks are generated by an external source. (Default)
Master mode; the LRCK and BCK clocks are derived from the Port A master clock source.
BOUTS[1:0]
Port B Output Source
These bits are used to select the output data source for Port B. The data is output at SDOUTB (pin 45).
BOUTS1
BOUTS0
Output Data Source
0
0
1
1
0
1
0
1
Port B Input, for data loop back. (Default)
Port A Input
DIR
SRC
BMUTE
Port B Output Mute
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This bit is used to mute the Port B audio data output.
BMUTE Output Mute
0
1
Disabled; SDOUTB is driven by the output data source. (Default)
Enabled; SDOUTB is forced low.
Register 06: Port B Control Register 2
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
BDIV0
0
0
BCLK1
BCLK0
BDIV1
BDIV[1:0]
Port B Master Mode Clock Divider
These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation.
BCKB is always set to 64 times the LRCKB clock rate in Master mode.
BDIV1
BDIV0
Master Mode Clock Divider
Divide By 128 (Default)
Divide By 256
0
0
1
1
0
1
0
1
Divide By 384
Divide By 512
BCLK[1:0]
Port B Master Clock Source
These bits are used to set the master clock source for Port B when configured for Master mode operation.
BCLK1
BCLK0
Master Clock Source
MCLK (Default)
RXCKI
0
0
1
1
0
1
0
1
RXCKO
Reserved
Register 07: Transmitter Control Register 1
Bit 7 (MSB)
TXCLK
Bit 6
TXDIV1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
BSSL
TXDIV0
TXIS1
TXIS0
BLSM
VALID
BSSL
Block Start or Asynchronous Data Slip Interrupt Trigger Selection
This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit.
BSSL
TSLIP Interrupt Trigger Source
Data Slip Condition (Default)
Block Start Condition
0
1
VALID
Validity (V) Data Bit
This bit may be used to set the validity (or V) data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for
V-bit source selection.
VALID
Transmitted Validity (V) Bit Data
Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital
processing. (Default)
0
Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further
digital processing.
1
BLSM
Transmitter Block Start Input/Output Mode
This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35).
BLSM
BLS Pin Mode
Input (Default)
Output
0
1
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TXIS[1:0]
Transmitter Input Data Source
These bits are used to select the audio data source for the DIT function block.
TXIS1
TXIS0
Output Word Length
0
0
1
1
0
1
0
1
Port A (Default)
Port B
DIR
SRC
TXDIV[1:0]
Transmitter Master Clock Divider
These bits are used to select the Transmitter master clock divider, which determines the output frame rate.
TXDIV1
TXDIV0
Clock Divider
0
0
1
1
0
1
0
1
Divide the master clock by 128. (Default)
Divide the master clock by 256.
Divide the master clock by 384.
Divide the master clock by 512.
TXCLK
Transmitter Master Clock Source
This bit is used to select the master clock source for the Transmitter block.
TXCLK
Transmitter Master Clock Source
0
1
MCLK Input (Default)
RXCKO; the recovered master clock from the DIR function block.
Register 08: Transmitter Control Register 2
Bit 7 (MSB)
BYPMUX1
Bit 6
BYPMUX0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
TXOFF
AESMUX
LDMUX
TXBTD
AESOFF
TXMUTE
TXOFF
Transmitter Line Driver Output Enable
This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs.
TXOFF
Transmitter Line Driver
0
1
Enabled; the line driver outputs function normally. (Default)
Disabled; the line driver outputs are forced low.
TXMUTE
AESOFF
TXBTD
Transmitter Audio Data Mute
This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and 2.
TXMUTE
Transmitter Audio Data Mute
0
1
Disabled (Default)
Enabled; the audio data for both Channels 1 and 2 are set to all zeros.
AESOUT Output Enable
This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output.
AESOFF
AESOUT Output
0
1
Enabled; the AESOUT pin functions normally. (Default)
Disabled; the AESOUT pin is forced low.
Transmitter C and U Data Buffer Transfer Disable
This bit is used to enable and disable buffer transfers between the DIT User Access (UA) and DIT Transmitter Access (TA) buffers for both
channel status (C) and user (U) data.
Buffer transfers may be disabled, allowing the user to write new C and U data to the UA buffers via the SPI or I2C serial host interface.
Once updated, UA-to-TA buffer transfers may then be re-enabled, allowing the TA buffer to be updated and the new C and U data to be
transmitted at the start of the next block.
TXBTD
User Access (UA) to Transmitter Access (TA) Buffer Transfers
Enabled (Default)
0
1
Disabled; allows the user to update DIT C and U data buffers.
Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur.
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LDMUX
Transmitter Line Driver Input Source Selection
This bit is used to select the input source for the DIT differential line driver outputs.
LDMUX
Line Driver Input Source
0
1
DIT AES3 Encoder Output (Default)
Bypass Multiplexer Output
AESMUX
AESOUT CMOS Buffer Input Source Selection
This bit is used to select the input source for the AESOUT CMOS logic level output.
AESMUX
AESOUT Buffer Input Source
DIT AES3 Encoder Output (Default)
Bypass Multiplexer Output
0
1
BYPMUX[1:0]
Bypass Multiplexer Source Selection
These bits select the line receiver output to be utilized as the Bypass multiplexer data source.
BYPMUX1
BYPMUX0
Line Receiver Output Selection
0
0
1
1
0
1
0
1
RX1 (Default)
RX2
RX3
RX4
Register 09: Transmitter Control Register 3
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
TXCUS0
0
0
0
0
VALSEL
TXCUS1
TXCUS[1:0]
Transmitter Channel Status and User Data Source
These bits select the source of the channel status (or C) data and user (or U) data which is used to load the DIT User Access (UA) buffers.
TXCUS1
TXCUS0
DIT UA Buffer Source
0
0
1
0
1
0
The buffers will not be updated. (Default)
The buffers are updated via the SPI or I2C host interface.
The buffers are updated via the DIR RA buffers.
The first 10 bytes of the buffers are updated via the SPI or I2C host, while the
remainder of the buffers are updated via the DIR RA buffers.
1
1
VALSEL
Transmitter Validity Bit Source
This bit is utilized to select the source for the validity (or V) bit in the AES3-encoded output data stream.
VALSEL
Validity (or V) Bit Source Selection
0
1
The VALID bit in control register 0x07.
The V bit is transferred from the DIR block with zero latency.
Register 0A: SRC and DIT Status (Read-Only)
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
TBTI
0
RATIO
READY
0
0
TSLIP
TBTI
Transmitter Buffer Transfer Status, Active High
When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to
0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the
UA-to-TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status
register 0x02 to be set to 1, indicating that an interrupt has occurred.
TSLIP
Transmitter Source Data Slip Status, Active High
The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is
unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this
interrupt.
The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set
to 1, indicating that an interrupt has occurred.
READY
SRC Rate Estimator Ready Status, Active High
The READY bit will be set to 1 when the input and output rate estimators have completed the Fast mode portion of the rate estimation
process, and the READY interrupt is unmasked (the MREADY bit in control register 0x0B is set to 1). This will also cause the INT
output (pin 23) to be driven low and the SRC bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.
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RATIO
SRC Ratio Status, Active High
The RATIO bit will be set to 1 when the input sampling rate is higher than the output sampling rate, and the RATIO interrupt is
unmasked (the MRATIO bit in control register 0x0B is set to 1). This will also cause the INT output (pin 23) to be driven low and the
SRC bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.
Register 0B: SRC and DIT Interrupt Mask Register
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
MTBTI
MRATIO
MREADY
0
0
MTSLIP
MBTI
Transmitter Buffer Transfer Interrupt Mask
MTBI
BTI Interrupt Mask
0
1
BTI interrupt is masked. (Default)
BTI interrupt is enabled.
MTSLIP
MREADY
MRATIO
Transmitter TSLIP Interrupt Mask
MTSLIP
TSLIP Interrupt Mask
0
1
TSLIP interrupt is masked. (Default)
TSLIP interrupt is enabled.
SRC Ready Interrupt Mask
MREADY
READY Interrupt Mask
0
1
READY interrupt is masked. (Default)
READY interrupt is enabled.
SRC Ratio Interrupt Mask
MRATIO
RATIO Interrupt Mask
0
1
RATIO interrupt is masked. (Default)
RATIO interrupt is enabled.
Register 0C: SRC and DIT Interrupt Mode Register
Bit 7 (MSB)
RATIOM1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
TBTIM0
RATIOM0
READYM1
READYM0
TSLIPM1
TSLIPM0
TBTIM1
TBTIM[1:0]
Transmitter Buffer Transfer Interrupt Mode
These bits are utilized to select the active trigger state for the BTI interrupt.
TBTIM1
TBTIM0
Interrupt Active State
0
0
1
1
0
1
0
1
Rising Edge Active (Default)
Falling Edge Active
Level Active
Reserved
TSLIPM[1:0]
Transmitter Data Source Slip Interrupt Mode
These bits are utilized to select the active trigger state for the TSLIP interrupt.
TSLIPM1
TSLIPM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
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READYM[1:0]
SRC Ready Interrupt Mode
These bits are utilized to select the active trigger state for the READY interrupt.
READYM1
READYM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
RATIOM[1:0]
SRC Ratio Interrupt Mode
These bits are utilized to select the active trigger state for the RATIO interrupt.
RATIOM1
RATIOM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
Register 0D: Receiver Control Register 1
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RXMUX0
0
0
RXBTD
RXCLK
0
RXMUX1
RXMUX[1:0]
Receiver Input Source Selection
These bits are used to select the output of the line receiver to be used as the input data source for the DIR core.
RXMUX1
RXMUX0
Input Selection
RX1 (Default)
RX2
0
0
1
1
0
1
0
1
RX3
RX4
RXCLK
RXBTD
Receiver Reference Clock Source
This bit is used to select the reference clock source for PLL1 in the DIR core.
RXCLK
Receiver Reference Clock
RXCKI (Default)
MCLK
0
1
Receiver C and U Data Buffer Transfer Disable
This bit is used to enable and disable buffer transfers between the Receiver Access (RA) and User Access (UA) buffers for both channel
status (C) and user (U) data.
Buffer transfers are typically disabled to allow the customer to read C and U data from the DIR UA buffer via the SPI or I2C serial host
interface. Once read, the RA-to-UA buffer transfer can be re-enabled to allow the RA buffer to update the contents of the UA buffer in real
time.
RXBTD
Receiver Access (RA) to User Access (UA) Buffer Transfers
Enabled (Default)
0
1
Disabled; the user may read C and U data from the DIR UA buffers.
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Register 0E: Receiver Control Register 2
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RXCKOE
0
LOL
RXAMLL
RXCKOD1
RXCKOD0
RXCKOE
RXCKOE Output Enable
This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance
state.
RXCKOE
RXCKO Output State
0
1
Disabled; the RXCKO output is set to high-impedance. (Default)
Enabled; the recovered master clock is available at RXCKO.
RXCKOD[1:0]
RXCKO Output Clock Divider
These bits are utilized to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at
the RXCKO output (pin 12).
RXCKOD1
RXCKOD0
RXCKO Output Divider
0
0
1
1
0
1
0
1
Passthrough, no division is performed. (Default)
Divide the PLL2 clock output by 2.
Divide the PLL2 clock output by 4.
Divide the PLL2 clock output by 8.
RXAMLL
Receiver Automatic Mute for Loss of Lock
This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2.
RXAMLL
Receiver Auto-Mute Function
0
1
Disabled (Default)
Enabled; audio data output from the DIR block is forced low for a loss of lock condition.
LOL
Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2)
This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs.
LOL
Receiver PLL2 Operation
0
1
The PLL2 output clock is stopped for a loss of lock condition. (Default)
The PLL2 output clock free runs when a loss of lock condition occurs.
Register 0F: Receiver PLL1 Configuration Register 1
Bit 7 (MSB)
P3
Bit 6
P2
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
J3
Bit 0 (LSB)
J2
P1
P0
J5
J4
Register 10: Receiver PLL1 Configuration Register 2
Bit 7 (MSB)
J1
Bit 6
J0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
D9
Bit 0 (LSB)
D8
D13
D12
D11
D10
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Register 11: Receiver PLL1 Configuration Register 3
Bit 7 (MSB)
D7
Bit 6
D6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
D1
Bit 0 (LSB)
D0
D5
D4
D3
D2
Registers 0x0F through 0x11 are utilized to program PLL1 in the DIR core. PLL1 multiplies the DIR reference clock source to an oversampling rate which is
adequate for AES3 decoder operation. PLL1 is programmed using the following relationship:
(CLOCK
נ
K) / P = 98.304MHz where:
CLOCK = frequency of the DIR reference clock source.
K = J.D, where the integer part J = 1 to 63, and the fractional part D = 0 to 9999.
P = the pre-divider value, which may be set to any 4-bit value that meets the conditions stated below.
The following conditions must be met for the values of P, J, and D:
If D = 0, then:
If D ≠ 0, then:
2 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤ 55.
10 MHz ≤ (CLOCK / P) ≤ 20 MHz and 4 ≤ J ≤11.
Referring to registers 0x0F through 0x11:
P is programmed using bits P[3:0].
J is programmed using bits J[5:0].
D is programmed using bits D[13:0].
Table 4 shows values for P, J, and D for common DIR reference clock rates.
Table 4. PLL1 Register Values for Common Reference Clock Rates
REFERENCE CLOCK RATE (MHz)
P
1
1
1
1
2
2
2
J
12
8
D
0
ERROR (%)
0.0000
0.0002
0.0000
0.0000
0.0002
0.0000
0.0003
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
27.0000
7075
0
8
6
0
8
7075
0
8
7
2818
Register 12: Non-PCM Audio Detection Status Register (Read-Only)
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
IEC61937
0
0
0
0
0
DTS CD/LD
IEC61937
This bit is utilized to indicate the detection of an IEC 61937 data reduced audio format (includes Dolby AC-3, DTS, etc.) for DVD
playback or general transmission purposes.
IEC61937
Status
0
Data is not an IEC61937 format.
Data is an IEC61937 format. Refer to the PC and PD preamble registers (addresses 0x29
through 0x2C) for data type and burst length.
1
DTS CD/LD
This bit is used to indicate the detection of a DTS encoded audio compact disc (CD) or Laserdisc (LD) playback.
DTS CD/LD
Status
0
1
The CD/LD is not DTS encoded.
DTS CD/LD playback detected.
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Register 13: Receiver Status Register 1 (Read-Only)
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RXCKR0
0
0
0
0
RXCKR1
RXCKR[1:0]
Maximum Available Recovered Clock Rate
These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection circuitry, which determines the frame rate
of the incoming AES3-encoded bit stream. Based upon the estimated frame rate, a maximum rate for the recovered clock output (RXCKO)
is determined and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits.
The status of the RXCKR0 and RXCKR1 bits may be utilized to determine the programmed value for the PLL2 output clock divider, set by
the RXCKOD0 and RXCKOD1 bits in control register 0x0E.
RXCKR1
RXCKR0
Maximum Available RXCKO Rate
0
0
1
1
0
1
0
1
Clock rate not determined.
128fS
256fS
512fS
Register 14: Receiver Status Register 2 (Read-Only)
Bit 7 (MSB)
CSCRC
Bit 6
PARITY
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RBTI
VBIT
BPERR
QCHG
UNLOCK
QCRC
Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated.
CSCRC
PARITY
VBIT
Channel Status CRC Status
CSCRC
CRC Status
0
1
No Error
CRC Error Detected
Parity Status
PARITY
Parity Status
No Error
0
1
Parity Error Detected
Validity Bit Status
VBIT
Validity Bit
0
1
Valid Audio Data Indicated
Non-Valid Data Indicated
BPERR
QCHG
Bipolar Encoding Error Status
BPERR
Bipolar Encoding Status
No Error
0
1
Bipolar Encoding Error Detected
Q-Channel Sub-Code Data Change Status
QCHG
Q-Channel Data Status
0
No change in Q-channel sub-code data.
Q-channel data has changed. May be used to trigger a read of the Q-channel sub-code
data, registers 0x1F through 0x28.
1
UNLOCK
QCRC
RBTI
DIR Unlock Error Status
UNLOCK
DIR Lock Status
0
1
No error; the DIR AES3 decoder and PLL2 are locked.
DIR lock error; the AES3 decoder and PLL2 are unlocked.
Q-Channel Sub-Code CRC Status
QCRC
Q-Channel CRC Status
No Error
0
1
Q-channel sub-code data CRC error detected.
Receiver Buffer Transfer Interrupt Status
RBTI
DIR RA Buffer-to-UA Buffer Transfer Status
0
Buffer Transfer Incomplete, or No Buffer Transfer Interrupt Indicated
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1
Buffer Transfer Completed
Register 15: Receiver Status Register 3 (Read-Only)
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0 (LSB)
OSLIP
0
0
0
0
Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated.
OSLIP
Receiver Output Data Slip Error Status
OSLIP
Receiver OSLIP Error Status
No Error
0
1
DIR Output Data Slip/Repeat Error Detected
An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate in
slave mode. Figure 93 shows the timing associated with the OSLIP interrupt.
When only one audio serial port (Port A or Port B) is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and
Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only.
AES3 Bit Stream
Y
X
Y
X
DIR SYNC
R
L
L
L
R
R
R
L
L
L
R
R
LRCK, Left or Right
Justified Formats (input)
LRCK, I2S Format (input)
±5%
±5%
Data Slip or Repeat may occur when the LRCK edges indicated are within the ±5% window.
Figure 93. DIR Output Slip/Repeat (OSLIP) Behavior
Register 16: Receiver Interrupt Mask Register 1
Bit 7 (MSB)
MCSCRC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
MRBTI
MPARITY
MVBIT
MBPERR
MQCHG
MUNLOCK
MQCRC
MCSCRC
Channel Status CRC Error Interrupt Mask
MCSCRC
CRC Interrupt
Masked (Default)
Enabled
0
1
MPARITY
MVBIT
Parity Error Interrupt Mask
MPARITY
Parity Error Interrupt
Masked (Default)
Enabled
0
1
Validity Error Interrupt Mask
MVBIT
Validity Error Interrupt
Masked (Default)
Enabled
0
1
MBPERR
Bipolar Encoding Error Interrupt Mask
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MBPERR
Bipolar Error Interrupt
Masked (Default)
Enabled
0
1
MQCHG
Q-Channel Sub-Code Data Change Interrupt Mask
MQCHG
Q-Channel Data Change Interrupt
0
1
Masked (Default)
Enabled
MUNLOCK
MQCRC
MRBTI
DIR Unlock Error Interrupt Mask
MUNLOCK
DIR Unlock Interrupt
Masked (Default)
Enabled
0
1
Q-Channel Sub-Code CRC Error Interrupt Mask
MQCRC
Q-Channel CRC Error Interrupt
0
1
Masked (Default)
Enabled
Receiver Buffer Transfer Interrupt Mask
MRBTI
Receiver Buffer Transfer Interrupt
Masked (Default)
0
1
Enabled
Register 17: Receiver Interrupt Mask Register 2
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
Bit 0 (LSB)
MOSLIP
0
0
0
0
MOSLIP
Receiver Output Data Slip Error Mask
MOSLIP
Receiver OSLIP Error Interrupt
Masked (Default)
0
1
Enabled
Register 18: Receiver Interrupt Mode Register 1
Bit 7 (MSB)
QCHGM1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RBTIM0
QCHGM0
UNLOCKM1
UNLOCKM0
QCRCM1
QCRCM0
RBTIM1
QCHGM[1:0]
UNLOCKM[1:0]
QCRCM[1:0]
Q-Channel Sub-Code Data Change Interrupt Mode
QCHGM1
QCHGM0
Interrupt Active State
0
0
1
1
0
1
0
1
Rising Edge Active (Default)
Falling Edge Active
Level Active
Reserved
DIR Unlock Error Interrupt Mode
UNLOCKM1
UNLOCKM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
Q-Channel Sub-Code CRC Error Interrupt Mode
QCRCM1
QCRCM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
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RBTIM[1:0]
Receive Buffer Transfer Interrupt Mode
RBTIM1
RBTIM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
Register 19: Receiver Interrupt Mode Register 2
Bit 7 (MSB)
CSCRCM1
Bit 6
CSCRCM0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
BPERRM0
PARITYM1
PARITYM0
VBITM1
VBITM0
BPERRM1
CSCRCM[1:0]
PARITYM[1:0]
VBITM[1:0]
Channel Status CRC Error Interrupt Mode
CSCRCM1
CSCRCM0
Interrupt Active State
0
0
1
1
0
1
0
1
Rising Edge Active (Default)
Falling Edge Active
Level Active
Reserved
Parity Error Interrupt Mode
PARITYM1
PARITYM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
Validity Error Interrupt Mode
VBITM1
VBITM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
BPERRM[1:0]
Bipolar Encoding Error Interrupt Mode
BPERRM1
BPERRM0
Interrupt Active State
Rising Edge Active (Default)
Falling Edge Active
Level Active
0
0
1
1
0
1
0
1
Reserved
Register 1A: Receiver Interrupt Mode Register 3
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
OSLIPM0
0
0
0
0
0
OSLIPM1
OSLIPM[1:0]
Receiver Output Data Slip Error Interrupt Mode
OSLIPM1
OSLIPM0
Interrupt Active State
0
0
1
1
0
1
0
1
Rising Edge Active (Default)
Falling Edge Active
Level Active
Reserved
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Register 1B: General-Purpose Output 1 (GPO1) Control Register
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
GPO10
0
0
0
GPO13
GPO12
GPO11
GPO[13:10]
General-Purpose Output 1 (GPO1) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO1.
GPO13
GPO12
GPO11
GPO10
GPO1 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO1 is Forced Low (Default)
GPO1 is Forced High
SRC Interrupt, Active Low
Transmitter Interrupt, Active Low
Receiver Interrupt, Active Low
Receiver 50/15μs Pre-Emphasis, Active Low
Receiver Non-Audio Data, Active High
Receiver Non-Valid Data, Active High
Receiver Channel Status Bit
Receiver User Data Bit
Receiver Block Start Clock
Receiver COPY Bit
(0 = Copyright Asserted, 1 = Copyright Not Asserted)
1
1
0
1
1
0
1
0
Receiver L-Bit
(0 = First Generation or Higher, 1 = Original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver Parity Error, Active High
Receiver Internal Sync Clock
Transmitter Internal Sync Clock
Register 1C: General-Purpose Output 2 (GPO2) Control Register
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
GPO20
0
0
0
GPO23
GPO22
GPO21
GPO[23:20]
General-Purpose Output 2 (GPO2) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO2.
GPO23
GPO22
GPO21
GPO20
GPO2 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO2 is Forced Low (Default)
GPO2 is Forced High
SRC Interrupt, Active Low
Transmitter Interrupt, Active Low
Receiver Interrupt, Active Low
Receiver 50/15μs Pre-Emphasis, Active Low
Receiver Non-Audio Data, Active High
Receiver Non-Valid Data, Active High
Receiver Channel Status Bit
Receiver User Data Bit
Receiver Block Start Clock
Receiver COPY Bit
(0 = Copyright Asserted, 1 = Copyright Not Asserted)
1
1
0
1
1
0
1
0
Receiver L-Bit
(0 = First Generation or Higher, 1 = Original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver Parity Error, Active High
Receiver Internal Sync Clock
Transmitter Internal Sync Clock
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Register 1D: General-Purpose Output 3 (GPO3) Control Register
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
GPO30
0
0
0
GPO33
GPO32
GPO31
GPO[33:30]
General-Purpose Output 3 (GPO3) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO3.
GPO33
GPO32
GPO31
GPO30
GPO3 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO3 is Forced Low (Default)
GPO3 is Forced High
SRC Interrupt, Active Low
Transmitter Interrupt, Active Low
Receiver Interrupt, Active Low
Receiver 50/15μs Pre-Emphasis, Active Low
Receiver Non-Audio Data, Active High
Receiver Non-Valid Data, Active High
Receiver Channel Status Bit
Receiver User Data Bit
Receiver Block Start Clock
Receiver COPY Bit
(0 = Copyright Asserted, 1 = Copyright Not Asserted)
1
1
0
1
1
0
1
0
Receiver L-Bit
(0 = First Generation or Higher, 1 = Original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver Parity Error, Active High
Receiver Internal Sync Clock
Transmitter Internal Sync Clock
Register 1E: General-Purpose Output 4 (GPO4) Control Register
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
GPO40
0
0
0
GPO43
GPO42
GPO41
GPO[43:40]
General-Purpose Output 4 (GPO4) Configuration
These bits are used to set the state or data source for the general-purpose digital output pin GPO4.
GPO43
GPO42
GPO41
GPO40
GPO4 Function
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
GPO4 is Forced Low (Default)
GPO4 is Forced High
SRC Interrupt, Active Low
Transmitter Interrupt, Active Low
Receiver Interrupt, Active Low
Receiver 50/15μs Pre-Emphasis, Active Low
Receiver Non-Audio Data, Active High
Receiver Non-Valid Data, Active High
Receiver Channel Status Bit
Receiver User Data Bit
Receiver Block Start Clock
Receiver COPY Bit
(0 = Copyright Asserted, 1 = Copyright Not Asserted)
1
1
0
1
1
0
1
0
Receiver L-Bit
(0 = First Generation or Higher, 1 = Original)
1
1
1
1
1
1
0
1
1
1
0
1
Receiver Parity Error, Active High
Receiver Internal Sync Clock
Transmitter Internal Sync Clock
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Registers 1F through 28: Q-Channel Sub-Code Data Registers
Registers 0x1F through 0x28 comprise the Q-channel sub-code buffer, which may be accessed for audio CD playback. The Q-channel data provides
information regarding the playback status for the current disc. The buffer data is decoded by the DIR block.
Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track
Bit 7 (MSB)
Q8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q15
Q9
Q10
Q11
Q12
Q13
Q14
Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index
Bit 7 (MSB)
Q16
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q23
Q17
Q18
Q19
Q20
Q21
Q22
Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes
Bit 7 (MSB)
Q24
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q31
Q25
Q26
Q27
Q28
Q29
Q30
Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q32
Q33
Q34
Q35
Q36
Q37
Q38
Q39
Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame
Bit 7 (MSB)
Q40
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q47
Q41
Q42
Q43
Q44
Q45
Q46
Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero
Bit 7 (MSB)
Q48
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q55
Q49
Q50
Q51
Q52
Q53
Q54
Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN
Bit 7 (MSB)
Q56
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q63
Q57
Q58
Q59
Q60
Q61
Q62
Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC
Bit 7 (MSB)
Q64
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q71
Q65
Q66
Q67
Q68
Q69
Q70
Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Q72
Q73
Q74
Q75
Q76
Q77
Q78
Q79
Registers 29 through 2C: IEC61937 PC/PD Burst Preamble
The PC and PD burst preambles are part of the IEC61937 standard for transmission of data reduced, non-PCM audio over a standard two-channel interface
(IEC60958). Examples of data-reduced formats include Dolby AC-3, DTS, various flavors of MPEG audio (including AAC), and Sony ATRAC. The PA and PB
preambles provide synchronization data, and are fixed values of 0xF872 and 0x4E1F, respectively. The PC preamble indicates the type of data being carried by
the interface and the PD preamble indicates the length of the burst, given as number of bits.
Registers 0x29 through 0x2C contain the PC and PD preambles as decoded by the DIR block.
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Register 29: Burst Preamble PC High-Byte Status Register (Read-Only)
Bit 7 (MSB)
PC15
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PC08
PC14
PC13
PC12
PC11
PC10
PC09
Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only)
Bit 7 (MSB)
PC07
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PC00
PC06
PC05
PC04
PC03
PC02
PC01
PC[4:0], Hex
Data Type
00
01
Null
Dolby AC-3
Reserved
Pause
02
03
04
MPEG-1 Layer 1
05
MPEG-1 Layer 2 or 3, or MPEG-2 Without Extension
06
MPEG-2 Data With Extension
MPEG-2 AAC ADTS
MPEG-2 Layer 1 Low Sample Rate
MPEG-2 Layer 2 or 3 Low Sample Rate
Reserved
07
08
09
0A
0B
0C
0D
0E
0F
DTS Type 1
DTS Type 2
DTS Type 3
ATRAC
ATRAC2/3
10-1F
Reserved
Bits PC[6:5] are both set to 0.
Bit PC[7] is an Error Flag, where: 0 = A valid burst-payload; 1 = Burst-payload may contain errors.
Bits PC[12:8] are data-type dependent.
Bits PC[15:13] indicate the stream number, which is set to 0.
Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only)
Bit 7 (MSB)
PD15
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PD08
PD14
PD13
PD12
PD11
PD10
PD09
Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)
Bit 7 (MSB)
PD07
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PD00
PD06
PD05
PD04
PD03
PD02
PD01
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Register 2D: SRC Control Register 1
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
SRCIS0
TRACK
0
MUTE
SRCCLK1
SRCCLK0
SRCIS1
SRCIS[1:0]
SRC Input Data Source
These bits select the input data source for the SRC.
SRCIS1
SRCIS0
Input Source
Port A (Default)
Port B
0
0
1
1
0
1
0
1
DIR
Reserved
SRCCLK[1:0]
SRC Reference Clock Source
These bits select the reference clock source for the SRC.
SRCCLK1
SRCCLK0
Reference Clock Source
MCLK (Default)
RXCKI
0
0
1
1
0
1
0
1
RXCKO
Reserved
MUTE
SRC Output Soft Mute Function
This bit enables or disables the SRC output soft mute function.
MUTE
Mute Function
0
1
Mute Disabled (Default)
Mute enabled; output data set to all zeros.
TRACK
SRC Digital Output Attenuation Tracking
This bit enables or disables left and right channel attenuation tracking.
TRACK
Output Attenuation Tracking
Tracking Disabled (Default)
0
The Left and Right channel attenuation is programmed separately using registers 0x30 and 0x31,
respectively.
Tracking Enabled
1
The Left channel attenuation setting is also used for the Right channel. The Right channel tracks the Left
channel setting.
Register 2E: SRC Control Register 2
Bit 7 (MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
IGRP0
0
AUTODEM
DEM1
DEM0
DDN
IGRP1
IGRP[1:0]
SRC Interpolation Filter Group Delay
These bits select the interpolation filter group delay by configuring the number of samples which are pre-buffered prior to the re-sampler
function.
IGRP1
IGRP0
Number of Samples Pre-Buffered
64 Samples (Default)
32 Samples
0
0
1
1
0
1
0
1
16 Samples
8 Samples
DDN
SRC Decimation Filter/Direct Down-Sampling Function
This bit selects the mode of the decimation function, either true decimation filter or direct down-sampling without filtering.
DDN
Decimation Function
Decimation Filter (Default)
Direct Down Sampling
0
1
Note: Direct down-sampling should only be used when the output sampling rate is higher than the input sampling rate. When the output
sampling rate is equal to or lower than the input sampling rate, the Decimation Filter must be used in order to avoid aliasing.
DEM[1:0]
Digital De-Emphasis Filter, Manual Configuration
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These bits are utilized to enable or disable the digital de-emphasis filter manually. The de-emphasis filter is intended to process 50/15μs
pre-emphasized audio material at the following input sampling rates:
DEM1
DEM0
De-Emphasis Filter Function
0
0
1
1
0
1
0
1
De-Emphasis Disabled (Default)
De-Emphasis Enabled for fS = 48kHz
De-Emphasis Enabled for fS = 44.1kHz
De-Emphasis Enabled for fS = 32kHz
Note: When the AUTODEM bit is set to 1, the setting of the DEM0 and DEM1 bits are ignored.
AUTODEM
Automatic De-Emphasis Configuration
This bit enables or disables the automatic de-emphasis function, which monitors the channel status bits from the DIR function block and
determines whether de-emphasis is enabled and for which sampling frequency. This function is valid for only 50/15μs pre-emphasized data
and one of the three supported sampling rates (32kHz, 44.1kHz, or 48kHz).
AUTODEM
Automatic De-Emphasis Function
Disabled (Default)
0
1
Enabled
Register 2F: SRC Control Register 3
Bit 7 (MSB)
OWL1
Bit 6
OWL0
Bit 5
0
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0 (LSB)
0
0
0
OWL[1:0]
SRC Output Word Length
These bits select the word length for the SRC output data. The word length reduction is performed by utilizing triangular PDF dithering.
OWL1
OWL0
SRC Output Word Length
24 Bits (Default)
20 Bits
0
0
1
1
0
1
0
1
18 Bits
16 Bits
Note: When the SRC is selected as the output data source for Port A or B and the data format for the port is set to Right-Justified, the
proper word length must be selected in the Port A or B control registers such that it matches the corresponding SRC output data word
length set by the OWL0 and OWL1 bits.
Register 30: SRC Control Register 4
Bit 7 (MSB)
AL7
Bit 6
AL6
Bit 5
AL5
Bit 4
Bit 3
Bit 2
AL2
Bit 1
AL1
Bit 0 (LSB)
AL0
AL4
AL3
These bits are utilized to configure the SRC digital output attenuation for the Left Channel when the TRACK bit in register 0x2D is set to 0. The attenuation
setting for the Left channel also applies to the Right channel when TRACK bit in register 0x2D is set to 1.
Output Attenuation (dB) = –N
נ
0.5, where N = AL[7:0]DEC .
Register 31: SRC Control Register 5
Bit 7 (MSB)
AR7
Bit 6
AR6
Bit 5
AR5
Bit 4
Bit 3
Bit 2
AR2
Bit 1
AR1
Bit 0 (LSB)
AR0
AR4
AR3
These bits are utilized to configure the SRC digital output attenuation for the Right Channel when the TRACK bit in register 0x2D is set to 0.
Output Attenuation (dB) = –N
נ
0.5, where N = AR[7:0]DEC .
Register 32: SRC Ratio Readback Register (Read-Only)
Bit 7 (MSB)
SRI4
Bit 6
SRI3
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
SRF8
SRI2
SRI1
SRI0
SRF10
SRF9
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Register 33: SRC Ratio Readback Register (Read-Only)
Bit 7 (MSB)
SRF7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
SRF0
SRF6
SRF5
SRF4
SRF3
SRF2
SRF1
SRI[4:0]
Integer Part of the Input-to-Output Sampling Ratio
Fractional Part of the Input-to-Output Sampling Ratio
SRF[10:0]
In order to properly read back the ratio, these registers must be read back in sequence, starting with register 0x32.
Register 7F: Page Selection Register
Bit 7 (MSB)
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
PAGE0
0
0
0
0
PAGE1
PAGE[1:0]
Page Selection
These bits are utilized to select one of three register pages for write and/or read access via the SPI or I2C serial host interface. The Page
Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.
PAGE1
PAGE0
Register/Buffer Page Selection
0
0
1
1
0
1
0
1
Page 0, Control and Status Registers (Default)
Page 1, DIR Channel Status and User Data Buffers
Page 2, DIT Channel Status and User Data Buffers
Page 3, Reserved
CHANNEL STATUS AND USER DATA BUFFER MAPS
Table 5 through Table 8 show the buffer maps for the DIR and DIT channel status and user data buffers.
For Table 5, the channel status byte definitions are dependent on the transmission mode, either Professional or
Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode.
This is applicable for Table 5 and Table 6.
For Table 7, the channel status byte definitions are dependent on the transmission mode, either Professional or
Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In
Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and
encoded by the DIT. There is no need to program Byte 23 for either channel in Professional mode.
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Table 5. DIR Channel Status Data Buffer Map (Register Page 1)
ADDRESS
(Hex)
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
0
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
2
1
3
1
4
2
5
2
6
3
7
3
8
4
9
4
A
5
B
5
C
6
D
6
E
7
F
7
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
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Table 6. DIR User Data Buffer Map (Register Page 1)
ADDRESS
(Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
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SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
Table 7. DIT Channel Status Data Buffer Map (Register Page 2)
ADDRESS
(Hex)
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
0
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
2
1
3
1
4
2
5
2
6
3
7
3
8
4
9
4
A
5
B
5
C
6
D
6
E
7
F
7
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
74
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Product Folder Link(s): SRC4382
SRC4382
www.ti.com
SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
Table 8. DIT User Data Buffer Map (Register Page 2)
ADDRESS
(Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
CHANNEL
BYTE
0
BIT 0 (MSB)
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
BIT 1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
BIT 2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
BIT 3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
BIT 4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
BIT 5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
BIT 6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
BIT 7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Copyright © 2006–2007, Texas Instruments Incorporated
Submit Documentation Feedback
75
Product Folder Link(s): SRC4382
SRC4382
www.ti.com
SBFS030C–JANUARY 2006–REVISED SEPTEMBER 2007
REFERENCE DOCUMENTS
Throughout this data sheet, various standards and documents are repeatedly cited as references. Sources for
these documents are listed here so that the reader may obtain the documents for further study.
Audio Engineering Society (AES) standards documents, including the AES3, AES11, AES18, and related
specifications are available from the AES web site: http://www.aes.org.
International Electrotechnical Committee (IEC) standards, including the IEC60958 and IEC61937 are available
from the IEC web site: http://www.iec.ch; or the ANSI web site: http://www.ansi.org.
The EIAJ CP-1212 (formerly CP-1201) standard is available from the Japanese Electronics and Information
Technologies Industries Association (JEITA): http://www.jeita.or.jp/english.
The Philips I2C bus specification is available from Philips: http://www.philips.com.The version utilized as a
reference for this product is Version 2.1, published in January 2000.
Several papers regarding balanced and unbalanced transformer-coupled digital audio interfaces have been
published and presented at past AES conventions by Jon D. Paul of Scientific Conversion, Inc. These papers are
available for download from: http://www.scientificonversion.com.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REV
PAGE
—
SECTION
—
DESCRIPTION
Changed from Product Preview to Production Data.
Corrected spelling of Typical.
12
Typical Characteristics
Product Overview,
35
Asynchronous Sample Rate
Converter Operation
Figure 74: Corrected alignment of text.
Product Overview,
Interrupt Output
Figure 79: Changed reference to multiple SRC4392 devices.
Corrected spelling error.
40
45
Applications Information,
Receiver Input Interfacing
Figure 85, Figure 86: Corrected spelling errors.
4/06
B
Applications Information,
Transmitter Output
Interfacing
Figure 89, Figure 90: Corrected spelling errors.
Figure 90: Renamed Optical Receiver block to Optical
Transmitter.
47
Changed wording in paragraph describing Control Registers
to accurately explain which register addresses are reserved
for factory or future use.
Applications Information,
Control Registers
49
Corrected punctuation errors: AES3-encoded,
transformer-coupled.
Global
—
Changes from Revision B (April 2006) to Revision C .................................................................................................... Page
•
Added U.S. patent number to front page............................................................................................................................... 1
76
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Product Folder Link(s): SRC4382
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SRC4382IPFB
SRC4382IPFBG4
SRC4382IPFBR
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
SRC4382I
NIPDAU
NIPDAU
SRC4382I
SRC4382I
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SRC4382IPFBR
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PFB 48
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
SRC4382IPFBR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
SRC4382IPFB
PFB
PFB
TQFP
TQFP
48
48
250
250
10 x 25
10 x 25
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
SRC4382IPFBG4
Pack Materials-Page 3
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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Copyright © 2023, Texas Instruments Incorporated
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