TAS2505TRGERQ1_技术文档

TAS2505-Q1

ZHCSGI2D –JULY 2017 –REVISED JUNE 2023

TAS2505-Q1 具有音频处理功能的2.6W 数字/模拟输入车载D 类扬声器放大器

1 特性

3 说明

• 符合AEC-Q100 标准，其中包括以下适用于汽车应

用的内容：

– 器件温度等级2：-40°C 至105°C 环境运行温度

范围

– 器件HBM ESD 分类等级H2

– 器件CDM ESD 分类等级C4B

• 单声道D 类BTL 扬声器放大器

TAS2505-Q1 是一款支持数字和模拟输入的单声道 D

类扬声器放大器。该器件非常适用于汽车仪表组、紧急

呼叫 (eCall) 和远程信息处理应用。直接 I²S 输入免除

了音频信号路径对外部 DAC 的需求，集成式 LDO 则

支持单电源供电。除了集成之外，该器件还具有可编程

音频处理功能。板载 DSP 支持低音增强、高音和 EQ

（多达 6 个二阶滤波器）。片上 PLL 提供 DSP 所需

的高速时钟。音量由寄存器控制。

– 10% THD_N 时的功率为2.6W（4Ω，5.5V）

– 10% THD+N 时功率为1.7W（8Ω，5.5V）

• 支持数字和模拟输入

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

VQFN (24)

• 2.7V 至5.5V 单电源

TAS2505-Q1

4.00mm × 4.00mm

• 负载诊断功能：

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 输出至GND 短路

– 终端至终端短路

– 输出至电源短路

AINR

0

dB to -78 dB and Mute

(Min 0.5 dB steps)

– 过热

AINL

0

dB to -78 dB

and Mute

(Min 0.5 dB steps)

6

dB to +24 dB

(6 dB steps)

• 支持9kHz 至96kHz 的采样率

• 具有输出混合和电平控制功能的两个单端输入

• 嵌入式上电复位

SPKP

SPKM

Dig

Vol

Mono S-D

DAC

DAC Signal Proc.

S

• 可编程数字音频处理：

– 低音增强

– 高音

– EQ（多达6 个二阶滤波器）

• I²S，左平衡，右平衡，数字信号处理器(DSP) 和

时分复用(TDM) 音频接口

• 支持自动递增的I²C 和SPI 控制

• 24 引脚VQFN 可润湿侧翼（汽车级）封装

POR

LDO

LDO_SEL

SPKVDD

AVDD

DVDD

IOVDD

PLL

Interrupt

Control

SPI/I²

Control Block

C

Secondary I²

Interface

S

Primary I²

Interface

S

SPI_SEL

RST

SPKVSS

AVSS

Pin Muxing

/

Clock Routing

DVSS

MISO

2 应用

• 仪表组

• 自动紧急呼叫(eCall)

• 远程信息处理

简化版方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEI9

TAS2505-Q1

ZHCSGI2D –JULY 2017 –REVISED JUNE 2023

www.ti.com.cn

Table of Contents

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................17

8.5 Register Map.............................................................21

9 Application and Implementation..................................24

9.1 Application Information............................................. 24

9.2 Typical Applications.................................................. 24

10 Power Supply Recommendations..............................27

11 Layout...........................................................................28

11.1 Layout Guidelines................................................... 28

11.2 Layout Example...................................................... 28

11.3 Thermal Pad............................................................29

12 Device and Documentation Support..........................30

12.1 Documentation Support.......................................... 30

12.2 Receiving Notification of Documentation Updates..30

12.3 Community Resources............................................30

12.4 Trademarks.............................................................30

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 I²S/LJF/RJF Timing in Master Mode...........................8

6.7 I²S/LJF/RJF Timing in Slave Mode.............................8

6.8 DSP Timing in Master Mode....................................... 8

6.9 DSP Timing in Slave Mode......................................... 8

6.10 I²C Interface Timing.................................................. 9

6.11 SPI Interface Timing..................................................9

6.12 Typical Characteristics............................................12

7 Parameter Measurement Information..........................14

8 Detailed Description......................................................15

Information.................................................................... 30

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (February 2022) to Revision D (June 2023)

Page

• Errata in RevC datasheet with the LDO_SEL feature fixed................................................................................3

Changes from Revision B (October 2018) to Revision C (February 2022)

Page

• 调整了“特性”部分中的温度等级，使之与“建议运行条件”中的温度等级相匹配..........................................1

Changes from Revision A (December 2017) to Revision B (October 2018)

Page

• Added the Thermal Pad section....................................................................................................................... 29

Changes from Revision * (July 2017) to Revision A (December 2017)

Page

• 添加了 AEC 分类等级.........................................................................................................................................1

• 在封装特性中添加了“可润湿侧翼（汽车级）”说明.........................................................................................1

English Data Sheet: SLASEI9

2

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5 Pin Configuration and Functions

SPI_SEL

RST

1

2

3

4

5

6

18

17

16

15

14

13

GPIO/DOUT

MISO

AINL

MCLK

BCLK

Thermal

Pad

AINR

NC

WCLK

DIN

AVSS

Not to scale

图5-1. RGE Package 24-Pin VQFN Top View

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

1

NAME

SPI_SEL

RST

I

Selects between SPI and I²C digital interface modes; (1 = SPI mode) (0 = I²C mode)

Reset for logic, state machines, and digital filters; asserted LOW.

Analog single-ended line left input

2

I

3

AINL

I

4

AINR

I

Analog single-ended line right input

5

NC

O

No Connect (Leave unconnected)

6

AVSS

GND

Analog Ground, 0 V

7

AVDD

LDO_SEL

SPKM

SPKVDD

SPKVSS

SPKP

DIN

PWR

Analog Core Supply Voltage, 1.5 V to 1.95 V, tied internally to the LDO output

Select Pin for LDO; ties to either SPKVDD or SPKVSS

Class-D speaker driver inverting output

8

I

9

O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

PWR

Class-D speaker driver power supply

PWR

Class-D speaker driver power supply ground supply

Class-D speaker driver noninverting output

Audio Serial Data Bus Input Data

O

I

WCLK

BCLK

I/O

Audio Serial Data Bus Word Clock

I/O

Audio Serial Data Bus Bit Clock

MCLK

MISO

I

Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)

SPI Serial Data Output

O

GPIO/DOUT

SCL/SSZ

SDA/MOSI

SCLK

I/O/Z

GPIO / Audio Serial Bus Output

I

Either I²C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state

Either I²C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.

Serial clock for SPI interface

I

IOVDD

PWR

I/O Power Supply, 1.1 V to 3.6 V

DVDD

Digital Power Supply, 1.65 V to 1.95 V

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English Data Sheet: SLASEI9

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ZHCSGI2D –JULY 2017 –REVISED JUNE 2023

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表5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

24

DVSS

GND

Digital Ground, 0 V

(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance

English Data Sheet: SLASEI9

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

MAX

UNIT

V

AVDD to AVSS

2.2

DVDD to DVSS

2.2

V

–0.3

SPKVDD to SPKVSS

6

3.9

V

–0.3

IOVDD to IOVSS

V

–0.3

Digital input voltage

IOVDD + 0.3

AVDD + 0.3

105

V

IOVSS –0.3

AVSS –0.3

–40

Analog input voltage

V

Operating temperature

°C

W

°C

Junction temperature, T_JMax

Power dissipation for VQFN package (with thermal pad soldered to board)

Storage temperature, T_stg

125

(T_JMax –T_A) / θ_JA

150

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.5

1.65

2.7

1.1

4

NOM

1.8

MAX

1.95

5.5

UNIT

AVDD⁽²⁾

DVDD

Referenced to AVSS⁽¹⁾

Referenced to DVSS⁽¹⁾

Referenced to SPKVSS⁽¹⁾

Referenced to IOVSS⁽¹⁾

1.8

Power-supply voltage

Speaker impedance

V

SPKVDD⁽²⁾

IOVDD

1.8

0.5

3.6

Load applied across class-D output pins (BTL)

Ω

Analog audio full-scale input

voltage

V_I

AVDD = 1.8 V, single-ended

IOVDD = DVDD = 1.8 V

V_RMS

MCLK⁽³⁾

SCL

Master clock frequency

SCL clock frequency

50

400

105

MHz

kHz

°C

T_A

Operating free-air temperature

–40

(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground

signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.

(2) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.

(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.

6.4 Thermal Information

TAS2505-Q1

THERMAL METRIC⁽¹⁾

RGE (QFN)

24 PINS

32.2

UNIT

Junction-to-ambient thermal resistance

°C/W

θ_JA

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UNIT

TAS2505-Q1

THERMAL METRIC⁽¹⁾

RGE (QFN)

24 PINS

30

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

θ_JCtop

θ_JB

9.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JT

9.2

ψ_JB

2.2

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, f_S(audio) = 48 kHz, CODEC_CLKIN = 256 × f_S,

PLL = Off

PARAMETER

INTERNAL OSCILLATOR—RC_CLK

Oscillator frequency

TEST CONDITIONS

MIN

TYP

MAX UNIT

8.48

MHz

DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS

See TAS2505 Application Reference Guide (SLAU472) for DAC interpolation filter characteristics.

DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω(DIFFERENTIAL)

BTL measurement, class-D gain = 6 dB, Measured

ICN

Idle channel noise

37

1.4

μVms

Vrms

dB

as idle-channel noise, A-weighted^{(2) (1)}

BTL measurement, class-D gain = 6 dB, –3-dBFS

input

Output voltage

BTL measurement, DAC input = –6 dBFS, class-D

gain = 6 dB

THD+N

PSRR

Total harmonic distortion + noise

–73.9

BTL measurement, ripple on SPKVDD = 200 mV_PP

at 1 kHz

Power-supply rejection ratio

Mute attenuation

55

103

1.1

dB

Mute

SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,

class-D gain = 18 dB, THD = 10%

SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 10%

1.4

0.8

1.1

SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,

class-D gain = 18 dB, THD = 1%

P_O

Maximum output power

W

SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,

class-D gain = 18 dB, THD = 1%

SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,

class-D gain = 18 dB

2

DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)

BTL measurement, class-D gain = 6 dB, measured

as idle-channel noise, A-weighted^{(2) (1)}

ICN

Idle channel noise

35.2

1.4

μVms

Vrms

dB

BTL measurement, class-D gain = 6 dB, –3-dBFS

input

Output voltage

BTL measurement, DAC input = –6 dBFS, class-D

gain = 6 dB

THD+N

Total harmonic distortion + noise

–73.6

English Data Sheet: SLASEI9

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At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, f_S(audio) = 48 kHz, CODEC_CLKIN = 256 × f_S,

PLL = Off

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 10%

0.7

SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 10%

1

1.7

0.5

0.8

1.3

SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 10%

P_O

Maximum output power

W

SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 1%

SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 1%

SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,

class-D gain = 18 dB, THD = 1%

ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER

Device setup

BTL measurement, driver gain = 6 dB, load = 4 Ω

(differential), 50 pF, input signal frequency fi = 1

KHz

Voltage gain

Gain error

Input common-mode = 0.9 V

4

V/V

dB

±0.7

–1 dBFS (446 mVrms), 1-kHz input signal

Idle channel, IN1L and IN1R ac-shorted to ground,

measured as idle-channel noise, A-weighted^{(2) (1)}

ICN

Idle channel noise

32.6

μVms

THD+N

Total harmonic distortion + noise

dB

–1 dBFS (446 mVrms), 1-kHz input signal

–73.7

SHUTDOWN POWER CONSUMPTION

Power down POR, /RST held low, AVDD = 1.8V,

IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V

Device setup

I(AVDD)

I(DVDD)

1.32

0.04

0.68

2.24

µA

I(IOVDD)

I(SPKVDD)

DIGITAL INPUT/OUTPUT

Logic family

CMOS

0.7 ×

IOVDD

I_IH= 5 μA, IOVDD ≥1.6 V

I_IH= 5 μA, IOVDD < 1.6 V

I_IL= 5 μA, IOVDD ≥1.6 V

I_IL= 5 μA, IOVDD < 1.6 V

I_OH= 2 TTL loads

V_IH

V

IOVDD

0.3 ×

–0.3

IOVDD

Logic level

V_IL

V

0

0.8 ×

IOVDD

V_OH

V_OL

I_OL= 2 TTL loads

0.25

V

Capacitive load

10

pF

(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(2) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over

a 20-Hz to 20-kHz bandwidth using an audio analyzer.

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6.6 I²S/LJF/RJF Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

PARAMETER

IOVDD = 1.8 V

IOVDD = 3.3 V

UNIT

MIN

MAX

MIN

MAX

45

t_d(WS)

t_s(DI)

t_h(DI)

t_r

WCLK delay

DIN setup

DIN hold

45

ns

8

6

Rise time

Fall time

25

10

t_f

(1) ll timing specifications are measured at characterization but not tested at final test.

6.7 I²S/LJF/RJF Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

IOVDD = 1.8 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

35

8

MAX

MIN

35

6

MAX

t_H(BCLK)

t_L(BCLK)

t_s(WS)

t_h(WS)

t_s(DI)

t_h(DI)

t_r

BCLK high period

BCLK low period

WCLK setup

WCLK hold

DIN setup

ns

8

6

8

6

DIN hold

8

6

Rise time

4

t_f

Fall time

(1) All timing specifications are measured at characterization but not tested at final test.

6.8 DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

IOVDD = 1.8 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

t_d(WS)

t_s(DI)

t_h(DI)

t_r

WCLK delay

DIN setup

DIN hold

45

ns

8

6

Rise time

Fall time

25

10

t_f

(1) All timing specifications are measured at characterization but not tested at final test.

6.9 DSP Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

IOVDD = 1.8V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

35

8

MAX

MIN

35

8

MAX

t_H(BCLK)

t_L(BCLK)

t_s(WS)

t_h(WS)

t_s(DI)

BCLK high period

BCLK low period

WCLK setup

WCLK hold

DIN setup

ns

8

t_h(DI)

DIN hold

8

t_r

Rise time

4

English Data Sheet: SLASEI9

8

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All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

PARAMETER

IOVDD = 1.8V

IOVDD = 3.3 V

MIN MAX

UNIT

MIN

MAX

t_f

Fall time

4

ns

(1) All timing specifications are measured at characterization but not tested at final test.

6.10 I²C Interface Timing

All specifications at 25°C, DVDD = 1.8 V⁽¹⁾

PARAMETER

STANDARD MODE

FAST MODE

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

f_SCL

SCL clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD;STA

4

0.8

μs

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

Setup time for a repeated START condition

Data hold time for I²C bus devices

Data setup time

4.7

4

1.3

0.6

0.8

0

μs

ns

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

4.7

0

3.45

0.9

250

100

SDA and SCL rise time

1000

300

20 + 0.1 C_b

0.8

300

ns

t_f

SDA and SCL fall time

ns

t_SU;STO

Set-up time for STOP condition

4

μs

Bus free time between a STOP and

START condition

t_BUF

C_b

4.7

1.3

μs

Capacitive load for each bus line

400

pF

(1) All timing specifications are measured at characterization but not tested at final test.

6.11 SPI Interface Timing

At 25°C, DVDD = 1.8V

PARAMETER

TEST CONDITION

IOVDD=1.8V

MIN TYP MAX

IOVDD=3.3V

MIN TYP

UNIT

MAX

t_sck

t_sckh

t_sckl

t_lead

t_lag

t_d

SCLK period ⁽¹⁾

100

50

30

40

50

25

20

ns

SCLK pulse width High

SCLK pulse width Low

Enable lead time

Enable lag time

Sequential transfer delay

Slave DOUT access time

Slave DOUT disable time

DIN data setup time

DIN data hold time

t_a

40

t_dis

t_su

15

10

t_hi

t_v;DOUTDOUT data valid time

25

4

18

4

t_r

t_f

SCLK rise time

SCLK fall time

4

(1) These parameters are based on characterization and are not tested in production.

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WCLK

t_d(WS)

t_r

BCLK

t_f

t_S(DI)

t_h(DI)

DIN

T0145-10

图6-1. I²S/LJF/RJF Timing in Master Mode

WCLK

BCLK

DIN

t_h(WS)

t_r

t_H(BCLK)

t_S(WS)

t_L(BCLK)

t_S(DI)

t_f

t_h(DI)

T0145-11

图6-2. I²S/LJF/RJF Timing in Slave Mode

WCLK

BCLK

DIN

t_d(WS)

t_f

t_S(DI)

t_r

t_h(DI)

T0146-09

图6-3. DSP Timing in Master Mode

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WCLK

t_S(WS)

t_h(WS)

t_S(WS)

t_h(WS)

t_L(BCLK)

t_f

BCLK

t_H(BCLK)

t_S(DI)

t_r

DIN

t_h(DI)

T0146-10

图6-4. DSP Timing in Slave Mode

SDA

t_BUF

t_LOW

t_HIGH

t_f

t_HD;STA

t_r

SCL

t_HD;STA

t_SU;DAT

t_HD;DAT

t_SU;STO

t_SU;STA

STO

STA

STO

T0295-02

图6-5. I²C Interface Timing

SS

S

t

td

t_Lag

t

t_Lead

sck

t_f

t_r

SCLK

MISO

t_sckl

t_sckh

t_v(DOUT)

t_dis

MSB OUT

t_h(DIN)

BIT 6 . . . 1

LSB OUT

t

a

t_su

MOSI

MSB IN

BIT 6 . . . 1

LSB IN

图6-6. SPI Interface Timing Diagram

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6.12 Typical Characteristics

6.12.1 Class D Speaker Driver Performance

20

0

20

0

œ20

œ40

œ60

œ80

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

0

4000

8000

12000

16000

20000

0

4000

8000

12000

16000

20000

C001

C002

Frequency (Hz)

(4-ΩLoad)

图6-7. DAC To Speaker Amplitude at 0 dBFS vs

图6-8. AINL To Speaker FFT Amplitude at 0 dBFS

Frequency

vs Frequency

100

100.00

10.00

1.00

Gain = 6 dB

Gain = 12 dB

Gain = 18 dB

10

1

Gain = 24 dB

SPKVDD=2.7V

Series1

SPKVDD=3V

Series2

SPKVDD=3.3V

Series4

SPKVDD=3.6V

Series5

SPKVDD=4.2V

Series6

SPKVDD=5.5V

Series7

0.1

0.01

0.10

0.01

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

2.5

3

C003

C004

Output Power (W)

(SPKVDD = 5.5 V)

(Gain = 18 dB)

图6-9. Total Harmonic Distortion + Noise vs 4-Ω 图6-10. Total Harmonic Distortion + Noise + NOISE

Speaker Power

vs 4-ΩSpeaker Power

100.00

10.00

1.00

100

Gain = 6 dB

Series1

^GS^aieⁿr⁼ie¹²s2^dB

^GS^aieⁿr⁼ie¹⁸s4^dB

^GS^aieⁿr⁼ie²⁴s5^dB

10

1

SPKVDD = 2.7 V

Series1

^SPKS^VDe^Dri⁼e³s2^V

^SPKS^VDe^Dri⁼e³s^.4^{3 V}

^SPKS^VDe^Dri⁼e³s^.5^{6 V}

^SPKS^VDe^Dri⁼e⁴s^.6^{2 V}

^SPKS^VDe^Dri⁼e⁵s^.7^{5 V}

0.10

0.1

0.01

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

C005

C006

Output Power (W)

(SPKVDD = 5.5 V)

(Gain = 18 dB)

图6-11. Total Harmonic Distortion + Noise + NOISE 图6-12. Total Harmonic Distortion + Noise + NOISE

vs 8-ΩSpeaker Power

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90

80

70

60

50

40

30

20

10

0

SPKVDD = 2.7 V

SPKVDD = 3 V

SPKVDD = 3.3 V

SPKVDD = 3.6 V

SPKVDD = 4.2 V

SPKVDD = 5.5 V

0

200 400 600 800 1000 1200 1400 1600 1800

C007

Output Power (mWatt)

(Gain = 18 dB, Load = 4 Ω)

图6-13. Total Power Consumption vs Output Power Consumption

6.12.2 HP Driver Performance

20

0

20

0

œ20

œ40

œ60

œ80

0dBFS

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

0

4000

8000

12000

16000

20000

0

4000

8000

12000

16000

20000

C008

Frequency (Hz)

(16-ΩLoad)

图6-14. DAC TO HP FFT Amplitude at 0 dBFS vs

图6-15. AINL TO HP FFT Amplitude at 0 dBFS vs

Frequency

0

œ10

œ20

œ30

œ40

0

œ10

œ20

œ30

œ40

^CS^M=e⁰r^.i⁷e⁵s^V1^,

AVDD=1.5V

CM=0.75V,AVDD=1.5V

œ50

^CS^M=e⁰r^.i⁷e⁵s^V2^,

AVDD=1.8V

CM=0.75V,AVDD=1.8V

œ60

^CS^M=e⁰r^.i⁷e⁵s^V4^,

AVDD=1.95V

CM=0.75V,AVDD=1.95V

œ70

^CS^M=e⁰r^.i⁹e^Vs^,5

CM=0.9V,AVDD=1.8V

AVDD=1.8V

œ80

CM=0.9V,AVDD=1.95V

^CS^M=e⁰r^.i⁹e^Vs^,6

AVDD=1.95V

œ90

0.0

5.0

10.0 15.0 20.0 25.0 30.0 35.0 40.0

0.0

5.0

10.0

15.0

20.0

25.0

C010

C011

Output Power (mW)

(Gain = 9 dB)

(Gain = 32 dB)

图6-16. Total Harmonic Distortion + Noise vs HP

图6-17. Total Harmonic Distortion + Noise vs HP

Power

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7 Parameter Measurement Information

All parameters are measured according to the conditions described in the 节6 section.

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8 Detailed Description

8.1 Overview

TAS2505-Q1 is a low power analog and digital input class-D speaker amplifier. It supports 24-bit digital I2S data

for mono playback. This device is able to drive a speaker up to 4 Ω and programmable digital-signal processing

block. The programmable digital-signal processing block can support Bass boost, treble or EQ functions. The

volume level can be controlled by register control. The device can be controlled through I²C or SPI bus.

TAS2505-Q1 also includes an on-board LDO that runs off the speaker power supply to handle all internal device

analog and digital power needs. The device also includes two analog inputs for mixing in speaker path.

8.2 Functional Block Diagram

AINR

0 dB to -78 dB and Mute

(Min 0.5 dB steps)

AINL

0 dB to -78 dB

6 dB to +24 dB

and Mute

(6 dB steps)

(Min 0.5 dB steps)

SPKP

Dig

Vol

Mono S-D

DAC

DAC Signal Proc.

S

SPKM

POR

LDO

LDO_SEL

SPKVDD

AVDD

DVDD

IOVDD

PLL

Interrupt

Control

SPI/I²C

Control Block

Secondary I²S

Interface

Primary I²S

Interface

SPI_SEL

RST

SPKVSS

AVSS

Pin Muxing / Clock Routing

DVSS

MISO

8.3 Feature Description

8.3.1 Audio Analog I/O

The TAS2505-Q1 features a mono audio DAC. TheTAS2505 can drive a speaker up to 4-Ω impedance.

8.3.2 Audio DAC and Audio Analog Outputs

The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital delta-

sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is between 32

and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma

modulator stays outside of the audio frequency band. Audio analog outputs include mono class-D speaker

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outputs. Because the TAS2505-Q1 contains a mono DAC, it inputs the mono data from the left channel, the right

channel, or a mix of the left and right channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.3.3 DAC

The TAS2505-Q1 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the mono

DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multibit

digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced

performance at low sampling rates through increased oversampling and image filtering, thereby keeping

quantization noise generated within the delta-sigma modulator and observed in the signal images strongly

suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power

dissipation and performance, the TAS2505-Q1 allows the system designer to program the oversampling rates

over a wide range from 1 to 1024 by configuring page 0, register 13 and page 0 / register 14. The system

designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for

higher input data rates.

The TAS2505-Q1 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the

delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required

frequency response, group delay, and sampling rate.

The DAC path of the TAS2505-Q1 features many options for signal conditioning and signal routing:

• Digital volume control with a range of –63.5 to +24 dB

• Mute function

In addition to the standard set of DAC features the TAS2505-Q1 also offers the following special features:

• Digital auto mute

• Adaptive filter mode

8.3.4 POR

TAS2505-Q1 has a POR (Power-On-Reset) function. This function insures that all registers are automatically set

to defaults when a proper power up sequence is executed.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.3.5 CLOCK Generation and PLL

The TAS2505-Q1 supports a wide range of options for generating clocks for the DAC sections as well as

interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can be

provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference clock for the

codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits D1–D0. The

CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in Figure 2 through 7 in the

TAS2505 Application Reference Guide to generate the various clocks required for the DAC and the Digital

Effects section also found in the TAS2505 Application Reference Guide (SLAU472). In the event that the desired

audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2505-Q1 also

provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to

generate the required clocks. Starting from CODEC_CLKIN, the TAS2505-Q1 provides several programmable

clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the Digital Effects sections.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.3.6 Speaker Driver

The TAS2505-Q1 has an integrated class-D mono speaker driver (SPKP/SPKM) capable of driving an 8-Ω or 4-

Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the

SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolute maximum

voltage of 6 V. The speaker driver is capable of supplying 800 mW per channel with a 3.6-V power supply.

Through the use of digital mixing, the device can connect one or both digital audio playback data channels to

either speaker driver; this also allows digital channel swapping if needed. The class-D speaker driver can be

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powered on by writing to page 1, register 45, bit D1. The class-D output-driver gain can be controlled by writing

to page 1, register 48, bits D6–D4, and it can be muted by writing to page 1, register 48, bit D6 - D4 = 000.

8.3.7 Automotive Diagnostics

The TAS2505-Q1 has SHORT-CIRCUIT PROTECTION /OVER CURRENT PROTECTION (OCP) feature for the

speaker drivers that is always enabled to provide protection. This protects outputs against short to ground,

short to supply and short between output terminals. The output stage shuts down on the over current

condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In case

of a short circuit, the output is disabled. A status flag for OC condition occurrence is provided as a read-

only bit on page 1, register 45, bit D1. The D1 bit is cleared when any of the above short circuit condition

happens. If shutdown occurs due to an over current condition, then the device requires a reset to re-enable the

output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires

either toggling the RST pin or using the software reset. If master reset is used, it resets all of the registers.

Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The

speaker power-stage reset is done by setting page 1, register 45, bit D1 for SPKP and SPKM. If the fault

condition has been removed, then the device returns to normal operation. If the fault is still present, then another

shutdown occurs. Repeated resetting (more than three times) is not recommended, as this could lead to

overheating. To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD

voltage level.

The TAS2505 has a OVER TEMPERATURE PROTECTION (OTP) feature for the speaker driver which is

always enabled to provide protection. If the device is overheated, then the output stops switching. When the

device cools down, the output resumes switching. An over temperature status flag is provided as a read-

only bit on page 0, register 45, bit D7. The OTP feature is for self-protection of the device. If die temperature

can be controlled at the system/board level, then over temperature does not occur.

8.4 Device Functional Modes

8.4.1 Digital Pins

Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a

default function, and also can be reprogrammed to cover alternative functions for various applications.

The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending on the

state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I²C or SPI

protocol.

Other digital IO pins can be configured for various functions through register control. An overview of available

functionality is given in 节8.4.3.

8.4.2 Analog Pins

Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are

powered down by default. The blocks can be powered up with fine granularity according to the application

needs.

8.4.3 Multifunction Pins

表 8-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be

programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

表8-1. Multifunction Pin Assignments

1

2

3

4

5

6

7

PIN FUNCTION

MCLK

BCLK

WCLK

DIN

GPIO

SCLK

MISO

/DOUT

A

B

C

D

PLL Input

S⁽²⁾

S⁽³⁾

E

S⁽⁴⁾

Codec Clock Input

I²S BCLK input

I²S BCLK output

S⁽²⁾,D⁽⁵⁾

S⁽³⁾,D

E⁽¹⁾

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表8-1. Multifunction Pin Assignments (continued)

1

2

3

4

5

6

7

PIN FUNCTION

MCLK

BCLK

WCLK

DIN

GPIO

SCLK

MISO

/DOUT

E

F

G

I

I²S WCLK input

E, D

E

I²S WCLK output

I²S DIN

E, D

E

General-Purpose Output I

General-Purpose Output II

General-Purpose Input I

General-Purpose Input II

General-Purpose Input III

INT1 output

E

I

E

J

E

K

L

M

N

O

P

Q

R

S

E

INT2 output

Secondary I²S BCLK input

Secondary I²S WCLK input

Secondary I²S DIN

E

Secondary I²S BCLK OUT

Secondary I²S WCLK OUT

Secondary I²S DOUT

Aux Clock Output

E

(1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been

allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)

(2) S⁽¹⁾: The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.

(3) S⁽²⁾: The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.

(4) S⁽³⁾: The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.

(5) D: Default Function

8.4.4 Analog Signals

The TAS2505-Q1 analog signals consist of:

• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output stages

• Analog outputs class-D speaker driver providing output capability for the DAC, AINR, AINL, or a mix of the

three

8.4.4.1 Analog Inputs AINL and AINR

AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output. Also

AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for

determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be attenuated by

Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of HP driver can be

attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural differential input with

use Mixer P and Mixer M by Page1 / register 12 setting.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.5 DAC Processing Blocks —Overview

The TAS2505-Q1 implements signal-processing capabilities and interpolation filtering through processing blocks.

These fixed processing blocks give users the choice of how much and what type of signal processing they may

use and which interpolation filter is applied.

The choices among these processing blocks allows the system designer to balance power conservation and

signal-processing flexibility. 表 8-2 gives an overview of all available processing blocks of the DAC channel and

their properties. The resource-class column gives an approximate indication of power consumption for the digital

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(DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the

drivers (AVDD) may differ.

The signal-processing blocks available are:

• First-order IIR

• Scalable number of biquad filters

The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in

combination with various signal-processing effects such as audio effects and frequency shaping. The available

first-order IIR and biquad filters have fully user-programmable coefficients.

表8-2. Overview –DAC Predefined Processing Blocks

PROCESSING

BLOCK NO.

INTERPOLATION

FILTER

FIRST-ORDER

IIR AVAILABLE

NUMBER OF RESOURCE

CHANNEL

BIQUADS

CLASS

PRB_P1

PRB_P2

PRB_P3

A

B

Mono

Yes

No

6

3

6

4

Yes

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.6 Digital Mixing and Routing

The TAS2505-Q1 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the

digital audio data. The first mixer or multiplexer can be used to select input data for the mono DAC from left

channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by

writing to page 0, register 63, bits D5–D4.

8.4.7 Analog Audio Routing

The TAS2505-Q1 has the capability to route the DAC output to the speaker output. If desirable, both output

drivers can be operated at the same time while playing at different volume levels. The TAS2505-Q1 provides

various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All

analog outputs other than the selected ones can be powered down for optimal power consumption.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.8 5V LDO

The TAS2505-Q1 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply

(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is 50 mA

or less, then this LDO can deliver power to both analog and digital power supplies. If the only speaker power

supply is present and LDO Select pin is enabled, the LDO can power up without requiring other supplies. This

LDO requires a minimum dropout voltage of 300 mV and can support load currents up to 50 mA. For stability

reasons the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the analog supply (AVDD) pin and

the digital supply (DVDD) pin. If use this LDO output voltage for the digital supply (DVDD) pin, the analog supply

(AVDD) pin connected to the digital supply (DVDD) externally is required.

The LDO is by default powered down for low sleep mode currents and can be enabled driving the LDO_SELECT

pin to SPKVDD (speaker power supply). When the LDO is disabled the AVDD pin is tri-stated and the device

AVDD needs to be powered using external supply. In that case the DVDD pin is also tri-stated and the device

DVDD needs to be powered using external supply. The output voltage of this LDO can be adjusted to a few

different values as given in the 表8-3.

表8-3. AVDD LDO Settings

Page-1, Register 2, D(5:4)

LDO Output

00

01

10

1.8 V

1.6 V

1.7 V

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表8-3. AVDD LDO Settings (continued)

Page-1, Register 2, D(5:4)

LDO Output

00

1.5 V

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.9 Digital Audio and Control Interface

8.4.9.1 Digital Audio Interface

Audio data is transferred between the host processor and the TAS2505-Q1 via the digital audio data serial

interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,

support for I²S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation,

flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple

devices within a system directly.

The audio bus of the TAS2505-Q1 can be configured for left- or right-justified, I²S, DSP, or TDM modes of

operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0,

register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either

master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define

the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of

this clock corresponds to the maximum of the selected DAC sampling frequencies.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.9.2 Control Interface

The TAS2505-Q1 control interface supports SPI or I²C communication protocols, with the protocol selectable

using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I²C, SPI_SEL should be tied low. TI does not

recommend changing the state of SPI_SEL during device operation.

8.4.9.2.1 I²C Control Mode

The TAS2505-Q1 supports the I²C control protocol, and will respond to the I²C address of 0011 000. I²C is a two-

wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only

drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus

wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This

way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

8.4.9.2.2 SPI Digital Interface

In the SPI control mode, the TAS2505-Q1 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO, SDA/

MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL

= 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master)

and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing

clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TAS2505-Q1) depend

on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The

byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock

(driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift

register.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

8.4.9.3 Device Special Functions

• Interrupt generation

• Flexible pin multiplexing

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

English Data Sheet: SLASEI9

20

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8.5 Register Map

表8-4. Summary of Register Map

Decimal

Hex

DESCRIPTION

PAGE NO. REG. NO.

0

0x00

0x01

Page Select Register

1

Software Reset Register

2 - 3

4

0x02 - 0x03 Reserved Registers

0x04

0x05

0x06

0x07

0x08

Clock Setting Register 1, Multiplexers

Clock Setting Register 2, PLL P and R Values

5

6

Clock Setting Register 3, PLL J Values

7

Clock Setting Register 4, PLL D Values (MSB)

Clock Setting Register 5, PLL D Values (LSB)

8

9 - 10

11

0x09 - 0x0A Reserved Registers

0x0B

0x0C

0x0D

0x0E

Clock Setting Register 6, NDAC Values

12

Clock Setting Register 7, MDAC Values

DAC OSR Setting Register 1, MSB Value

DAC OSR Setting Register 2, LSB Value

13

14

15 - 24

25

0x0F - 0x18 Reserved Registers

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

Clock Setting Register 10, Multiplexers

26

Clock Setting Register 11, CLKOUT M divider value

Audio Interface Setting Register 1

27

28

Audio Interface Setting Register 2, Data offset setting

Audio Interface Setting Register 3

29

30

Clock Setting Register 12, BCLK N Divider

Audio Interface Setting Register 4, Secondary Audio Interface

Audio Interface Setting Register 5

31

32

33

Audio Interface Setting Register 6

34

Reserved Register

35 - 36

37

0x23 - 0x24 Reserved Registers

0x25

DAC Flag Register 1

38

0x26

DAC Flag Register 2

39-41

42

0x27-0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

Reserved Registers

Sticky Flag Register 1

43

Interrupt Flag Register 1

Sticky Flag Register 2

44

45

Reserved Register

46

Interrupt Flag Register 2

Reserved Register

47

48

0x30

INT1 Interrupt Control Register

INT2 Interrupt Control Register

Reserved Registers

49

0x31

50-51

52

0x32-0x33

0x34

GPIO/DOUT Control Register

DOUT Function Control Register

DIN Function Control Register

MISO Function Control Register

SCLK/DMDIN2 Function Control Register

53

0x35

54

0x36

55

0x37

56

0x38

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表8-4. Summary of Register Map (continued)

Decimal

Hex

DESCRIPTION

PAGE NO. REG. NO.

0

57-59

60

0x00

0x01

0x39-0x3B Reserved Registers

0x3C DAC Instruction Set

0x3D -0x3E Reserved Registers

0

61 - 62

63

0

0x3F

0x40

0x41

DAC Channel Setup Register 1

0

64

DAC Channel Setup Register 2

0

65

DAC Channel Digital Volume Control Register

0

66 - 80

81

0x42 - 0x50 Reserved Registers

0x51 Dig_Mic Control Register

0x52 - 0x7F Reserved Registers

0

82 - 127

0

1

0x00

0x01

0x02

0x03

Page Select Register

1

REF, POR and LDO BGAP Control Register

LDO Control Register

1

2

1

3

Playback Configuration Register 1

1

4 - 7

8

0x04 - 0x07 Reserved Registers

1

0x08

0x09

0x0A

0x0B

0x0C

DAC PGA Control Register

1

9

Output Drivers, AINL, AINR, Control Register

Common Mode Control Register

1

10

1

11

HP Over Current Protection Configuration Register

HP Routing Selection Register

1

12

1

13 - 15

16

0x0D - 0x0F Reserved Registers

0x10 Reserved Registers

0x11 - 0x13 Reserved Registers

1

17 - 19

20

1

0x14

0x15

0x16

0x17

0x18

0x19

Reserved Registers

1

21

Reserved Register

1

22

Reserved Registers

1

23

Reserved Register

1

24

AINL Volume Control Register

AINR Volume Control Register

1

25

1

26 - 44

45

0x1A - 0x2C Reserved Registers

1

0x2D

0x2E

0x2F

0x30

Speaker Amplifier Control 1

1

46

Speaker Volume Control Register

Reserved Register

1

47

1

48

Speaker Amplifier Volume Control 2

1

49 - 62

64 - 121

122

123 - 127

0 - 127

0

0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register

0x40 - 0x79 Reserved Registers

1

0x7A

0x7B - 0x7F Reserved Registers

0x02 - 0x2B 0x00 - 0x7F Reserved Registers

Reference Power Up Delay

1

2 - 43

44

0x2C

0x00

0x01

Page Select Register

44

1

DAC Adaptive Filter Configuration Register

44

2 - 7

8 - 127

0

0x02 - 0x07 Reserved

44

0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)

45 - 52

0x2D-0x34 0x00

Page Select Register

1 - 7

0x2D-0x34 0x01 - 0x07 Reserved.

English Data Sheet: SLASEI9

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表8-4. Summary of Register Map (continued)

Decimal

PAGE NO. REG. NO.

Hex

DESCRIPTION

PAGE NO. REG. NO.

45 - 52

53 - 61

62 - 70

71 - 255

8 - 127

0 - 127

0

0x2D-0x34 0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)

0x35 - 0x3D 0x00 - 0x7F Reserved Registers

0x3E-0x46 0x00

Page Select Register

1 - 7

0x3E-0x46 0x01 - 0x07 Reserved Registers

8 - 127

0 - 127

0x3E-0x46 0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)

0x47 - 0x7F 0x00 - 0x7F Reserved Registers

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TAS2505-Q1 is a digital or analog input Class-D audio power amplifier. This device include an internal LDO

that can be used to supply the analog and digital internal supply rails. Below are shown different setups that

show the features of the TAS2505-Q1.

9.2 Typical Applications

9.2.1 Typical Configuration

+1.8VA

SVDD

IOVDD

0.1mF

22mF

0.1mF

22mF

2.7k

AVSS

AVDD

LDO_SEL

SPKVSS

SPKVDD

GPIO/DOUT

SDA/MOSI

SCL/SSZ

MCLK

8-W or

4-W

Speaker

SPKP

SPKM

WCLK

DIN

TAS2505

BCLK

Headphone jack

RST

HPOUT

0.1mF

47mF

AINL

AINR

MISO

Analog Input

SCLK

SPI_SEL

DVDD DVSS

IOVDD IOVSS

+1.8VD

0.1mF

IOVDD

10mF

0.1mF

图9-1. Typical Circuit Configuration

English Data Sheet: SLASEI9

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9.2.1.1 Design Requirements

表9-1 shows the design parameters.

表9-1. Design Parameters

PARAMETER

EXAMPLE VALUE

Audio input

Internal LDO

Speaker

Digital Audio (I²S), Analog Audio AINx

Not used

8-Ωor 4-Ω

9.2.1.2 Detailed Design Procedure

In this application, the device is able to use both digital and analog inputs, working in mono output by summing

left and right analog inputs and output from DAC and routing this signal into the speaker output.

The internal LDO is not used in this application becasuse the LDO_SEL pin is tied to GND. External 1.8-V supply

is used to power AVDD and DVDD. IOVDD can be supplied by voltages between 1.1 V and 3.6 V which lets the

system to use conventional 1.8-V or 3.3-V supplies. The SPKVDD can be connected to voltages between 2.7 V

and 5.5 V, although it is usually supplied by a 5-V voltage.

Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1-µF, 10-µF, and 22-µF

capacitors for a better system performance.

Decoupling series capacitors must be used at the analog input.

All grounds are tied together; route analog and digital paths are separated to avoid interference.

9.2.1.3 Application Curves

100

100.00

10.00

1.00

Gain = 6 dB

Gain = 12 dB

Gain = 18 dB

Gain = 24 dB

10

1

SPKVDD=2.7V

Series1

SPKVDD=3V

Series2

SPKVDD=3.3V

Series4

SPKVDD=3.6V

Series5

SPKVDD=4.2V

Series6

SPKVDD=5.5V

Series7

0.1

0.01

0.10

0.01

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

2.5

3

C003

C004

Output Power (W)

(SPKVDD = 5.5 V)

(Gain = 18 dB)

图9-2. Total Harmonic Distortion + Noise vs 4-Ω

图9-3. Total Harmonic Distortion + Noise vs 4-Ω

Speaker Power

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0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

CM=0.75V,AVDD=1.5V

CM=0.75V,AVDD=1.8V

CM=0.75V,AVDD=1.95V

CM=0.9V,AVDD=1.8V

CM=0.9V,AVDD=1.95V

0.0

5.0

10.0 15.0 20.0 25.0 30.0 35.0 40.0

C010

Output Power (mW)

(Gain = 9 dB)

图9-4. Total Harmonic Distortion + Noise vs HP Power

9.2.2 Circuit Configuration With Internal LDO

SVDD

IOVDD

0.1mF

22mF

10mF

0.1mF

22mF

2.7k

DVSS

AVDD

DVDD

AVSS

LDO_SEL SPKVSS

SPKVDD

GPIO/DOUT

SDA/MOSI

SCL/SSZ

MCLK

8-W or

4-W

Speaker

SPKP

SPKM

WCLK

DIN

TAS2505

BCLK

Headphone jack

RST

HPOUT

0.1mF

47mF

AINL

AINR

MISO

Analog Input

SCLK

SPI_SEL

IOVDD IOVSS

IOVDD

0.1mF

10mF

图9-5. Application Schematics for LDO

English Data Sheet: SLASEI9

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9.2.2.1 Design Requirements

表9-2 shows the design parameters.

表9-2. Design Parameters

PARAMETER

EXAMPLE VALUE

Audio input

Internal LDO

Speaker

Digital Audio (I²S), Analog Audio AINx

Used

8-Ωor 4-Ω

10 Power Supply Recommendations

The TAS2505-Q1 integrates a large amount of digital and analog functionality, and each of these blocks can be

powered separately to enable the system to select appropriate power supplies for desired performance and

power consumption. The device has separate power domains for digital IO, digital core, analog core, analog

input and speaker drivers. If desired, all of the supplies (except for the supplies for speaker drivers, which can

directly connect to the battery) can be connected together and be supplied from one source in the range of 1.65

to 1.95 V. Individually, the IOVDD voltage can be supplied in the range of 1.1 V to 3.6 V. For improved power

efficiency, the digital core power supply can range from 1.26 V to 1.95 V. The analog core supply can either be

derived from the internal LDO accepting an SPKVDD voltage in the range of 2.7V to 5.5V or the AVDD pin can

directly be driven with a voltage in the range of 1.5 V to 1.95 V. The speaker driver voltages (SPKVDD) can

range from 2.7 V to 5.5 V.

For more detailed information see the TAS2505 Application Reference Guide (SLAU472).

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11 Layout

11.1 Layout Guidelines

• If the analog input, AINR and AINL, are:

– Used, analog input traces must be routed symmetrically for true differential performance.

– Used, do not run analog input traces parallel to digital lines.

– Used, they must be AC-coupled.

– Not used, they must be shorted together.

• Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for

minimum ground noise.

• Use supply decoupling capacitors.

11.2 Layout Example

图11-1. Layout Diagram

English Data Sheet: SLASEI9

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11.3 Thermal Pad

Solder the Thermal PAD to GND plane. The plane will work as heat sink. For details about the corner pads size

and location, refer to the 节13 at the end of this document.

A1

A4

1

2

3

4

5

6

18

17

16

15

14

13

Thermal

Pad

A3

A2

图11-2. Thermal Pad Corner Locations

表11-1. Thermal Pad Corner

CORNER

DESCRIPTION

A1

A2

A3

A4

Internally connected to thermal pad. Leave floating or connect to the same plane as thermal pad.

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

TAS2505 Application Reference Guide (SLAU472)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

12.4 Trademarks

所有商标均为其各自所有者的财产。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLASEI9

30

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GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

RGE0024K

VQFN - 1 mm max height

S

C

A

L

E

3

.

3

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

0.5

0.3

0.2

PIN 1 INDEX AREA

DETAIL

OPTIONAL TERMINAL

TYPICAL

4.1

3.9

0.1 MIN

(0.05)

A

-

A

2

5

.

0

SECTION A-A

TYPICAL

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2.8 0.1

2X 2.5

(0.2) TYP

8X (0.38)

EXPOSED

THERMAL PAD

7

12

A3

13

A2

20X 0.5

6

8X (0.2)

2X

25

SYMM

A

2.5

SEE TERMINAL

DETAIL

1

18

A4

0.3

0.2

0.1

24X

A1

C A B

24

19

SYMM

PIN 1 ID

(OPTIONAL)

0.05

0.5

0.3

24X

4223589/B 05/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024K

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.8)

4X (1.72)

SYMM

8X (0.58)

8X (0.2)

24X (0.6)

24

19

A4

A1

18

1

4X

(1.72)

24X (0.25)

25

SYMM

(3.8)

20X (0.5)

(1.15)

6

13

(

0.2) TYP

VIA

A2

A3

(R0.05)

TYP

7

12

(1.15)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223589/B 05/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024K

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (1.72)

(0.715)

TYP

8X (0.58)

8X (0.2)

24X (0.6)

24

19

A4

A1

25

18

1

4X

(1.72)

24X (0.25)

(0.715)

TYP

SYMM

(3.8)

20X (0.5)

4X

1.23)

(

6

13

EXPOSED METAL

TYP

A2

A3

(R0.05) TYP

12

7

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

THERMAL PAD 25:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223589/B 05/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RGE0024Y

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

4.1

3.9

0.1 MIN

(0.13)

A

-

A

4

0

.

0

SECTION A-A

1.0

0.8

TYPICAL

C

SEATING PLANE

0.08 C

0.05

0.00

2.8 0.1

2X 2.5

SYMM

(0.2) TYP

12

7

EXPOSED

THERMAL PAD

(0.16)

TYP

6

13

SYMM

25

A

2X 2.5

2.8 0.1

20X 0.5

1

18

0.3

0.2

0.1

PIN 1 ID

24X

24

19

C A B

C

0.5

0.3

0.05

24X

4229066/A 09/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024Y

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.8)

SYMM

SEE SOLDER MASK

DETAIL

19

24

24X (0.6)

1

24X (0.25)

18

(2.8)

20X (0.5)

SYMM

25

(3.8)

(

0.2) TYP

VIA

(1.15)

(R0.05) TYP

13

6

7

12

(1.15)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4229066/A 09/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024Y

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.715) TYP

19

24

24X (0.6)

24X (0.25)

1

18

20X (0.5)

SYMM

(0.715) TYP

(3.8)

25

(R0.05) TYP

4X (1.23)

13

6

7

12

4X (1.23)

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 25

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4229066/A 09/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TAS2505TRGERQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有音频处理和集成负载诊断功能的汽车类 2W 单声道数字输入 D 类音频放大器 \| RGE \| 24 \| -40 to 105 放大器音频放大器
文件：	总42页 (文件大小：2832K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TAS2505TRGERQ1 [TI]

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