TAS2521IRGER [TI]
具有 miniDSP 和 18mW 单声道耳机驱动器的 2W 单声道、数字和模拟输入 D 类音频放大器 | RGE | 24 | -40 to 85;
| 型号： | TAS2521IRGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 miniDSP 和 18mW 单声道耳机驱动器的 2W 单声道、数字和模拟输入 D 类音频放大器 | RGE | 24 | -40 to 85 放大器 驱动 商用集成电路 音频放大器 驱动器 |
| 文件： | 总37页 (文件大小：2269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS2521
www.ti.com.cn
ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
具有嵌入式微型数字信号处理器 (miniDSP) 和单声道头戴式耳机放大器
的数字输入 D 类扬声器放大器
查询样品: TAS2521
1 介绍
1.1 特性
1
• 数字输入单声道扬声器放大器
1.2 应用
• 指令可编程嵌入式 miniDSP
• 支持 8kHz 至 192kHz 的采样率
• 单声道 D 类平衡桥式功放电路 (BTL) 扬声器驱动
器（为 4Ω 负载提供 2W 输入功率，或为 8Ω 负载
提供 1.7W 输入功率）
•
•
•
便携式音频器件
大型家用电器
便携式导航器件
• 单声道头戴式耳机驱动器
• 具有输出混合和电平控制的两个单端输入
• 嵌入式上电复位
1.3 说明
TAS2521 是一款低功耗数字输入扬声器放大器，此放
大器支持 24 位数字 I2S 数据单声道回放。
• 集成型低压降稳压器 (LDO)
除了驱动负载最高为 4Ω 的扬声器放大器，该器件还特
有一个单声道头戴式耳机驱动器和一个用于信号处理的
完全可编程 miniDSP。 可对数字音频数据格式进行设
定以实现与主控，受控，DSP 和 TDM 模式中常见的
音频标准协议（I2S，左/右平衡）一同工作。 完全可编
程的 miniDSP 可以支持多种功能，例如音频均衡，多
频动态范围压缩 (DRC)，音调生成和其它几个用户定
义功能。 一个片载 PLL 提供数字信号处理块所需的高
速时钟。 音量可以由寄存器控制。 此音频功能由
I2C™ 串行总线或 SPI 总线控制。 该器件包括一个板
载低压降稳压器 (LDO)，它脱离扬声器电源运行以处
理所有内部器件模拟和数字电源需求。 所包含的加电
复位电路 POR 可靠地将器件复位至其缺省状态，因此
在正常使用时不需要外部复位；但是，该器件没有一个
适合更加复杂系统初始化所需要的复位引脚。 该器件
还包括两个模拟输入，用于在扬声器和头戴式耳机模拟
路径中的混音和多路复用。
• 具有用户可编程的双二阶滤波器的内置数字音频处
理块
• 用于可编程数字音频处理器的集成 PLL
• I2S，左平衡，右平衡，DSP 和 TDM 音频接口
• 支持自动递增的 I2C 和串行外设接口 (SPI) 控制
• 完全断电控制
• 电源：
– 模拟：1.5V - 1.95V
– 数字内核：1.65V - 1.95V
– 数字 I/O：1.1V - 3.6V
– D 类：2.7V - 5.5V (SPKVDD≥AVDD)
• 24 引脚四方扁平无引线 (QFN) 封装 (4mm 4mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
版权 © 2013, Texas Instruments Incorporated
English Data Sheet: SLAS687
TAS2521
ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
这些装置包含有限的内置 ESD 保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
6 dB to +24 dB
(6 dB steps)
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
SPKP
SPKM
DAC Signal
Proc.
Dig
Vol
Mono S-
D DAC
S
-6 dB to +29 dB
and Mute
(1 dB steps)
miniDSP
HPOUT
S
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
POR
LDO_SEL
LDO
SPKVDD
AVDD
SPI/I2C
Control Block
Secondary I2S
Interface
Primary I2S
Interface
Interrupt
Control
SPI_SEL
RST
PLL
DVDD
IOVDD
SPKVSS
AVSS
Pin Muxing / Clock Routing
DVSS
图 1-1. 简化方框图
注
本数据手册被设计成采用 PDF 文档浏览特性，此特性可实现信息快速访问。 例如，执行一
个“页 0 / 寄存器 27”的全局搜索可在一个列表中生成所有涉及这一页和寄存器的内容。 这样可
轻松遍历列表并找到所有与某一页和寄存器相关的信息。 请注意，搜索字符串必须为指定格
式。 此外，本文档包括文档超链接以使用户能够快速找到文档引用。 要返回到原来那一页，
请单击文件底部 PDF 页码附件的绿色左箭头。 针对此功能的热键是键盘上的左侧 alt 键。 另
外一个快速查找信息的方法是使用 PDF 书签。
2
介绍
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TAS2521
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ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1 Package/Ordering Information
OPERATING
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
TRANSPORT MEDIA,
ORDERING NUMBER
PRODUCT
PACKAGE
QUANTITY
TAS2521IRGET
TAS2521IRGER
Tape and reel, 250
Tape and reel, 3000
TAS2521
QFN-24
RGE
–40°C to 85°C
2.2 Device Information
RGE PACKAGE
(TOP VIEW)
24 23 22 21 20 19
GPIO/DOUT
MISO
SPI_SEL
1
2
3
4
5
6
18
RST
17
16
15
14
13
MCLK
BCLK
AINL
AINR
HPOUT
AVSS
WCLK
DIN
7
8
9
10 11 12
Table 2-1. RGE PIN FUNCTIONS
PIN
I/O(1)
DESCRIPTION
NAME
SPI_SEL
RST
NO.
1
I
I
Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
Reset for logic, state machines, and digital filters; asserted LOW.
Analog single-ended line left input
2
AINL
3
I
AINR
4
I
Analog single-ended line right input
HPOUT
AVSS
5
O
Headphone and Lineout Driver Output
6
GND Analog Ground, 0V
AVDD
LDO_SEL
SPKM
SPKVDD
SPKVSS
SPKP
7
PWR Analog Core Supply Voltage, 1.5V - 1.95V, tied internally to the LDO output
8
I
Select Pin for LDO; ties to either SPKVDD or SPKVSS
Class-D speaker driver inverting output
9
O
10
11
12
13
14
15
16
PWR Class-D speaker driver power supply
PWR Class-D speaker driver power supply ground supply
O
I
Class-D speaker driver non-inverting output
Audio Serial Data Bus Input Data
DIN
WCLK
BCLK
I/O
I/O
I
Audio Serial Data Bus Word Clock
Audio Serial Data Bus Bit Clock
MCLK
Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
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PACKAGE AND SIGNAL DESCRIPTIONS
3
TAS2521
ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
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Table 2-1. RGE PIN FUNCTIONS (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
17
18
19
20
21
22
23
24
MISO
O
SPI Serial Data Output
GPIO/DOUT
SCL/SSZ
SDA/MOSI
SCLK
I/O/Z GPIO / Audio Serial Bus Output
I
I
I
Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
Serial clock for SPI interface
IOVDD
PWR I/O Power Supply, 1.1V - 3.6V
PWR Digital Power Supply, 1.65V - 1.95V
GND Digital Ground, 0V
DVDD
DVSS
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
–0.3
MAX
2.2
2.2
6
AVDD to AVSS
V
V
DVDD to DVSS
–0.3
SPKVDD to SPKVSS
IOVDD to IOVSS
–0.3
V
–0.3
3.9
V
Digital input voltage
IOVSS – 0.3
AVSS – 0.3
–40
IOVDD + 0.3
V
Analog input voltage
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
AVDD + 0.3
V
85
°C
°C
°C
W
–55
150
105
QFN
Power dissipation(with thermal pad soldered to board)
(TJ Max – TA) / θJA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2 THERMAL INFORMATION
TAS2521
THERMAL METRIC(1)
UNITS
RGE (24 PINS)
θJA
Junction-to-ambient thermal resistance
32.2
30.0
9.2
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
9.2
θJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
4
ELECTRICAL SPECIFICATIONS
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ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
3.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
1.65
2.7
1.1
4
NOM
1.8
MAX
1.95
1.95
5.5
UNIT
AVDD(1)
DVDD
SPKVDD(1)
Referenced to AVSS(2)
Power-supply voltage range
(2)
Referenced to DVSS
1.8
V
(2)
Referenced to SPKVSS
(2)
IOVDD
Referenced to IOVSS
1.8
3.6
Speaker impedance
Load applied across class-D output pins (BTL)
AC-coupled to RL
Ω
Ω
Headphone impedance
16
Analog audio full-scale input
voltage
VI
AVDD = 1.8 V, single-ended
0.5
10
VRMS
Line output load impedance
(in half drive ability mode)
AC-coupled to RL
kΩ
MCLK(3)
SCL
Master clock frequency
SCL clock frequency
IOVDD = DVDD = 1.8V
50
400
85
MHz
kHz
°C
TA
Operating free-air temperature
–40
(1) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
3.4 Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
8.48
MHz
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.9V, DOSR = 128, Device Setup MCLK = 256* fs,
Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
Device Setup
Full-scale output voltage (0 dB)
Idle channel noise
0.5
20.7
-78.2
103.7
47.2
88.1
±0.3
11
Vrms
μVms
dB
ICN
Measured as idle-channel noise, A-weighted(1) (2)
THD+N
Total harmonic distortion + noise 0-dBFS input, 1-kHz input signal
Mute attenuation
Power-supply rejection ratio(3)
Dynamic range, A-weighted(1) (2) –60dB 1kHz input full-scale signal
Mute
dB
PSRR
DR
Ripple on AVDD (1.8 V) = 200 mVPP at 1 kHz
dB
Gain error
0dB, 1kHz input full scale signal
RL = 32 Ω, THD+N ≤ –40 dB
RL = 16 Ω, THD+N ≤ –40 dB
dB
PO
Maximum output power
mW
18
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆VHP / ∆VAVDD).
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ELECTRICAL SPECIFICATIONS
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.75V, DOSR = 128, Device Setup MCLK = 256*
fs, Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
Device Setup
Full-scale output voltage (0 dB)
Idle channel noise
0.375
18.1
-78.2
105.5
48.4
86.8
±0.3
8
Vrms
μVms
dB
ICN
Measured as idle-channel noise, A-weighted(1) (2)
THD+N
Total harmonic distortion + noise 0-dBFS input, 1-kHz input signal
Mute attenuation
Power-supply rejection ratio(3)
Dynamic range, A-weighted(1) (2) –60dB 1kHz input full-scale signal
Mute
dB
PSRR
DR
Ripple on AVDD (1.8 V) = 200 mVPP at 1 kHz
dB
Gain error
0dB, 1kHz input full scale signal
RL = 32 Ω, THD+N ≤ –40 dB
RL = 16 Ω, THD+N ≤ –40 dB
dB
PO
Maximum output power
mW
16
DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS
See for DAC interpolation filter characteristics.
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL)
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted(1) (2)
ICN
Idle channel noise
37
1.4
μVms
Vrms
dB
BTL measurement, class-D gain = 6 dB, -3dBFS
input
Output voltage
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
THD+N
PSRR
Total harmonic distortion + noise
–73.9
BTL measurement, ripple on SPKVDD = 200 mVPP
at 1 kHz
Power-supply rejection ratio
Mute attenuation
55
103
1.1
dB
dB
Mute
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.4
0.8
1.1
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
PO
Maximum output power
W
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB
2
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆VHP / ∆VAVDD).
6
ELECTRICAL SPECIFICATIONS
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ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted(1) (2)
ICN
Idle channel noise
35.2
1.4
μVms
Vrms
dB
BTL measurement, class-D gain = 6 dB, -3dBFS
input
Output voltage
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
THD+N
Total harmonic distortion + noise
–73.6
0.7
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1.7
PO
Maximum output power
W
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.5
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
1.3
ANALOG BYPASS TO HEADPHONE AMPLIFIER
AC-COUPLED LOAD = 16 Ω (SINGLE-ENDED),
Device Setup
DRIVER GAIN = 0 dB, Input and output common-
mode = 0.9 V, input signal frequency fi = 1kHz
Voltage Gain
Gain Error
Input common-mode = 0.9 V
1
V/V
dB
-1dBFS (446mVrms), 1-kHz input signal
±0.8
Idle channel, IN1L and IN1R ac-shorted to ground,
Measured as idle-channel noise, A-weighted(1) (2)
ICN
Idle channel noise
10.2
μVms
THD+N
Total harmonic distortion + noise -1 dBFS (446mVrms), 1-kHz input signal
-80.4
dB
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
7
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER
BTL measurement, DRIVER GAIN = 6 dB, LOAD
= 4 Ω (DIFFERENTIAL), 50 pF, input signal
frequency fi = 1 KHz
Device Setup
Voltage Gain
Gain Error
Input common-mode = 0.9 V
4
V/V
dB
-1dBFS (446mVrms), 1-kHz input signal
±0.7
Idle channel, IN1L and IN1R ac-shorted to ground,
Measured as idle-channel noise, A-weighted(1) (2)
ICN
Idle channel noise
32.6
μVms
THD+N
Total harmonic distortion + noise -1 dBFS (446mVrms), 1-kHz input signal
-73.7
dB
LOW DROPOUT REGULATOR (AVDD)
SPKVDD = 2.7V, Page 1, Reg 2, D5-D4 = 00, IO
50mA
=
=
=
AVDD Output Voltage 1.8V
1.79
1.79
1.79
V
V
V
SPKVDD = 3.6V, Page 1, Reg 2, D5-D4 = 00, IO
50mA
SPKVDD = 5.5V, Page 1, Reg 2, D5-D4 = 00, IO
50mA
Output Voltage Accuracy
Load Regulation
SPVDD = 2.7V
±2
7
%
mV
mV
uF
SPVDD = 2.7V, 0A to 50mA
Input Supply Range 2.7V to 5.5V
Line Regulation
0.6
Decoupling Capacitor
Bias Current
1.0
55
166
174
uA
uV
uV
Noise @0A Load
A-weighted, 20Hz to 20kHz bandwidth
A-weighted, 20Hz to 20kHz bandwidth
Noise @50mA Load
SHUTDOWN POWER CONSUMPTION
Power down POR, /RST held low, AVDD = 1.8V,
IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V
Device Setup
I(AVDD)
I(DVDD)
1.32
0.04
0.68
2.24
µA
µA
µA
µA
I(IOVDD)
I(SPKVDD)
DIGITAL INPUT/OUTPUT
Logic family
CMOS
0.7 ×
IOVDD
IIH = 5 μA, IOVDD ≥ 1.6 V
IIH = 5 μA, IOVDD < 1.6 V
IIL = 5 μA, IOVDD ≥ 1.6 V
IIL = 5 μA, IOVDD < 1.6 V
IOH = 2 TTL loads
VIH
V
IOVDD
0.3 ×
–0.3
IOVDD
VIL
Logic level
V
V
0
0.8 ×
IOVDD
VOH
VOL
IOL = 2 TTL loads
0.25
V
Capacitive load
10
pF
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
8
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3.5 Timing Characteristics
3.5.1 I2S/LJF/RJF Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
tr
BCLK
tf
tS(DI)
th(DI)
DIN
T0145-10
PARAMETER
IOVDD = 1.8 V
IOVDD = 3.3 V
UNIT
MIN
MAX
MIN
MAX
td(WS)
ts(DI)
th(DI)
tr
WCLK delay
DIN setup
DIN hold
45
45
ns
ns
ns
ns
ns
8
8
6
6
Rise time
Fall time
25
25
10
10
tf
Figure 3-1. I2S/LJF/RJF Timing in Master Mode
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3.5.2 I2S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
th(WS)
tr
tH(BCLK)
tS(WS)
BCLK
tL(BCLK)
tS(DI)
tf
DIN
th(DI)
T0145-11
IOVDD = 1.8 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
35
35
8
MAX
MIN
35
35
6
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
ns
ns
ns
ns
ns
ns
ns
ns
8
6
8
6
DIN hold
8
6
Rise time
4
4
4
4
tf
Fall time
Figure 3-2. I2S/LJF/RJF Timing in Slave Mode
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3.5.3 DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
td(WS)
tf
BCLK
tS(DI)
tr
DIN
th(DI)
T0146-09
IOVDD = 1.8 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td(WS)
ts(DI)
th(DI)
tr
WCLK delay
DIN setup
DIN hold
45
45
ns
ns
ns
ns
ns
8
8
6
6
Rise time
Fall time
25
25
10
10
tf
Figure 3-3. DSP Timing in Master Mode
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3.5.4 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
tS(WS)
th(WS)
tS(WS)
th(WS)
tL(BCLK)
tf
BCLK
tH(BCLK)
tS(DI)
tr
DIN
th(DI)
T0146-10
IOVDD = 1.8V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
35
35
8
MAX
MIN
35
35
8
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
ns
ns
ns
ns
ns
ns
8
8
8
8
DIN hold
8
8
Rise time
4
4
4
ns
ns
tf
Fall time
4
Figure 3-4. DSP Timing in Slave Mode
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3.5.5 I2C Interface Timing
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
SDA
tBUF
tLOW
tr
tHIGH
tf
tHD;STA
SCL
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tSU;STA
STO
STA
STA
STO
T0295-02
PARAMETER
SCL clock frequency
Standard-Mode
MIN TYP
Fast-Mode
UNITS
MAX
MIN
TYP
MAX
400
fSCL
0
100
0
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD;STA
4
0.8
μs
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4
1.3
0.6
μs
μs
Setup time for a repeated START
condition
Data hold time: For I2C bus devices
tSU;STA
4.7
0
0.8
μs
tHD;DAT
tSU;DAT
tr
3.45
0
0.9
μs
ns
ns
ns
μs
Data setup time
250
100
SDA and SCL rise time
1000
300
20 + 0.1 Cb
20 + 0.1 Cb
0.8
300
300
tf
SDA and SCL fall time
tSU;STO
Set-up time for STOP condition
4
Bus free time between a STOP and
START condition
tBUF
Cb
4.7
1.3
μs
Capacitive load for each bus line
400
400
pF
Figure 3-5. I2C Interface Timing
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3.5.6 SPI Interface Timing
SS
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv(DOUT)
tdis
MSB OUT
thi
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 3-6. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVDD = 1.8V
Table 3-1. SPI Interface Timing
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN TYP MAX
IOVDD=3.3V
MIN TYP
UNITS
MAX
(1)
tsck
tsckh
tsckl
tlead
tlag
td
SCLK Period
100
50
50
30
30
40
50
25
25
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse width High
SCLK Pulse width Low
Enable Lead Time
Enable Lag Time
Sequential Transfer Delay
Slave DOUT access time
Slave DOUT disable time
DIN data setup time
DIN data hold time
ta
40
40
40
40
tdis
tsu
15
15
15
10
thi
tv;DOUT DOUT data valid time
25
4
18
4
tr
tf
SCLK Rise Time
SCLK Fall Time
4
4
(1) These parameters are based on characterization and are not tested in production.
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4 Typical Performance
4.1 Class D Speaker Driver Performance
20
0
20
0
œ20
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
0
4000
8000
12000
16000
20000
0
4000
8000
12000
16000
20000
C001
C002
Frequency (Hz)
Frequency (Hz)
Figure 4-1. DAC To Speaker Amplitude at 0 dBFS vs Frequency (4
Figure 4-2. AINL To Speaker FFT Amplitude at 0 dBFS vs
Ω Load)
Frequency (4 Ω Load)
100
100.00
10.00
1.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
10
1
Gain = 24 dB
SPKVDD=2.7V
SPKVDD=3V
SPKVDD=3.3V
0.1
0.01
0.10
0.01
SPKVDD=3.6V
SPKVDD=4.2V
SPKVDD=5.5V
Sri7
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
C003
C004
Output Power (W)
Output Power (W)
Figure 4-3. Total Harmonic Distortion + Noise vs 4 Ω Speaker
Figure 4-4. Total Harmonic Distortion + Noise + NOISE vs 4 Ω
Power (SPKVDD = 5.5 V)
Speaker Power (Gain = 18 dB)
100.00
100
10
1
Gain = 6 dB
Series1
Gain = 12 dB
Gain = 18 dB
10.00
Gain = 24 dB
1.00
0.10
0.01
SPKVDD = 2.7 V
SPKVDD = 3 V
SPKVDD=3.3 V
SPKVDD=3.6 V
SPKVDD=4.2 V
SPKVDDi=5.5 V
0.1
0.01
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
C005
C006
Output Power (W)
Output Power (W)
Figure 4-5. Total Harmonic Distortion + Noise + NOISE vs 8 Ω
Figure 4-6. Total Harmonic Distortion + Noise + NOISE vs 8 Ω
Speaker Power (SPKVDD = 5.5 V)
Speaker Power (Gain = 18 dB)
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Typical Performance
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90
80
70
60
50
40
30
20
10
SPKVDD = 2.7 V
SPKVDD = 3 V
SPKVDD = 3.3 V
SPKVDD = 3.6 V
SPKVDD = 4.2 V
SPKVDD = 5.5 V
0
0
200 400 600 800 1000 1200 1400 1600 1800
C007
Output Power (mWatt)
Figure 4-7. Total Power Consumption vs Output Power Consumption (Gain = 18 dB, Load = 4 Ω)
16
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4.2 HP Driver Performance
20
0
20
0
œ20
œ20
œ40
œ40
œ60
œ60
œ80
œ80
0dBFS
0dBFS
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
œ180
0
4000
8000
12000
16000
20000
0
4000
8000
12000
16000
20000
C008
C008
Frequency (Hz)
Frequency (Hz)
Figure 4-8. DAC TO HP FFT Amplitude at 0 dBFS vs Frequency
Figure 4-9. AINL TO HP FFT Amplitude at 0 dBFS vs Frequency
(16 Ω Load)
(16 Ω Load)
0
œ10
œ20
œ30
œ40
0
œ10
œ20
œ30
œ40
CM=0.75V,
AVDD=1.5V
CM=0.75V,AVDD=1.5V
œ50
œ50
CM=0.75V,
AVDD=1.8V
CM=0.75V,AVDD=1.8V
œ60
œ60
CM=0.75V,
AVDD=1.95V
CM=0.75V,AVDD=1.95V
œ70
œ70
CM=0.9V,
CM=0.9V,AVDD=1.8V
AVDD=1.8V
œ80
œ80
CM=0.9V,AVDD=1.95V
CM=0.9V,
AVDD=1.95V
œ90
œ90
0.0
5.0
10.0 15.0 20.0 25.0 30.0 35.0 40.0
0.0
5.0
10.0
15.0
20.0
25.0
C010
C011
Output Power (mW)
Output Power (mW)
Figure 4-10. Total Harmonic Distortion + Noise vs HP Power
(Gain = 9 dB)
Figure 4-11. Total Harmonic Distortion + Noise vs HP Power
(Gain = 32 dB)
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Typical Performance
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5 Application Overview
The TAS2521 offers a wide range of configuration options. 图 1-1 shows the simplified functional blocks of
the device.
5.1 Typical Circuit Configuration
+1.8VA
SVDD
IOVDD
0.1mF
22mF
0.1mF
22mF
2.7k
2.7k
AVSS
AVDD
LDO_SEL
SPKVSS
SPKVDD
GPIO/DOUT
SDA/MOSI
SCL/SSZ
MCLK
8-W or
4-W
Speaker
SPKP
SPKM
WCLK
DIN
TAS2521
BCLK
Headphone jack
RST
HPOUT
0.1mF
0.1mF
47mF
AINL
AINR
MISO
Analog Input
SCLK
SPI_SEL
DVDD DVSS
IOVDD IOVSS
+1.8VD
IOVDD
0.1mF
10mF
10mF
0.1mF
Figure 5-1. Typical Circuit Configuration
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5.2 Circuit Configuration with Internal LDO
SVDD
IOVDD
0.1mF
0.1mF
22mF
10mF
0.1mF
22mF
2.7k
2.7k
DVSS
AVDD
DVDD
AVSS
LDO_SEL SPKVSS
SPKVDD
GPIO/DOUT
SDA/MOSI
SCL/SSZ
MCLK
8-W or
4-W
Speaker
SPKP
SPKM
WCLK
DIN
TAS2521
BCLK
RST
HPOUT
0.1mF
0.1mF
47mF
AINL
AINR
MISO
Analog Input
SCLK
SPI_SEL
IOVDD IOVSS
IOVDD
0.1mF
10mF
Figure 5-2. Application Schematics for LDO
5.3 Device Connections
5.3.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending
on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C
or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 5.3.3.
5.3.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
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5.3.3 Multifunction Pins
Table 5-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 5-1. Multifunction Pin Assignments
1
2
3
4
5
6
7
Pin Function
MCLK
BCLK
WCLK
DIN
GPIO
SCLK
MISO
/DOUT
A
B
C
D
E
F
G
H
I
PLL Input
S(1)
S(1),D(4)
S(2)
S(2)
S(2),D
E(5)
E
S(3)
S(3)
Codec Clock Input
I2S BCLK input
I2S BCLK output
I2S WCLK input
I2S WCLK output
I2S DIN
I2S DOUT
E, D
E
E, D
E
E
General Purpose Output I
General Purpose Output II
General Purpose Input I
General Purpose Input II
General Purpose Input III
INT1 output
I
E
J
E
J
E
J
E
K
L
M
N
O
P
Q
R
S
E
E
E
E
E
E
E
E
E
INT2 output
Secondary I2S BCLK input
Secondary I2S WCLK input
Secondary I2S DIN
Secondary I2S BCLK OUT
Secondary I2S WCLK OUT
Secondary I2S DOUT
Aux Clock Output
E
E
E
E
E
E
E
E
(1) S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
(2) S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
(3) S(3): The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
(4) D: Default Function
(5) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
5.4 Audio Analog I/O
The TAS2521 features a mono audio DAC. It supports a wide range of analog interfaces to support
different headsets such as 16-Ω to 200-Ω impedance and analog line outputs. TheTAS2521 can drive a
speaker upto 4-Ω impedance.
5.5 Analog Signals
The TAS2521 analog signals consist of:
•
Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output
stages
•
Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the
DAC, AINR, AINL, or a mix of the three
20
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5.5.1 Analog Inputs AINL and AINR
AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output.
Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for
determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be
attenuated by Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of
HP driver can be attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural
differential input with use Mixer P and Mixer M by Page1 / register 12 setting.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6 Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is
between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated
within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include
mono headphone and lineout and mono class-D speaker outputs. Because the TAS2521 contains a mono
DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right
channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.1 DAC
The TAS2521 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the
mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP,
a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The
DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and
observed in the signal images strongly suppressed within the audio band to beyond 20 kHz. To handle
multiple input rates and optimize power dissipation and performance, the TAS2521 allows the system
designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0,
register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower
input data rates and lower oversampling ratios for higher input data rates.
The TAS2521 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on
required frequency response, group delay, and sampling rate.
The DAC path of the TAS2521 features many options for signal conditioning and signal routing:
•
•
Digital volume control with a range of -63.5 to +24dB
Mute function
In addition to the standard set of DAC features the TAS2521 also offers the following special features:
•
•
Digital auto mute
Adaptive filter mode
5.6.1.1 DAC Processing Blocks — Overview
The TAS2521 implements signal-processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they
may use and which interpolation filter is applied.
The choices among these processing blocks allows the system designer to balance power conservation
and signal-processing flexibility. Table 5-2 gives an overview of all available processing blocks of the DAC
channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (AVDD) may differ.
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The signal-processing blocks available are:
•
•
First-order IIR
Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.
Table 5-2. Overview – DAC Predefined Processing Blocks
Processing
Block No.
First-Order
IIR Available
Number of
Biquads
Resource
Class
Interpolation Filter
Channel
PRB_P1
PRB_P2
PRB_P3
A
A
B
Mono
Mono
Mono
Yes
No
6
3
6
6
4
4
Yes
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.2 Digital Mixing and Routing
The TAS2521 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the
digital audio data. The first mixer/multiplexer can be used to select input data for the mono DAC from left
channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by
writing to page 0, register 63, bits D5–D4.
5.6.3 Analog Audio Routing
The TAS2521 has the capability to route the DAC output to either the headphone or the speaker output. If
desirable, both output drivers can be operated at the same time while playing at different volume levels.
The TAS2521 provides various digital routing capabilities, allowing digital mixing or even channel
swapping in the digital domain. All analog outputs other than the selected ones can be powered down for
optimal power consumption.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.4 5V LDO
The TAS2521 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply
(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is
50 mA or less, then this LDO can deliver power to both analog and digital power supplies. If the only
speaker power supply is present and LDO Select pin is enabled, the LDO can power up without requiring
other supplies. This LDO requires a minimum dropout voltage of 300 mV and can support load currents up
to 50 mA. For stability reasons the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the
analog supply (AVDD) pin and the digital supply (DVDD) pin. If use this LDO output voltage for the digital
supply (DVDD) pin, the analog supply (AVDD) pin connected to the digital supply (DVDD) externally is
required.
The LDO is by default powered down for low sleep mode currents and can be enabled driving the
LDO_SELECT pin to SPKVDD (Speaker power supply). When the LDO is disabled the AVDD pin is tri-
stated and the device AVDD needs to be powered using external supply. In that case the DVDD pin is
also tri-stated and the device DVDD needs to be powered using external supply. The output voltage of this
LDO can be adjusted to a few different values as given in the Table 5-3.
22
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Table 5-3. AVDD LDO Settings
Page-1, Register 2, D(5:4)
00
LDO Output
1.8 V
1.6 V
1.7 V
1.5 V
01
10
00
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.5 POR
TAS2521 has a POR (Power On Reset) function. This function insures that all registers are automatically
set to defaults when a proper power up sequence is executed.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.6 CLOCK Generation and PLL
The TAS2521 supports a wide range of options for generating clocks for the DAC sections as well as
interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can
be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference
clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits
D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in to
generate the various clocks required for the DAC and the miniDSP section. In the event that the desired
audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2521 also
provides the option of using the on-chip PLL which supports a wide range of fractional multiplication
values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2521 provides several
programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the
miniDSP sections.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7 Digital Audio and Control Interface
5.6.7.1 Digital Audio Interface
Audio data is transferred between the host processor and the TAS2521 via the digital audio data serial
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data
options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for
multichannel operation, flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TAS2521 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently
configured in either master or slave mode for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC
sampling frequencies.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.2 Control Interface
The TAS2521 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. It is
not recommended to change the state of SPI_SEL during device operation.
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5.6.7.2.1 I2C Control Mode
The TAS2521 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is
driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously,
there is no driver contention.
5.6.7.2.2 SPI Digital Interface
In the SPI control mode,the TAS2521 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI
control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host
processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor)
generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices
(such as the TAS2521) depend on a master to start and synchronize transmissions. A transmission begins
when initiated by an SPI master.The byte from the SPI master begins shifting in on the slave MOSI pin
under the control of the master serial clock(driven onto SCLK). As the byte shifts in on the MOSI pin, a
byte shifts out on the MISO pin to the master shif tregister.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.3 Power Supply
The TAS2521 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance
and power consumption. The device has separate power domains for digital IO, digital core, analog core,
analog input, headphone driver, and speaker drivers. If desired, all of the supplies (except for the supplies
for speaker drivers, which can directly connect to the battery) can be connected together and be supplied
from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied in the
range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core supply can either be derived from the internal LDO accepting an SPKVDD
voltage in the range of 2.7V to 5.5V, or the AVDD pin can directly be driven with a voltage in the range of
1.5V to 1.95V. The speaker driver voltages (SPKVDD) can range from 2.7V to 5.5V.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.4 Device Special Functions
•
•
Interrupt generation
Flexible pin multiplexing
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.5 miniDSP
The TAS2521 features a miniDSP core which is tightly coupled to the DAC. The fully programmable
algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access
to the digital audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The
miniDSP has 512 programmable instructions, 896 data memory locations, and 512 programmable
coefficients (in the adaptive mode, each bank has 256 programmable coefficients).
24
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ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
5.6.7.5.1 Software
Software development for the TAS2521 is supported through TI's comprehensive PurePath™ Studio
software development environment, a powerful, easy-to-use tool designed specifically to simplify software
development on Texas Instruments miniDSP audio platforms. The graphical development environment
consists of a library of common audio functions that can be dragged and dropped into an audio signal flow
and graphically connected together. The DSP code can then be assembled from the graphical signal flow
with the click of a mouse. See the TAS2521 product folder on www.ti.com to learn more about PurePath
Studio and the latest status on available, ready-to-use DSP algorithms.
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6 Register Map
6.1 Register Map Summary
Table 6-1. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO. REG. NO.
PAGE NO. REG. NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Page Select Register
1
Software Reset Register
2 - 3
4
0x02 - 0x03 Reserved Registers
0x04
0x05
0x06
0x07
0x08
Clock Setting Register 1, Multiplexers
5
Clock Setting Register 2, PLL P and R Values
Clock Setting Register 3, PLL J Values
6
7
Clock Setting Register 4, PLL D Values (MSB)
Clock Setting Register 5, PLL D Values (LSB)
8
9 - 10
11
0x09 - 0x0A Reserved Registers
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Clock Setting Register 6, NDAC Values
12
Clock Setting Register 7, MDAC Values
DAC OSR Setting Register 1, MSB Value
DAC OSR Setting Register 2, LSB Value
miniDSP_D Instruction Control Register 1
miniDSP_D Instruction Control Register 2
miniDSP_D Interpolation Factor Setting Register
13
14
15
16
17
18 - 24
25
0x12 - 0x18 Reserved Registers
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
Clock Setting Register 10, Multiplexers
26
Clock Setting Register 11, CLKOUT M divider value
Audio Interface Setting Register 1
27
28
Audio Interface Setting Register 2, Data offset setting
Audio Interface Setting Register 3
29
30
Clock Setting Register 12, BCLK N Divider
Audio Interface Setting Register 4, Secondary Audio Interface
Audio Interface Setting Register 5
31
32
33
Audio Interface Setting Register 6
34
Reserved Register
35 - 36
37
0x23 - 0x24 Reserved Registers
0x25
DAC Flag Register 1
38
0x26
DAC Flag Register 2
39-41
42
0x27-0x29
0x2A
Reserved Registers
Sticky Flag Register 1
Interrupt Flag Register 1
Sticky Flag Register 2
Reserved Register
43
0x2B
44
0x2C
45
0x2D
46
0x2E
Interrupt Flag Register 2
Reserved Register
47
0x2F
48
0x30
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Reserved Registers
49
0x31
50-51
52
0x32-0x33
0x34
GPIO/DOUT Control Register
DOUT Function Control Register
53
0x35
26
Register Map
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ZHCSAR2A –FEBRUARY 2013–REVISED FEBRUARY 2013
Table 6-1. Summary of Register Map (continued)
Decimal
PAGE NO. REG. NO.
Hex
DESCRIPTION
PAGE NO. REG. NO.
0
54
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x36
DIN Function Control Register
0
55
0x37
MISO Function Control Register
SCLK/DMDIN2 Function Control Register
Reserved Registers
0
56
0x38
0
57-59
60
0x39-0x3B
0x3C
0x3D
0x3E
0x3F
0
DAC Instruction Set
0
61
Reserved Registers
0
62
miniDSP_D Configuration Register
DAC Channel Setup Register 1
DAC Channel Setup Register 2
DAC Channel Digital Volume Control Register
0
63
0
64
0x40
0
65
0x41
0
66 - 80
81
0x42 - 0x50 Reserved Registers
0x51 Dig_Mic Control Register
0x52 - 0x7F Reserved Registers
0
0
82 - 127
0
1
0x00
0x01
0x02
0x03
Page Select Register
1
1
REF, POR and LDO BGAP Control Register
LDO Control Register
1
2
1
3
Playback Configuration Register 1
1
4 - 7
8
0x04 - 0x07 Reserved Registers
1
0x08
0x09
0x0A
0x0B
0x0C
DAC PGA Control Register
1
9
Output Drivers, AINL, AINR, Control Register
Common Mode Control Register
1
10
1
11
HP Over Current Protection Configuration Register
HP Routing Selection Register
1
12
1
13 - 15
16
0x0D - 0x0F Reserved Registers
1
0x10
HP Driver Gain Setting Register
1
17 - 19
20
0x11 - 0x13 HPR Driver Gain Setting Register
1
0x14
0x15
0x16
0x17
0x18
0x19
Headphone Driver Startup Control Register
Reserved Register
1
21
1
22
HP Volume Control Register
Reserved Register
1
23
1
24
AINL Volume Control Register
AINR Volume Control Register
1
25
1
26 - 44
45
0x1A - 0x2C Reserved Registers
1
0x2D
0x2E
0x2F
0x30
Speaker Amplifier Control 1
1
46
Speaker Volume Control Register
Reserved Register
1
47
1
48
Speaker Amplifier Volume Control 2
1
49 - 62
64 - 121
122
123 - 127
0 - 127
0
0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register
0x40 - 0x79 Reserved Registers
1
1
0x7A
0x7B - 0x7F Reserved Registers
0x02 - 0x2B 0x00 - 0x7F Reserved Registers
Reference Power Up Delay
1
2 - 43
44
44
44
44
0x2C
0x2C
0x2C
0x2C
0x00
0x01
Page Select Register
1
DAC Adaptive Filter Configuration Register
2 - 7
8 - 127
0x02 - 0x07 Reserved
0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)
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Register Map
27
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Table 6-1. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO. REG. NO.
PAGE NO. REG. NO.
0x2D-0x34 0x00
45 - 52
0
Page Select Register
45 - 52
1 - 7
8 - 127
0 - 127
0
0x2D-0x34 0x01 - 0x07 Reserved.
45 - 52
0x2D-0x34 0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)
0x35 - 0x3D 0x00 - 0x7F Reserved Registers
53 - 61
62 - 70
0x3E-0x46
0x3E-0x46
0x3E-0x46
0x00
Page Select Register
62 - 70
1 - 7
8 - 127
0 - 127
0
0x01 - 0x07 Reserved Registers
62 - 70
0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)
71 - 151
152 - 169
152 - 169
152 - 169
170 - 255
0x47 - 0x97 0x00 - 0x7F Reserved Registers
0x98-0xA9
0x98-0xA9
0x98-0xA9
0x00
Page Select Register
1 - 7
8 - 127
0 - 127
0x01 - 0x07 Reserved Registers
0x08 - 0x7F miniDSP_D Instructions
0xAA - 0x7F 0x00 - 0x7F Reserved Registers
spacer
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2013) to Revision A
Page
•
•
Deleted PO (Max Output power) SPKVDD = 5.5 V, THD = 10% .............................................................. 6
Changed PO (Max Output power) SPKVDD = 5.5 V value From: TYP = 2.1 W To: MAX = 2 W ......................... 6
28
Register Map
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS2521IRGER
TAS2521IRGET
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TAS
2521
ACTIVE
RGE
NIPDAU
TAS
2521
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS2521IRGER
TAS2521IRGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS2521IRGER
TAS2521IRGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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