TAS2563 [TI]
TAS2563 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP And IV Sense;
| 型号： | TAS2563 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TAS2563 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP And IV Sense |
| 文件： | 总127页 (文件大小：5492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS2563
SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TAS2563 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP And IV Sense
1 Features
3 Description
•
Key Features
The TAS2563 is a digital input Class-D audio amplifier
optimized for efficiently driving high peak power into
small loudspeakers. The Class-D amplifier is capable
of delivering 6.1 W of peak power into a 4 Ω load at
battery voltage of 3.6 V using the integrated 11.5V
Class-H boost, or 10W peak power into 4Ω load in
boost bypass mode using external 12V supply.
– 11.5V, 12-step Look-ahead Class-H boost
– Integrated DSP for speaker protection and
audio processing
– Full Scale Ultrasonic Output to 40kHz
– 2 PDM Microphone inputs
Powerful Class-D audio amplifier :
– 6.1-W 1% THD+N (4 Ω, 3.6 V)
– 5-W 1% THD+N (8 Ω, 3.6 V)
– 10-W 1% THD+N (4 Ω, 12 V)
Advanced Audio Processing
•
•
An on-chip, low-latency DSP supports Texas
Instruments SmartAmp speaker protection algorithms.
The integrated current and voltage sense provide for
real-time monitoring of the loudspeakers, which
permits pushing peak sound pressure levels (SPL)
while keeping speakers from being damaged.
– Dedicated Real-time DSP with:
•
•
•
Real-time I/V-sense Speaker Protection
Short and Open Load Protection
Speaker Thermal and Over Current
Protection
3-band equalization
Psychoacoustic bass
The integrated look-ahead Class-H boost dynamically
adjusts boost voltage during playback, increasing
efficiency and saving battery life in battery-powered
systems. For regulated wall-powered systems,
TAS2563 also features a boost bypass mode,
supporting supply voltages of up to 16V for even
higher output power.
•
•
•
Dynamic range compression
•
Flexible Interfaces and Control :
– I2S/TDM: 8 Channels of 32 bit up to 96 KSPS
– I2C: Selectable Addresses with Fast Mode+
Support
– Inter-Chp Communication Bus (DSBGA
package)
Two PDM microphone inputs simplify audio signal
chain for two-way audio systems, interfacing digital
microphones with the host processor. A battery
tracking peak voltage limiter with brown-out protection
prevents systems shutdowns by optimizing amplifier
headroom over the entire charge cycle.
– 8 kHz to 96 kHz Sample Rates
Power Efficiency and Flexibility :
– 83.5% Efficiency at 1W
– <1uA HW shutdown VBAT current
– Boost-bypass mode
Device Information (1)
•
•
PART NUMBER
TAS2563
TAS2563
PACKAGE
DSBGA
QFN
BODY SIZE (NOM)
2.5 mm × 3 mm
4.5 mm x 4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Power Supplies and Management
– VBAT: 2.7 V to 5.5 V
IOVDD VBAT
IOVDD
VBAT
PVDD
L1
– PVDD: 2.7 V to 13 V (QFN package), 2.7 V to
16 V (DSBGA package)
C1
C1
VBAT SW
VBAT SW
GREG
GREG
IOVDD
IOVDD
– IOVDD: 1.65 V to 3.6 V
VBST
PVDD
VBST
PVDD
C2
C2
– VBAT Tracking Peak Voltage Limiter
– Advanced Brown Out Prevention
– Thermal and Over Current Protection
PDM
I2S
PDM
2
4
2
4
TAS2563
TAS2563
I2S
I2C
VSNS_P
VSNS_P
Ferrite bead
(optional)
Ferrite bead
(optional)
I2C
OUT_P
OUT_N
OUT_P
OUT_N
+
+
2
2
-
-
SDZ
SDZ
Ferrite bead
(optional)
Ferrite bead
(optional)
2 Applications
IRQZ
IRQZ
VSNS_N
VSNS_N
Boost Bypass
(external PVDD)
Internal Boost Mode
•
•
•
•
•
Smart phone, Tablets and Laptops
Smart Speakers with Voice Assistance
Bluetooth and Wireless Speakers
Smart Home
Simplified Schematic
IP Camera
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TAS2563
www.ti.com
SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................7
6.5 Electrical Characteristics ............................................7
6.6 I2C Timing Requirements .........................................14
6.7 SPI Timing Requirements ........................................ 15
6.8 PDM Port Timing Requirements .............................. 15
6.9 TDM Port Timing Requirements ...............................15
6.10 Timing Diagrams.....................................................16
6.11 Typical Characteristics............................................ 18
7 Parameter Measurement Information..........................26
8 Detailed Description......................................................27
8.1 Overview...................................................................27
8.2 Functional Block Diagram.........................................27
8.3 Feature Description...................................................28
8.4 Device Functional Modes..........................................39
8.5 Register Maps...........................................................68
9 Application and Implementation..................................99
9.1 Application Information............................................. 99
9.2 Typical Application.................................................... 99
10 Power Supply Recommendations............................102
10.1 Power Supplies.....................................................102
10.2 Power Supply Sequencing....................................102
11 Layout.........................................................................103
11.1 Layout Guidelines................................................. 103
11.2 Layout Example.................................................... 104
12 Device and Documentation Support........................108
12.1 Documentation Support........................................ 108
12.2 Receiving Notification of Documentation Updates108
12.3 Support Resources............................................... 108
12.4 Trademarks...........................................................108
12.5 Electrostatic Discharge Caution............................108
12.6 Glossary................................................................108
13 Mechanical, Packaging, and Orderable
Information.................................................................. 109
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2019) to Revision B (December 2020)
Page
•
•
•
Added RPP mechanical data .............................................................................................................................1
Changed device status to Mixed Production...................................................................................................... 1
Added QFN package as Advanced Information ................................................................................................ 1
Changes from Revision * (April 2019) to Revision A (August 2019)
Page
•
Changed TAS2562 from Advance Information to Production Data ................................................................... 1
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
5 Pin Configuration and Functions
1
2
3
4
5
6
A
B
C
D
E
F
PDMCK
PDMD
SDOUT2
SDIN2
SBCLK2
IOVDD
SDZ
SDOUT1
VBAT
BGND
SW
SBCLK1
SDIN1
VBAT
BGND
SW
FSYNC
SCL_SELZ
SDA_MOSI
DREG
SPII2CZ
_MISO
ADDR
_SPICLK
IRQZ
VDD
VSNS_N
BGND
SW
GREG
GND
VSNS_P
GPIO
PGND
PGND
OUT_N
GNDD
PVDD
OUT_P
PVDD
G
VBST
VBST
VBST
PVDD
Not to scale
Figure 5-1. YBG Package 42-Ball DSBGA Top View
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
23
21
22
19
20
18
17
24
PDMD
NC
25
26
16
PVDD
VBST
SW
15
14
OUT_N
GNDP 27
GNDB
GREG
28
29
GNDD
13
12
11
VSNS_N
SPII2CZ_MISO
SDIN1
VBAT 30
31
10
9
VDD
SDOUT1
PDMCLK
IOVDD 32
NC
NC
2
4
8
3
6
5
7
1
Not to scale
Figure 5-2. RPP Package 32-pin QFN Top View
Pin Functions
PIN
TYPE
DESCRIPTION
DSBGA
NO.
NAME
QFN NO.
ADDR_SPI
CLK
I2C Mode - Address selection pin See General I2C operation. SPI Mode - SPI
clock
C4
B6
19
2
I
Digital core voltage regulator output. Bypass to GND with a cap. Do not connect
to external load.
DREG
P
FSYNC
GNDB
GNDD
GND
B3
E1, E2, E3
F4
5
14
28
N/A
27
22
13
32
I
P
P
P
P
IO
P
P
I2S word clock or TDM frame sync for ASI1 and ASI2 channels.
Boost ground. Connect to PCB GND plane.
Digital ground. Connect to PCB GND plane.
E4
Analog ground. Connect to PCB GND plane.
GNDP
GPIO
E5,E6
D6
Power stage ground. Connect to PCB GND plane.
General purpose input-ouput or MCLK base on register configuration.
High-side gate CP regulator output. Do not connect to external load.
3.3-V/1.8-V IOVDD Supply
GREG
IOVDD
D4
A6
Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional
internal pull up is not used.
IRQZ
C5
18
O
OUT_N
OUT_P
PDMCLK
F6
F5
A1
26
21
9
O
O
Class-D negative output for receiver channel.
Class-D positive output for receiver channel.
PDM clock.
IO
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NAME
SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
PIN
TYPE
DESCRIPTION
DSBGA
NO.
QFN NO.
PDMD
A2
G4, G5, G6
B2
24
25
6
IO
P
I
PDM data.
PVDD
Power stage supply.
SBCLK1
SBCLK2
ASI1 channel I2S/TDM serial bit clock.
ASI2 channel I2S/TDM serial bit clock.
A5
I
I2C Mode: I2C Data Pin. Pull up to IOVDD with a resistor. SPI Mode: Serial data
input pin.
SDA_MOSI
B5
3
IO
SDIN1
SDIN2
SDOUT1
SDOUT2
SDZ
C2
A4
C1
A3
B1
11
I
I
ASI1 channel I2S/TDM serial data input.
ASI2 channel I2S/TDM serial data input.
ASI1 channel I2S/TDM serial data output.
ASI2 channel I2S/TDM serial data output.
Active low hardware shutdown.
10
IO
IO
I
7
4
I2C Mode: I2C clock pin. Pull up to IOVDD with a resistor. SPI Mode: active low
chip select.
SCL_SELZ
B4
IO
SPII2CZ_MI
SO
Pin is queried on power-up. Short to GND for I2C Mode. Pull to IOVDD with
resistor for SPI mode. SPI serial data output pin.
C3
F1, F2, F3
D1, D2
12
15
30
16
31
IO
P
SW
Boost converter switch input.
Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with
a cap.
VBAT
VBST
VDD
P
G1, G2, G3
C6
P
Boost converter output. Do not connect to external load.
Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to
GND with cap.
P
Voltage sense negative input. Connect to Class-D OUT_N output after Ferrite
bead filter.
VSNS_N
D3
D5
29
I
I
Voltage sense positive input. Connect to Class-D OUT_P output after Ferrite
bead filter.
VSNS_P
NC
20
1, 8, 17
No Connect.
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
-0.3
–0.3
–0.3
-0.3
-0.3
-0.7
-0.3
-0.3
–0.3
–40
–40
–65
MAX
3.9
UNIT
V
IO Supply IOVDD
Analog Voltage
IOVDD
VDD
2
V
Battery Supply Voltage VBAT
6
V
Boost Pin
VBST
PVDD(3)
SW
18.5
18.5
16
V
Power Supply Voltage
Switching Pin
V
V
High Side Regulator Pin GREG
PVDD+6
1.65
VDD+0.3
85
V
Digital Regular Pin
Input voltage(2)
DREG
V
Digital IOs referenced to VDD supply
V
Operating free-air temperature, TA
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
°C
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Procedures. Exposure to absolute-maximum-rated conditions for extended periods can affect device
reliability.
(2) All digital inputs and IOs are failsafe.
(3) PVDD can handle 19V transients for less than 10ns
6.2 ESD Ratings
VALUE
±3000
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 OUT_N /
OUT_P / VSNS_N / VSNS_P Pins(1)
V
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
3
NOM
1.8
MAX
1.98
3.6
UNIT
IOVDD
IOVDD
VBAT
VDD
IO Supplly Voltage 1.8V
IO Supply Voltage 3.3V
Supply voltage
V
V
V
V
3.3
2.5
3.6
5.5
Supply voltage
1.62
1.8
1.95
Supply voltage - external boost mode (DSBGA
package)
PVDDDSBGA (VBST)
VBAT
VBAT
16
13
V
PVDDQFN (VBST)
Supply voltage - external boost mode (QFN package)
High-level digital input voltage
V
V
VIH
0.7 x IOVDD
0
VIL
Low-level digital input voltage
V
RSPK
LSPK
Minimum speaker impedance
3.2
10
Ω
Minimum speaker inductance
µH
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6.4 Thermal Information
TAS2563
THERMAL METRIC(1)
RPP (QFN)
32 PINS
43.7
YBG (WCSP)
42 PINS
55.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
20.3
0.3
10.5
11.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
0.2
ψJB
10.5
11.6
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT
and OUTPUT
High-level digital input logic voltage All digital pins except SDA_MOSI
threshold (max current limit = 30 mA) and SCL_SELZ
0.65 ×
IOVDD
VIH
VIL
V
V
Low-level digital input logic voltage
All digital pins except SDA_MOSI
0.35 ×
IOVDD
threshold (max current limit = 30 mA) and SCL_SELZ
High-level digital input logic voltage
threshold (max current limit = 30
mA)
0.7 ×
IOVDD
VIH(I2C)
VIL(I2C)
VOH
SDA_MOSI and SCL_SELZ
V
V
V
Low-level digital input logic voltage
threshold (max current limit = 30 mA)
0.3 ×
IOVDD
SDA_MOSI and SCL_SELZ
All digital pins except
SDA_MOSI ,SCL_SELZ and IRQZ;
IOH = 2 mA.
High-level digital output voltage (max
current limit = 30 mA)
IOVDD –
0.45 V
All digital pins except
SDA_MOSI ,SCL_SELZ and IRQZ;
IOL = –2 mA.
Low-level digital output voltage (max
current limit = 30 mA)
VOL
0.45
V
V
Low-level digital output voltage (max
current limit = 30 mA)
0.2 ×
IOVDD
VOL(I2C)
VOL(IRQZ)
IIH
SDA and SCL; IOL(I2C) = –2 mA.
IRQZ; IOL(IRQZ) = –2 mA.
Low-level digital output voltage for
IRQZ open drain Output (max
current limit = 30 mA)
0.45
V
Input logic-high leakage for digital
inputs
All digital pins; Input = VDD.
–5
–5
0.1
5
5
µA
Input logic-low leakage for digital
inputs
IIL
All digital pins; Input = GND.
All digital pins
0.1
8
µA
pF
kΩ
CIN
RPD
Input capacitance for digital inputs
Pull down resistance for digital
input/IO pins when asserted on
SDOUT, SDIN, FSYNC, SBCLK
50
AMPLIFIER PERFORMANCE - Internal Boost
Output Voltage for Full-scale digital
Input
Measured at -6 dB FS input
6.32
Vrms
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 32Ω + 33 µH, THD+N = 0.03 %,
fin = 1 kHz
1.25
W
RL = 8 Ω + 33 µH, THD+N = 0.03 %,
fin = 1 kHz
POUT
Maximum Continuous Output Power
5
W
W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin
= 1 kHz
6.1
RL = 8 Ω + 33 µH, fin = 1 kHz
RL = 4 Ω + 33 µH, fin = 1 kHz
82
%
%
78.5
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT
= 4.2 V
System efficiency at POUT = 1 W
82.5
84.2
%
%
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT
= 4.2 V
RL = 8 Ω + 33 µH, fin = 1 kHz
RL = 4 Ω + 33 µH, fin = 1 kHz
76.6
81.1
%
%
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT
= 4.2 V
System efficiency at POUT =0.5 W
84.2
81.6
78.8
80
%
%
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT
= 4.2 V
RL = 32 Ω + 33 µH, POUT = TBD W,
fin = 1 kHz,
%
System efficiency at 0.1% THD+N
power level
RL = 8 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz,
%
RL = 4 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz
76.2
0.01
0.01
0.01
14.8
384
384
%
POUT = 0.25 W, RL = 32Ω + 33 µH, fin
= 1 kHz
%
POUT = 1 W, RL = 8 Ω + 33 µH, fin
1 kHz
=
THD+N
Total harmonic distortion + noise
Idle channel noise
%
POUT = 1 W, RL = 4 Ω + 33 µH, fin
1 kHz
=
%
A-Weighted, 20 Hz - 20 kHz, DAC
Modulator Running
VN
µV
kHz
kHz
Average frequency in Spread
Spectrum Mode, CLASSD_SYNC=0
Fixed Frequency Mode,
CLASSD_SYNC=0
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 44.1, 88.2,
174.6 kHz
FPWM
Class-D PWM switching frequency
352.8
384
kHz
kHz
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 48, 96, 192
kHz
VOS
Output offset voltage
Dynamic range
-1
1
mV
dB
DNR
A-Weighted, -60 dBFS Method
109
A-Weighted, Referenced to 1 % THD
+N Output Level
SNR
KCP
Signal to noise ratio
112.5
dB
Into and out of Mute, Shutdown,
Power Up, Power Down and audio
clocks starting and stopping.
Measured with APx Plugin.
Click and pop performance
3.4
mV
Programmable output level range
8
18
dBV
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TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Programmable output level step size
Amplifier gain error
0.5
dB
AVERROR
POUT = 1 W
±0.1
dB
Device in Shutdown or Muted in
Normal Operation
Mute attenuation
110
108
90
dB
dB
dB
dB
dB
VBAT = 3.6 V + 200 mVpp, fripple
217 Hz
=
VBAT power-supply rejection ratio
VBAT = 3.6 V + 200 mVpp, fripple = 20
kHz
VDD = 1.8 V + 200 mVpp, fripple
217 Hz
=
98
AVDD power-supply rejection ratio
VDD = 1.8 V + 200 mVpp, fripple = 20
kHz
93
No Volume Ramping
Volume Ramping
1.8
4.5
ms
ms
ms
ms
Turn on time from release of SW
shutdown
No Volume Ramping
Volume Ramping
1.5
Turn off time from assertion of SW
shutdown to amp Hi-Z
12.5
AMPLIFIER PERFORMANCE - External PVDD
Output Voltage for Full-scale digital
Input
Measured at -6 dB FS input
7.94
1.3
Vrms
W
RL = 32Ω + 33 µH, THD+N = 1 %, fin
= 1 kHz
RL = 8 Ω + 33 µH, THD+N = 1 %, fin
= 1 kHz
5.2
W
RL = 4 Ω + 33 µH, THD+N = 1 %, fin
= 1 kHz
10.4
1.6
W
POUT
Maximum Continuous Output Power
RL = 32Ω + 33 µH, THD+N = 10 %,
fin = 1 kHz
W
RL = 8 Ω + 33 µH, THD+N = 10 %, fin
= 1 kHz
6.3
W
RL = 4 Ω + 33 µH, THD+N = 10%, fin
= 1 kHz
12.6
W
RL = 8 Ω + 33 µH, fin = 1 kHz
RL = 4 Ω + 33 µH, fin = 1 kHz
83.8
80
%
%
RL = 8 Ω + 33 µH, fin = 1 kHz,
External PVDD = 8.4 V
System efficiency at POUT = 1 W
85.9
81.8
87.4
90
%
%
%
%
%
%
%
%
RL = 4 Ω + 33 µH, fin = 1 kHz,
External PVDD = 8.4 V
RL = 32 Ω + 33 µH, POUT = TBD W,
fin = 1 kHz,
RL = 8 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz,
RL = 4 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz
85.2
81.9
90
System efficiency at 0.1% THD+N
power level
RL = 32 Ω + 33 µH, POUT = TBD W,
fin = 1 kHz, External PVDD = 8.4 V
RL = 8 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz, External PVDD = 8.4 V
RL = 4 Ω + 33 µH, POUT = TBD W, fin
= 1 kHz, External PVDD = 8.4 V
86
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POUT = 0.25 W, RL = 32Ω + 33 µH, fin
= 1 kHz
0.01
%
POUT = 1 W, RL = 8 Ω + 33 µH, fin
1 kHz
=
THD+N
Total harmonic distortion + noise
0.01
0.02
21.3
384
%
%
POUT = 1 W, RL = 4 Ω + 33 µH, fin
1 kHz
=
A-Weighted, 20 Hz - 20 kHz, DAC
Modulator Running
VN
Idle channel noise
µV
Average frequency in Spread
Spectrum Mode, CLASSD_SYNC=0
kHz
kHz
Fixed Frequency Mode,
CLASSD_SYNC=0
384
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 44.1, 88.2,
174.6 kHz
FPWM
Class-D PWM switching frequency
352.8
384
kHz
kHz
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 48, 96, 192
kHz
VOS
Output offset voltage
Dynamic range
-1
1
mV
dB
DNR
A-Weighted, -60 dBFS Method
109
A-Weighted, Referenced to 1 % THD
+N Output Level
SNR
KCP
Signal to noise ratio
109.5
dB
Into and out of Mute, Shutdown,
Power Up, Power Down and audio
clocks starting and stopping.
Measured with APx Plugin.
Click and pop performance
3
mV
Programmable output level range
Programmable output level step size
Amplifier gain error
8
18
dBV
dB
0.5
AVERROR
POUT = 1 W
±0.1
dB
Device in Shutdown or Muted in
Normal Operation
Mute attenuation
110
110
90
dB
dB
dB
dB
dB
dB
dB
VBAT = 3.6 V + 200 mVpp, fripple
217 Hz
=
VBAT power-supply rejection ratio
VBAT = 3.6 V + 200 mVpp, fripple = 20
kHz
PVDD = 12 V + 200 mVpp, fripple
217 Hz
=
105
90
PVDD power-supply rejection ratio
AVDD power-supply rejection ratio
PVDD = 12 V + 200 mVpp, fripple = 20
kHz
VDD = 1.8 V + 200 mVpp, fripple
217 Hz
=
86
VDD = 1.8 V + 200 mVpp, fripple = 20
kHz
73
No Volume Ramping
Volume Ramping
2
4.8
ms
ms
ms
ms
Turn on time from release of SW
shutdown
No Volume Ramping
Volume Ramping
1.08
12.58
Turn off time from assertion of SW
shutdown to amp Hi-Z
BOOST
CONVERTER
Startup inrush current limit
default setting
default setting
1.5
A
Startup inrush limit time
0.45
ms
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
50
4
MAX
UNIT
kHz
MHz
A
PFM mode
Switching Frequency
Current Control Mode
default setting
Inductor Peak Current Limit
4
DIE TEMPERATURE
SENSOR
Resolution
8
bits
°C
°C
°C
Die temperature measurement range
Die temperature resolution
Die temperature accuracy
-40
150
0.75
±5
VOLTAGE
MONITOR
Resolution
10
bits
V
VBAT measurement range
VBAT resolution
VBAT accuracy
2
6
6
mV
mV
±25
PDM INPUT PORT
No signal, Input generated using a
4th order PDM modulator
118
128
SNR
Signal to Noise Ratio
dB
No signal, Input generated using a
5th order PDM modulator
20Hz to 20kHz, -60dBFS input
signal, A-weighted, Input generated
using a 4th order PDM modulator
117
127
DR
Dynamic Range
dB
dB
20Hz to 20kHz, -60dBFS input
signal, A-weighted, Input generated
using a 5th order PDM modulator
FR
Frequency Response
Group Delay
20Hz to 20kHz
-0.1
0
FSYNC
Cycles
GD
Input signal fs/50
TBD
TDM SERIAL AUDIO
PORT
PCM Sample Rates & FSYNC Input
Frequency
8
96
kHz
SBCLK Input Frequency
I2S/TDM Operation
0.512
24.57
MHz
RMS Jitter below 40 kHz that can be
tolerated without performance
degradation
1
ns
SBCLK Maximum Input Jitter
RMS Jitter above 40 kHz that can be
tolerated without performance
degradation
10
ns
SBCLK Cycles per FSYNC in I2S
and TDM Modes
Values: 64, 96, 128, 192, 256, 384
and 512
64
512
Cycles
PCM PLAYBACK
CHARACTERISTICS to fs ≤ 48 kHz
fs
Sample Rates
8
48
kHz
fs
Passband LPF Corner
Passband Ripple
0.454
20 Hz to LPF cutoff
≥ 0.55 fs
-0.3
0.3
dB
dB
dB
60
65
Stop Band Attenuation
≥ 1 fs
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Group Delay (ROM MODE)
Group Delay (RAM Mode)
DC to 0.454 fs
38
1/fs
DC to 0.454 fs
TBD
1/fs
PCM PLAYBACK
CHARACTERISTICS fs > 48 kHz
fs
Sample Rates
88.2
-0.5
96
0.5
kHz
fs
fs = 96 kHz
0.42
0.21
Passband LPF Corner
Passband Ripple
fs = 192 kHz
DC to LPF cutoff
≥ 0.55 fs
fs
dB
dB
dB
1/fs
60
65
Stop Band Attenuation
Group Delay (RAM Mode)
≥ 1 fs
DC to 0.375 fs for 96 kHz
TBD
CURRENT
SENSE
DNR
Dynamic range
Un-Weighted, Relative to 0 dBFS
69
dB
dB
RL = 8 Ω + 33 µH, fin = 1 kHz, POUT
= 1 W
-56
THD+N
Total harmonic distortion + noise
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT
= 1 W
-57
2.0
±1
dB
A
Full-scale input current
Current-sense accuracy
RL = 8 Ω + 33 µH, IOUT = 354 mARMS
(POUT = 1 W @ 1kHz)
%
Current-sense gain error over
temperature
0°C to 70°C, 8 Ω, using a 60Hz
-40dB pilot tone
±1
%
%
50mW to 0.1 % THD+N level, fin = 1
kHz, 8 Ω, using a 60Hz -40dB pilot
tone
Current-sense gain error over output
power
±1.5
fs = 8 kHz to 48 kHz
fs = 88.2 kHz
0.417
0.208
0.208
fs
fs
LPF passband corner
fs = 96 kHz
fs
LPF passband ripple
-0.05
0.05
dB
dB
LPF stopband attenuation
0.55 fs
60
VOLTAGE
SENSE
DNR
Dynamic range
Un-Weighted, Relative 0 dBFS
69
dB
dB
RL = 8 Ω + 33 µH, fin = 1 kHz, POUT
= 1W
-60
THD+N
Total harmonic distortion + noise
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT
= 1W
-60
14
dB
Full-scale input voltage
Voltage-sense accuracy
VPK
RL = 8 Ω + 33 µH, IOUT = 354 mARMS
(POUT = 1 W)
±0.5%
Voltage-sense gain error over
temperature
0°C to 70°C, 8 Ω, using a 60Hz
-40dB pilot tone
±0.5%
±0.5%
Voltage-sense gain error over output 50mV to 0.1 % THD+N level, 8 Ω,
power
using a 60Hz -40dB pilot tone
fs = 14.7 kHz to 48 kHz
fs = 88.2 kHz
0.417
0.208
0.208
fs
fs
fs
LPF passband corner
fs = 96 kHz
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
TA = 25 °C, VBAT = 3.6 V, (External PVDD = 12 V), VDD = 1.8 V, RL = 8Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 16
dBV (External PVDD Gain=18 dBV), SDZ = 1, Thermal Foldback Disabled, Measured filter free with an Audio Precision with
a 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LPF passband ripple
LPF stopband attenuation
-0.05
0.05
dB
0.55 fs
60
dB
VOLTAGE/CURRENT
SENSE RATIO
50mW to 0.1 % THD+N level, fin = 1
kHz, 8Ω, using a 60Hz -40dB pilot
tone
Gain ratio error over output power
±1%
Gain ratio drift over temperature
V/I phase error
0°C to 70°C
±1%
300
ns
TYPICAL CURRENT
CONSUMPTION
SDZ = 0, VBAT
1
1
µA
µA
µA
µA
mA
Current consumption in hardware
shutdown
SDZ = 0, VDD
All Clocks Stopped, VBAT
All Clocks Stopped, VDD
Clocking 0s PCM mode, VBAT
Clocking 0s PCM mode, VDD,
1
Current consumption in software
shutdown
10
2.7
10.9
11.7
mA
mA
Current consumption in idle channel DSBGA Package
Clocking 0s PCM mode, VDD, QFN
Package
fs = 48 kHz, VBAT
4.6
10.9
11.7
4.6
mA
mA
mA
mA
mA
mA
Current consumption during active
operation with IV sense disabled
fs = 48 kHz, VDD, DSBGA Package
fs = 48 kHz, VDD, QFN Package
fs = 48 kHz, VBAT
Current consumption during active
operation with IV sense enabled
fs = 48 kHz, VDD, DSBGA Package
fs = 48 kHz, VDD, QFN Package
12.5
13.3
PROTECTION
CIRCUITRY
Thermal shutdown temperature
Thermal shutdown retry
140
1.5
°C
s
UVLO is asserted
UVLO is released
2
V
VBAT undervoltage lockout threshold
(UVLO)
2.55
V
Output to Output, Output to GND,
Output to VBST or Output to VBAT
Short
Output short circuit limit
3.75
A
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UNIT
SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6.6 I2C Timing Requirements
TA = 25 °C, VDD = 1.8 V (unless otherwise noted)
MIN
NOM
MAX
Standard-Mode
fSCL
SCL clock frequency
0
4
100
kHz
μs
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
4.7
4
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
0
3.45
250
SDA and SCL rise time
1000
300
tf
SDA and SCL fall time
tSU;STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
4
4.7
Cb
400
400
Fast-Mode
fSCL
SCL clock frequency
0
kHz
μs
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
0.6
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
1.3
0.6
0.6
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
0.9
100
20 + 0.1 ×
Cb
tr
tf
SDA and SCL rise time
SDA and SCL fall time
300
300
ns
ns
20 + 0.1 ×
Cb
tSU;STO
tBUF
Set-up time for STOP condition
0.6
1.3
μs
μs
pF
Bus free time between a STOP and START condition
Capacitive load for each bus line
Cb
400
Fast-Mode
Plus
fSCL
SCL clock frequency
0
1000
kHz
μs
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
0.26
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
0.5
0.26
0.26
0
μs
μs
μs
μs
ns
ns
ns
μs
μs
pF
50
SDA and SCL Rise Time
120
120
tf
SDA and SCL Fall Time
tSU;STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
0.5
Cb
TBD
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6.7 SPI Timing Requirements
For SPI interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications
are specified by design but not tested at final test.
IOVDD = 1.8 IOVDD = 3.3
V
V
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN MAX MIN MAX
tsck
SCLK Period
60
30
30
60
60
60
50
25
25
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kΩ
tsckh
tsckl
tlead
ttrail
SCLK Pulse width High
SCLK Pulse width Low
Enable Lead Time
Enable Trail Time
td;seqxfr
ta
Sequential Transfer Delay
Slave DOUT access time
Slave DOUT disable time
DIN data setup time
35
35
25
25
tdis
tsu
8
8
8
8
th;DIN
tv;DOUT
tr
DIN data hold time
DOUT data valid time
SCLK Rise Time
35
4
25
4
tf
SCLK Fall Time
4
4
Pd-spi
External Pullup on SPII2CSELZ_MISO_PAD
18
18
6.8 PDM Port Timing Requirements
TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MIN
20
3
NOM
MAX
UNIT
tSU(PDM) PDM IN setup time
tHLD(PDM) PDM IN hold time
ns
ns
ns
ns
tr(PDM)
tf(PDM)
PDM IN rise time
PDM IN fall time
10 % - 90 % Rise Time
90 % - 10 % Fall Time
4
4
6.9 TDM Port Timing Requirements
TA = 25 °C, VDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MIN
20
NOM
MAX
UNIT
ns
tH(SBCLK)
tL(SBCLK)
SBCLK high period
SBCLK low period
20
ns
tSU(FSYNC) FSYNC setup time
tHLD(FSYNC) FSYNC hold time
tSU(FSYNC) SDIN setup time
6.5
6.5
6.5
6.5
ns
ns
ns
tHLD(SDIN)
SDIN hold time
ns
td(DO-
SBCLK)
SBCLK to SDOUT delay
50% of SBCLK to 50% of SDOUT
29
ns
tr(SBCLK)
tf(SBCLK)
SBCLK rise time
SBCLK fall time
10% - 90 % Rise Time
90% - 10 % Fall Time
8
8
ns
ns
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6.10 Timing Diagrams
SDA
tBUF
tLOW
tr
th(STA)
SCL
th(STA)
th(DAT)
tHIGH
tsu(STA)
tsu(STO)
STO
STA
tf
tsu(DAT)
STA
STO
Figure 6-1. I2C Timing Diagram
FSYNC
tSU(FSYNC)
td(DO-FSYNC)
tHLD(FSYNC)
tL(SBCLK)
SBCLK
SDIN
tH(SBCLK)
tHLD(SDIN)
tr(SBCLK)
tf(SBCLK)
tSU(SDIN)
td(DO-SBCLK)
SDOUT
Figure 6-2. TDM Timing Diagram
tSU(PDM)
tHLD(PDM)
tSU(PDM)
tHLD(PDM)
PDM CLK
PDM IN
tr
tf
Falling Edge Captured
Rising Edge Captured
Figure 6-3. PDM Timing Diagram
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
SS
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv(DOUT)
tdis
MSB OUT
th(DIN)
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 6-4. SPI Interface Timing Diagram
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SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
6.11 Typical Characteristics
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load
Resistance is 30 µH, unless otherwise noted.
100
100
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT = 3.1 V
VBAT = 3.6 V
VBAT = 4.2 V
VBAT = 5.5 V
10
10
1
1
0.1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
Pout (W)
1
10
0.001
0.01
0.1
POUT (W)
1
10
D002
RL = 8 Ω + 30 µH
FIN = 1 kHz
RL = 4 Ω + 30 µH
FIN = 1 kHz
Figure 6-6. THD+N vs Output Power
Figure 6-5. THD+N vs Output Power
10
10
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
1
0.1
1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
Pout (W)
1
10 20
0.001
0.01
0.1
Pout (W)
1
10 20
D003
D004
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-7. THD+N vs Output Power
Figure 6-8. THD+N vs Output Power
100
100
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
10
1
10
1
0.1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
Pout (W)
1
10
0.001
0.01
0.1
Pout (W)
1
10
D005
D006
RL = 4 Ω + 30 µH
FIN = 6.667 kHz
RL = 8 Ω + 30 µH
FIN = 6.667 kHz
Figure 6-9. THD+N vs Output Power
Figure 6-10. THD+N vs Output Power
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10
10
1
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
1
0.1
0.1
0.01
0.01
0.001
0.001
0.001
0.01
0.1
Pout (W)
1
10 20
0.001
0.01
0.1
Pout (W)
1
10 20
D007
D008
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-11. THD+N vs Output Power
Figure 6-12. THD+N vs Output Power
10
10
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
1
0.1
1
0.1
0.01
0.01
0.001
0.001
20
100
1000
Frequency (Hz)
1000020000
20
100
1000
Frequency (Hz)
1000020000
D009
D010
RL = 4 Ω + 30 µH
P = 0.1 W
RL = 8 Ω + 30 µH
P = 0.1 W
Figure 6-13. THD+N vs Frequency
Figure 6-14. THD+N vs Frequency
10
1
10
1
VBAT=3.1V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1000
Frequency (Hz)
1000020000
20
100
1000
Frequency (Hz)
1000020000
D012
D011
RL = 8 Ω + 30 µH
P = 1 W
RL = 4 Ω + 30 µH
P = 1 W
Figure 6-16. THD+N vs Frequency
Figure 6-15. THD+N vs Frequency
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20
24
23
22
21
20
19
18
17
16
15
14
ICN A weighted(mV)
19
18
17
16
15
14
13
12
11
10
2.7
3.7
4.7
5.7
2
3
4
5
6
7
8
9
PVDD Supply (V)
10 11 12 13 14 15 16
VBAT Supply (V)
D015
D016
Figure 6-17. Idle Channel Noise (A-Weighted) vs
VBAT
Figure 6-18. Idle Channel Noise (A-Weighted) vs
PVDD
9.2
13
PVDD=8.4V
PVDD=12.6V
12
9
11
10
9
8.8
8.6
8.4
8.2
8
8
7
6
20
100
1000
Frequency (Hz)
10000 30000
0.1
1
THD+N (%)
10
D017
D018
RL = 8 Ω + 30 µH
FS = 48 kHz
RL = 4 Ω + 30 µH
Figure 6-19. Amplitude vs Frequency
Figure 6-20. Max Output Power vs THD+N
6.5
6
100
PVDD=8.4V
PVDD=12.6V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
90
80
VBAT=5.5V
70
5.5
5
60
50
40
30
20
10
0
4.5
4
3.5
0.0005
0.01
0.1
Pout (W)
1
10
0.1
1
THD+N (%)
10
D020
D019
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
Figure 6-22. Efficiency vs Output Power
Figure 6-21. Max Output Power vs THD+N
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100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
0.0001
0.001
0.01
0.1
Pout (W)
1
10 20
0.0005
0.01
0.1
Pout (W)
1
10
D022
D021
RL = 4 Ω + 30 µH
FIN = 1 kHz
Bypass Mode
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-24. Efficiency vs Output Power
Figure 6-23. Efficiency vs Output Power
100
110
90
80
70
60
50
40
30
20
10
105
100
95
90
0
0.0001
85
20
0.001
0.01
Pout (W)
0.1
1
10
100
1000
Frequency (Hz)
1000020000
D023
D024
RL = 8 Ω + 30 µH
FIN = 1 kHz
Bypass Mode
RL = 8 Ω + 30 µH
Idle Channel
Figure 6-25. Efficiency vs Output Power
Figure 6-26. AVDD PSRR vs Frequency
140
130
PVDD=2.5V
PVDD=8.4V
PVDD=12V
PVDD=16V
126
122
118
114
110
106
102
98
120
100
80
60
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.4V
40
94
20
90
20
100
1000
Frequency (Hz)
1000020000
10
100
1000
Frequency (Hz)
10000 30000
D025
D026
RL = 8 Ω + 30 µH
Idle Channel
RL = 8 Ω + 30 µH
Idle Channel
Figure 6-27. VBAT PSRR vs Frequency
Figure 6-28. PVDD PSRR vs Frequency
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11
10.98
10.96
10.94
10.92
10.9
10
9
8
7
6
5
4
3
2
1
Idle Channel Input
10.88
10.86
10.84
10.82
10.8
1.65
1.7
1.75
1.8
AVDD (V)
1.85
1.9
1.95
2.5
3
3.5 4
VBAT Voltage (V)
4.5
5
5.5
D027
D028
Idle Channel
Idle Channel
Figure 6-29. AVDD Idle Current vs AVDD
Figure 6-30. VBAT Idle Current vs VBAT
100
100
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
10
1
10
1
0.1
0.1
0.01
0.01
0.001
0.01
0.1
Pout (W)
1
10
0.001
0.01
0.1
Pout (W)
1
10
D030
D031
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-31. I-sense THD+N vs Output Power
Figure 6-32. I-sense THD+N vs Output Power
5
4
3.2
2.4
1.6
0.8
0
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
4
3
VBAT=5.5V
2
1
0
-0.8
-1
-2
-3
-4
-5
-1.6
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
-2.4
-3.2
-4
0.01
0.1
1
10
0.01
0.1
1
10
Pout (W)
Pout (W)
D035
D034
RL = 8 Ω + 30 µH
FIN = 1 kHz
RL = 4 Ω + 30 µH
FIN = 1 kHz
Figure 6-34. I-sense Linearity vs Output Power
Figure 6-33. I-sense Linearity vs Output Power
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10
10
1
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
1
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1000
Frequency (Hz)
1000020000
20
100
1000
Frequency (Hz)
1000020000
D038
D039
RL = 4 Ω + 30 µH
P = 1 W
RL = 8 Ω + 30 µH
P = 1 W
Figure 6-35. I-sense THD+N vs Frequency
Figure 6-36. I-sense THD+N vs Frequency
50
10
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
10
1
1
0.1
0.1
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
0.01
0.01
0.001
0.01
0.1
Pout (W)
1
10
0.001
0.01
0.1
Pout (W)
1
10
D042
D043
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-37. V-sense THD+N vs Output Power
Figure 6-38. V-sense THD+N vs Output Power
4
4
VBAT=3.1V
VBAT=3.6V
VBAT=3.1V
VBAT=3.6V
3.2
3.2
VBAT=4.2V
VBAT=5.5V
VBAT=4.2V
VBAT=5.5V
2.4
1.6
2.4
1.6
0.8
0
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
0.01
0.1
1
10
0.01
0.1
1
10
Pout (W)
Pout (W)
D046
D047
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-39. V-sense Linearity vs Output Power
Figure 6-40. V-sense Linearity vs Output Power
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10
10
1
VBAT=3.1V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
1
0.1
0.1
0.01
0.001
0.01
20
100
1000
Frequency (Hz)
1000020000
20
100
1000
Frequency (Hz)
1000020000
D051
D050
RL = 8 Ω + 30 µH
P = 1 W
RL = 4 Ω + 30 µH
P = 1 W
Figure 6-42. V-sense THD+N vs Frequency
Figure 6-41. V-sense THD+N vs Frequency
4
4
VBAT=3.1V
VBAT=3.6V
VBAT=3.1V
VBAT=3.6V
3.2
3.2
VBAT=4.2V
VBAT=5.5V
VBAT=4.2V
VBAT=5.5V
2.4
1.6
2.4
1.6
0.8
0
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
0.01
0.1
1
10
0.01
0.1
1
10
Pout (W)
Pout (W)
D054
D055
RL = 4 Ω + 30 µH
FIN = 1 kHz
RL = 8 Ω + 30 µH
FIN = 1 kHz
Figure 6-43. V/I-sense Linearity vs Output Power
Figure 6-44. V/I-sense Linearity vs Output Power
4
4
VBAT=3.1V
VBAT=3.6V
VBAT=3.1V
VBAT=3.6V
3.2
3.2
VBAT=4.2V
VBAT=5.5V
VBAT=4.2V
VBAT=5.5V
2.4
1.6
2.4
1.6
0.8
0
0.8
0
-0.8
-1.6
-2.4
-3.2
-4
-0.8
-1.6
-2.4
-3.2
-4
-25
0
25
Temperature (èC)
50
75
-25
0
25
Temperature (èC)
50
75
D058
D059
RL = 8 Ω + 30 µH
P = 1 W
RL = 8 Ω + 30 µH
P = 1 W
Figure 6-45. I-sense Linearity vs Temperature
Figure 6-46. V-sense Linearity vs Temperature
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4
3.2
2.4
1.6
0.8
0
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
-0.8
-1.6
-2.4
-3.2
-4
-25
0
25
Temperature (èC)
50
75
D060
RL = 8 Ω + 30 µH
P = 1 W
Figure 6-47. V/I-sense Linearity vs Temperature
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7 Parameter Measurement Information
DF2SE
R11
OUT1+
OUT1-
VSENSE1+
VSENSE1-
0
R12
0
1.8V
VBAT
VBAT1
C22
0.01uF
C23
4.7uF
C19
10µF
25V
C18
10µF
25V
C17
0.1µF
R22
0
C47
1µF
OUT1+
OUT1-
J12
VDD1
R23
0
C48
1µF
J10
VBAT1
GND
GND
IOVDD
GND
GND
GND
SNUBBER
GND
C24
0.01uF
C25
1µF
U1
L2
OUT1+
J14
D1
D2
F5 OUT-1P
D5 VSNS_P1
R9
0
0
VBAT
OUT_P
J13
IOVDD1
VBAT
R18
1uH
VSNS_P
OUT1+
OUT1-
GND
GND
F1
F2
F3
C46
1µF
OUT1+
OUT1-
SW
SW
SW
SW1
D3 VSNS_N1
F6 OUT-1N
R19
R10
0
0
VSNS_N
OUT_N
OUT1
OUT1-
VDD1
IOVDD1
C6
A6
VDD
IOVDD
TP6
PVDD1
C20
C21
PVDD1
G1
G2
G3
VBST
VBST
VBST
C26
1µF
16V
C27
10µF
25V
C28
10µF
25V
C1 SDOUT1
SDOUT1
SDOUT2
ASI1
SBCLK1
FSYNC
SDIN1
AUX Connector
J11
GND
GND
G4
G5
G6
A3 SDOUT2-1
PVDD
PVDD
PVDD
OUT1+
OUT1-
GND
GND
GND
SBCLK1
FSYNC
SDIN1
B2
B3
C2
C5 IRQ1
SBCK1
IRQ
DREG
GREG
GPIO
OUT1
FSYNC
SDIN1
ASI2
SDOUT2-2
B6 DREG1
D4 GREG1
SBCLK1
SDOUT2-2
A5
A4
SBCLK2
SDIN2
J15
D6
GPIO1
SDOUT1
SDOUT2-1
1
3
2
4
PCMCK1
PDMD1
A1
A2
PDMCK
PDMD
ASI1/ASI2
CONTROL
F4
E6
E5
E4
E3
E2
E1
GNDD
GNDP
GNDP
GNDD
GNDB
GNDB
GNDB
PDM1
SCL_SEL1
SDA_MOSI
B4
B5
SCL_SEL
SDA_MOSI
GND
IRQ1
SD
SPII2C_MISO
B1
C3
SD
SPII2C_MISO
ADDR_SPICLK
SD
CONTROL
ADDR_SPICLK1 C4
C29
1µF
C44
0.01uF
I2C/SPI
TAS2563YBG
GND
SCL_SEL1
Address = 0x98
GND
GND
SDA_MOSI
SPII2C_MISO
C30
PVDD1
0.1µF
ADDR_SPICLK1
Figure 7-1. TAS2563 Circuit
All typical characteristics for the devices are measured using the Bench EVM and an Audio Precision SYS-2722
Audio Analyzer. A PSIA interface is used to allow the I2S interface to be driven directly into the SYS-2722.
Speaker output terminals are connected to the Audio-Precision analyzer analog inputs through a differential-to-
single ended (D2S) filter as shown below. The D2S filter contains a 1st order Passive pole at 120 kHz. The D2S
filter ensures the TAS2563 high performance class-D amplifier sees a fully differential matched loading at its
outputs. This prevents measurement errors due to loading effects of AUX-0025 filter on the class-D outputs.
1kΩ
0.01%
1kΩ
0.01%
-
1kΩ
SPK_P
+
-
AP
680pF
AUX-0025
SYS-2772
+
SPK_N
1kΩ
0.01%
+
-
1kΩ
1kΩ
0.01%
Figure 7-2. Differential To Single Ended (D2S) Filter
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8 Detailed Description
8.1 Overview
The TAS2563 is a mono digital input Class-D amplifier optimized for mobile applications where efficient battery
operation and small solution size are crucial. It integrates speaker voltage and current sensing and battery
tracking limiting with brown out prevention.
8.2 Functional Block Diagram
1.8V / 3.3V
1.8V
2.7V œ 5.5V
10uF
1uF
4.7uF
1uF
VBAT
IOVDD
VDD
DREG
1uH
SDZ
Power Management
SW
Boost
BGND
VBST
OTP Trim
PVDD
SAR
ADC
Brown Out
Protection
IRQZ
VBAT
TEMP
100nF
10uF
Gate
Drive
CP
GREG
MCLK
SDIN
SDOUT
FSYNC
SBCLK
TDM
Port
Smart AMP
DSP
PVDD
DAC
Class-D +
I-V Sense
PDMCLK
PDMD
PDM
Port
I-V Sense
ADCs
SDIN2
VSNS_P
IC
Link
SDOUT2
SBCLK2
Clock
Watchdog
& Timers
Reference &
Temp
Protection
OUTP
OUTN
I2C / SPI Port
VSNS_N
ADDR / SPII2CZ / SDA /
SCLK MISO MOSI
SCL /
SELZ
PLL
PGND
GND
Figure 8-1. Functional Block Diagram
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1.8V / 3.3V
1.8V
2.7V œ 5.5V
10uF
1uF
4.7uF
1uF
VBAT
IOVDD
VDD
DREG
1uH
SDZ
Power Management
SW
Boost
BGND
VBST
OTP Trim
PVDD
SAR
ADC
Brown Out
Protection
IRQZ
VBAT
TEMP
100nF
10uF
Gate
Drive
CP
GREG
MCLK
SDIN
SDOUT
FSYNC
SBCLK
TDM
Port
Smart AMP
DSP
PVDD
DAC
Class-D +
I-V Sense
PDMCLK
PDMD
PDM
Port
I-V Sense
ADCs
VSNS_P
Clock
Watchdog
& Timers
Reference &
Temp
Protection
OUTP
OUTN
I2C / SPI Port
VSNS_N
ADDR / SPII2CZ / SDA /
SCLK MISO MOSI
SCL /
SELZ
PLL
PGND
GND
Figure 8-2. TAS2563 QFN Functional Block Diagram
8.3 Feature Description
8.3.1 PurePath™ Console 3 Software
The TAS2563 advanced features and device configuration should be performed using PurePath Console 3
(PPC3) software. The base software PPC3 is downloaded and installed from the TI website. Once installed the
TAS2563 application can be download from with-in PPC3. The PCC3 tool will calculate necessary register
coefficients that are described in the following sections. It is the recommended method to configure the device.
Once the TAS2563 application calculates and updates the device, the registers values can be read back using
the PPC3 tool for final system integration.
8.3.2 Device Mode and Address Selection
The TAS2563 has a global 7-bit I2C address 0x48. When enabled the device will additionally respond to I2C
commands at this address once it is put in I2C Mode. This is used to speed up device configuration when using
multiple TAS2563 devices and programming similar settings across all devices. The I2C ACK / NACK cannot be
used during the multi-device writes since multiple devices are responding to the I2C command. The I2C CRC
function should be used to ensure each device properly received the I2C commands. At the completion of writing
multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device
using the local address for a proper value. The global I2C address can be disabled using I2C_GBL_EN register.
The I2C address is detected by sampling the address pins when SDZ pin is released. Additionally, the address
may be re-detected by setting I2C_AD_DET high after power up and the pins will be resampled.
Table 8-1. I2C Global Address Enable
I2C_GBL_EN
SETTING
Disabled
0
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Table 8-1. I2C Global Address Enable (continued)
I2C_GBL_EN
SETTING
Enabled (default)
1
Table 8-2. I2C Global Address Detection
I2C_AD_DET
SETTING
normal (default)
0
Re-detect
1
8.3.3 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system using serial data transmission. The address and data 8-bit bytes are transferred most-significant bit
(MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an
acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and
ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal
(SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA
indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the
low time of the clock period. shows a typical sequence.
To configure the TAS2563 for I2C operation set the SPII2CZ_MISO pin to ground. The I2C address can then be
set using pins ADDR_SPICLK according to Table 8-3. The pin configures the two LSB bits of the following 7-bit
binary address A6-A0 of 10011xx. This permits the I2C address of TAS2563 to be 0x4C(7-bit) through 0x4F(7-
bit). For example, if ADDR_SPICLK is connected to ground the I2C address for the TAS2563 would be 0x4C(7-
bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading. The ADDR_SPICLK should be only
pulled high to the IOVDD pin voltage.
Table 8-3. I2C Mode Address Selection
I2C SLAVE ADDRESS
ADDR_SPICLK PIN
0x48 (global address)
NA
0x4C
0x4D
0x4E
0x4F
GND
10k to GND
10k to VDD
VDD
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock
period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bi-directional bus using a wired-AND connection.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull Up
Resistor can be calculated as per the table below. For Capacitive Loads different from mentioned below in table,
use interpolated values.
Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD. The I2C pins are fault
tolerant and will not load the I2C bus when the device is powered down.
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Table 8-4. I2C Pull Up Resistor Selection
I2C Mode of Operation
Capacitive Load
Recommended Pull Up Resistor
10pF
500 Ω to 4.7 KΩ
Standard/Fast
400pF
500 Ω to 1 KΩ
10pF
500 Ω to 4 KΩ
Fast Mode Plus
550pF
350 Ω to 400 Ω
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 8-3. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. Figure 8-3 shows a generic data
transfer sequence.
8.3.4 General SPI Operation
The TAS2563 operates as an SPI slave over the IOVDD voltage range. To enable SPI mode the SPII2CZ_MISO
pin is pulled to IOVDD using a resistor. During the device power up the pin state is queried and if high will enter
SPI mode.
In the SPI control mode, the TAS2563 uses the terminals SCL_SELZ as SS, ADDR_SPICLK as SCLK,
SPII2CZ_MISO as MISO, SDA_MOSI as MOSI; The SPI port allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this
case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The
SPI slave device depends on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI terminal under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI terminal, a byte shifts out
on the MISO terminal to the master shift register.
The TAS2563 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI control
bit CPHA = 1), the master begins driving its MOSI terminal and the slave begins driving its MISO terminal on the
first serial clock edge. The SSZ terminal can remain low between transmissions; however, the TAS2563 only
interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and the next 8 bits as a
data byte only if writing to a register. Reserved register bits should be written to their default values. The
TAS2563 is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-bit
command sent to the MOSI terminal of the part prior to the data for that register. The command is structured as
shown in Table 8-5 below. The first 7 bits specify the address of the register which is being written or read, from
0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the
serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is sent to the
MOSI terminal and contains the data to be written to the register. Reading of registers is accomplished in a
similar fashion. The 8-bit command word sends the 7-bit register address, followed by the R/W bit = 1 to signify a
register read is occurring. The 8-bit register data is then clocked out of the part on the MISO terminal during the
second 8 SCLK clocks in the frame.
Table 8-5. Command Word
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR(6)
ADDR(5)
ADDR(4)
ADDR(3)
ADDR(2)
ADDR(1)
ADDR(0)
R/WZ
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SS
SCLK
MOSI
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7-bit Register Address
Write
8-bit Register Data
Hi-Z
Hi-Z
MISO
Figure 8-4. SPI Timing Diagram for Register Write
SS
SCLK
MOSI
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
Don’t Care
7-bit Register Address
Read
8-bit Register Data
Hi-Z
Hi-Z
MISO
D(7)
D(6)
D(0)
Figure 8-5. SPI Timing Diagram for Register Read
8.3.5 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the TAS2563 responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
The TAS2563 supports sequential I2C addressing. For write transactions, if a register is issued followed by data
for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For
I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
8.3.6 Single-Byte Write
As shown in Figure 8-6, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TAS2563 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the device internal memory address being accessed. After receiving
the register byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single-byte data-write transfer.
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Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
Figure 8-6. Single-Byte Write Transfer
8.3.7 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TAS2563 as shown in Figure 8-7. After receiving each data byte, the
device responds with an acknowledge bit.
Register
Figure 8-7. Multi-Byte Write Transfer
8.3.8 Single-Byte Read
As shown in Figure 8-8, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TAS2563 address and the read/write bit, the device responds with an acknowledge bit. The
master then sends the internal memory address byte, after which the device issues an acknowledge bit. The
master device transmits another start condition followed by the TAS2563 address and the read/write bit again.
This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2563 transmits the data byte from
the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
Figure 8-8. Single-Byte Read Transfer
8.3.9 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS2563 to the master device as shown in Figure 8-9. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
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Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
Condition
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Figure 8-9. Multi-Byte Read Transfer
8.3.10 Register Organization
Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes
and each book contains 256 pages. All device configuration registers are stored in book 0, page 0, which is the
default setting at power up (and after a software reset). The book and page can be set by the BOOK[7:0] and
PAGE[7:0] registers respectively.
8.3.11 Operational Modes
8.3.11.1 Hardware Shutdown
The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the
device consumes the minimum quiescent current from VDD and VBAT supplies. All registers loose state in this
mode and I2C communication is disabled.
In normal shutdown mode if SDZ is asserted low while audio is playing, the device will ramp down volume on the
audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware
Shutdown mode. If configured in normal with timeout shutdown mode the device will force a hard shutdown after
a timeout of the configurable shutdown timer. Finally the device can be configured for hard shutdown and will not
attempt to gracefully stop the audio channel.
Table 8-6. Shutdown Control
SDZ_MODE[1:0]
SETTING
Normal Shutdown with Timer
(default)
00
Immediate Shutdown
Normal Shutdown
Reserved
01
10
11
Table 8-7. Shutdown Control
SDZ_TIMEOUT[1:0]
SETTING
2 ms
00
4 ms
01
10
6 ms (default)
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Table 8-7. Shutdown Control (continued)
SDZ_TIMEOUT[1:0]
SETTING
23.8 ms
11
When SDZ is released, the device will sample the AD0 and AD1 pins and enter the software shutdown mode.
8.3.11.2 Software Shutdown
Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the
device to loose register state. Software Shutdown is enabled by asserting the MODE[1:0] register bits to 2'b10. If
audio is playing when Software Shutdown is asserted, the Class-D will volume ramp down before shutting down.
When deasserted, the Class-D will begin switching and volume ramp back to the programmed digital volume
setting.
8.3.11.3 Mute
The TAS2563 will volume ramp down the Class-D amplifier to a mute state by setting the MODE[1:0] register bits
to 2'b01. During mute the Class-D still switches, but transmits no audio content. If mute is deasserted, the device
will volume ramp back to the programmed digital volume setting.
8.3.11.4 Active
In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational
if enabled. Set the MODE[1:0] register bits to 2'b00 to enter active mode.
8.3.11.5 Perform Load Diagnostics
In Load Diagnostics Mode, TAS2563 checks the speaker terminal for an open or short. This can be used to
determine if a problem exists with the speaker or trace to the speaker. The entire operation is performed by the
TAS2563 and results reported using the IRQZ pin or read over I2C bus on completion. Set the MODE[1:0]
register bits to 2'b11 to enter load diagnostics mode.
8.3.11.6 Mode Control and Software Reset
The TAS2563 mode can be configured by writing the MODE[1:0] bits.
Table 8-8. Mode Control
MODE[1:0]
SETTING
Section 8.3.11.4
00
Section 8.3.11.3
Section 8.3.11.2 (default)
Section 8.3.11.5
01
10
11
A software reset can be accomplished by asserting the SW_RESET bit, which is self clearing. This will restore all
registers to their default values.
Table 8-9. Software Reset
SW_RESET
SETTING
Don't reset (default)
0
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Table 8-9. Software Reset (continued)
SW_RESET
SETTING
Reset
1
8.3.12 Faults and Status
During the power-up sequence, the power-on-reset circuit (POR) monitoring the VDD and VBAT pins will hold
the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware
shutdown until VDD and VBAT are valid and the SDZ pin is released. Once SDZ is released, the digital core
voltage regulator will power up, enabling detection of the operational mode. If VDD dips below the POR
threshold, the device will immediately be forced into a reset state.
The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the
UVLO threshold. If the TAS2563 is in active operation and a UVLO fault occurs, the analog supplies will
immediately power down to protect the device. These faults are latching and require a transition through HW/SW
shutdown to clear the fault. The live and latched registers will report UVLO faults.
The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:
• Invalid SBCLK to FSYNC ratio
• Invalid FSYNC frequency
• Halting of SBCLK or FSYNC clocks
Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible
to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to
its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt
mask register bit is set low (INT_MASK[2]). The clock fault is also available for readback in the live or latched
fault status registers (INT_LIVE[2] and INT_LTCH[2]). Reading the latched fault status register (INT_LTCH[7:0])
clears the register.
The TAS2563 also monitors die temperature and Class-D load current and will enter software shutdown mode if
either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if
the appropriate fault interrupt mask register bit is set low (INT_MASK[0] for over temp and INT_MASK[1] for over
current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.
Die over temp and Class-D over current errors can either be latching (for example the device will enter software
shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a
prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over
temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over
temp or over current error until the retry time period (1.5 s) has elapsed. This prevents applying repeated stress
to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW
shutdown, the device will only begin to operate after the retry time period.
The status registers (and IRQZ pin if enabled via the status mask register) also indicates limiter behavior
including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has
been applied, when the limiter is in infinite hold and when the limiter has muted the audio.
Interrupts can be queried using the INT_LIVE[9:0] and INT_LTCH[13:0] registers and correspond to the
INT_MASK[10:0] Interrupts. The latched registers are cleared by writing the self clearing register
INT_CLR_LTCH high.
The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be
pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2563 and can be accessed
by setting the IRQZ_PU register bit high. Figure 8-10 below highlights the IRQZ pin circuit.
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IOVDD
IOVDD
IRQZ_PU
To
System
Master
IRQZ
Interrupt
Figure 8-10. IRQZ Pin
Table 8-10. Fault Interrupt Mask
INT_MASK[10:0] BIT
INTERRUPT
DEFAULT (1 = Mask)
0
Over Temp Error
0
0
1
Over Current Error
TDM Clock Error
Limiter Active
2
1
3
1
4
Limter Voltage < Inf
Point
1
5
Limiter Max Atten
Limiter Inf Hold
Limiter Mute
1
6
1
7
1
8
Brown Out on VBAT
Supply
0
9
Brown Out Protection
Active
1
10
11:12
13
Brown Out Power
Down (Latched Only)
1
Speaker Open Load
(Latched Only)
00
1
Load Diagnostic
Complete (Latched
Only)
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Table 8-11. IRQ Clear Latched
INT_CLR_LTCH
STATE
Don't Clear
0
Clear (self clearing)
1
Table 8-12. IRQZ Internal Pull Up Enable
IRQZ_PU
STATE
Disabled (default)
0
Enabled
1
Table 8-13. IRQZ Polarity
IRQZ_POL
STATE
Active High
0
Active Low (default)
1
Table 8-14. IRQZ Assert Interrupt Configuration
IRQZ_PIN_CFG[1:0]
VALUE
On any unmasked live interrupts
00
On any unmasked latched
interrupts (default)
01
10
11
For 2-4 ms one time on any
unmasked live interrupt event
For 2-4 ms every 4 ms on any
unmasked latched interrupts
Table 8-15. Retry after Over Current Event
OCE_RETRY
STATE
Disabled (default)
0
Enabled
1
Table 8-16. Retry after Over Temperature Event
OTE_RETRY
VALUE
Do not retry (default)
0
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Table 8-16. Retry after Over Temperature Event
(continued)
OTE_RETRY
VALUE
Retry after 1.5s
1
8.3.13 Power Sequencing Requirements
There are no other power sequencing requirements for order of rate of ramping up or down.
8.3.14 Digital Input Pull Downs
Each digital input and IO has an optional weak pull down to prevent the pin from floating. Pull downs are not
enabled during HW shutdown.
Table 8-17. Digital Input Pull Down Enables
REGISTER BIT
DESCRIPTION
BIT VALUE
STATE
0
Disabled (default)
DIN_PD[0]
Weak pull down for SBCLK.
1
0
1
0
1
0
1
0
1
0
1
Enabled
Disabled (default)
Enabled
DIN_PD[1]
DIN_PD[2]
DIN_PD[3]
DIN_PD[4]
DIN_PD[5]
Weak pull down for FSYNC.
Weak pull down for SDIN.
Weak pull down for SDOUT.
Weak pull down forAD0.
Weak pull down for AD1.
Disabled (default)
Enabled
Disabled (default)
Enabled
Disabled (default)
Enabled
Disabled(default)
Enabled
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Table 8-17. Digital Input Pull Down Enables (continued)
REGISTER BIT
DESCRIPTION
BIT VALUE
STATE
0
Disabled
DIN_PD[7]
Weak pull down for GPIO.
1
Enabled (default)
8.4 Device Functional Modes
8.4.1 PDM Input
The TAS2563 provides one PDM input. Figure 8-11 below illustrates the double data rate nature of the PDM
input. It has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of
the clock.
PDM CLK
PDM DATA
Rising
Channel
Falling
Channel
Figure 8-11. PDM Waveform
The PDM inputs are sampled by the PDMCLK pin, which can be configured as either a PDM clock slave input or
a PDM clock master output. The PDM_MIC_EDGE and PDM_MIC_SLV register bits select the sample clock
edge and master/slave mode PDM inputs. In master mode the PDMCLK pin can disable the clocks (and drive a
logic 0) by setting the PDM_GATE_PAD0 register bits low.
When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the
system clock (SBCLK in TDM/I2S Mode), but must be from the same source as audio sample rate. This is
equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed sample rate. The
PDM rate is set by the PDM_RATE_PAD0 .
When PDMCLK pin is configured as a clock master, the TAS2563 will output a 50% duty cycle clock of frequency
that is set by the PDM_RATE_PAD0 and register bit (64/32/16 or 128/64/32 times a single/double/quadruple
speed sample rate).
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Table 8-18. PDM Clock Slave
PDM INPUT
PIN
REGISTER BIT
VALUE
MASTER/
SLAVE
0
Master
PDMD
PDM_MIC_SLV
1
Slave (default)
Table 8-19. PDM Master Mode Clock Gate
PDM CLOCK REGISTER BIT
PIN
VALUE
GATING
Gated Off
(default)
1
PDM_GATE_PA
PDMCLK
D0
0
Active
Table 8-20. PDM Input Sample Rate
PDM INPUT
PIN
REGISTER
BITS
VALUE
SAMPLE RATE
3.072 MHz
(default)
0
PDM_RATE_PA
D0
PDMD
1
6.144 MHz
Table 8-21. PDM MIC Enable
PDM_MIC_EN
MAPPING
Disable MIC2
Enable MIC2
Disable MIC1
Enable MIC1
PDM_MIC2_EN= 0
PDM_MIC2_EN= 1
PDM_MIC1_EN= 0
PDM_MIC1_EN= 1
8.4.2 TDM Port
The TAS2563 provides a flexible TDM serial audio port. The port can be configured to support a variety of
formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The
SDOUT pin is used to transmit sample streams including speaker voltage and current sense, VBAT voltage, die
temperature and channel gain.
The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96 kHz
sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in
width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, 256,
384 and 512. The device will automatically detect the number of time slots and this does not need to be
programmed.
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By default, the TAS2563 will automatically detect the PCM playback sample rate. This can be disabled by setting
the AUTO_RATE register bit high and manually configuring the device.
The SAMP_RATE[2:0] register bits set the PCM audio sample rate when AUTO_RATE is enabled. The TAS2563
employs a robust clock fault detection engine that will automatically volume ramp down the playback path if
FSYNC does not match the configured sample rate (AUTO_RATE enabled) or the ratio of SBCLK to FSYNC is
not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and
ratio, the device will automatically volume ramp the playback path back to the configured volume and resume
playback.
When using the auto rate detection the sampling rate and SBCLK to FSYNC ratio detected on the TDM bus is
reported back on the read-only register FS_RATE and FS_RATIO respectively.
While the sampling rate of 192 kHz is supported, it is internally down-sampled to 96 kHz. Therefore audio
content greater than 40 kHz should not be applied to prevent aliasing. This additionally affects all processing
blocks like BOP and limiter which should use 96 kHz fs when accepting 192 kHz audio. It is recommend to use
Section 8.3.1 to configure the device.
Table 8-22. PCM Auto Sample Rate Detection
AUTO_RATE
SETTING
Enabled (default)
0
Disabled
1
Table 8-23. PCM Audio Sample Rates
SAMP_RATE[2:0] FS_RATE(read only)
SAMPLE RATE
Reserved
14.7 kHz / 16 kHz
Reserved
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
29.4 kHz / 32 kHz
44.1 kHz / 48 kHz
(default)
88.2 kHz / 96 kHz
176.4 kHz / 192 kHz
supported only by
QFN device package.
Reserved
Table 8-24. PCM SBCLK to FSYNC Ratio
FS_RATIO[3:0]
SBCLK to FSYNC Ratio
Reserved
0x0-0x3
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Table 8-24. PCM SBCLK to FSYNC Ratio (continued)
FS_RATIO[3:0]
SBCLK to FSYNC Ratio
64
0x4
0x5
96
128
0x6
192
0x7
256
0x8
384
0x9
512
0xA
Reserved
Error Condition
0xB-0xE
0xF
Figure 8-12 and Figure 8-13 below illustrates the receiver frame parameters required to configure the port for
playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the
FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge
(set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from
the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified
format and 1 for an I2S format.
SBCLK
FSYNC
MSB
MSB-1
LSB+1
LSB
SDIN
RX_OFFSET
RX_WLEN
RX_SLEN
Figure 8-12. TDM RX Time Slot with Left Justification
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SBCLK
FSYNC
SDIN
Slot 0
Bit 31
Slot0
Bit 0
Slot 1
Bit 31
Slot1
Bit 0
Slot2
Bit 31
RX_OFFSET
Time Slot 0
Time Slot 1
Figure 8-13. TDM RX Time Slots
Table 8-25. TDM Start of Frame Polarity
FRAME_START
POLARITY
Low to High on FSYNC(1)
0
High to Low on FSYNC (default)
(2)
1
(1) When Low to High is used RX_EDGE and TX_EDGE cannot
both simultaneously be set to rising edge.
(2) When High to Low is used RX_EDGE and TX_EDGE cannot
both simultaneously be set to falling edge.
Table 8-26. TDM RX Capture Polarity
RX_EDGE
FSYNC AND SDIN CAPTURE
EDGE
Rising edge of SBCLK (default)
Falling edge of SBCLK
0
1
Table 8-27. TDM RX Start of Frame to Time Slot 0
Offset
RX_OFFSET[4:0]
SBCLK CYCLES
0
0x00
1 (default)
0x01
0x02
...
2
...
30
31
0x1E
0x1F
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The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within
the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within
the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The
TAS2563 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time
slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default
the device will playback mono from the time slot equal to the I2C base address offset for playback. The
RX_SCFG [1:0] register bits can be used to override the playback source to the left time slot, right time slot or
stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.
If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return
a null sample equivalent to a digitally muted sample.
Table 8-28. TDM RX Time Slot Length
RX_SLEN[1:0]
TIME SLOT LENGTH
16-bits
00
24-bits
32-bits (default)
reserved
01
10
11
Table 8-29. TDM RX Sample Word Length
RX_WLEN[1:0]
LENGTH
16-bits
00
20-bits
24-bits (default)
32-bits
01
10
11
Table 8-30. TDM RX Sample Justification
RX_JUSTIFY
JUSTIFICATION
Left (default)
0
Right
1
Table 8-31. TDM RX Time Slot Select Configuration
RX_SCFG[1:0]
CONFIG ORIGIN
Mono with Time Slot equal to I2C
Address Offset (default)
00
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Table 8-31. TDM RX Time Slot Select Configuration
(continued)
RX_SCFG[1:0]
CONFIG ORIGIN
Mono Left Channel
01
Mono Right Channel
10
11
Stereo Down Mix [L+R]/2
Table 8-32. TDM RX Left Channel Time Slot
RX_SLOT_L[3:0]
TIME SLOT
0 (default)
0x0
1
0x1
...
0xE
0xF
...
14
15
Table 8-33. TDM RX Right Channel Time Slot
RX_SLOT_R[3:0]
TIME SLOT
0
0x0
1 (default)
0x1
...
0xE
0xF
...
14
15
The TDM port can transmit a number sample streams on the SDOUT pin including speaker voltage sense,
speaker current sense, VBAT voltage, die temperature and channel gain. Figure 8-14 below illustrates the
alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots.
Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can be
configured by setting the TX_EDGE register bit. The TX_OFFSET register defines the number SBCLK cycles
between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left
Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of
the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all devices
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driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the
TX_KEEPEN register bit. The bus-keeper can additionally be configured to be enabled for only 1LSB cycle or
always using TX_KEEPLN and to drive the full or half cycle of the LSB using TX_KEEPCY.
Each sample stream is composed of either one or two 8-bit time slots. , so they will always utilize two TX time
slots. The VBAT voltage stream is 10-bit precision, and can either be transmitted left justified in a 16-bit word
(using two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This
is configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are
transmitted in a single time slot.
SBCLK
FSYNC
Slot 0
Bit 7
Slot0
Bit 0
Slot 1
Bit 7
Slot1
Bit 0
Slot2
Bit 7
SDOUT
TX_OFFSET
Time Slot 0
Time Slot 1
Ex: V_SENSE[15:0]
Figure 8-14. TDM Port TX Diagram
Table 8-34. TDM TX Transmit Polarity
TX_EDGE
SDOUT TRANSMIT EDGE
Rising edge of SBCLK
0
Falling edge of SBCLK (default)
1
Table 8-35. TDM TX Start of Frame to Time Slot 0
Offset
TX_OFFSET[2:0]
SBCLK CYCLES
0
0x0
1 (default)
0x1
0x2
...
0x6
0x7
2
...
6
7
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Table 8-36. TDM TX Unused Bit Field Fill
TX_FILL
SDOUT UNUSED BIT FIELDS
Transmit 0
0
Transmit Hi-Z (default)
1
Table 8-37. TDM TX SDOUT Bus Keeper Enable
TX_KEEPEN
SDOUT BUS KEEPER
Disable bus keeper
0
Enable bus keeper (default)
1
Table 8-38. TDM TX SDOUT Bus Keeper Length
TX_KEEPLN
SDOUT BUS KEEPER
ENABLED FOR
1 LSB cycle (default)
Always
0
1
Table 8-39. TDM TX SDOUT Bus Keeper LSB Cycle
TX_KEEPCY
SDOUT BUS KEEPER DRIVEN
full-cycle (default)
0
half-cycle
1
The time slot register for each sample stream defines where the MSB transmission begins. For instance, if
VSNS_SLOT is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be
transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage
limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.
It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For
instance, if VSNS_SLOT is set to 2 and ISNS_SLOT is set to 3, the lower 8 LSBs of voltage sense will conflict
with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the conflicting bit
slots (for example the priority is not defined).
The current and voltage values are transmitted at the full 16-bit measured values by default. The IVMON_LEN
register can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values across multiple slots. The
special 12-bit mode is used when only 24-bit I2S/TDM data can be processed by the host processor. The device
should be configured with the voltage-sense slot and current-sense slot off by 1 slot and will consume 3
consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by the second 12 MSB
bits specified by the preceding slot.
If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at
the frame boundary.
It is recommended to keep the following slot ordering:
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ISNS_SLOT<VSNS_SLOT<VBAT_SLOT<TEMP_SLOT<GAIN_SLOT<BIL_ILIM_SLOT.
Table 8-40. TDM Voltage/Current Length
IVMON_LEN[1:0]
LENGTH BITS
16 bits (default)
00
12 bits
8 bits
01
10
11
Reserved
Table 8-41. TDM Voltage Sense Time Slot
VSNS_SLOT[5:0]
SLOT
0
0x00
1
0x01
0x02
...
2 (default)
...
62
63
0x3E
0x3F
Table 8-42. TDM Voltage Sense Transmit Enable
VSNS_TX
STATE
Disabled (default)
0
Enabled
1
Table 8-43. TDM Current Sense Time Slot
ISNS_SLOT[5:0]
SLOT
0 (default)
0x00
1
0x01
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Table 8-43. TDM Current Sense Time Slot
(continued)
ISNS_SLOT[5:0]
SLOT
2
0x02
...
62
63
...
0x3E
0x3F
Table 8-44. TDM Current Sense Transmit Enable
ISNS_TX
STATE
Disabled (default)
0
Enabled
1
Table 8-45. TDM VBAT Time Slot
VBAT_SLOT[5:0]
SLOT
0
0x00
0x01
...
1
...
4 (default)
0x04
...
...
62
63
0x3E
0x3F
Table 8-46. TDM VBAT Time Slot Length
VBAT_SLEN
SLOT LENGTH
Truncate to 8-bits (default)
0
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Table 8-46. TDM VBAT Time Slot Length (continued)
VBAT_SLEN
SLOT LENGTH
Left justify to 16-bits
1
Table 8-47. TDM VBAT Transmit Enable
VBAT_TX
STATE
Disabled (default)
0
Enabled
1
Table 8-48. TDM Temp Sensor Time Slot
TEMP_SLOT[5:0]
SLOT
0
0x00
1
0x01
...
...
5 (default)
0x05
...
...
62
63
0x3E
0x3F
Table 8-49. TDM Temp Sensor Transmit Enable
TEMP_TX
STATE
Disabled (default)
0
Enabled
1
The following sample streams are part of the system. These data streams can be routed over the audio TDM
bus .
Table 8-50. TDM Limiter Gain Reduction Time Slot
GAIN_SLOT[5:0]
SLOT
0
0x00
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Table 8-50. TDM Limiter Gain Reduction Time Slot
(continued)
GAIN_SLOT[5:0]
SLOT
1
0x01
...
...
0x06
...
6 (default)
...
62
63
0x3E
0x3F
Table 8-51. TDM Limiter Gain Reduction Transmit
Enable
GAIN_TX
STATE
Disabled (default)
0
Enabled
1
Table 8-52. TDM Boost Sync Time Slot
BST_SLOT[5:0]
SLOT
0
0x00
1
0x01
...
...
7 (default)
0x07
...
...
62
63
0x3E
0x3F
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Table 8-53. TDM Boost Sync Enable
BST_TX
STATE
Disabled (default)
0
1
Enabled
Note that the boost sync function is only operational with input sample rates higher than 16 kHz.
8.4.3 Playback Signal Path
8.4.3.1 Digital Signal Processor
An on-chip, low-latency DSP supports Texas Instruments' Smart Amp speaker protection algorithms to maximize
loudness while maintaining safe speaker conditions.
8.4.3.2 High Pass Filter
Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The TAS2563
employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. The HPF can be
disabled using register HPF_EN. The HPF Bi-Quad filter coefficients can be changed from the default 2 Hz using
the HPFC_N0, HPFC_N1, HPFC_D1 registers using the equation [N, D] = butter(1, fc/(fs/2), 'high');
round(N(0)*2^31);. These coefficients should be calculated and set using Section 8.3.1.
Table 8-54. HPF Enable
HPF_EN
STATE
Enabled (default)
0
Disabled
1
8.4.3.3 Digital Volume Control and Amplifier Output Level
The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital
volume control (DVC).
Amplifier output level settings are presented in dBV (dB relative to 1 Vrms) with a full scale digital audio input (0
dBFS) and the digital volume control set to 0 dB. It should be noted that these levels may not be achievable
because of analog clipping in the amplifier, so they should be used to convey gain only. Table 8-55 below shows
gain settings that can be programmed via the AMP_LEVEL register.
Table 8-55. Amplifier Output Level Settings
FULL SCALE OUTPUT
AMP_LEVEL[4:0]
dBV
VPEAK (V)
0x00
0x01
0x02
...
8
3.55
8.5
9
3.76
3.99
...
...
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Table 8-55. Amplifier Output Level Settings
(continued)
FULL SCALE OUTPUT
AMP_LEVEL[4:0]
dBV
VPEAK (V)
0x10
16
8.92
...
0x13
...
17.5
...
10.60
0x14
18
11.23
0x15-0x1F
Reserved
Reserved
Equation 1 calculates the amplifiers output voltage.
= Input + A + A dBV
V
AMP
dvc
AMP
(1)
where
•
•
•
•
VAMP is the amplifier output voltage in dBV
Input is the digital input amplitude in dB with respect to 0 dBFS
Advc is the digital volume control setting, 0 dB to -100 dB in 0.5 dB steps
AAMP is the amplifier output level setting in dBV
Settings greater than 0xC8 are interpreted as mute. When a change in digital volume control occurs, the device
ramps the volume to the new setting based on the DVC_RAMP register bits. If DVC_RAMP is set to 0x0000
0000, volume ramping is disabled. This can be used to speed up startup, shutdown and digital volume changes
when volume ramping is handled by the system master.
The digital voltage control registers DVC_PCM represent the volume in a 2.X format. To calculate the value to
write to these 4 registers apply the following formula to the desired dB DVC_PCM = round(10^(dB/20)*2^30).
A volume ramp rate can be set using DVC_RAMP and represents a rate in 1.X format. To calculate the value to
write to these 4 registers apply the following formula DVC_RAMP = round((1-exp(-1/(0.2*fs*time in
seconds)))*2^31).
Table 8-56. PCM Digital Volume Control
DVC_PCM[31:0]
VOLUME (dB)
-110
0x0000 0D43 (MIN)
...
0 (default)
...
...
0x4000 0000
...
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Table 8-56. PCM Digital Volume Control (continued)
DVC_PCM[31:0]
VOLUME (dB)
2
0x5092 BEE4 (MAX)
Table 8-57. Digital Volume Ramp Rate
DVC_RAMP[31:0]
RAMP RATE @ 48kHz (s)
0
0x0000 0D43
...
1 s
0x7FFC 963B
where
•
•
•
•
•
VPK(max,preclip) is the maximum peak unclipped output voltage in V
VBAT is the power supply voltage
RL is the speaker load in Ω
Rinterconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
RFET(on) is the power stage total on resistance (HS FET+LS FET+Sense Resistor+bonding+packaging) in Ω
8.4.3.4 Auto-mute During Idle Channel Mode
Device will stop playing audio if the input audio level drops below the programmable threshold for a
programmable timer window. If this behavior is not preferred, threshold level can be kept at very low levels.
8.4.3.5 Auto-start/stop on Audio Clocks
The TAS2563 can enter low power software shutdown when the TDM clocks are stopped instead of going into
clock error. The device will resume operation when the clocks resume.
8.4.3.6 Supply Tracking Limiters with Brown Out Prevention
The TAS2563 monitors battery voltage (VBAT) and the class-D voltage (PVDD) along with the audio signal to
automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent
clipping and extends playback time through end of charge battery conditions. The limiters threshold can be
configured to track the monitored voltage below a programmable inflection point with a programmable slope. A
minimum threshold sets the limit of threshold reduction from the voltage tracking. Configurable attack rate, hold
time and release rate are provided to shape the dynamic response of each limiter. The total attenuation is the
sum of both the VBAT and PVDD limiter. If the ICLA is enabled the actual attenuation is based on the ICLA
configuration using the calculated attenuation value of all devices on the selected ICLA bus.
A Brown Out Prevention (BOP) feature provides a priority input to provide a very fast response to transient dips
in the battery supply (VBAT) which at end of charge conditions that can cause system level brown out. When the
selected supply dips below the brown-out threshold the BOP will begin reducing gain with an first attack latency
of less than 10 µs and a configurable attack rate. When the VBAT supply rises above the brownout threshold,
the BOP will begin to release after the programmed hold time. During a BOP event the limiter updates will be
paused. This is to prevent a limiter from releasing during a BOP event. The VBAT and PVDD limiters are
enabled by setting the respective LIMB_EN and LIMP_EN bits high.
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Table 8-58. VBAT Tracking Limiter Enable
LIMB_EN
VALUE
Disabled (default)
0
Enabled
1
Table 8-59. PVDD Tracking Limiter Enable
LIMP_EN
VALUE
Disabled (default)
0
Enabled
1
The limiters have configurable attack rates, hold times and release rates, which are available via the
LIMB_ATK_RT[2:0], LIMB_HLD_TM[2:0], LIMB_RLS_RT[2:0] register bits respectively for VBAT and
LIMP_ATK_RT[2:0], LIMP_HLD_TM[2:0], LIMP_RLS_RT[2:0] register bits respectively for PVDD . The limiters
attack and release step sizes can be set by configuring the LIMB_ATK_ST[1:0] and LIMB_RLS_ST[1:0] register
bits respectively for VBAT and LIMP_ATK_ST[1:0] and LIMP_RLS_ST[1:0] register bits respectively for PVDD.
For sampling rates less that 44.1kHz and greater than 8 kHz the minimum attack rate is 20µs and for sampling
rates of 8kHz or less the minimum attack rate is 40µs.
A maximum level of attenuation applied by the limiters and brown out prevention feature is configurable via the
LIM_MAX_ATN register. This attenuation limit is shared between the features. For instance, if the maximum
attenuation is set to 6 dB and the limiters have reduced gain by 4 dB, the brown out prevention feature will only
be able to reduce the gain further by another 2 dB. If the limiter or brown out prevention feature is attacking and
it reaches the maximum attenuation, gain will not be reduced any further.
The limiter max attenuation LIM_MAX_ATN represent the limit in a 1.X format. To calculate the value to write to
the 4 registers by apply the following formula to the desired dB using equation LIMB_MAX_ATN = round(10^(-
dB/20)*2^31).
Table 8-60. Limiter Max Attenuation
LIM_MAX_ATN[31:0]
ATTENUATION (dB)
-1
0x7214 82C0
...
-9 (default)
...
...
0x2D6A 866F
...
-16.5
0x1326 DD71
The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can
be configured to track selected supply below a programmable inflection point with a minimum threshold value.
Figure 8-15 below shows the limiter configured to limit to a constant level regardless of the selected supply level.
To achieve this behavior, set the limiter maximum threshold to the desired level using LIM_TH_MAX. Set the
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limiter inflection point using LIM_INF_PT below the minimum allowable supply setting. The limiter minimum
threshold register LIM_TH_MIN does not impact limiter behavior in this use case.
LIM_TH_MAX
Brown
Out
BOP_TH
VBAT (V)
Figure 8-15. Limiter with Fixed Threshold
The VBAT limiter threshold max LIMB_TH_MAX and min LIMB_TH_MIN registers represent the limit in a 5.X
format. To calculate the value to write to the 4 registers by apply the following formula to the desired threshold
voltage using the equation LIMB_TH_MAX or LIMB_TH_MIN = round(Volts*2^27).
Table 8-61. VBAT Limiter Maximum Threshold
LIMB_TH_MAX[31:0]
THRESHOLD (V)
2.5
0x1400 0000
...
9 (default)
...
...
0x4800 0000
...
15.5
0x7C00 0000
Table 8-62. VBAT Limiter Minimum Threshold
LIMB_TH_MIN[31:0]
THRESHOLD (V)
2.5
0x1400 0000
...
4 (default)
...
...
0x2000 0000
...
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Table 8-62. VBAT Limiter Minimum Threshold
(continued)
LIMB_TH_MIN[31:0]
THRESHOLD (V)
15.5
0x7C00 0000
The VBAT limiter inflection point LIMB_INF_PT represent the limit in a 5.X format. To calculate the value to write
to the 4 registers by apply the following formula to the desired infection voltage using the equation LIMB_INF_PT
= round(Volts*2^27).
Table 8-63. VBAT Limiter Inflection Point
LIMB_INF_PT[31:0]
THRESHOLD (V)
2
0x2000 0000
...
...
3.3 (default)
0x34CC CCCD
...
...
6
0x3000 0000
Figure 8-16 shows how to configure the limiter to track selected supply below a threshold without a minimum
threshold. Set the LIM_TH_MAX register to the desired threshold and LIM_INF_PT register to the desired
inflection point where the limiter will begin reducing the threshold with the selected supply. The default value of 1
V/V will reduce the threshold 1 V for every 1 V of drop in the supply voltage. More aggressive tracking slopes
can be programmed if desired. Program the LIM_TH_MIN below the minimum the selected supply to prevent the
limiter from having a minimum threshold reduction when tracking the selected supply.
The VBAT limiter tracking slope LIMB_SLOPE[31:0] represent the limit in a 5.X format. To calculate the value to
write to the 4 registers by apply the following formula to the desired infection voltage using equation
LIMB_SLOPE = round(slope(V/V)*2^27)
Inflection
Point
LIM_TH_MAX
slope
Brown
Out
BOP_TH
LIM_INF_PT
VBAT (V)
Figure 8-16. Limiter with Inflection Point
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To achieve a limiter that tracks the selected supply below a threshold, configure the limiter as explained in the
previous example, except program the LIM_TH_MIN register to the desired minimum threshold. This is shown in
Figure 8-17 below.
Inflection
Point
LIM_TH_MAX
slope
LIM_TH_MIN
Brown
Out
BOP_TH
LIM_INF_PT
VBAT (V)
Figure 8-17. Limiter with Inflection Point and Minimum Threshold
The TAS2563 also employs a Brown Out Prevention (BOP) feature that serves as a low latency priority input to
the limiter engine that begins attacking the VBAT supply dipping below the programmed BOP threshold. This
feature can be enabled by setting the BOP_EN register bit high. It should be noted that the BOP feature is
independent of the limiter and will function if enabled, even if the limiter is disabled. The BOP threshold is
configured by setting the threshold with register bits BOP_TH.
Table 8-64. Brown Out Prevention Enable
BOP_EN
VALUE
Disabled
0
Enabled (default)
1
The Brownout prevention threshold BOP_TH represent a threshold in a 5.X format. To calculate the value to
write to the 4 registers by apply the following formula to the desired brownout threshold using equation BOP_TH
= round(Volts*2^27).
Table 8-65. Brown Out Prevention Threshold
BOP_TH[31:0]
VBAT THRESHOLD (V)
Reserved
0x0000 000 - 0x1FFF
FFFF
2.5
...
0x2000 0000
...
2.9 (default)
0x2E66 6666
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Table 8-65. Brown Out Prevention Threshold
(continued)
BOP_TH[31:0]
VBAT THRESHOLD (V)
...
...
4
0x2000 0000
Reserved
0x2000 0001 - 0xFFFF
FFFF
The BOP feature has a separate attack rate BOP_ATK_RT, attack step size BOP_ATK_ST and hold time
BOP_HLD_TM from the battery tracking limiter. The BOP feature uses the LIMB_RLS_RT register setting to
release after a brown out event. The rates are based on the number of audio samples and actual time values
can be calculated by multiplying by 1/fs. For example the attack rate of 4 samples at 48 ksps would be
approximately 83 µs.
Table 8-66. Brown Out Prevention Attack Rate
BOP_ATK_RT[2:0]
ATTACK RATE
(samples/step)
ATTACK RATE @ 48
ksps (~µs)
1
2
20
42
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
4
83
8
167
333
666
1300
2700
16
32
64
128
Table 8-67. Brown Out Prevention Attack Step Size
BOP_ATK_ST[1:0]
STEP SIZE (dB)
0.5
00
1 (default)
01
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Table 8-67. Brown Out Prevention Attack Step Size
(continued)
BOP_ATK_ST[1:0]
STEP SIZE (dB)
1.5
10
2
11
Table 8-68. Brown Out Prevention Hold Time
BOP_HLD_TM[2:0]
HOLD TIME (ms)
0
0x0
10
25
0x1
0x2
0x3
0x4
0x5
0x6
0x7
50
100
250
500 (default)
1000
The TAS2563 can also shutdown the device when a brown out event occurs if the BOP_MUTE register bit is set
high. For the device to continue playing audio again, the device must transition through a SW/HW shutdown
state. Setting the BOP_INF_HLD high will cause the limiter to stay in the hold state (i.e. never release) after a
cleared brown out event until either the device transitions through a mute or SW/HW shutdown state or the
register bit BOP_HLD_CLR is written to a high value (which will cause the device to exit the hold state and begin
releasing). This bit is self clearing and will always readback low. Figure 8-18 below illustrates the entering and
exiting from a brown out event.
VBAT
BOP Thresh
BOP Active
BOP
Attacking
BOP
Holding
Limiter Releasing
(BOP Inactive)
BOP Inactive
BOP Inactive
BOP Mode
Figure 8-18. Brown Out Prevention Event
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Table 8-69. Shutdown on Brown Out Event
BOP_MUTE
VALUE
Don't Shutdown (default)
0
Mute then shutdown
1
Table 8-70. Infinite Hold on Brown Out Event
BOP_INF_HLD
VALUE
Use BOP_HLD_TM after Brown
0
Out event (default)
Do not release until
BOP_HLD_CLR is asserted high
1
Table 8-71. BOP Infinite Hold Clear
BOP_HLD_CLR
VALUE
Don't clear (default)
0
Clear event (self clearing)
1
A hard brownout level can be set to shutdown the TAS2563 if the BOP cannot mitigate the drop in battery
voltage VBAT. This will shutdown the device and should not be used if the BOP_MUTE is enable. The brownout
shutdown will only function if brownout engine is enabled using BOP_EN.
Table 8-72. Brown Out Shutdown Enable
BOSD_EN
VALUE
Disabled (default)
0
Enabled
1
The Brownout prevention shutdown threshold BOSD_TH represent a threshold in a 5.X format. To calculate the
value to write to the 4 registers by apply the following formula to the desired brownout threshold using equation
BOSD_TH = round(Volts*2^27).
Table 8-73. Brown Out Shutdown Threshold
BOSD_TH[31:0]
VBAT THRESHOLD (V)
2.5
0x2000 0000
...
...
2.7 (default)
0x2B33 3333
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Table 8-73. Brown Out Shutdown Threshold
(continued)
BOSD_TH[31:0]
VBAT THRESHOLD (V)
...
...
3.99
0x3FFF FFFF
8.4.3.7 Class-D Settings
The TAS2563 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting
the AMP_SS register bit high. This can help reduce EMI in some systems.
Table 8-74. Low EMI Spread Spectrum Mode
AMP_SS
SPREAD SPECTRUM
Disabled
0
Enabled (default)
1
By default the Class-D amplifier's switching frequency is based on the device's trimmed internal oscillator. To
synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is
synchronized to the audio sample rate, the RATE_RAMP register bit must be set based whether the audio
sample rate is based on a 44.1 kHz or 48 kHz frequency. For 44.1, 88.2 and 176.4 kHz, set this bit high. for 48,
96 and 192 kHz, set this bit low. This ensures that the internal ramp generator has the appropriate slope.
Table 8-75. Class-D Synchronization Mode
CLASSD_SYNC
SYNCHRONIZATION MODE
Not synchronized to audio clocks
(default)
0
Synchronized to audio clocks
1
Table 8-76. Sample Rate for Class-D Synchronized
Mode
RAMP_RATE
PLAYBACK SAMPLE RATE
multiples of 48 kHz(default)
0
multiples of 44.1 kHz
1
8.4.4 SAR ADC
A 10-bit SAR ADC monitors VBAT voltage VBAT_CNV , PVDD voltage PVDD_CNV and die temperature
TMP_CNV. VBAT voltage conversions are also used by the limiter and brown out prevention features.
Actual VBAT voltage is calculated by dividing the VBAT_CNV register by 64. Actual die temperature is calculated
by subtracting 93 from TMP_CNV register. The battery voltage VBAT can be filtered using VBAT_FLT register
but will increase the latency. The VBAT_CNV registers should be read VBAT_MSB followed by VBAT_LSB.
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Table 8-77. ADC VBAT Voltage Conversion
VBAT_CNV[9:0]
VBAT VOLTAGE (V)
0 V
0.0156 V
...
0x000
0x001
...
4.0 V
...
0x100
...
5.9844 V
6.0 V
0x17F
0x180
Table 8-78. ADC Die Temperature Conversion
TMP_CNV[7:0]
DIE TEMPERATURE (°C)
-93 °C
0x00
-92 °C
...
0x01
...
25 °C
...
0x76
...
161 °C
162 °C
0xFE
0xFF
8.4.5 IV Sense
The TAS2563 provides speaker voltage and current sense for real time monitoring of loudspeaker behavior. The
VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or directly to the OUT_P and
OUT_N connections if no EMI filter is used). The V-Sense connections eliminate IR drop error due to packaging,
PCB interconnect or ferrite bead filter resistance. It should be noted that any interconnect resistance after the V-
Sense terminals will not be corrected for, so it is advised to connect the sense connections as close to the load
as possible.
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OUT_P
fb
fb
OUT_N
VSNS_P
VSNS_N
Figure 8-19. V-Sense Connections
I-Sense and V-Sense can be powered down by asserting the ISNS_PD and VSNS_PD register bits respectively.
When powered down, the device will return null samples for the powered down block. The IV-sense is High Pass
Filtered and the Bi-Quad filter coefficients can be changed from the default 2 Hz using the IVHPFC_N0,
IVHPFC_N1, IVHPFC_D1 registers using the equations [N, D] = butter(1, fc/(fs/2), 'high'); round(N(0)*2^31);.
These coefficients can be calculated and set using Section 8.3.1.
Table 8-79. I-Sense Power Down
ISNS_PD
SETTING
I-Sense is active
0
I-Sense is powered down
(default)
1
Table 8-80. V-Sense Power Down
VSNS_PD
SETTING
V-Sense is active
0
V-Sense is powered down
(default)
1
8.4.6 Load Diagnostics
The TAS2563 can check the speaker terminal for an open or short. This can be used to determine if a problem
exists with the speaker or trace to the speaker. The entire operation is performed by the TAS2563 and results
reported using the IRQZ pin or read over I2C bus on completion. The load diagnostics can be performed using
external audio clock or the internal oscillator.
Open Load
LDG_RES_UT
LDG_RES_LT
Short Load
Figure 8-20. Load Diagnostics
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The speaker open and short thresholds are configured using the respective LDG_RES_UT and LDG_RES_LT
registers using equation round(Ω/7*2^22). The load diagnostic mode can be run in two ways. First if the device is
in Section 8.3.11.2 the load diagnostic mode can be run by setting LDG_MODE high. The diagnostic will be run
and the device will return to Section 8.3.11.2. The load diagnostics can also be run before transitioning to
Section 8.3.11.4. This is done by setting the MODE register to Section 8.3.11.5. If the load is within the specified
range the device will transition to Section 8.3.11.4 otherwise it will transition to Section 8.3.11.2. When the load
diagnostics is run it will play a 22 kHz at -35 dBFS for 100 ms and measure the resistance of the speaker trace.
The result is averaged over the time specified by the IVSNS_AVG register. The measured speaker impedance
can be read from LDS_RES_VAL1 using the equations Impedance = 7*(LD_RES_VAL1)/2^22) Ω.
Table 8-81. IV-sense Averaging
IVSNS_AVG[1:0]
SETTING
5 ms (default)
00
10 ms
50 ms
01
10
11
100 ms
Table 8-82. Load Diagnostic Mode
LDG_MODE
SETTING
Load Diagnostic Not Running
(default)
0
Run Load Diagnostic
1
Table 8-83. Load Diagnostic Clock Source
LDG_CLK
SETTING
External TDM
0
Internal Oscillator (default)
1
8.4.7 Clocks and PLL
In TDM/I2S Mode, the device operates from SBCLK. Table 8-84 and Table 8-85 below shows the valid SBCLK
frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies
respectively.
If the sample rate is properly configured via the SAMP_RATE[1:0] bits, no additional configuration is required as
long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and SBCLK to
FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock error is
detected the device will enter a low power halt mode after CLK_HALT_TIMER if CLK_HALT_EN is enabled.
Additionally the device can automatically power up and down on valid clock signals if CLK_ERR_PWR_EN is
set. The device sampling rate should not be changed while this feature is enabled. Additionally, the
CLK_HALT_EN should be set when CLK_ERR_PWR_EN is set for this feature to work properly.
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Table 8-84. Supported SBCLK Frequencies (48 kHz based sample rates)
SBCLK to FSYNC Ratio
Sample Rate
(kHz)
64
96
128
192
256
384
512
16 kHz
32 kHz
48 kHz
96 kHz
1.024 MHz
2.048 MHz
3.072 MHz
6.144 MHz
1.536 MHz
3.072 MHz
4.608 MHz
9.216 MHz
2.048 MHz
3.072 MHz
4.096 MHz
8.192 MHz
12.288 MHz
24.576 MHz
6.144 MHz
12.288 MHz
18.432 MHz
-
8.192 MHz
16.384 MHz
24.576 MHz
-
4.0960 MHz
6.144 MHz
12.288 MHz
6.144 MHz
9.216 MHz
18.432 MHz
Table 8-85. Supported SBCLK Frequencies (44.1 kHz based sample rates)
SBCLK to FSYNC Ratio
Sample Rate
(kHz)
64
96
128
192
256
384
512
14.7 kHz
29.4 kHz
44.1 kHz
88.2 kHz
940.8 kHz
1.8816 MHz
2.8224 MHz
5.6448 MHz
1.4112 MHz
2.8224 MHz
4.2336 MHz
8.4672 MHz
1.8816 MHz
3.7632 MHz
5.6448 MHz
11.2896 MHz
2.8224 MHz
5.6448 MHz
8.4672 MHz
16.9344 MHz
3.7632 MHz
7.5264 MHz
11.2896 MHz
22.5792 MHz
5.6448 MHz
11.2896 MHz
16.9344 MHz
-
7.5264 MHz
15.0528 MHz
22.5792 MHz
-
Table 8-86. Clock Power Up/Down on Valid ASI
Clocks
CLK_ERR_PWR_EN
Setting
Disabled (default)
0
Enabled
1
Table 8-87. Clock Halt(Sleep) After Errors Longer
Than Halt Timer
CLK_HALT_EN
Setting
Enabled (default)
0
Disabled
1
Table 8-88. Clock Halt Timer
CLK_HALT_TIMER[2:0]
Setting
1 ms
000
3.27 ms
26.21 ms
001
010
011
100
52.42 ms (default)
104.85 ms
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Table 8-88. Clock Halt Timer (continued)
CLK_HALT_TIMER[2:0]
Setting
209.71 ms
419.43 ms
838.86 ms
101
110
111
8.4.8 Thermal Foldback
The TAS2563 monitors the die temperature and can automatically limit the audio signal when the die
temperature reaches a set threshold. It is recommended to use Section 8.3.1 to configure the thermal foldback
as the software will perform the necessary math for each register.
Thermal foldback can be disabled using TF_EN. If the die temperature reaches TF_TEMP_TH this feature will
begin to attenuate the audio signal to prevent the device from shutting down due to over-temperature. It will
attenuate the audio signal by TF_LIMS db per degree of temperature over TF_TEMP_TH. The thermal foldback
with attack at a fixed rate of 0.25 dB per sample. A maximum attenuation of TF_MAX_ATTN can be specified.
However if the device continue to heat up eventually the device over-temperature will be triggered. The
attenuation will be held for TF_HOLD_CNT samples before the attenuation will begin releasing.
Table 8-89. Thermal Foldback Enable
TF_EN
SETTING
Disabled
0
Enabled (default)
1
Table 8-90. Thermal Foldback Registers
REGISTER
DESCRIPTION
CALCULATION
Thermal foldback
limiter slope (in
db/°C)
round(10^(-slope /
20)*2^31)
TF_LIMS
Thermal foldback hold
count (samples)
round(seconds *
1000)
TF_HOLD_CNT
TF_REL_RATE
TF_TEMP_TH
TF_MAX_ATTN
Thermal foldback
limiter release rate
(db/samples)
round(10^(dB per
sample / 20)*2^30)
Thermal foldback
limiter temperature
threshold (°C)
round(°C * 2^23)
Thermal foldback max round(10^(max attn
gain reduction (dB)
dB/20)*2^31)
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8.5 Register Maps
8.5.1 Register Summary Table Page=0x00
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
Register
Description
Section
PAGE
Device Page
Section 8.5.2
Section 8.5.3
Section 8.5.4
Section 8.5.5
Section 8.5.6
Section 8.5.7
Section 8.5.8
Section 8.5.9
Section 8.5.10
Section 8.5.11
Section 8.5.12
Section 8.5.13
Section 8.5.14
Section 8.5.15
Section 8.5.16
Section 8.5.17
Section 8.5.18
Section 8.5.19
Section 8.5.20
Section 8.5.21
Section 8.5.22
SW_RESET
PWR_CTL
Software Reset
Power Control
PB_CFG1
Playback Configuration 1
Misc Configuration 1
Misc Configuration 2
TDM Configuration 0
TDM Configuration 1
TDM Configuration 2
TDM Configuration 3
TDM Configuration 4
TDM Configuration 5
TDM Configuration 6
TDM Configuration 7
TDM Configuration 8
TDM Configuration 9
TDM Configuration 10
TDM Clock detection monitor
Limiter Configuration 0
Limiter Configuration 1
Brown Out Prevention 0
MISC_CFG1
MISC_CFG2
TDM_CFG0
TDM_CFG1
TDM_CFG2
TDM_CFG3
TDM_CFG4
TDM_CFG5
TDM_CFG6
TDM_CFG7
TDM_CFG8
TDM_CFG9
TDM_CFG10
DSP Mode & TDM_DET
LIM_CFG0
LIM_CFG1
DSP FREQUENCY &
BOP_CFG0
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1F
0x20
0x21
0x22
0x24
0x25
0x26
0x27
0x2A
0x2B
0x2C
0x30
0x31
0x32
0x33
0x34
0x35
BOP_CFG0
BIL_and_ICLA_CFG0
BIL_ICLA_CFG1
GAIN_ICLA_CFG0
ICLA_CFG1
INT_MASK0
INT_MASK1
INT_MASK2
INT_MASK3
INT_LIVE0
Brown Out Prevention 2
Boost Current limiter and ICLA
Inter Chip Limiter Alignment 0
Inter Chip Limiter Alignment 0
Inter Chip Limiter Alignment 1
Interrupt Mask 0
Section 8.5.23
Section 8.5.24
Section 8.5.25
Section 8.5.26
Section 8.5.27
Section 8.5.28
Section 8.5.29
Section 8.5.30
Section 8.5.31
Section 8.5.32
Section 8.5.33
Section 8.5.34
Section 8.5.35
Section 8.5.36
Section 8.5.37
Section 8.5.38
Section 8.5.39
Section 8.5.40
Section 8.5.41
Section 8.5.42
Section 8.5.43
Section 8.5.44
Section 8.5.45
Section 8.5.46
Section 8.5.47
Section 8.5.48
Interrupt Mask 1
Interrupt Mask 2
Interrupt Mask 3
Live Interrupt Readback 0
Live Interrupt Readback 1
Live Interrupt Readback 2
Live Interrupt Readback 3
Latched Interrupt Readback 0
Latched Interrupt Readback 1
Latched Interrupt Readback 2
Latched Interrupt Readback 3
SAR ADC Conversion 0
SAR ADC Conversion 1
SAR ADC Conversion 2
INT_LIVE1
INT_LIVE3
INT_LIVE4
INT_LTCH0
INT_LTCH1
INT_LTCH3
INT_LTCH4
VBAT_MSB
VBAT_LSB
TEMP
INT & CLK CFG
DIN_PD
Digital Input Pin Pull Down
Misc Configuration
Boost Configure 1
MISC
BOOST_CFG1
BOOST_CFG2
BOOST_CFG3
Boost Configure 2
Boost Configure 3
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0x3B
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x49
0x4A
0x7D
0x7E
0x7F
MISC
Section 8.5.49
Section 8.5.50
Section 8.5.51
Section 8.5.52
Section 8.5.53
Section 8.5.54
Section 8.5.55
Section 8.5.56
Section 8.5.57
Section 8.5.58
Section 8.5.59
Section 8.5.60
Section 8.5.61
Section 8.5.62
TG_CFG0
Tone Generator
BST_ILIM_CFG0
PDM_CONFIG0
DIN_PD & PDM_CONFIG3
ASI2_CONFIG0
ASI2_CONFIG1
ASI2_CONFIG2
ASI2_CONFIG3
PVDD_MSB_DSP
PVDD_LSB_DSP
REV_ID
Boost ILIM configuration-0
SAR ADC Conversion 0
SAR ADC Conversion 1
Revision and PG ID
I2C Checksum
I2C_CKSUM
BOOK
Device Book
8.5.2 PAGE (page=0x00 address=0x00) [reset=0h]
The device's memory map is divided into pages and books. This register sets the page.
Figure 8-21. PAGE Register Address: 0x00
7
6
5
4
3
2
1
0
PAGE[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-91. Device Page Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
RW
0h
Sets the device page.
00h = Page 0
01h = Page 1
...
FFh = Page 255
8.5.3 SW_RESET (page=0x00 address=0x01) [reset=0h]
Asserting Software Reset will place all register values in their default POR (Power on Reset) state.
Figure 8-22. SW_RESET Register Address: 0x01
7
6
5
4
3
2
1
0
Reserved
R-0h
SW_RESET
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-92. Software Reset Field Descriptions
Bit
7-1
0
Field
Type
Reset
Description
Reserved
SW_RESET
R
0h
Reserved
RW
0h
Software reset. Bit is self clearing.
0b = Don't reset
1b = Reset
8.5.4 PWR_CTL (page=0x00 address=0x02) [reset=Eh]
Sets device's mode of operation and power down of IV sense blocks.
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Figure 8-23. PWR_CTL Register Address: 0x02
7
6
5
4
3
2
1
0
PDM_I2S_MOD LDG_MODE_O
Reserved
Reserved
ISNS_PD
VSNS_PD
MODE[1:0]
RW-2h
E
NLY
RW-0h
RW-0h
RW-0h
RW-0h
RW-1h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-93. Power Control Field Descriptions
Bit
Field
Type
Reset
Description
7
PDM_I2S_MODE
RW
0h
PDM I2S mode
0b = PDM_I2S mode disabled
1b = PDM_I2S mode enabled
6
LDG_MODE_ONLY
RW
0h
Only Load Diagnostics mode, self clearing bit
0b = Only Load diagnostics mode disabled
1b = Only Load diagnostics mode enabled
5
4
3
Reserved
Reserved
ISNS_PD
RW
RW
RW
0h
0h
1h
Reserved
Reserved
Current sense power down.
0b = Current sense active
1b = Current sense is powered down
2
VSNS_PD
MODE[1:0]
RW
RW
1h
2h
Voltage sense power down.
0b = voltage sense is active
1b = Voltage sense is powered down
1-0
Device operational mode.
00b = Active
01b = Mute
10b = Software Shutdown
11b = Load Diagnostics followed by device ACTIVE
8.5.5 PB_CFG1 (page=0x00 address=0x03) [reset=20h]
Sets playback high pass filter corner (PCM playback only).
Figure 8-24. PB_CFG1 Register Address: 0x03
7
6
5
4
3
2
1
0
Reserved
DIS_DC_BLOC
KER
AMP_LEVEL[4:0]
RW-10h
Reserved
R-0h
RW-0h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-94. Playback Configuration 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
R
0h
Reserved
6
DIS_DC_BLOCKER
RW
0h
Disable DC Blocker
0b = DC Blocker Enabled
1b = DC Blocker Disabled
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Table 8-94. Playback Configuration 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-1
AMP_LEVEL[4:0]
RW
10h
1Dh-1Fh - Reserved
01h = 8.5 dBV(3.76Vpk)
02h = 9.0 dBV(3.99Vpk)
03h = 9.5 dBV(4.22Vpk)
04h = 10.0 dBV(4.47Vpk)
05h = 10.5 dBV(4.74Vpk)
06h = 11.0 dBV (5.02 Vpk)
07h = 11.5 dBV (5.32 Vpk)
08h = 12.0 dBV (5.63 Vpk)
09h = 12.5 dBV (5.96 Vpk)
0Ah = 13.0 dBV (6.32 Vpk)
0Bh = 13.5 dBV (6.69 Vpk)
0Ch = 14.0 dBV (7.09 Vpk)
0Dh = 14.5 dBV (7.51 Vpk)
0Eh = 15.0 dBV (7.95 Vpk)
0Fh = 15.5 dBV (8.42 Vpk)
10h = 16.0 dBV (8.92 Vpk)
11h = 16.5 dBV (9.45 Vpk)
12h = 17.0 dBV (10.01 Vpk)
13h = 17.5 dBV (10.61 Vpk)
14h = 18.0 dBV (11.23 Vpk)
15h = 18.5dBV(11.90 Vpk)
16h = 19dBV(12.60Vpk)
17h = 19.5dBV(13.35Vpk)
18h = 20.0dBV(14.14Vpk)
19h = 20.5dBV(14.98Vpk)
1Ah = 21dBV(15.87Vpk)
1Bh = 21.5dBV(16.81Vpk)
1Ch = 22dBV(17.8Vpk)
1Dh-1Fh - Reserved
0
Reserved
RW
0h
Reserved
8.5.6 MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
Sets DVC Ramp Rate, OTE/OCE retry, IRQZ pull up, amp spread spectrum and I-Sense current range.
Figure 8-25. MISC_CFG1 Register Address: 0x04
7
6
5
4
3
2
1
0
CP_PG_RETR VBAT_POR_RE OCE_RETRY
OTE_RETRY
IRQZ_PU
AMP_SS
Reserved
RW-2h
Y
TRY
RW-1h
RW-1h
RW-0h
RW-0h
RW-0h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-95. Misc Configuration 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CP_PG_RETRY
RW
1h
Retry after vbat por event.
0b = Do not retry
1b = Retry after 1.5 s
6
5
4
VBAT_POR_RETRY
OCE_RETRY
RW
RW
RW
1h
0h
0h
Retry after vbat por event.
0b = Do not retry
1b = Retry after 1.5 s
Retry after over current event.
0b = Do not retry
1b = Retry after 1.5 s
OTE_RETRY
Retry after over temperature event.
0b = Do not retry
1b = Retry after 1.5 s
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Table 8-95. Misc Configuration 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
IRQZ_PU
RW
0h
IRQZ internal pull up enable.
0b = Disabled
1b = Enabled
2
AMP_SS
Reserved
RW
RW
1h
2h
Low EMI spread spectrum enable.
0b = Disabled
1b = Enabled
1-0
Reserved
8.5.7 MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
Figure 8-26. MISC_CFG2 Register Address: 0x05
7
6
5
4
3
2
1
0
SDZ_MODE[1:0]
RW-0h
SDZ_TIMEOUT[1:0]
RW-2h
Reserved
DIS_VBAT_FLT I2C_GBL_EN DIS_PVDD_FL
T
RW-0h
RW-0h
RW-1h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-96. Misc Configuration 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SDZ_MODE[1:0]
RW
0h
SDZ Mode configuration.
00b = initiates normal shutdown; force shutdown after timeout
01b = immediate force shutdown
10b = normal shutdown only
11b = reserved
5-4
SDZ_TIMEOUT[1:0]
RW
2h
SDZ Timeout value
00b = 2 ms
01b = 4 ms
10b = 6 ms
11b = 23.8 ms
3
2
Reserved
RW
RW
0h
0h
Reserved
DIS_VBAT_FLT
VBAT filter into SAR ADC
0b = VBAT filter with 100kHz cut off
1b = Bypass VBAT FLT
1
0
I2C_GBL_EN
RW
RW
1h
0h
I2C global address is
0b = disabled
1b = enabled
DIS_PVDD_FLT
PVDD filter into SAR ADC
0b = PVDD filter with 100kHz cut off
1b = Bypass PVDD FLT
8.5.8 TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
Sets the TDM frame start, TDM sample rate, TDM auto rate detection and whether rate is based on 44.1 kHz or
48 kHz frequency.
Figure 8-27. TDM_CFG0 Register Address: 0x06
7
6
5
4
3
2
1
0
Reserved
CLASSD_SYN RAMP_RATE
C
AUTO_RATE
SAMP_RATE[2:0]
FRAME_START
R-0h
RW-0h
RW-0h
RW-0h
RW-4h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-97. TDM Configuration 0 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
CLASSD_SYNC
R
0h
Reserved
6
RW
0h
Class-D synchronization mode.
0b = Not synchronized to audio clocks
1b = Synchronized to audio clocks
5
RAMP_RATE
RW
0h
Sample rate based on 44.1kHz or 48kHz when
CLASSD_SYNC=1.
0b = 48kHz
1b = 44.1kHz
4
AUTO_RATE
RW
RW
0h
4h
Auto detection of TDM sample rate.
0b = Enabled
1b = Disabled
3-1
SAMP_RATE[2:0]
Sample rate of the TDM bus.
000b = 7.35/8 kHz
001b = 14.7/16 kHz
010b = 22.05/24 kHz
011b = 29.4/32 kHz
100b = 44.1/48 kHz
101b = 88.2/96 kHz
110b = 176.4/192 kHz
111b = Reserved
0
FRAME_START
RW
1h
TDM frame start polarity.
0b = Low to High on FSYNC
1b = High to Low on FSYNC
8.5.9 TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
Sets TDM RX justification, offset and capture edge.
Figure 8-28. TDM_CFG1 Register Address: 0x07
7
6
5
4
3
2
1
0
Reserved
R-0h
RX_JUSTIFY
RW-0h
RX_OFFSET[4:0]
RW-1h
RX_EDGE
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-98. TDM Configuration 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
RX_JUSTIFY
R
0h
Reserved
6
RW
0h
TDM RX sample justification within the time slot.
0b = Left
1b = Right
5-1
0
RX_OFFSET[4:0]
RX_EDGE
RW
RW
1h
0h
TDM RX start of frame to time slot 0 offset (SBCLK cycles).
TDM RX capture clock polarity.
0b = Rising edge of SBCLK
1b = Falling edge of SBCLK
8.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
Sets TDM RX time slot select, word length and time slot length.
Figure 8-29. TDM_CFG2 Register Address: 0x08
7
6
5
4
3
2
1
0
IVMON_LEN[1:0]
RW-1h
RX_SCFG[1:0]
RW-0h
RX_WLEN[1:0]
RW-2h
RX_SLEN[1:0]
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-99. TDM Configuration 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
IVMON_LEN[1:0]
RW
1h
Sets the current and voltage data to length of
00b = 8 bits
01b = 16 bits
10b = 24 bits
11b = 32 bits
5-4
3-2
1-0
RX_SCFG[1:0]
RX_WLEN[1:0]
RX_SLEN[1:0]
RW
RW
RW
0h
2h
2h
TDM RX time slot select config.
00b = Mono with time slot equal to I2C address offset
01b = Mono left channel
10b = Mono right channel
11b = Stereo downmix (L+R)/2
TDM RX word length.
00b = 16-bits
01b = 20-bits
10b = 24-bits
11b = 32-bits
TDM RX time slot length.
00b = 16-bits
01b = 24-bits
10b = 32-bits
11b = Reserved
8.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
Sets TDM RX left and right time slots.
Figure 8-30. TDM_CFG3 Register Address: 0x09
7
6
5
4
3
2
1
0
RX_SLOT_R[3:0]
RW-1h
RX_SLOT_L[3:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-100. TDM Configuration 3 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RX_SLOT_R[3:0]
RX_SLOT_L[3:0]
RW
1h
TDM RX Right Channel Time Slot.
TDM RX Left Channel Time Slot.
RW
0h
8.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
Sets TDM TX bus keeper, fill, offset and transmit edge.
Figure 8-31. TDM_CFG4 Register Address: 0x0A
7
6
5
4
3
2
1
0
TX_KEEPCY
RW-0h
TX_KEEPLN
RW-0h
TX_KEEPEN
RW-0h
TX_FILL
RW-1h
TX_OFFSET[2:0]
RW-1h
TX_EDGE
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-101. TDM Configuration 4 Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_KEEPCY
RW
0h
TDM TX SDOUT LSB data will be driven for
0b = full-cycle
1b = half-cycle
6
TX_KEEPLN
RW
0h
TDM TX SDOUT will hold the bus for the following when
TX_KEEPEN is enabled
0b = 1 LSB cycle
1b = always
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Table 8-101. TDM Configuration 4 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
TX_KEEPEN
RW
0h
TDM TX SDOUT bus keeper enable.
0b = Disable bus keeper
1b = Enable bus keeper
4
TX_FILL
RW
1h
TDM TX SDOUT unused bitfield fill.
0b = Transmit 0
1b = Transmit Hi-Z
3-1
0
TX_OFFSET[2:0]
TX_EDGE
RW
RW
1h
1h
TDM TX start of frame to time slot 0 offset.
TDM TX launch clock polarity.
0b = Rising edge of SBCLK
1b = Falling edge of SBCLK
8.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
Sets TDM TX V-Sense time slot and enable.
Figure 8-32. TDM_CFG5 Register Address: 0x0B
7
6
5
4
3
2
1
0
0
0
Reserved
R-0h
VSNS_TX
RW-0h
VSNS_SLOT[5:0]
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-102. TDM Configuration 5 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
VSNS_TX
R
0h
Reserved
6
RW
0h
TDM TX voltage sense transmit enable.
0b = Disabled
1b = Enabled
5-0
VSNS_SLOT[5:0]
RW
2h
TDM TX voltage sense time slot.
8.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
Sets TDM TX I-Sense time slot and enable.
Figure 8-33. TDM_CFG6 Register Address: 0x0C
7
6
5
4
3
2
1
Reserved
R-0h
ISNS_TX
RW-0h
ISNS_SLOT[5:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-103. TDM Configuration 6 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
ISNS_TX
R
0h
Reserved
6
RW
0h
TDM TX current sense transmit enable.
0b = Disabled
1b = Enabled
5-0
ISNS_SLOT[5:0]
RW
0h
TDM TX current sense time slot.
8.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
Sets TDM TX VBAT time slot and enable.
Figure 8-34. TDM_CFG7 Register Address: 0x0D
7
6
5
4
3
2
1
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Figure 8-34. TDM_CFG7 Register Address: 0x0D (continued)
VBAT_SLEN
RW-0h
VBAT_TX
VBAT_SLOT[5:0]
RW-0h
RW-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-104. TDM Configuration 7 Field Descriptions
Bit
Field
Type
Reset
Description
7
VBAT_SLEN
RW
0h
TDM TX VBAT time slot length.
0b = Truncate to 8-bits
1b = Left justify to 16-bits
6
VBAT_TX
RW
RW
0h
4h
TDM TX VBAT transmit enable.
0b = Disabled
1b = Enabled
5-0
VBAT_SLOT[5:0]
TDM TX VBAT time slot.
8.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
Sets TDM TX temp time slot and enable.
Figure 8-35. TDM_CFG8 Register Address: 0x0E
7
6
5
4
3
2
1
0
Reserved
R-0h
TEMP_TX
RW-0h
TEMP_SLOT[5:0]
RW-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-105. TDM Configuration 8 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
TEMP_TX
R
0h
Reserved
6
RW
0h
TDM TX temp sensor transmit enable.
0b = Disabled
1b = Enabled
5-0
TEMP_SLOT[5:0]
RW
5h
TDM TX temp sensor time slot.
8.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
Sets ICLA bus, TDM TX limiter gain reduction time slot and enable.
Figure 8-36. TDM_CFG9 Register Address: 0x0F
7
6
5
4
3
2
1
0
Reserved
R-0h
GAIN_TX
RW-0h
GAIN_SLOT[5:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-106. TDM Configuration 9 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
GAIN_TX
R
0h
Reserved
6
RW
0h
TDM TX limiter gain reduction transmit enable.
0b = Disabled
1b = Enabled
5-0
GAIN_SLOT[5:0]
RW
6h
TDM TX limiter gain reduction time slot.
8.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
Sets boost current limiter slot and enable
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Figure 8-37. TDM_CFG10 Register Address: 0x10
7
6
5
4
3
2
1
0
BST_TX
RW-0h
BST_SYNC_TX
RW-0h
BST_SLOT[5:0]
RW-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-107. TDM Configuration 10 Field Descriptions
Bit
Field
Type
Reset
Description
7
BST_TX
RW
0h
TDM TX boost current limiter enable.
0b = Disabled
1b = Enabled
6
BST_SYNC_TX
BST_SLOT[5:0]
RW
RW
0h
7h
TDM TX boost clock sync enable.
0b = Disabled
1b = Enabled
5-0
TDM TX boost sync and current limit time slot.
8.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
Readback of internal auto-rate detection.
Figure 8-38. DSP Mode & TDM_DET Register Address: 0x11
7
6
5
4
3
2
1
0
Reserved
R-0h
FS_RATIO[3:0]
R-Fh
FS_RATE[2:0]
R-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-108. TDM Clock detection monitor Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
FS_RATIO[3:0]
R
0h
Reserved
6-3
R
Fh
Detected SBCLK to FSYNC ratio.
00h = 16
01h = 24
02h = 32
03h = 48
04h = 64
05h = 96
06h = 128
07h = 192
08h = 256
09h = 384
0Ah = 512
0Bh-0Eh = Reserved
0F = Invalid ratio
2-0
FS_RATE[2:0]
R
7h
Detected sample rate of TDM bus.
000b = 7.35/8 KHz
001b = 14.7/16 KHz
010b = 22.05/24 KHz
011b = 29.4/32 KHz
100b = 44.1/48 KHz
101b = 88.2/96 kHz
110b = 176.4/192 kHz
111b = Error condition
8.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
Sets Limiter attack step size, attack rate and enable.
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Figure 8-39. LIM_CFG0 Register Address: 0x12
7
6
5
4
3
2
1
0
Reserved
VBAT_LIM_TH_
SELECTION
LIMB_ATK_ST[1:0]
RW-1h
LIMB_ATK_RT[2:0]
LIMB_EN
R-0h
RW-0h
RW-1h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-109. Limiter Configuration 0 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
R
0h
Reserved
6
VBAT_LIM_TH_SELECTION
RW
0h
Select source of threshold for VBAT based limiting
0b = User configured Thresholds
1b = PVDD based thresholds
5-4
3-1
LIMB_ATK_ST[1:0]
LIMB_ATK_RT[2:0]
RW
RW
1h
1h
VBAT Limiter attack step size.
00b = 0.25 dB
01b = 0.5 dB
10b = 1 dB
11b = 2 dB
VBAT Limiter attack rate.
000b = 1 step in 1 sample
001b = 1 step in 2 samples
010b = 1 step in 4 samples
011b = 1 step in 8 samples
100b = 1 step in 16 samples
101b = 1 step in 32 samples
110b = 1 step in 64 samples
111b = 1 step in 128 samples
0
LIMB_EN
RW
0h
Limiter enable.
0b = Disabled
1b = Enabled
8.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
Sets VBAT limiter release step size, release rate and hold time.
Figure 8-40. LIM_CFG1 Register Address: 0x13
7
6
5
4
3
2
1
0
LIMB_RLS_ST[1:0]
RW-1h
LIMB_RLS_RT[2:0]
RW-6h
LIMB_HLD_TM[2:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-110. Limiter Configuration 1 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
LIMB_RLS_ST[1:0]
RW
1h
VBAT Limiter/BOP/ICLA release step size.
00b = 0.25 dB
01b = 0.5 dB
10b = 1 dB
11b = 2 dB
5-3
LIMB_RLS_RT[2:0]
RW
6h
VBAT Limiter/BOP/ICLA release rate.
000b = 1 step in 10 ms
001b = 1 step in 20 ms
010b = 1 step in 40 ms
011b = 1 step in 80 ms
100b = 1 step in 160 ms
101b = 1 step in 320 ms
110b = 1 step in 640 ms
111b = 1 step in 1280 ms
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Table 8-110. Limiter Configuration 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
LIMB_HLD_TM[2:0]
RW
6h
VBAT Limiter hold time.
000b = 0 ms
001b = 10 ms
010b = 25 ms
011b = 50 ms
100b = 100 ms
101b = 250 ms
110b = 500 ms
111b = 1000 ms
8.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
Sets BOP infinite hold clear, infinite hold enable, mute on brown out and enable.
Figure 8-41. DSP FREQUENCY & BOP_CFG0 Register Address: 0x14
7
6
5
4
3
2
1
0
Reserved
R-0h
BOSD_EN
RW-0h
BOP_HLD_CLR BOP_INF_HLD
RW-0h RW-0h
BOP_MUTE
RW-0h
BOP_EN
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-111. Brown Out Prevention 0 Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
Reserved
BOSD_EN
R
0h
Reserved
RW
0h
Brown out prevention enable.
0b = Disabled
1b = Enabled
3
2
1
0
BOP_HLD_CLR
BOP_INF_HLD
BOP_MUTE
BOP_EN
RW
RW
RW
RW
0h
0h
0h
1h
BOP infinite hold clear (self clearing).
0b = Don't clear
1b = Clear
Infinite hold on brown out event.
0b = Use BOP_HLD_TM after brown out event
1b = Don't release until BOP_HLD_CLR is asserted high
Mute on brown out event.
0b = Don't mute
1b = Mute followed by device shutdown
Brown out prevention enable.
0b = Disabled
1b = Enabled
8.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
BOP attack rate, attack step size and hold time.
Figure 8-42. BOP_CFG0 Register Address: 0x15
7
6
5
4
3
2
1
0
BOP_ATK_RT[2:0]
RW-1h
BOP_ATK_ST[1:0]
RW-1h
BOP_HLD_TM[2:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-112. Brown Out Prevention 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
BOP_ATK_RT[2:0]
RW
1h
Brown out prevention attack rate.
000b = 1 step in 1 sample
001b = 1 step in 2 samples
010b = 1 step in 4 samples
011b = 1 step in 8 samples
100b = 1 step in 16 samples
101b = 1 step in 32 samples
110b = 1 step in 64 samples
111b = 1 step in 128 samples
4-3
2-0
BOP_ATK_ST[1:0]
BOP_HLD_TM[2:0]
RW
RW
1h
6h
Brown out prevention attack step size.
00b = 0.5 dB
01b = 1 dB
10b = 1.5 dB
11b = 2 dB
Brown out prevention hold time.
000b = 0 ms
001b = 10 ms
010b = 25 ms
011b = 50 ms
100b = 100 ms
101b = 250 ms
110b = 500 ms
111b = 1000 ms
8.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
Boost Current limiter and ICLA
Figure 8-43. BIL_and_ICLA_CFG0 Register Address: 0x16
7
6
5
4
3
2
1
0
Reserved
R-0h
BIL_HLD_TM[2:0]
RW-6h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-113. Boost Current limiter and ICLA Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
R
0h
Reserved
6-4
BIL_HLD_TM[2:0]
RW
6h
VBAT current limiter hold time
000b = 0 ms
001b = 10 ms
010b = 25 ms
011b = 50 ms
100b = 100 ms
101b = 250 ms
110b = 500 ms
111b = 1000 ms
3-0
Reserved
R
0h
Reserved
8.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
ICLA starting time slot and enable.
Figure 8-44. BIL_ICLA_CFG1 Register Address: 0x17
7
6
5
4
3
2
1
0
Reserved
RW-0h
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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-114. Inter Chip Limiter Alignment 0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
RW
0h
Reserved
8.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
ICLA starting time slot and enable.
Figure 8-45. GAIN_ICLA_CFG0 Register Address: 0x18
7
6
5
4
3
2
1
1
1
0
0
0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-115. Inter Chip Limiter Alignment 0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
R
0h
Reserved
8.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
ICLA time slot enables.
Figure 8-46. ICLA_CFG1 Register Address: 0x19
7
6
5
4
3
2
Reserved
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-116. Inter Chip Limiter Alignment 1 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
RW
0h
Reserved
8.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
Interrupt masks.
Figure 8-47. INT_MASK0 Register Address: 0x1A
7
6
5
4
3
2
INT_MASK0[7] INT_MASK0[6] INT_MASK0[5] INT_MASK0[4] INT_MASK0[3] INT_MASK0[2] INT_MASK0[1] INT_MASK0[0]
RW-1h RW-1h RW-1h RW-1h RW-1h RW-1h RW-0h RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-117. Interrupt Mask 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK0[7]
RW
1h
Limiter mute mask.
0b = Don't Mask
1b = Mask
6
INT_MASK0[6]
RW
1h
Limiter infinite hold mask.
0b = Don't Mask
1b = Mask
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Table 8-117. Interrupt Mask 0 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
INT_MASK0[5]
RW
1h
Limiter max attenuation mask.
0b = Don't Mask
1b = Mask
4
3
2
1
0
INT_MASK0[4]
INT_MASK0[3]
INT_MASK0[2]
INT_MASK0[1]
INT_MASK0[0]
RW
RW
RW
RW
RW
1h
1h
1h
0h
0h
VBAT below limiter inflection point mask.
0b = Don't Mask
1b = Mask
Limiter active mask.
0b = Don't Mask
1b = Mask
TDM clock error mask.
0b = Don't Mask
1b = Mask
Over current error mask.
0b = Don't Mask
1b = Mask
Over temp error mask.
0b = Don't Mask
1b = Mask
8.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
Interrupt masks.
Figure 8-48. INT_MASK1 Register Address: 0x1B
7
6
5
4
3
2
1
0
Reserved
RW-1h
Reserved
RW-0h
INT_MASK1[5]
RW-1h
INT_MASK1[4:3][1:0]
RW-0h
INT_MASK1[2] INT_MASK1[1] INT_MASK1[0]
RW-1h
RW-1h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-118. Interrupt Mask 1 Field Descriptions
Bit
7
Field
Type
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
Reserved
INT_MASK1[5]
1h
6
0h
5
1h
Load Diagnostic Completion Mask
0b = Don't Mask
1b = Masked
4-3
INT_MASK1[4:3]
RW
0h
Speaker open load mask
00b = Don't Mask
01b = Mask open Load detection
10b = Mask Short Load detection
11b = Mask both Open,Short Load detection
2
1
0
INT_MASK1[2]
INT_MASK1[1]
INT_MASK1[0]
RW
RW
RW
1h
1h
0h
Brownout device power down start mask
0b = Don't Mask
1b = Mask
Brownout Protection Active mask
0b = Don't Mask
1b = Mask
VBAT Brown out detected mask
0b = Don't Mask
1b = Mask
8.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
Interrupt masks.
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Figure 8-49. INT_MASK2 Register Address: 0x1C
7
6
5
4
3
2
1
0
INT_MASK2[7] INT_MASK2[6] INT_MASK2[5] INT_MASK2[4] INT_MASK2[3] INT_MASK2[2] INT_MASK2[1] INT_MASK2[0]
RW-1h
RW-1h
RW-0h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-119. Interrupt Mask 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK2[7]
RW
1h
DAC MOD clock error mask
0b = Don't Mask
1b = Mask
6
5
4
3
2
1
0
INT_MASK2[6]
INT_MASK2[5]
INT_MASK2[4]
INT_MASK2[3]
INT_MASK2[2]
INT_MASK2[1]
INT_MASK2[0]
RW
RW
RW
RW
RW
RW
RW
1h
0h
1h
1h
1h
1h
1h
Boost Clock Error mask
0b = Don't Mask
1b = Mask
VBAT POR mask
0b = Don't Mask
1b = Mask
PLL Lock interrupt mask
0b = Don't Mask
1b = Mask
DC DETECT mask
0b = Don't Mask
1b = Mask
BOOST OV Clamp interrupt mask
0b = Don't Mask
1b = Mask
CP PG mask
0b = Don't Mask
1b = Mask
Device power up intp mask
0b = Don't Mask
1b = Mask
8.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
Interrupt masks.
Figure 8-50. INT_MASK3 Register Address: 0x1D
7
6
5
4
3
2
1
0
INT_MASK3[7]
RW-1h
Reserved
RW-1h
Reserved
RW-1h
INT_MASK3[4] INT_MASK3[3]
RW-1h RW-1h
Reserved
RW-1h
Reserved
RW-1h
Reserved
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-120. Interrupt Mask 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK3[7]
RW
1h
Device power down intp mask
0b = Don't Mask
1b = Mask
6
5
4
Reserved
RW
RW
RW
1h
1h
1h
Reserved
Reserved
Reserved
INT_MASK3[4]
PDM mic clock error intp mask
0b = Don't Mask
1b = Mask
3
INT_MASK3[3]
RW
1h
ASI2 clock error intp mask
0b = Don't Mask
1b = Mask
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Table 8-120. Interrupt Mask 3 Field Descriptions (continued)
Bit
2
Field
Type
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1h
1
1h
0
1h
8.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
Live interrupt readback.
Figure 8-51. INT_LIVE0 Register Address: 0x1F
7
6
5
4
3
2
1
0
INT_LIVE0[7]
R-0h
INT_LIVE0[6]
R-0h
INT_LIVE0[5]
R-0h
INT_LIVE0[4]
R-0h
INT_LIVE0[3]
R-0h
INT_LIVE0[2]
R-0h
INT_LIVE0[1]
R-0h
INT_LIVE0[0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-121. Live Interrupt Readback 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE0[7]
R
0h
Interrupt due to limiter mute.
0b = No interrupt
1b = Interrupt
6
5
4
3
2
1
0
INT_LIVE0[6]
INT_LIVE0[5]
INT_LIVE0[4]
INT_LIVE0[3]
INT_LIVE0[2]
INT_LIVE0[1]
INT_LIVE0[0]
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
Interrupt due to limiter infinite hold.
0b = No interrupt
1b = Interrupt
Interrupt due to limiter max attenuation.
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT below limiter inflection point.
0b = No interrupt
1b = Interrupt
Interrupt due to limiter active.
0b = No interrupt
1b = Interrupt
Interrupt due to TDM clock error.
0b = No interrupt
1b = Interrupt
Interrupt due to over current error.
0b = No interrupt
1b = Interrupt
Interrupt due to over temp error.
0b = No interrupt
1b = Interrupt
8.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
Live interrupt readback.
Figure 8-52. INT_LIVE1 Register Address: 0x20
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
INT_LIVE1[5]
R-0h
INT_LIVE1[4]
R-0h
INT_LIVE1[3]
INT_LIVE1[2]
R-0h
INT_LIVE1[1]
R-0h
INT_LIVE1[0]
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-122. Live Interrupt Readback 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
R
0h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
Reserved
R
0h
5
INT_LIVE1[5]
INT_LIVE1[4]
INT_LIVE1[3]
INT_LIVE1[2]
INT_LIVE1[1]
R
0h
4
R
0h
3
R
0h
2
R
0h
1
R
0h
Brownout Protection Active flag
0b = No interrupt
1b = Interrupt
0
INT_LIVE1[0]
R
0h
Interrupt due to VBAT brown out detected flag.
0b = No interrupt
1b = Interrupt
8.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
Live interrupt readback.
Figure 8-53. INT_LIVE3 Register Address: 0x21
7
6
5
4
3
2
1
0
INT_LIVE2[7]
R-0h
INT_LIVE2[6]
R-0h
INT_LIVE2[5]
R-0h
INT_LIVE2[4]
R-0h
INT_LIVE2[3]
R-0h
INT_LIVE2[2]
R-0h
INT_LIVE2[1]
R-0h
INT_LIVE2[0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-123. Live Interrupt Readback 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE2[7]
R
0h
DAC MOD clock error flag
0b = No interrupt
1b = Interrupt
6
5
4
3
2
1
0
INT_LIVE2[6]
INT_LIVE2[5]
INT_LIVE2[4]
INT_LIVE2[3]
INT_LIVE2[2]
INT_LIVE2[1]
INT_LIVE2[0]
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
Boost Clock error flag
0b = No interrupt
1b = Interrupt
VBAT_POR flag
0b = No interrupt
1b = Interrupt
PLL LOCK flag
0b = No interrupt
1b = Interrupt
DC DETECT flag
0b = No interrupt
1b = Interrupt
BOOST OV Clamp flag
0b = No interrupt
1b = Interrupt
CP PG flag
0b = No interrupt
1b = Interrupt
Device powe up flag
0b = No interrupt
1b = Interrupt
8.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
Live interrupt readback.
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Figure 8-54. INT_LIVE4 Register Address: 0x22
7
6
5
4
3
2
1
0
INT_LIVE3[7]
R-0h
Reserved
R-0h
Reserved
R-0h
INT_LIVE3[4]
R-0h
INT_LIVE3[3]
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-124. Live Interrupt Readback 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE3[7]
R
0h
Device powe down flag
0b = No interrupt
1b = Interrupt
6
5
4
Reserved
R
R
R
0h
0h
0h
Reserved
Reserved
Reserved
INT_LIVE3[4]
PDM mic clock error flag
0b = No interrupt
1b = Interrupt
3
INT_LIVE3[3]
R
0h
ASI2 clock error flag
0b = No interrupt
1b = Interrupt
2
1
0
Reserved
Reserved
Reserved
R
R
R
0h
0h
0h
Reserved
Reserved
Reserved
8.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
Latched interrupt readback.
Figure 8-55. INT_LTCH0 Register Address: 0x24
7
6
5
4
3
2
1
0
INT_LTCH0[7] INT_LTCH0[6] INT_LTCH0[5] INT_LTCH0[4] INT_LTCH0[3] INT_LTCH0[2] INT_LTCH0[1] INT_LTCH0[0]
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-125. Latched Interrupt Readback 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH0[7]
R
0h
Interrupt due to limiter mute (cleared using CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
6
5
4
3
INT_LTCH0[6]
INT_LTCH0[5]
INT_LTCH0[4]
INT_LTCH0[3]
R
R
R
R
0h
0h
0h
0h
Interrupt due to limiter infinite hold (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
Interrupt due to limiter max attenuation (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT below limiter inflection point (cleared
using CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
Interrupt due to limiter active (cleared using CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
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Table 8-125. Latched Interrupt Readback 0 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
INT_LTCH0[2]
R
0h
Interrupt due to TDM clock error (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
1
0
INT_LTCH0[1]
INT_LTCH0[0]
R
R
0h
0h
Interrupt due to over current error (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
Interrupt due to over temp error (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
8.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
Latched interrupt readback.
Figure 8-56. INT_LTCH1 Register Address: 0x25
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
INT_LTCH1[5]
R-0h
INT_LTCH1[4:3][1:0]
R-0h
INT_LTCH1[2] INT_LTCH1[1] INT_LTCH1[0]
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-126. Latched Interrupt Readback 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
INT_LTCH1[5]
R
0h
6
R
0h
5
R
0h
Interrupt due to Load Diagnostic Mode Completion(cleared
using CLR_INTP_LTCH).
0b = Load Diagnostic Mode Not completed
1b = Load Diagnostic Mode Completed
4-3
INT_LTCH1[4:3]
R
0h
Interrupt due to Load Diagnostic Mode Fault Status(cleared
using CLR_INTP_LTCH).
00b = Normal Load
01b = Open Load Detected
10b = Short Load Detected
11b = Reserved
2
1
0
INT_LTCH1[2]
INT_LTCH1[1]
INT_LTCH1[0]
R
R
R
0h
0h
0h
Interrupt due to Brownout Protection Triggered shutdown
(cleared using CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to Brownout Protection Active flag (cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT brown out detected flag (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
8.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
Latched interrupt readback.
Figure 8-57. INT_LTCH3 Register Address: 0x26
7
6
5
4
3
2
1
0
INT_LTCH2[7] INT_LTCH2[6] INT_LTCH2[5] INT_LTCH2[4] INT_LTCH2[3] INT_LTCH2[2] INT_LTCH2[1] INT_LTCH2[0]
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Figure 8-57. INT_LTCH3 Register Address: 0x26 (continued)
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-127. Latched Interrupt Readback 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH2[7]
R
0h
Interrupt due to DAC MOD clock error (cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
6
INT_LTCH2[6]
R
0h
Interrupt due to Boost Clock error (cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
5
4
3
2
INT_LTCH2[5]
INT_LTCH2[4]
INT_LTCH2[3]
INT_LTCH2[2]
R
R
R
R
0h
0h
0h
0h
Interrupt due to VBAT_POR (cleared using CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to PLL LOCK (cleared using CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to DC DETECT (cleared using CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to BOOST OV Clamp (cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
1
0
INT_LTCH2[1]
INT_LTCH2[0]
R
R
0h
0h
Interrupt due to CP PG(cleared using CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
Interrupt due to DEVICE POWER UP(cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
8.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
Latched interrupt readback.
Figure 8-58. INT_LTCH4 Register Address: 0x27
7
6
5
4
3
2
1
0
INT_LTCH3[7]
R-0h
Reserved
R-0h
Reserved
R-0h
INT_LTCH3[4] INT_LTCH3[3]
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-128. Latched Interrupt Readback 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH3[7]
R
0h
Interrupt due to DEVICE POWER DOWN(cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
6
5
4
Reserved
R
R
R
0h
0h
0h
Reserved
Reserved
Reserved
INT_LTCH3[4]
Interrupt due to PDM mic clock error(cleared using
CLR_INTP_LTCH)
0b = No interrupt
1b = Interrupt
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Table 8-128. Latched Interrupt Readback 3 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
INT_LTCH3[3]
R
0h
Interrupt due to ASI2 clock error (cleared using
CLR_INTP_LTCH).
0b = No interrupt
1b = Interrupt
2
1
0
Reserved
Reserved
Reserved
R
R
R
0h
0h
0h
Reserved
Reserved
Reserved
8.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
MSBs of SAR ADC VBAT conversion.
Figure 8-59. VBAT_MSB Register Address: 0x2A
7
6
5
4
3
2
1
0
VBAT_CNV[9:2]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-129. SAR ADC Conversion 0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
VBAT_CNV[9:2]
R
0h
Returns SAR ADC VBAT conversion MSBs.
8.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
LSBs of SAR ADC VBAT conversion.
Figure 8-60. VBAT_LSB Register Address: 0x2B
7
6
5
4
3
2
1
0
VBAT_CNV[1:0]
R-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-130. SAR ADC Conversion 1 Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
VBAT_CNV[1:0]
Reserved
R
0h
Returns SAR ADC VBAT conversion LSBs.
Reserved
R
0h
8.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
SARD ADC Temp conversion.
Figure 8-61. TEMP Register Address: 0x2C
7
6
5
4
3
2
1
0
TMP_CNV[7:0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-131. SAR ADC Conversion 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TMP_CNV[7:0]
R
0h
Returns SAR ADC temp sensor conversion.
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8.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
Figure 8-62. INT & CLK CFG Register Address: 0x30
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
CLR_INTP_LTC
H
IRQZ_PIN_CFG[1:0]
RW-0h
RW-0h
RW-3h
RW-0h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-132. Field Descriptions
Bit
7
Field
Type
RW
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CLR_INTP_LTCH
0h
6
0h
5-3
2
3h
0h
Clear INT_LTCH registers to clear interrupts (self clearing bit)
0b = Don't clear
1b = Clear INT_LTCH registers
1-0
IRQZ_PIN_CFG[1:0]
RW
1h
IRQZ interrupt configuration.
00b = IRQZ will assert on any unmasked live interrupts
01b = IRQZ will assert on any unmasked latched interrupts
10b = IRQZ will assert for 2-4ms one time on any unmasked live
interrupt event
11b = IRQZ will assert for 2-4ms every 4ms on any unmasked
latched interrupts
8.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
Sets enables of input pin weak pull down.
Figure 8-63. DIN_PD Register Address: 0x31
7
6
5
4
3
2
1
0
DIN_PD[7]
RW-0h
Reserved
RW-1h
DIN_PD[5]
RW-0h
DIN_PD[4]
RW-0h
DIN_PD[3]
RW-0h
DIN_PD[2]
RW-0h
DIN_PD[1]
RW-0h
DIN_PD[0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-133. Digital Input Pin Pull Down Field Descriptions
Bit
Field
Type
Reset
Description
7
DIN_PD[7]
RW
0h
Weak pull down for SBCLK2
0b = Disabled
1b = Enabled
6
5
Reserved
RW
RW
1h
0h
Reserved
DIN_PD[5]
Weak pull down for SPII2CZ_MISO
0b = Disabled
1b = Enabled
4
3
2
1
DIN_PD[4]
DIN_PD[3]
DIN_PD[2]
DIN_PD[1]
RW
RW
RW
RW
0h
0h
0h
0h
Weak pull down for ADDR_SPICLK
0b = Disabled
1b = Enabled
Weak pull down for SDOUT
0b = Disabled
1b = Enabled
Weak pull down for SDIN.
0b = Disabled
1b = Enabled
Weak pull down for FSYNC.
0b = Disabled
1b = Enabled
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Table 8-133. Digital Input Pin Pull Down Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
DIN_PD[0]
RW
0h
Weak pull down for SBCLK.
0b = Disabled
1b = Enabled
8.5.45 MISC (page=0x00 address=0x32) [reset=80h]
Set IRQZ pin active state
Figure 8-64. MISC Register Address: 0x32
7
6
5
4
3
2
1
0
IRQZ_POL
RW-1h
Reserved
RW-0h
Reserved
R-0h
Reserved
RW-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-134. Misc Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7
IRQZ_POL
RW
1h
IRQZ pin polarity for interrupt.
0b = Active high (IRQ)
1b = Active low (IRQZ)
6-4
3-2
1
Reserved
Reserved
Reserved
Reserved
RW
R
0h
0h
0h
0h
Reserved
Reserved
Reserved
Reserved
RW
R
0
8.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
Boost Configure 1
Figure 8-65. BOOST_CFG1 Register Address: 0x33
7
6
5
4
3
2
1
0
BST_MODE
BST_MODE
BST_EN
Reserved
RW-2h
BST_PFML[1:0]
RW-2h
BST_DYNAMIC
_ILIM_EN
RW-0h
RW-0h
RW-1h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-135. Boost Configure 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
BST_MODE
BST_MODE
RW
0h
Boost Mode
6
RW
0h
Boost Mode
00b = Class-H
01b = Class-G
10b = Boost always ON
11b = Boost always OFF(Passthrough)
5
BST_EN
RW
1h
Boost enable
0b = Disabled
1b = Enabled
4-3
2-1
Reserved
RW
RW
2h
2h
Reserved
BST_PFML[1:0]
Boost active mode PFM lower limit
00b = No lower limit
01b = 25 kHz
10b = 50 kHz
11b = 100 kHz
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Table 8-135. Boost Configure 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
BST_DYNAMIC_ILIM_EN
RW
0h
Dynamic Current Limiter based on VBAT
0b = Disabled
1b = Enabled
8.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
Boost Configure 2
Figure 8-66. BOOST_CFG2 Register Address: 0x34
7
6
5
4
3
2
1
0
BST_IR[1:0]
RW-1h
BST_SYNC
RW-0h
BST_PA
RW-0h
BST_VREG[3:0]
RW-Bh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-136. Boost Configure 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
BST_IR[1:0]
RW
1h
Boost inductor range
00b = less than 0.6 uH
01b = 0.6 uH to 1.3 uH
10b = 1.3 uH to 2.5 uH
11b = Reserved
5
4
BST_SYNC
BST_PA
RW
RW
RW
0h
0h
Bh
Boost sync to clock
0b = Not synced
1b = Synced
Boost sync phase
0b = 0 deg
1b = 180 deg
3-0
BST_VREG[3:0]
Boost Maximum Voltage(Default 11 V)
0000b = Reserved
0001b = 6 V
0010b = 6.5 V
....
1110b = 12.5 V
1111b = Reserved
8.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
Boost Configure 3
Figure 8-67. BOOST_CFG3 Register Address: 0x35
7
6
5
4
3
2
1
0
BST_CLASSH_STEP_TIME[3:0]
RW-7h
BST_LR[1:0]
RW-1h
Reserved
RW-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-137. Boost Configure 3 Field Descriptions
Bit
Field
Type
Reset
Description
7-4
BST_CLASSH_STEP_TIME[3:0]
RW
7h
Step Time for Boost if in Class-H mode
0000b = 9us
0001b = 18us
0010b = 36us
0011b = 54us
0100b = 72us
0101b = 90us
0110b = 108us
0111b = 135us
1000b = 162us
1001b = 198us
1010b = 252us
1011b = 342us
1100b = 477us
1101b = 612us
1110b = 792us
1111b = 990us
3-2
BST_LR[1:0]
RW
1h
Slope of boost load regulation.
00b = Reserved
01b = 3A/V; load regulation = 1V (default)
10b = 2A/V; load regulation = 1.5V
11b = Reserved
1
0
Reserved
Reserved
RW
R
0h
0h
Reserved
Reserved
8.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
Figure 8-68. MISC Register Address: 0x3B
7
6
5
4
3
2
1
0
HAPTIC_EN
RW-0h
Reserved
RW-2h
Reserved
RW-3h
Reserved
RW-0h
Reserved
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-138. Field Descriptions
Bit
Field
Type
Reset
Description
7
HAPTIC_EN
RW
0h
Haptics mode is
0b = Disabled
1b = Enabled
6-5
4-3
2
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
2h
3h
0h
0h
Reserved
Reserved
Reserved
Reserved
1-0
8.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
Tone Generator
Figure 8-69. TG_CFG0 Register Address: 0x3F
7
6
5
4
3
2
1
0
TG1_EN[1:0]
RW-0h
TG1_PINEN[1:0]
RW-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 8-139. Tone Generator Field Descriptions
Bit
Field
Type
Reset
Description
7-6
TG1_EN[1:0]
RW
0h
Tone Generator 1 is
00b = Disabled or pin triggered
01b = Enabled - play tone
10b = audio level enabled
11b = reserved
5-4
3-0
TG1_PINEN[1:0]
Reserved
RW
R
0h
0h
Tone pin trigger
00b = Disabled
01b = SDIN
10b = GPIO
11b = AD1
Reserved
8.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
Boost ILIM configuration-0
Figure 8-70. BST_ILIM_CFG0 Register Address: 0x40
7
6
5
4
3
2
1
0
BST_SSL[7:6]
RW-0h
BST_ILIM[5:0]
RW-36h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-140. Boost ILIM configuration-0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BST_SSL[7:0]
RW
0h
Boost peak current limit
00h = 0.99 A
01h = 1.045 A
02h = 1.1 A
...
36h = 3.96 A
37h = 4 A
38h-3Fh = Reserved
8.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
Figure 8-71. PDM_CONFIG0 Register Address: 0x41
7
6
5
4
3
2
1
0
Reserved
PDM_GATE_PA PDM_RATE_PA DIS_PDM_MIC PDM_PAD0_C PDM_MIC2_E PDM_MIC1_E PDM_MIC_SLV
D0[6:6]
RW-1h
D0[5:5]
RW-0h
_CLK_ERR_PA AP_EDGE[3:3]
D0[4:4]
N[2:2]
N[1:1]
R-0h
RW-0h
RW-0h
RW-0h
RW-0h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-141. Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
R
0h
Reserved
6
PDM_GATE_PAD0
RW
1h
Clock gating for master mode PAD0
0b=Disabled
1b=Enabled
5
4
PDM_RATE_PAD0
RW
RW
0h
0h
PDM data rate of PAD0
0b=3.072 MHz
1b=6.144 MHz
DIS_PDM_MIC_CLK_ERR_PAD0
Disable PDM Mic. clock error on PAD0 detection
0b=Clock error detection is enabled
1b=Clock error detection is disabled
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Table 8-141. Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
PDM_PAD0_CAP_EDGE
RW
0h
Capture edge of PDM mic data for PAD0
0b=MIC1 captured on positive edge. MIC2 captured on negative
edge
1b=MIC1 captured on negative edge. MIC2 captured on positive
edge
2
1
0
PDM_MIC2_EN
PDM_MIC1_EN
PDM_MIC_SLV
RW
RW
RW
0h
0h
1h
Control for PDM MIC2 path
0b=MIC2 path is disabled
1b=MIC2 path is enabled
Control for PDM MIC1 path
0b=MIC1 path is disabled
1b=MIC1 path is enabled
Device in PDM MIC SLAVE or MASTER
0b=Device is in PDM MIC master mode
1b=Device is in PDM Slave mode
8.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
Figure 8-72. DIN_PD & PDM_CONFIG3 Register Address: 0x42
7
6
5
4
3
2
1
0
DIN_PD[14]
DIN_PD[13]
Reserved
wk_pulldown_p wk_pulldown_p
Reserved
dmd_pad0
dmck_pad0
RW-0h
RW-0h
R-0h
RW-0h
RW-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-142. Field Descriptions
Bit
Field
Type
Reset
Description
7
DIN_PD[14]
RW
0h
Weak pull down for SDIN2
0b=Disabled
1b=Enabled
6
DIN_PD[13]
RW
0h
Weak pull down for SDIN1
0b=Disabled
1b=Enabled
5
4
Reserved
R
0h
0h
Reserved
wk_pulldown_pdmd_pad0
RW
Control for pull down of PDMD PAD0
0b=Disable the pull down control
1b=Enable the pull down control
3
wk_pulldown_pdmck_pad0
Reserved
RW
R
0h
0h
Control for pull down of PDMD PAD0
0b=Disable the pull down control
1b=Enable the pull down control
2-0
Reserved
8.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
Figure 8-73. ASI2_CONFIG0 Register Address: 0x43
7
6
5
4
3
2
1
0
tx_fill_asi2[7:7]
RW-0h
asi2_sbclk_fs_ratio[6:3]
RW-1h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-143. Field Descriptions
Bit
Field
Type
Reset
Description
7-0
tx_fill_asi2[7:0]
RW
0h
Reserved
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8.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
Figure 8-74. ASI2_CONFIG1 Register Address: 0x44
7
6
5
4
3
2
1
0
asi2_auto_rate[ asi2_tx_lsb_half rx_edge_asi2[5: tx_edge_asi2[4:
Reserved
asi2_sbclk_mas
ter
7:7]
_cycle_reg[6:6]
5]
4]
RW-0h
RW-0h
RW-0h
RW-0h
R-0h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-144. Field Descriptions
Bit
Field
Type
Reset
Description
7-0
asi2_auto_rate[7:0]
RW
0h
ASI2 SBCLK master mode enable
0b = SBCLK2 in slave mode
1b = SBCLK2 in master mode
8.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
Figure 8-75. ASI2_CONFIG2 Register Address: 0x45
7
6
5
4
3
2
1
0
tx_offset_asi2[7:5]
RW-0h
rx_offset_asi2[4:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-145. Field Descriptions
Bit
Field
Type
Reset
Description
7-0
tx_offset_asi2[7:0]
RW
0h
TDM2 RX start of frame to time slot 0 offset (ASI2_SBCLK
cycles)
8.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
Figure 8-76. ASI2_CONFIG3 Register Address: 0x46
7
6
5
4
3
2
1
0
Reserved
asi2_tx_keeper[ asi2_sdout_bus num_slots[4:4]
num_devices[3:2]
my_device_num[1:0]
6:6]
keeper_always_
en[5:5]
R-1h
RW-1h
RW-1h
RW-1h
RW-3h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-146. Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
R
1h
My device number on the common BUS
00b = 1st
01b = 2nd
10b = 3rd
11b = 4th
8.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
MSBs of SAR ADC PVDD conversion.
Figure 8-77. PVDD_MSB_DSP Register Address: 0x49
7
6
5
4
3
2
1
0
PVDD_CNV_DSP[9:2]
R-0h
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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-147. SAR ADC Conversion 0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PVDD_CNV_DSP[9:2]
R
0h
Returns SAR ADC PVDD conversion MSBs.
8.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
LSBs of SAR ADC PVDD conversion.
Figure 8-78. PVDD_LSB_DSP Register Address: 0x4A
7
6
5
4
3
2
1
0
0
0
PVDD_CNV_DSP[1:0]
R-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-148. SAR ADC Conversion 1 Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
PVDD_CNV_DSP[1:0]
Reserved
R
0h
Returns SAR ADC PVDD conversion LSBs.
Reserved
R
0h
8.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
Returns REV and PG ID.
Figure 8-79. REV_ID Register Address: 0x7D
5
7
6
4
3
2
1
REV_ID[3:0]
R-0h
PG_ID[3:0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-149. Revision and PG ID Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
REV_ID[3:0]
PG_ID[3:0]
R
0h
Returns the revision ID.
Returns the PG ID.
R
0h
8.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
Returns I2C checksum.
Figure 8-80. I2C_CKSUM Register Address: 0x7E
7
6
5
4
3
2
1
I2C_CKSUM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-150. I2C Checksum Field Descriptions
Bit
Field
Type
Reset
Description
7-0
I2C_CKSUM[7:0]
RW
0h
Returns I2C checksum. Writing to this register will reset the
checksum to the written value. This register is updated on writes
to other registers on all books and pages.
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8.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
Device's memory map is divided into pages and books. This register sets the book.
Figure 8-81. BOOK Register Address: 0x7F
7
6
5
4
3
2
1
0
BOOK[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-151. Device Book Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BOOK[7:0]
RW
0h
Sets the device book.
00h = Book 0
01h = Book 1
...
FFh = Book 255
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TAS2563 is a digital input high efficiency Class-D audio power amplifier with advanced battery current
management and an integrated Class-H boost converter. In auto passthrough mode, the Class-H boost
converter generates the Class-D amplifier supply rail. During low Class-D output power, the boost improves
efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When high power audio
is required, the boost quickly activates to provide louder audio than a stand-alone amplifier connected directly to
the battery. To enable load monitoring, the TAS2563 constantly measures the current and voltage across the
load and provides a digital stream of this information back to a processor. It is recommended to configure the
TAS2563 using Section 8.3.1.
9.2 Typical Application
1.8V
2.5 V œ 5.5 V
4.5 V œ 9 V
L1
1 mH
C1
10 mF
C5
4.7 mF
C8
1 mF
VDD
SW
VBAT2S
VBAT
GREG
C7
100 nF
DREG
VBST
PVDD
C6
1mF
C2
10 mF
Enable
SDZ
L2 (opt.)
+
-
OUT_P
OUT_M
To
Speaker
AD1
AD0
L3 (opt.)
I2C Interface
I2S Interface
I2C
I2S
2
4
C4
1 nF
(opt.)
C3
1 nF
(opt.)
GND
BGND
PGND
Figure 9-1. Typical Application - Digital Audio Input
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Table 9-1. Recommended External Components
COMPONENT
DESCRIPTION
SPECIFICATION
Inductance, 20% Tolerance
Saturation Current
Impedance at 100 MHz
DC Resistance
MIN
TYP
MAX
UNIT
µH
A
0.47
1
L1
Boost Converter Inductor(1)
4.5
120
Ω
EMI Filter Inductors (optional). These are
not recommended as it degrades THD+N
performance. TAS2563 is a filter-less
Class-D and does not require these bead
inductors.
0.095
Ω
L2, L3
C1
DC Current
2
A
Size
0402
EIA
µF
Boost Converter Input Capacitor(1)
Capacitance, 20% Tolerance
Type
10
X5R
10
Capacitance, 20% Tolerance
Rated Voltage
47
µF
V
C2
Boost Converter Output Capacitor
16
Capacitance at 11.5 V derating
3.3
µF
EMI Filter Capacitors (optional, must use
L2, L3 if C3, C4 used)
C3, C4
Capacitance
1
nF
C5
C6
C7
VDD Decoupling Capacitor
DREG Decoupling Capacitor
GREG Fly Capacitor
Capacitance
Capacitance
Capacitance
4.7
1
µF
µF
nF
100
(1) See section Section 9.2.2.2 for additional requirements on derating, stability, and inductor value trade-offs.
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 9-2.
Table 9-2. Design Parameters
DESIGN PARAMETER
Audio Input
EXAMPLE VALUE
Digital Audio, I2S
Digital Audio, I2S
Mono
Current and Voltage Data Stream
Mono or Stereo Configuration
Max Output Power at 1% THD+N
5.0 W
9.2.2 Detailed Design Procedure
9.2.2.1 Mono/Stereo Configuration
In this application, the device is assumed to be operating in mono mode. See Section 8.3.2 for information on
changing the I2C address of the TAS2563 to support stereo operation. Mono or stereo configuration does not
impact the device performance.
9.2.2.2 Boost Converter Passive Devices
The boost converter requires three passive devices that are labeled L1, C1 and C2 in Section 9.2 and whose
specifications are provided in Table 9-1. These specifications are based on the design of the TAS2563 and are
necessary to meet the performance targets of the device. In particular, L1 should not be allowed to enter in the
current saturation region. The saturation current for L1 should be > ILIM to deliver Class-D peak power.
Additionally, the ratio of L1/C2 (the derated value of C2 at 11.5 V should be used in this ratio) has to be lesser
than 1/3 for boost stability. This 1/3 ratio should be maintained including the worst case variation of L1 and C2.
To satisfy sufficient energy transfer, L1 needs to be ≥ 0.47 μH at the boost switching frequency (100 kHz to 4
MHz). Using a 0.47 μH will have more boost ripple than a 1.0 μH or 2.2 μH but the high PSRR should minimize
the effect from the additional ripple. Finally, the minimum C2 (derated value at programmed boost voltage)
should be > 3.3 μF for Class-D power delivery specification.
9.2.2.3 EMI Passive Devices
The TAS2563 supports edge-rate control to minimize EMI, but the system designer may want to include passive
devices on the Class-D output devices. These passive devices that are labeled L2, L3, C3 and C4 in Section 9.2
and their recommended specifications are provided in Table 9-1. If C3 and C4 are used, L2 and L3 must also be
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installed, and C3 and C4 must be placed after L2 and L3 respectively to maintain the stability of the output
stage.
9.2.2.4 Miscellaneous Passive Devices
The GREG Capacitor requires 100 nF to meet boost and Class-D power delivery and efficiency specs. For best
device performance, the GREG capacitor should be placed very close to the device and be routed with wide
traces to minimize the impact of PCB parasitic effects.
9.2.3 Application Curves
10
5
10
5
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
VBAT=3.1V
VBAT=3.6V
VBAT=4.2V
VBAT=5.5V
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
0.001
0.010.02 0.05 0.1 0.2 0.5
Pout(W)
1
2
3 45 7 10
0.001
0.010.02 0.05 0.1 0.2 0.5
Pout(W)
1
2 3 45 7 10
D002
D006
RL = 4 Ω
FIN = 1 kHz
FIN = 20 Hz – 20 kHz
POUT = 0.1 W
RL = 8 Ω
Figure 9-2. THD+N vs Output Power
Figure 9-3. THD+N vs Frequency
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10 Power Supply Recommendations
10.1 Power Supplies
The TAS2563 requires four power supplies:
•
Boost Input (terminal: VBAT)
– Voltage: 2.9 V to 5.5 V
– Max Current: 5 A for ILIM = 4.0 A (default)
Analog Supply (terminal: VDD)
– Voltage: 1.65 V to 1.95 V
– Max Current: 30 mA
•
•
IO Supply (terminal: IOVDD)
– Voltage: 1.65 V to 3.6 V
– Max Current: 30 mA
The decoupling capacitors for the power supplies should be placed close to the device terminals.
10.2 Power Supply Sequencing
The power rail may be brought up and down in any order. There is no requirement on sequencing. However if
VDD is present without VBAT an additional rise in VDD current will be observed until VBAT is present.
When the supplies have settled, the SDZ terminal can be set HIGH to operate the device. Additionally the SDZ
pin can be tied to VDD and the internal POR will perform a reset of the device. After a hardware or software
reset additional commands to the device should be delayed for 100 uS to allow the OTP to load. The above
sequence should be completed before any I2C operation.
10.2.1 Boost Supply Details
The boost supply (VBAT) and associated passives need to be able to support the current requirements of the
device. By default, the peak current limit of the boost is set to 4 A. Refer to Section 8.5.51 for information on
changing the current limit. A minimum of a 10 µF capacitor is recommended on the boost supply to quickly
support changes in required current. Refer to Section 9.2 for the schematic.
The current requirements can also be reduced by lowering the gain of the amplifier, or in response to decreasing
battery through the use of the battery-tracking feature of the TAS2563 described in Section 8.4.3.6.
10.2.2 External Boost Mode (Boost Bypass Mode)
Its is very important that during external boost mode, VBAT and SW should be open on board.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
Place the boost inductor between VBAT and SW close to device terminals with no VIAS between the device
terminals and the inductor.
Place the capacitor between VBST close to device terminals with no VIAS between the device terminals and
capacitor.
Place the capacitor between VBST/VBAT and GND close to device terminals with no VIAS between the
device terminals and capacitor.
Do not use VIAS for traces that carry high current. These include the traces for VBST, SW, VBAT, PGND and
the speaker OUT_P, OUT_M.
•
•
Use epoxy filled vias for the interior pads.
Connect VSNS_P, VSNS_N as close as possible to the speaker.
– VSNS_P, VSNS_N should be connected between the EMI ferrite and the speaker if EMI ferrites are used
on OUT_P, OUT_M.
– EMI ferrites must be used if EMI capacitors are used on OUT_P, OUT_M.
•
Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for
minimum ground noise.
•
•
Use supply decoupling capacitors as shown in Section 9.2 and described in Section 10.1.
Place EMI ferrites, if used, close to the device.
Table 11-1. Pin Layout Guidelines
PIN
MAX PARASITIC INDUCTANCE
LAYOUT RECOMMENDATIONS
BGND, GND, PGND, GNDD
150 pH
Short BGND, GND, GNDD, PGDN below the package and
connect them to PCB ground plane strongly through
multiple vias. Minimize inductance as much as possible
DREG
500 pH
Bypass to GND with capacitor recommended in Table 9-1.
Do not connect to external load. Both ends of decoupling
cap should see as low inductance as possible between this
pin and gnd pins.
GREG
PVDD
SW
200 pH
100 pH
Connect it to PVDD with a star connection and not to boost
plane with recommended in Table 9-1. Do not connect to
external load.
Short it to VBST(boost) plane through strong conneciton.
Connect it to GREG with a star connection and not to
boost plane.
Connect to VBAT with boost inductor recommended in
Table 9-1. Reduce parasitic capacitor and resistance for
efficiency. Boost inductor should be as close as possible to
the SW pin. Inductor should be connected to SW through
thick plane. Traces should support currents up to device
over-current limit.
VBAT
VBST
500 pH
100 pH
Bypass to GND with capacitor recommended in Table 9-1.
Should be connected to inductor through thick plane. Both
ends of decoupling capacitor should see as low inductance
as possible between VBAT pin and PGND pin.
Do not connect to external load. Bypass to GND with
capacitor recommended in Table 9-1. Connect to PVDD
through thick plane. Both ends of decoupling capacitor
should see as low inductance as possible between VBST
pin and BGND pin. Traces should support currents up to
device over-current limit.
VDD
200 pH
Bypass to GND with capacitor recommended in Table 9-1.
Both the end of decoupling cap should see as low
inductance as possible between this pin and GND pin
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11.2 Layout Example
Figure 11-1. WCSP Package PCB Solution
Figure 11-2. WCSP package Top Layer
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Figure 11-3. WCSP Package Mid-Layer 1
Figure 11-4. WCSP Package Mid-Layer2
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Figure 11-5. WCSP Package Bottom Layer
Figure 11-6. QFN Package PCB Solution
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Figure 11-7. QFN Package Top Layer
Figure 11-8. QFN Package Bottom Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: TAS2563YBGEVM-DC Evaluation module user's guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PurePath™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
TAS2563YBG
YBG0042-C01
DSBGA - 0.5 mm max height
SCALE 5.000
DIE SIZE BALL GRID ARRAY
2.558
2.518
A
B
BALL A1
CORNER
3.017
2.977
C
0.5 MAX
SEATING PLANE
0.05 C
BALL TYP
0.20
0.14
2
TYP
(0.2111)
PKG
(0.3269)
G
(0.2409)
F
E
2.4
0.0576
TYP
BALL ARRAY
PKG
D
C
B
0.4 TYP
A
(0.3561)
0.27
0.23
2
1
4
5
6
3
42X
0.015
0.0579
C A B
BALL ARRAY
0.4 TYP
4224770/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
TAS2563YBG
YBG0042-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
42X ( 0.23)
(0.0579)
2
3
1
4
5
6
A
(0.4) TYP
B
C
PKG
SYMM
BALL ARRAY
D
E
(0.0576)
F
G
PKG
SYMM
BALL ARRAY
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224770/A 01/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
TAS2563YBG
YBG0042-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(0.0579)
42X ( 0.25)
(R0.05) TYP
2
3
1
4
5
6
A
(0.4) TYP
B
METAL
TYP
C
PKG
SYMM
BALL ARRAY
D
(0.0576)
E
F
G
SYMM
BALL ARRAY
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 30X
4224770/A 01/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OUTLINE
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
4.6
4.4
A
B
PIN 1 INDEX AREA
4.1
3.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08
C
0.533
PKG
0.5
0.3
(0.367)
8X
1.0
0.8
0.017
(0.167)
24X 0.4
TYP (0.1)
(0.226)
(0.3)
(0.626)
16
9
(0.25)
(0.65)
17
8
1.3
1.1
3X
0.7
0.5
3X
4X 0.55
PKG
2X 0.475
0.2
0.3
0.2
0.1
0.05
C A B
0.224
C
0.95
0.75
0.513
1.4
1.2
2X
1
0.75
0.55
(0.674)
24
(0.5)
32
25
0.55
0.35
(0.35)
(0.15)
5X
(0.175)
(0.3)
0.25
0.15
27X
(0.274)
0.6
0.4
2X (0.7)
4X
0.1
C
C
A B
0.05
4226018/A 07/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
(1.1)
2X (0.9)
(0.325)
(0.7)
(0.55)
PKG
(0.874)
(1.05)
2X (0.2)
(0.85)
25
32
(1.875)
(1.775)
(1.675)
24
(1.6626)
1
(1.526)
(1.45)
2X
(1.5)
(0.513)
5X (0.4)
4X (0.55)
(0.25)
PKG
24X (0.4)
(0.2)
(0.224)
(R0.05)
(0.826)
3X (0.8)
5X (0.65)
(1.5)
(1.574)
(1.8)
17
8
3X
(1.5499)
(1.4)
(0.85)
(1.875)
9
16
(1.9)
4X (0.7)
(0.017)
(0.567)
8X (0.6)
27X (0.2)
(0.5334)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 16X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
DEFINED
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226018/A 07/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
(1.1)
2X (0.875)
(0.325)
(0.7)
(0.55)
PKG
(0.849)
2X (0.2)
(1.05)
(0.85)
25
32
(1.875)
(1.775)
(1.675)
24
(1.6626)
1
(1.526)
(1.45)
2X
(1.5)
(0.513)
5X (0.35)
(0.25)
PKG
4X (0.55)
24X (0.4)
(0.224)
(R0.05)
(0.2)
(0.801)
3X (0.8)
5X (0.65)
(1.5)
(1.574)
(1.8)
17
8
3X
(1.5499)
(1.4)
(0.825)
(1.875)
9
16
(1.9)
4X (0.7)
(0.017)
(0.567)
8X (0.6)
27X (0.2)
(0.5334)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 1: 93% , PAD 8: 92%, PAD 17: 87%, PAD 24: 94%
SCALE: 16X
4226018/A 07/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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11-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTAS2563RPPT
TAS2563RPPR
TAS2563RPPT
ACTIVE
VQFN-HR
RPP
32
32
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Call TI
-40 to 85
-40 to 85
-40 to 85
TAS2563
P
PREVIEW VQFN-HR
PREVIEW VQFN-HR
RPP
3000 RoHS (In work)
& Non-Green
Call TI
Call TI
RPP
250
RoHS (In work)
& Non-Green
Call TI
TAS2563YBGR
TAS2563YBGT
ACTIVE
ACTIVE
DSBGA
DSBGA
YBG
YBG
42
42
3000 RoHS & Green
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TAS2-DSA
TAS2-DSA
250 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS2563YBGR
TAS2563YBGT
DSBGA
DSBGA
YBG
YBG
42
42
3000
250
330.0
330.0
12.4
12.4
2.71
2.71
3.17
3.17
0.6
0.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS2563YBGR
TAS2563YBGT
DSBGA
DSBGA
YBG
YBG
42
42
3000
250
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YBG0042
DSBGA - 0.5 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
0.20
0.14
BALL TYP
2 TYP
SYMM
G
F
E
D
2.4
TYP
SYMM
D: Max = 2.987 mm, Min =2.927 mm
E: Max = 2.529 mm, Min =2.468 mm
C
B
A
0.4 TYP
0.27
2
1
4
5
6
3
42X
0.23
0.015
C A B
0.4 TYP
4224566/A 09/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YBG0042
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
42X ( 0.23)
2
1
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
G
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224566/A 09/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBG0042
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
42X ( 0.25)
(0.4) TYP
(R0.05) TYP
6
2
1
4
5
A
B
C
SYMM
METAL
TYP
D
E
F
G
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 30X
4224566/A 09/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
RPP 32
4.5 x 4, 0.4 mm pitch
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226439/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
4.6
4.4
A
B
PIN 1 INDEX AREA
4.1
3.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08
C
0.533
PKG
0.5
0.3
8X
1.0
0.8
(0.367)
0.017
(0.167)
24X 0.4
TYP (0.1)
(0.226)
(0.3)
(0.626)
16
9
(0.25)
(0.65)
17
8
1.3
1.1
3X
0.7
0.5
3X
4X 0.55
PKG
2X 0.475
0.2
0.3
0.2
0.1
0.05
C A B
0.224
C
0.95
0.75
0.513
1.4
1.2
2X
1
0.75
0.55
(0.674)
24
(0.5)
32
25
0.55
0.35
(0.274)
(0.35)
(0.15)
5X
(0.175)
(0.3)
0.25
27X
0.15
0.6
0.4
2X (0.7)
4X
0.1
C
C
A B
0.05
4226018/A 07/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
(1.1)
2X (0.9)
(0.325)
(0.7)
(0.55)
2X (0.2)
PKG
(0.874)
(1.05)
(0.85)
25
32
(1.875)
(1.775)
(1.675)
24
(1.6626)
1
(1.526)
(1.45)
2X
(1.5)
(0.513)
5X (0.4)
4X (0.55)
(0.25)
PKG
24X (0.4)
(0.2)
(0.224)
(R0.05)
(0.826)
3X (0.8)
5X (0.65)
(1.5)
(1.574)
(1.8)
17
8
3X
(1.5499)
(1.4)
(0.85)
(1.875)
9
16
(1.9)
4X (0.7)
(0.017)
(0.567)
8X (0.6)
27X (0.2)
(0.5334)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 16X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226018/A 07/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RPP0032B
(1.1)
2X (0.875)
(0.325)
(0.7)
(0.55)
2X (0.2)
PKG
(0.849)
(1.05)
(0.85)
25
32
(1.875)
(1.775)
(1.675)
24
(1.6626)
1
(1.526)
(1.45)
2X
(1.5)
(0.513)
5X (0.35)
(0.25)
PKG
4X (0.55)
24X (0.4)
(0.224)
(R0.05)
(0.2)
(0.801)
3X (0.8)
5X (0.65)
(1.5)
(1.574)
(1.8)
17
8
3X
(1.5499)
(1.4)
(0.825)
(1.875)
9
16
(1.9)
4X (0.7)
(0.017)
(0.567)
8X (0.6)
27X (0.2)
(0.5334)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 1: 93% , PAD 8: 92%, PAD 17: 87%, PAD 24: 94%
SCALE: 16X
4226018/A 07/2020
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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