TAS2764_技术文档

TAS2764

ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

TAS2764 具有扬声器IV 检测功能的数字输入单声道D 类音频放大器

1 特性

3 说明

• 关键特性

– Y 桥电源架构

– 边沿和扩频控制

– 高达40kHz 的满量程超声波输出

• 输出功率(1 % THD+N)

TAS2764 是一款单声道数字输入 D 类音频放大器，专

为将高峰值功率有效驱动到小型扬声器进行了优化。该

D 类放大器在 12V 电源电压下可向 4Ω 负载提供 13W

的连续功率，同时保持THD+N 小于1 %。

Y 桥架构改善了低输出功率电平和闲置模式下的整体效

率。

– 13W（4Ω，12V）

– 8W（8Ω，12V）

• 功耗（1 % THD+N，4Ω，12V）

– 1W 下效率达81%

– 13W 下效率达85%

– 噪声门模式下为3mA

– 硬件关断模式下低于1uA

• 电源和管理

集成式扬声器电压和电流检测实时监控扬声器行为。电

源跟踪峰值电压限制器优化了放大器余量。具有多个阈

值的欠压预防方案能够在电源出现压降时减少信号路径

中的增益。

TAS2764 支持超声波输出，能够用于运动和接近检

测、姿势检测等高级超声波应用。

最多八个TAS2764 器件可通过I²S/TDM 和I²C 接口共

用一根公共总线。

– PVDD：2.3 V 至16 V

– VBAT1S：2.3V 至5.5V

– AVDD：1.8V

– IOVDD：1.2V/1.8V

– 欠压保护

该器件采用 30 焊球0.4mm 间距CSP 封装，可实现紧

凑的PCB 尺寸。

– PVDD 跟踪峰值电压限制器

• 接口和控制

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

– SDOUT 和I²S 反馈实现回声消除

– I²S/TDM：8 个通道（32 位），每个通道高达

96kHz

– I²C：具有快速模式增强版支持的8 个地址

– 44.1 kHz 至96kHz 采样速率

– 芯片间通信总线

TAS2764

DSBGA

2.128 mm x 2.542 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 集成扬声器管理和保护功能

– 扬声器电压和电流检测

– 短路和开路保护

– 热保护和过流保护

– 过功率保护

2 应用

• 笔记本电脑

• 平板电脑

• 无线扬声器

• 智能扬声器

• 消费类音频器件

原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLOS998

TAS2764

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

Table of Contents

9.1 Application Information............................................. 87

9.2 Typical Application.................................................... 87

9.3 Design Requirements............................................... 88

9.4 Detailed Design Procedure.......................................88

9.5 Application Curves....................................................89

10 Initialization Set Up..................................................... 90

10.1 Recommended Configuration at Power Up............ 90

10.2 Initial Device Configuration - 4 Channel Power

Up (Default Mode - PWR_MODE1).............................90

10.3 Initial Device Configuration - 44.1 kHz....................91

10.4 Sample Rate Change - 48 kHz to 44.1kHz.............91

10.5 Idle Channel Hysterisis........................................... 91

10.6 DSP Loopback........................................................91

11 Power Supply and I²C Recommendations................ 92

11.1 Power Supply Modes.............................................. 92

12 Layout...........................................................................94

12.1 Layout Guidelines................................................... 94

12.2 Layout Example...................................................... 94

13 Device and Documentation Support..........................96

13.1 接收文档更新通知................................................... 96

13.2 支持资源..................................................................96

13.3 Trademarks.............................................................96

13.4 Electrostatic Discharge Caution..............................96

13.5 术语表..................................................................... 96

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 I²C Timing Requirements.......................................... 11

6.7 TDM Port Timing Requirements................................12

6.8 Typical Characteristics..............................................13

7 Parameter Measurement Information..........................23

8 Detailed Description......................................................24

8.1 Overview...................................................................24

8.2 Functional Block Diagram.........................................24

8.3 Feature Description...................................................24

8.4 Device Functional Modes..........................................26

8.5 Operational Modes....................................................37

8.6 Faults and Status......................................................38

8.7 Power Sequencing Requirements............................ 40

8.8 Digital Input Pull Downs............................................40

8.9 Register Map.............................................................41

8.10 SDOUT Equations.................................................. 86

9 Application and Implementation..................................87

Information.................................................................... 97

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2020) to Revision A (September 2021)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

2

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

5 Pin Configuration and Functions

1

2

3

4

5

VSNS_N

A

BST_N

OUT_P

PGND

OUT_N

VSNS_P

BST_P

DREG

FSYNC

SDIN

OUT_P

PVDD_SNS

BYP_EN

IRQZ

PGND

PVDD

ADDR

GND

OUT_N

PVDD

B

C

D

E

GND

SDOUT

SBCLK

SDA

VBAT1S

AVDD

F

SCL

IOVDD

SDZ

ICC

Not to scale

图5-1. YBH Package 30-Ball DSBGA Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Address detect pin. Resistor value at this pin selects the I²C address. See 节8.3.1. Minimize

capacitive loading on this pin and do not connect to any other load.

ADDR

D4

I

AVDD

E5

A2

B2

P

Analog power input. Connect to 1.8V supply and decouple to GND with a capacitor.

Class-D negative bootstrap. Connect a capacitor between BST_N and OUT_N.

Class-D positive bootstrap. Connect a capacitor between BST_P and OUT_P.

BST_N

BST_P

Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to

external load.

DREG

C2

P

I

FSYNC

GND

D2

E4

C1

F5

F3

TDM Frame Sync.

P

Analog ground. Connect to PCB ground plane.

ICC

IO

P

Interchip communication pin used to transmit gain alignment.

IOVDD

Digital IO Supply. Connect to 1.2V or 1.8 V supply and decouple with a capacitor to GND.

Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up

is not used.

IRQZ

E3

D3

O

Low voltage signaling pin with open drain output. It can be used to enable/disable an

external converter.

BYP_EN

OUT_N

B5

A5

O

Class-D negative output.

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

表5-1. Pin Functions (continued)

I/O

O

DESCRIPTION

NAME

NO.

B3

A3

B4

A4

E1

F2

F1

E2

D1

F4

C4

C5

C3

D5

A1

B1

OUT_P

Class-D positive output.

PGND

P

Class-D ground. Connect to PCB ground plane.

SBCLK

SCL

I

TDM Serial Bit Clock.

I²C Clock Pin. Pull up to IOVDD with a resistor.

I²C Data Pin. Pull up to IOVDD with a resistor.

TDM Serial Data Input.

SDA

IO

I

SDIN

SDOUT

SDZ

IO

I

TDM Serial Data Output.

Active low hardware shutdown.

PVDD

P

Class-D power supply input. Decouple with a capacitor.

PVDD_SNS

VBAT1S

I

P

I

PVDD remote sense pin.

Single-cell battery supply input. Decouple with a capacitor.

Voltage Sense negative input. Connect to one speaker input.

Voltage Sense positive input. Connect to the other speaker input.

VSNS_N

VSNS_P

I

4

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

-0.3

MAX

2

UNIT

AVDD

V

IOVDD

2

Supply Voltage

PVDD

18.5

6

VBAT1S

PVDD-VBAT1S

18

Internal Supply

Voltage

DREG

-0.3

–0.3

–40

1.5

2.3

85

V

Input voltage⁽²⁾

Digital IOs referenced to IOVDD supply

Operating free-air temperature, T_A; Device is functional and reliable, some performance characteristics may be

degraded.

°C

Performance free-air temperature, T_P; All performance characteristics are met.

Operating junction temperature, T_J

70

125

150

°C

–20

–40

–65

Storage temperature, T_stg

(1) Stresses beyond those listed under 节6.1 can cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3 . Exposure to absolute

maximum rated conditions for extended periods can affect device reliability.

(2) All digital inputs and IOs are failsafe.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.65

1.1

NOM

1.8

MAX

1.95

1.3

UNIT

AVDD

Supply voltage

V

1.2

IOVDD

V

1.65

2.3⁽²⁾

3.0

1.8

1.95

16

Supply voltage (functional)⁽¹⁾

Supply voltage (performance)

Supply voltage (functional)⁽¹⁾

Supply voltage (performance)

High-level digital input voltage

Low-level digital input voltage

Speaker impedance

PVDD

16

2.3

5.5

VBAT1S

3.0

5.5

V_IH

IOVDD

0

V

V_IL

R_SPK

L_SPK

3.2

5

Ω

Speaker inductance

µH

(1) Device will remain functional but performance will degrade.

(2) PVDD>VBAT1S-0.7V.

6.4 Thermal Information

TAS2764

THERMAL METRIC⁽¹⁾

YBH (DSBGA)

30 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

59.9

°C/W

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UNIT

ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

TAS2764

YBH (DSBGA)

30 PINS

0.2

THERMAL METRIC⁽¹⁾

R_θJC(top)

R_θJB

ψ_JT

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

14.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.1

14.9

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

T_A= 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L= 4Ω+ 16µH, f_in= 1 kHz, f_s= 48 kHz, Gain = 21

dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT and OUTPUT

High-level digital input logic voltage

threshold

V_IH

All digital pins except SDA and SCL

SDA and SCL

0.7×IOVDD

V

Low-level digital input logic voltage

threshold

0.3 ×

IOVDD

V_IL

High-level digital input logic voltage

threshold

V_IH(I2C)

V_IL(I2C)

0.7xIOVDD

Low-level digital input logic voltage

threshold

0.3 x

IOVDD

SDA and SCL

V_OH

V_OL

High-level digital output voltage

Low-level digital output voltage

All digital pins except SDA, SCL and IRQZ; I_OH= 100 µA.

V

IOVDD–0.2V

0.2

All digital pins except SDA, SCL and IRQZ; I_OL= –100 µA.

0.2 x

IOVDD

V_OL(I2C)

V_OL(IRQZ)

I_IH

Low-level digital output voltage

SDA and SCL; I_OL(I2C)= -1 mA.

IRQZ; I_OL(IRQZ)= -1 mA.

-

V

Low-level digital output voltage for

IRQZ open drain Output

0.2

1

Input logic-high leakage for digital

inputs

All digital pins; Input = IOVDD.

All digital pins; Input = GND.

µA

–1

Input logic-low leakage for digital

inputs

I_IL

1

R_OS

C_IN

OUT to VSNS Resistors

Load disconnected

All digital pins

10

5

kΩ

Input capacitance for digital inputs

pF

Pull down resistance for IO pins

when asserted on

R_PD

SDOUT, SDIN, FSYNC, SBCLK

18

kΩ

Drive Mode 0 - Measured at (IOVDD-0.4V) and 0.4V

Drive Mode 1 - Measured at (IOVDD-0.4V) and 0.4V

Drive Mode 2 - Measured at (IOVDD-0.4V) and 0.4V

Drive Mode 3 - Measured at (IOVDD-0.4V) and 0.4V

8

6

4

2

IO

Output Current Strength

mA

AMPLIFIER PERFORMANCE

13

8

R_L= 4Ω+ 16µH, THD+N = 1 %

R_L= 8 Ω+ 16 µH, THD+N = 1 %

R_L= 4Ω+ 16µH, THD+N = 10 %

R_L= 8 Ω+ 16 µH, THD+N = 10 %

R_L= 4Ω+ 16µH, P_OUT= 1 W

P_OUT

Maximum Output Power

W

15.8

9.7

80.5

84

R_L= 8 Ω+ 16 µH, P_OUT= 1 W

76.5

82.5

85

R_L= 8 Ω+ 5µH, P_OUT= 1 W PWR_MODE2

R_L= 8 Ω+ 16µH, P_OUT= 1 W PWR_MODE2

R_L= 4Ω+ 16µH, P_OUT= 10 W

System Efficiency

%

90

R_L= 8 Ω+ 16 µH, P_OUT= 5 W

90

R_L= 8 Ω+ 5 µH, P_OUT= 8 W, PWR_MODE2

6

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T_A= 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L= 4Ω+ 16µH, f_in= 1 kHz, f_s= 48 kHz, Gain = 21

dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

P_OUT= 1 W, R_L= 4Ω+ 16µH, f_in= 1 kHz

P_OUT= 1 W, R_L= 4Ω+ 16µH, f_in= 6.67 kHz

MIN

TYP

MAX

UNIT

-83

THD+N

Total Harmonic Distortion and Noise

dB

POUT = 1 W, RL = 8 Ω+ 5µH, fin = 20 Hz - 20 kHz,

PWR_MODE2

-83

IMD

V_N

Intermodulation Distortion

Idle Channel Noise

ITU-R, 19kHz/20kHz, 1:1:6.5W

-80

27

dB

µV

A-Weighted, 20 Hz - 20 kHz, DAC in Mute, PWR_MODE1

A-Weghted, 20 Hz - 20k Hz, DAC in Mute, PWR_MODE2

A-Weighted, 20 Hz - 20 kHz, DAC in Mute, PWR_MODE4

27

32.7

Average frequency in Spread Spectrum Mode,

CLASSD_SYNC=0

384

Fixed Frequency Mode, CLASSD_SYNC=0

365

-1

404

F_PWM

Class-D PWM Switching Frequency

kHz

Fixed Frequency Mode, CLASSD_SYNC=1, f_s= 44.1, 88.2

kHz

352.8

384

Fixed Frequency Mode, CLASSD_SYNC=1, f_s= 48, 96 kHz

Idle Mode

V_OS

Output Offset Voltage

Dynamic Range

1

mV

dB

A-Weighted, -60 dBFS

109

DNR

A-Weighted, -60 dBFS, PWR_MODE2

A-Weighted, Referenced to 1 % THD+N Output Level

SNR

K_CP

Signal to Noise Ratio

dB

A-Weighted, Referenced to 1 % THD+N Output Level

PWR_MODE2

109

Click and Pop Performance

Full Scale Output Voltage

Into and out of Shutdown, A-weighted

f_s<= 48kHz

1

2.7

mV

dBV

21

11

21

Minimum Programmable Gain

Maximum Programmable Gain

f_s<= 48kHz

Programmable Output Level Step

Size

0.5

dB

Mute attenuation

Device in Software Shutdown or Muted in Normal Operation

110

dB

µs

dB

Chip to Chip Group Delay

EMI Margin to EN55022B

-1

1

6" cable, Pout = 1W

-6

100

112

96

PVDD = 12 V + 200 mV_pp, f_ripple= 217 Hz

PVDD Power Supply Rejection Ratio PVDD = 12 V + 200 mV_pp, f_ripple= 1 kHz

PVDD = 12 V + 200 mV_pp, f_ripple= 20 kHz

dB

VBAT1S = 3.8 V + 200 mV_pp, f_ripple= 217 Hz

100

112

88

VBAT1S Power Supply Rejection

VBAT1S = 3.8 V + 200 mV_pp, f_ripple= 1 kHz

Ratio

VBAT1S = 3.8 V + 200 mV_pp, f_ripple= 20 kHz

AVDD = 1.8 V + 200 mV_pp, f_ripple= 217 Hz

96

AVDD Power Supply Rejection Ratio AVDD = 1.8 V + 200 mV_pp, f_ripple= 1 kHz

AVDD = 1.8 V + 200 mV_pp, f_ripple= 20 kHz

90

96

PVDD 217 Hz, 100-mVpp, Input f=1kHz @ 400mW

-70

-118

-82

-70

1.2

5.3

0.5

5.9

VBAT1S 217 Hz, 100-mVpp, Input f=1kHz @ 400mW

Power Supply Intermodulation

dB

AVDD, 217 Hz, 100-mVpp, Input f=1kHz @ 400mW

IOVDD 217 Hz, 100-mVpp, Input f=1kHz @ 400mW

No Volume Ramping

Turn ON Time from Release of SW

Shutdown

ms

Volume Ramping

No Volume Ramping

Turn OFF Time From Assertion of

SW Shutdown to Amp Hi-Z

Volume Ramping

Release of SW Shutdown to new

assertion of SW Shutdown

1.5

1

ms

Out of HW Shutdown to first I²C

command

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

T_A= 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L= 4Ω+ 16µH, f_in= 1 kHz, f_s= 48 kHz, Gain = 21

dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

100

1.5

TYP

MAX

UNIT

Noise Gate recovery to Shutdown

latency

μs

Power up to BOP_SHDN latency

ms

DIAGNOSTIC GENERATOR

THD+N

f_err

Total Harmonic Distortion and Noise Pout=1W, DVC_LVL[7:0]=17h

-80

dB

%

Frequency Error

Using internal oscillator

5

DIE TEMPERATURE

SENSOR

Resolution

8

bits

°C

Minimum Die Temperature

Measurement

-40

Maximum Die Temperature

Measurement

150

1

°C

Die Temperature Resolution

Die Temperature Accuracy

°C

-5

5

VOLTAGE

MONITOR

Resolution

12

2

bits

V

Minimum PVDD Measurement

Maximum PVDD Measurements

PVDD Resolution

16

20

V

mV

V

PVDD Accuracy

-100

-45

100

45

Minimum VBAT1S Measurement

Maximum VBAT1S Measurement

VBAT1S Resolution

2

6

V

20

mV

VBAT1S Accuracy

TDM SERIAL AUDIO PORT

PCM Sample Rates and FSYNC

Typical values

44.1

96

24.576

0.5

kHz

Input Frequency

SBCLK Input Frequency

I²S/TDM Operation

0.7056

MHz

RMS Jitter below 40 kHz that can be tolerated without

performance degradation

SBCLK Maximum Input Jitter

ns

RMS Jitter above 40 kHz that can be tolerated without

performance degradation

1

SBCLK Cycles per FSYNC in I²S and Other values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256,

TDM Modes 384, 500

16

512

Cycles

PCM PLAYBACK CHARACTERISTICS f_s≤48 kHz

f_s

Sample Rates

44.1

-0.3

48

kHz

f_s

Passband Frequency Meeting Ripple

Passband Ripple

0.454

20Hz to LPF cutoff frequency

+0.3

dB

60

65

≥0.55 f_s

Stop Band Attenuation

Group Delay @ 1kHz

Group Delay

dB

1/f_s

≥1 f_s

Noise Gate Enabled

17.7

9

Noise Gate Disabled

DC to 0.454 f_s, Noise Gate enabled, DC blocker disabled

DC to 0.454 f_s, Noise Gate disabled, DC blocker disabled

16

7

19

10

f_s> 48 kHz

fs

Sample Rates

88.2

-0.5

96

kHz

f_s

Passband Frequency Meeting Ripple f_s= 96 kHz

0.375

0.409

Passband 3db Frequency

Passband Ripple

f_s= 96 kHz

f_s

DC to LPF cutoff frequency

0.5

dB

8

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ZHCSMU9A –DECEMBER 2020 –REVISED SEPTEMBER 2021

T_A= 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L= 4Ω+ 16µH, f_in= 1 kHz, f_s= 48 kHz, Gain = 21

dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

60

≥0.55 f_s

Stop Band Attenuation

dB

65

≥1 f_s

Noise Gate Enabled

Noise Gate Disabled

33.2

17.4

Group Delay @ 1kHz

Group Delay

1/f_s

DC to 0.375 f_sfor 96 kHz, Noise Gate Enabled, DC blocker

disabled

33

17

39

23

DC to 0.375 f_sfor 96 kHz, Noise Gate Disabled, DC blocker

disabled

SPEAKER CURRENT SENSE

Resolution

16

66

bits

dB

A

DNR

Dynamic Range

Un-Weighted, Relative to 0 dBFS

THD+N

Total Harmonic Distortion and Noise f_in= 1 kHz, Pout = 7. 5W

-58

3.75

Full Scale Input Current

Differential Mode Gain

-6dBFS Input Signal Level

Pout = 1W, using a 40Hz, -40dBFS pilot tone

0.98

-1.4

1.02

1.4

Pout = 100mW to 0.1% THD+N, using a 40Hz, -40dBFS pilot

tone, Calibrated at 100 mW

Differential Mode Gain Variability

%

Gain Error Over Temperature

Offset

-20⁰C to 70⁰C, Pout=1W, Calibrated at 25⁰C

HPF_FREQ_REC[2:0]=0h

20Hz-20kHz

-1.35

-2

1.35

2

%

mA

dB

Frequency Response

Group Delay

-0.1

0.1

8

1/f_s

SPEAKER VOLTAGE SENSE

Resolution

16

69

bits

dB

DNR

Dynamic Range

Un-Weighted, Relative 0 dBFS

THD+N

Total Harmonic Distortion and Noise f_in= 1 kHz, Pout = 7.5W

Full Scale Input Voltage

-60

14

dB

V_PK

Differential Mode Gain

Pout = 1W, using a 40Hz - 40dBFS pilot tone

0.99

1.01

Pout = 100mW to 0.1% THD+N, using a 40Hz, -40dBFS pilot

tone

Differential Mode Gain Variability

-0.45

+0.45

%

Gain error over temperature

Offset

-20C to 70C, Pout=1W

HPF_FREQ_REC[2:0]=0h

20Hz - 20kHz

-0.75

-10

+0.75

+10

%

mV

dB

Frequency Response

Group Delay

-0.1

0.1

8

1/f_s

SPEAKER VOLTAGE to CURRENT SENSE PHASE

Phase Error between V and I

300

ns

µs

PROTECTION CIRCUITRY

Brownout Prevention Latency to First

Attack

PWR_MODE2, Measured at BOP_TH0 of 8.25V

15

Thermal Shutdown Temperature -

Typical values

135

145

5.9

2.5

155

°C

A

Output Over Current Limit on PVDD Output to Output, Output to GND, Output to PVDD

Output Overt Current Limit on

Output to Output, Output to GND

VBAT1S

A

UVLO is asserted

2

VBAT1S Undervoltage Lockout

Threshold

V

UVLO is de-asserted

2.3

1.6

1.1

UVLO is asserted

1.4

0.7

AVDD Undervoltage Lockout

Threshold

UVLO is de-asserted

UVLO is asserted

IOVDD Undervoltage Lockout

Threshold

V

UVLO is de-asserted

VBAT1S Internal LDO Undervoltage

UVLO is asserted

4

Lockout Threshold

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T_A= 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L= 4Ω+ 16µH, f_in= 1 kHz, f_s= 48 kHz, Gain = 21

dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless

otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VBAT1S Internal LDO Overvoltage

Lockout Threshold

OVLO is asserted

5.5

V

TYPICAL CURRENT CONSUMPTION

SDZ = 0, PVDD

SDZ = 0, VBAT1S

SDZ = 0, AVDD

SDZ = 0, IOVDD

0.1

1

Hardware Shutdown

µA

0.1

1

All Clocks Stopped, PVDD

All Clocks Stopped, VBAT1S

All Clocks Stopped, AVDD

All Clocks Stopped, IOVDD

f_s= 48 kHz, PVDD

Software Shutdown

Noise Gate Mode

10

1

0.05

0.14

3.2

0.1

0.02

3

f_s= 48 kHz, VBAT1S

f_s= 48 kHz, AVDD

mA

f_s= 48 kHz, IOVDD

f_s= 48 kHz, PVDD

f_s= 48 kHz, VBAT1S

f_s= 48 kHz, AVDD

Idle Mode - PWR_MODE1,

PWR_MODE3

mA

8.9

0.1

3.2

9.3

0.1

4.1

9.3

0.1

f_s= 48 kHz, IOVDD

f_s= 48 kHz, PVDD

Idle Mode - PWR_MODE2

Idle Mode - PWR_MODE4

f_s= 48 kHz, AVDD

f_s= 48 kHz, IOVDD

f_s= 48 kHz, PVDD

f_s= 48 kHz, AVDD

mA

f_s= 48 kHz, IOVDD

Idle Mode - PWR_MODE1,

PWR_MODE3

f_s= 48 kHz, AVDD, IV Sense Disabled

6.3

* For definition of power modes see 节11.1.

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6.6 I²C Timing Requirements

T_A= 25 °C, AVDD = IOVDD = 1.8 V (unless otherwisenoted)

MIN

NOM

MAX

UNIT

Standard-Mode

f_SCL

SCL clock frequency

0

4

100

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

μs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

Setup time for a repeated START condition

Data hold time: For I²C bus devices

Data set-up time

4.7

4

μs

ns

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

4.7

0

3.45

250

SDA and SCL rise time

1000

300

ns

t_f

SDA and SCL fall time

ns

t_SU;STO

t_BUF

Set-up time for STOP condition

Bus free time between a STOP and START condition

Capacitive load for each bus line

4

μs

pF

4.7

C_b

400

Fast-Mode

f_SCL

SCL clock frequency

0

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

0.6

μs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

Setup time for a repeated START condition

Data hold time: For I²C bus devices

Data set-up time

1.3

0.6

0

μs

ns

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

0.9

100

20 + 0.1 ×

C_b[pF]

t_r

t_f

SDA and SCL rise time

SDA and SCL fall time

300

ns

20 + 0.1 ×

C_b[pF]

t_SU;STO

Set-up time for STOP condition

0.6

1.3

μs

pF

t_BUF

Bus free time between a STOP and START condition

Capacitive load for each bus line (10pF to 400pF)

C_b

400

Fast-Mode Plus

f_SCL

SCL clock frequency

0

1000

kHz

Hold time (repeated) START condition. After this period, the first clock pulse is

generated.

t_HD;STA

0.26

μs

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

LOW period of the SCL clock

HIGH period of the SCL clock

Setup time for a repeated START condition

Data hold time: For I²C bus devices

Data set-up time

0.5

0.26

0

μs

ns

50

SDA and SCL Rise Time

120

ns

t_f

SDA and SCL Fall Time

ns

t_SU;STO

t_BUF

Set-up time for STOP condition

Bus free time between a STOP and START condition

Capacitive load for each bus line

μs

pF

0.5

C_b

550

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6.7 TDM Port Timing Requirements

T_A= 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs(unless otherwise noted)

MIN

20

8

NOM

MAX

UNIT

ns

t_H(SBCLK)

SBCLK high period

SBCLK low period

FSYNC setup time

FSYNC hold time

SDIN/ICC setup time

SDIN/ICC hold time

t_L(SBCLK)

ns

t_SU(FSYNC)

t_HLD(FSYNC)

t_SU(SDIN/ICC)

t_HLD(SDIN/ICC)

ns

8

ns

8

ns

8

ns

50% of SBCLK to 50% of SDOUT/ICC,

IOVDD=1.8V

2.8

3.6

13

17

SBCLK to SDOUT/ICC

delay

t_d(SBCLK_SDOUT/ICC)

ns

50% of SBCLK to 50% of SDOUT/ICC,

IOVDD=1.2V

t_r(SBCLK)

t_f(SBCLK)

SBCLK rise time

SBCLK fall time

10 % - 90 % Rise Time

90 % - 10 % Fall Time

8

ns

SDA

SCL

t_BUF

t_LOW

t_h(STA)

t_r

t_h(STA)

STA

t_h(DAT)

t_HIGH

t_su(STA)

t_su(STO)

STO

t_f

t_su(DAT)

STA

STO

图6-1. I2C Timing Diagram

图6-2. TDM and ICC Timing Diagram

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7 Parameter Measurement Information

All typical characteristics for the devices are measured using the Bench Evaluation Module (EVM) and an Audio

Precision SYS-2722 Audio Analyzer. A PSIA interface is used to allow the I²S interface to be driven directly into

the SYS-2722. Speaker output terminals are connected to the Audio Precision Analyzer analog inputs through a

differential-to-single ended (D2S) filter as shown below. The D2S filter contains a first order passive pole at 120

kHz. The D2S filter ensures the TAS2764 high performance class-D amplifier sees a fully differential matched

loading at its outputs and the output signal is single ended.

1kΩ

0.01%

1kΩ

0.01%

-

1kΩ

SPK_P

+

-

AP

680pF

AUX-0025

SYS-2772

+

SPK_N

1kΩ

0.01%

+

-

1kΩ

0.01%

图7-1. Differential To Single Ended (D2S) Filter

Alternatively, the AUX-0025 filter can be connected directly to the class-D outputs.

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8 Detailed Description

8.1 Overview

The TAS2764 is a mono digital input Class-D amplifier optimized for portable applications where efficient battery

operation and small solution size are critical. It integrates speaker IV (current/voltage) sensing and battery

tracking limiting with brown out prevention. The device operates using a TDM/I²S and I²C interfaces.

表8-1. Full Scales

Input/Output Signal

Full Scale Value

Class-D Output

21 dBV

Voltage Monitor

PVDD: 16 V

VBAT1S: 6V

3.75 Apk

Current Sense

Voltage Sense

14 Vpk

8.2 Functional Block Diagram

VBAT1S

PVDD

PVDD_SNS

POWER MANAGEMENT

POR

AVDD

REFERENCE

1.5V LDO

POR

SDZ

5V LDO

DREG

0.9V Reference

+ Bias Currents

BST_P

DIGITAL

VSNS_P

OUT_P

IOVDD

Audio Engine +

Filters

Class-D

INTERFACE

ESD

DAC

Loop

Filter

Serial Interfaces

Comparator

OTP

Brownout +

Voltage Limiter

OUT_N

16V LDMOS Output

stage

BYP_EN

ADDR

û-ꢀ

ADC

ADDR

DETECT

VSNS_N

Analog Controller

I2C

I2S

I-SENSE

BST_N

Noise Gate +

Diagnostic

Generator

DIGITAL IO

û-ꢀ

ADC

V-Sense Amp + PGA

Temp Sensor

10b SAR

ADC

Thermal

OSC

PLL

BOP VBAT1S Tracker

Protection

B

BOP PVDD Tracker

(PVDD_SNS)

COMMON IP

PGND

GND

8.3 Feature Description

8.3.1 Device Address Selection

The TAS2764 operates using a TDM/I²S interface. Audio input and output are provided via the FSYNC, SBCLK,

SDIN and SDOUT pins using formats including I²S, Left Justified and TDM. Configuration and status are

provided via the SDA and SCL pins using the I²C protocol.

The table below illustrates how to configure the device for I²C address . The slave addresses are shown left

shifted by one bit with the R/W bit set to 0 (i.e. {ADDR[6:0],1b0}). Resistors with tolerance better than 5% must

be used for setting the address configuration.

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表8-2. I²C Address Selection

I²C SLAVE ADDRESS

ADDR PIN

0x70

0x72

0x74

0x76

0x78

0x7A

0x7C

0x7E

Short to

GND

Short to AVDD

470 Ωto

2.2k Ωto

10 kΩto

GND

AVDD

GND

AVDD

GND

AVDD

The TAS2764 has a global 7-bit I²C address 0x80. When enabled, the device will additionally respond to I²C

commands at this address regardless of the ADDR pin settings. This is used to speed up device configuration

when using multiple TAS2764 devices and programming similar settings across all devices. The I²C ACK /

NACK cannot be used during the multi-device writes since multiple devices are responding to the I²C command.

The I²C CRC function should be used to ensure each device properly received the I²C commands. At the

completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be

checked on each device using the local address for a proper value. The global I²C address can be disabled

using I2C_GBL_EN register bit. The I²C address is detected by sampling the ADDR pin when SDZ pin is

released. Additionally, the address may be re-detected by setting I2C_AD_DET register bit high after power up

and the ADDR pin will be re-sampled.

8.3.2 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system using serial data transmission. The address and 8 bit data are transferred starting with the most-

significant bit (MSB). In addition, each byte transferred on the bus is acknowledged by the receiving device with

an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus

and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data

terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on

SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within

the low time of the clock period.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock

period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each

device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals via a bi-directional bus using a wired-AND connection.

8- Bit Data for

Register (N)

8- Bit Data for

Register (N+1)

图8-1. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. 图 8-1 shows a generic data transfer

sequence.

For information about pull-up resistors and single-byte/multiple-byte transfers see .

8.3.3 Register Organization

Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes

and each book contains 256 pages. All device configuration registers are stored in book 0, page 0, which is the

default setting at power up (and after a software reset). The book and page can be set by the BOOK and PAGE

registers respectively.

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Note

Programming register bits from Book_0 and Page_4 needs to be done in groups of four registers (32

bit format), each byte corresponding to a register and with less significant byte programmed to 00h.

For instance, when programing DC level for diagnostic generator, registers 08 (MSB),09,0A will be

programmed to the desired value and register 0B will be programmed to 00h.

8.4 Device Functional Modes

8.4.1 TDM Port

The TAS2764 provides a flexible TDM serial audio port. The port can be configured to support a variety of

formats including stereo I²S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The

SDOUT pin is used to transmit sample streams including speaker voltage and current sense, PVDD voltage, die

temperature and channel gain.

The TDM serial audio port supports up to 16 of 32-bit time slots at 44.1/48 kHz or 8 of 32-bit time slots at a

88.2/96 kHz sample rate. Valid SBCLK to FSYNC ratios are 16, 24, 32, 48, 64, 96, 128, 192, 256, and 512. The

device will automatically detect the number of time slots and it does not need to be programmed.

By default, the TAS2764 will automatically detect the PCM playback sample rate. This can be disabled and

manually configured by setting the AUTO_RATE register bit high.

The SAMP_RATE[2:0] and SAMP_RATIO[3:0] register bits are used to configure the PCM audio sample rate

when AUTO_RATE register bit is high (auto detection of TDM sample rate is disabled). The TAS2764 employs a

robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does

not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported

(minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the

device will automatically volume ramp the playback path back to the configured volume and resume playback.

When using the auto rate detection the sampling rate and SBCLK to FSYNC ration detected on the TDM bus is

reported back on the read-only register bits FS_RATE[2:0] and FS_RATIO[3:0] respectively.

The TAS2764 supports a 12 MHz SBCLK operation. The system will detect or should be manually configured for

a ratio of 125 or 250. In this specific ratio the last 32-bit slot should not be used to transmit data over the TDM

port (节8.4.1) or ICC pin ( 节8.4.2.9.1) as data will be truncated.

图 8-2 and 图 8-3 below illustrate the receiver frame parameters required to configure the port for playback. A

frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START

register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the

RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the

transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format

and 1 for an I²S format.

SBCLK

FSYNC

SDIN

SBCLK

FSYNC

SDIN

Slot 0

Bit 31

Slot0

Bit 0

Slot 1

Bit 31

Slot1

Bit 0

Slot2

Bit 31

MSB

MSB-1

LSB+1

LSB

RX_OFFSET

RX_WLEN

RX_OFFSET

Time Slot 0

Time Slot 1

RX_SLEN

图8-3. TDM RX Time Slots

图8-2. TDM RX Time Slot with Left Justification

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of the

audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits to 16, 20, 24 (default) or

32 bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to

right justification via the RX_JUSTIFY register bit. The TAS2764 supports mono and stereo down mix playback

([L+R]/2). By default the device will playback mono from the time slot equal to the I²C base address offset (set by

the ADDR pin) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the

left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

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If time slot selection places reception either partially or fully beyond the frame boundary, the receiver will return a

null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin including speaker voltage sense,

speaker current sense, interrupts and status, PVDD voltage, die temperature and channel gain. 图 8-4 below

illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to

time slots.

SBCLK

FSYNC

Slot 0

Bit 7

Slot0

Bit 0

Slot 1

Bit 7

Slot1

Bit 0

Slot2

Bit 7

SDOUT

TX_OFFSET

Time Slot 0

Time Slot 1

Ex: V_SENSE[15:0]

图8-4. TDM Port TX Diagram

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be

configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK

cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for

Left Justified format and 1 for I²S format. The TDM and ICC TX can either transmit logic 0 or Hi-Z depending on

the setting of the TX_FILL register bit. An optional bus keeper will weakly hold the state of SDOUT and ICC pins

when all devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled

via the TX_KEEPEN register bit. The bus keeper can be configured to hold only 1LSB or Always using

TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using

TX_KEEPCY register bit.

TX_FILL is used in mono system where there is only one amplifier on I²S bus. All the slots unused by the

amplifier will be filled with zeros when TX_FILL is set to low.

The SDOUT_HIZ registers from page 0x01 are useful when multiple devices are on the same I²S bus. Each

device does not know configuration of slots in the other devices on the bus. It is required at the system level to

program the SDOUT_HIZ registers appropriately, in such way that the settings are done correctly and do not

create any contention both internally and externally.

Each sample stream is composed of either one or two 8-bit time slots. Speaker voltage sense and speaker

current sense sample streams are 16-bit precision, so they will always utilize two TX time slots. The PVDD

voltage stream is 12 bit precision, and can either be transmitted left justified in a 16-bit word (using two time

slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured

by setting PVDD_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in

a single time slot.

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if

VSNS_SLOT[5:0] register bits are set to 2 (decimal), the upper 8 MSBs will be transmitted in time slot 2 and the

lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled by

using VSNS_TX and ISNS_TX register bits. This is useful to manage limited TDM bandwidth since it may not be

necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For

instance, if VSNS_SLOT[5:0] bits are set to 2 (decimal) and ISNS_SLOT[5:0] bits are set to 3 (decimal), the

lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce

unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

When two or more devices are connected to the same SDOUT pin the slot assignment of the various devices

must be kept exclusive to avoid any contention. This constraint is applicable to both Software Shutdown and

Active Mode. Devices should not be programmed to transmit on the same slot.

The current and voltage values are transmitted at the full 16-bit measured values by default. The

IVMON_LEN[1:0] register bits can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values

across multiple slots. The special 12-bit mode is used when only 24-bit I2S/TDM data can be processed by the

host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot

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and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by

the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at

the frame boundary.

The time slots for VBAT1S, PVDD and TEMP measurements are set using VBAT1S_SLOT[5:0],

PVDD_SLOT[5:0] and TEMP_SLOT[5:0] register bits. To enable sample stream register bits VBAT1S_TX,

PVDD_TX and TEMP_TX must be set high. The slot length is selected by VBAT1S_SLEN, PVDD_SLEN and

TEMP_SLEN register bits.

To set TDM final processed audio slot, enable and length register bits the following register bits need to be

programmed: AUDIO_SLOT[5:0], AUDIO_TX and AUDIO_SLEN .

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set

high enables the status transmit.

The slot configuration for the TX limiter gain reduction can be set between 0 (default) and 63 by setting

GAIN_SLOT[5:0] register bits. It is used for the Inter Chip Gain Aligment ( 节8.4.2.9 ) and can be either over the

TDM Bus or ICC pin (节8.4.2.9.1). To use this feature, the register bit GAIN_TX needs to be set high (Enable).

8.4.2 Playback Signal Path

8.4.2.1 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The TAS2764

employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. The

HPF_FREQ_PB[2:0] register bits set the corner frequencies of HPF. The filter can be bypassed by setting the

register bits to 3'b000.

8.4.2.2 Amplifier Inversion

The device will output a non-inverted signal to the OUT_P and OUT_N pins. The output can be inverted with

respect to the digital input value by setting the AMP_INV register bit to high.

8.4.2.3 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital

volume control (DVC).

Amplifier output level settings are programmed using AMP_LEVEL[4:0] register bits. The levels are presented in

the Register Map in dBV (dB relative to 1 V_rms), with a full scale digital audio input (0 dBFS) and the DVC set by

default to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the

amplifier, so they should be used to convey gain only.

Equation 1 below calculates amplifier output voltage:

V_AMP= INPUT+A_DVC+A_AMP

(1)

where

• V_AMPis the amplifier output voltage in dBV

• INPUT is the digital input amplitude as a number of dB with respect to 0 dBFS

• A_DVCis the digital volume control setting as a number of dB

• A_AMPis the amplifier output level setting as a number of dBV

The digital volume control (DVC) is configurable from 0 dB to -100 dB in 0.5 dB steps by setting the

DVC_LVL[7:0] register bits. Settings greater than C8h are interpreted as mute. When a change in digital volume

control occurs, the device ramps the volume to the new setting based on the DVC_RAMP_RATE[1:0] register

bits status. If DVC_RAMP_RATE[1:0] bits are set to 2'b11 the volume ramping is disabled. This setting can be

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used to speed up startup, shutdown and digital volume changes when volume ramping is handled by the system

master.

The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on power supply. The

approximate threshold for the onset of analog clipping is calculated in Equation 2.

(2)

where

• V_PKis the maximum peak un-clipped output voltage in V

• V_SUPis the power supply of class-D output stage

• R_Lis the speaker load in Ω

• R_Pis the parasitic resistance on PCB (routing, filters) in Ω

• R_FETis the power stage total resistance (HS FET, LS FET, Sense Resistor, bonding, packaging) in Ω

When VBAT1S supplies class-D output stage typical R_FETvalue is 1 Ω. For PVDD supply R_FETtypical value is

0.5 Ω.

8.4.2.3.1 Safe Mode

The safe mode is a single bit that will enable 18 dB attenuation in the forward path. It is similar to setting the

DVC_LVL[7:0] register bits to a setting of 24h (-18dB). When the SMODE_EN bit is set to high, the

DVC_LVL[7:0] register bits will be ignored and volume ramping disabled.

8.4.2.4 VBAT1S Supply

The TAS2764 can operate with or without a VBAT1S supply. When configured without a VBAT1S supply, the

PVDD voltage will be used with an internal LDO to generate this supply voltage. A decoupling capacitor should

still be populated as recommended in 表 9-1. In this case, VBAT1S_MODE bit should be set to high before

transitioning from software shutdown. More details about VBAT1S supply modes of operation can be found in 节

11.1.

8.4.2.5 Low Voltage Signaling (LVS)

The TAS2764 monitors the absolute value of the audio stream.

When the input was initially above the programmed threshold set by LVS_FTH[4:0] register bits the Class D was

supplied by PVDD rail. If the signal level drops below this threshold for longer than the hysteresis time defined by

LVS_HYS[3:0] bits the Class-D supply will switch to VBAT1S.

The BYP_EN pin will be asserted (open drain released). All values of LVS_HYS[3:0] bit settings will ensure the

remaining samples will be output before BYP_EN is asserted. When multiple devices have BYP_EN pin

connected together, any device requiring a supply voltage higher than the threshold will pull the open drain

output low.

When the signal level crosses above the programmed threshold set by LVS_FTH[4:0] bits the Class-D supply

will switch to PVDD.

The open-drain BYP_EN pin will be de-asserted (actively pulling the output low) after a delay programmed by

the LVS_DLY[1:0] register bits . The Y Bridge will switch from VBAT1S to PVDD after a delay programmed by

the CDS_DLY[1:0] register bits.

LVS threshold is set based on the output signal level and is measured in dBFS.

The LVS threshold can alternately be configured to be a value relative to the VBAT1S voltage. To use the

alternate configuration set the LVS_TMODE bit to high and use the LVS_RTH[3:0] register bits for setting the

threshold.

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Below equations show the maximum level of the input signal in order to keep LVS below threshold (Class D

switching on VBAT).

For absolute threshold: Input (dBFS) < LVS_FTH + (21 dBV - ChannelGain [dBV]).

For relative threshold: Input (dBFS) < 20log10 (VBAT1S*CD_EFF - LVS_RTH) + (21 dBV - ChannelGain [dBV]) -

1.5dB.

Where:

* ChannelGain = AMP_LEVEL + DVC_LVL + SAFE_MODE (if enabled, it is -18dB).

* CD_EFF is set by registers 48h-4Bh from page 0x04 and LVH_RTH is set by bits [3:0] of register 6Ah from

page 0x00.

* 1.5dB is an inflection factor, already included for absolute threshold.

BOP, Limiter, Thermal Foldback and Thermal Gradient Gain Attenuation should not be taken into account for

calculating LV_EN threshold.

图8-5. Low Voltage Signaling (Input=0dB, Gain=0dB)

The group delay numbers are optimized based on whether the Noise Gate feature is enabled or disabled. The

delay on CDS_DLY path and LVS_DLY path varies depending on sampling rate and whether Noise Gate mode

is enabled or not (see 节8.9.91).

The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 from 节 11.1), can be set using register

bits LVS_FTH_LOW[1:0]. When CDS_MODE[1:0]=00 (PWR_MODE1 and PWR_MODE3 from 节 11.1) the

thresholds should be set with register bits LVS_FTH[4:0].

8.4.2.6 Y-Bridge

The TAS2764 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS (节

8.4.2.5) is internally used to select between the PVDD and VBAT1S supplies. This feature is enabled by setting

CDS_MODE[1:0] bits to 2'b00 when both PVDD and VBAT1S are supplied to the device. If not configured to Y-

bridge mode the device will use only the selected supply for class-D output even if clipping would otherwise

occur. The device can operate using only PVDD to supply class-D output. In this configuration the VBAT1S can

be provided from external supply (register bit VBAT1S=0) or generated by an internal LDO (register bit

VBAT1S=1). In this case CDS_MODE[1:0] bits should be set to 2'b10. The TAS2764 Y-Bridge with Low Power

on VBAT1S can be used to switch to the VBAT1S rail only at very low power when close to idle. This will reduce

the class-D output swing when near idle and limit the current requirements of the VBAT1S supply. Set the

CDS_MODE[1:0] register to 2'b11 for this mode.

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See 节11.1 for details on programming the power modes.

The change to the class-D supply determined by the LVS (节 8.4.2.5) can have a delay programed by

CDS_DLY[1:0] register bits.

When in Y-Bridge mode, if the PVDD falls below (VBAT1S+2.5V) level the Y-bridge will stop switching between

supplies and will remain on the PVDD supply.

8.4.2.7 Noise Gate

The TAS2764 has a noise-gate feature that monitors the input signal and powers down the class-D when the

signal goes below the threshold set by NG_LVL[1:0] bits for longer than the time set by NG_HYST[1:0] register

bits. When the signal goes above the threshold the class-D will re-power in 7 samples before the samples

applied to the audio input interface reach the class-D bridge. This feature is enabled by setting NG_EN bit to

high. Once enabled it is able to power up and down the channel within the device processing delay requiring no

additional external control. Volume ramping can be also used during noise gate operations by setting

NG_DVR_EN bit to low.

The noise gate can be configured with finer resolution at the expense of additional I²C writes. Use NGFR_EN bit

to enable this mode and register bits NGFR_LVL[31:0] to set the fine resolution. The fine resolution hysteresis is

set using NGFR_HYST[18:3] register bits.

When noise gate is enabled, once the signal is applied, the TAS2764 will be recovering from noise gate. In this

case, a shutdown command, if needed, can be programmed in two ways:

- after muting (zero-ing) the incoming data (recommended);

- 100 us after TAS2764 is exiting noise gate (incoming signal is not zero-ed).

8.4.2.8 Supply Tracking Limiter with Brown Out Prevention

The TAS2764 contains a supply tracking limiter to control distortion and brownout prevention to mitigate

brownout events. The gain reduction that occurs due to this block can be aligned across multiple devices using

the Inter Chip Gain Alignment feature ( 节 8.4.2.9) . The maximum device attenuation set by

DEV_MAX_ATTN[6:0] register bits can be used to limit the combination of the limiter and brownout attenuation

or the Inter Chip Gain Alignment.

The Supply Tracking Limiter (节 8.4.2.8.1) and the BOP (节 8.4.2.8.2) are configured independently. The Inter

Chip Gain Alignment, if enabled, keeps multiple device gains in sync if the Supply Tracking Limiter and BOP

need to reduce the gain. However, the BOP will take priority in the device. In order to prevent the Supply

Tracking Limiter and BOP from both making simultaneous adjustments to the system, the Supply Tracking

Limiter and Inter Chip Gain Alignment will be paused once the BOP engages until it is fully released .

By default, the limiter will attack the audio independent of BOP (bit LIM_PDB=0). If it is needed to pause the

limiter attenuation when BOP is engaged, the bit LIM_PDB should be set to high.

The attenuation applied to the device can be selected to be either the sum of the limiter attenuation (ICLA) and

Brownout attenuation (ICBA) or the maximum of the two of them by setting the ICG_MODE register bit.

8.4.2.8.1 Supply Tracking Limiter

The TAS2764 monitors the PVDD supply voltage and the audio signal to automatically decrease gain when the

audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time

through end of charge battery conditions. The limiter threshold can be configured to track PVDD below a

programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold

reduction from PVDD tracking.

The limiter is enabled by setting the LIM_EN bit register to high.

Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter

(LIM_ATK_RT[3:0], LIM_HLD_TM[2:0] and LIM_RLS_RT [3:0] register bits).

A maximum level of attenuation applied by the limiter is configurable via the LIM_MAX_ATTN[3:0] register bits. If

the limiter mode is attacking and if it reaches the maximum attenuation, gain will not be reduced any further.

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The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can

be configured to track PVDD below a programmable inflection point with a minimum threshold value. 图 8-6

below shows the limiter configured to limit to a constant level regardless of PVDD level. To achieve this behavior,

set the limiter maximum threshold to the desired level via the LIM_TH_MAX[31:0] register bits. Set the limiter

inflection point (register bits LIM_INF_PT[31:0]) below the minimum allowable PVDD setting. The limiter

minimum threshold, set by register bits LIM_TH_MIN[31:0], does not impact limiter behavior in this use case.

Inflection

Point

LIM_TH_MAX

slope

Brown

Out

Brown

Out

BOP_TH

BOP_TH LIM_INF_PT

PVDD (V)

图8-6. Limiter with Fixed Threshold

图8-7. Limiter with Inflection Point

Inflection

Point

1:1

LIM_TH_MAX

slope

- x%

Headroom

LIM_TH_MIN

Brown

+ x%

Out

Brown

Out

Headroom

BOP_TH

BOP_TH LIM_INF_PT

PVDD (V)

图8-8. Limiter with Dynamic Threshold

图8-9. Limiter with Inflection Point and Minimum

Threshold

图 8-7 shows how to configure the limiter to track PVDD below a threshold without a minimum threshold. Set the

LIM_TH_MAX[31:0] register bits to the desired threshold and LIM_INF_PT[31:0] register bits to the desired

inflection point where the limiter will begin reducing the threshold with PVDD. The LIM_SLOPE[31:0] register bits

can be used to change the slope of the limiter tracking with PVDD. The default value of 1 V/V will reduce the

threshold 1 V for every 1 V of drop in PVDD. More aggressive tracking slopes can be programmed if desired.

Program the LIM_TH_MIN[31:0] bits below the minimum PVDD to prevent the limiter from having a minimum

threshold reduction when tracking PVDD.

The limiter with a supply tracking slope can be configured in an alternate way. By setting LIM_HR_EN register bit

to 1'b1 , a headroom can be specified as a percentage of the supply voltage using a 1V/V slope by setting

LIM_DHR[4:0] register bits. For example if a headroom of -10% is specified, the peak output voltage will be set

to be 10% higher than PVDD. In this use case presented in 图 8-8 the limiting begins for signals above the

supply voltage and will result in a fixed clipping. If a positive headroom of +10% is specified the peak output

voltage will be dynamically set 10% below the current PVDD. In this use case the limiting will begin at signal

levels lower than the supply voltage and prevent clipping from occurring.

To achieve a limiter that tracks PVDD only up to a minimum threshold, configure the limiter LIM_TH_MAX [31:0]

and LIM_SLOPE[31:0] register bits as in the previous examples. Then additionally set the LIM_TH_MIN[31:0]

register bits to the desired minimum threshold. Supply voltage below this minimum threshold will not continue to

decrease the signal output voltage. This is shown in 图8-9.

By setting register bit LIM_DHYS_EN to low the limiter mechanism depends on settings for maximum/minimum

thresholds, inflection point and slope. Once this bit is set high the limiter dynamic headroom is enabled.

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When a BOP (节 8.4.2.8.2) event occurs the limiter updates can be paused (LIM_PDB register bit set to 1'b1)

until the BOP fully releases. This can be used to prevent undesired interactions between both protection

systems.

8.4.2.8.2 Brownout Prevention (BOP)

Brownout Prevention (BOP) feature provides a priority input to the limiter to generate a fast response to transient

dips in supply voltage at end of charge conditions that can cause system level brownout. When supply voltage

dips below the BOP threshold, the limiter begins reducing gain at a configurable attack rate. When supply

voltage rises above the BOP threshold, the limiter will begin to release after the programmed hold time. The

BOP feature can be enabled by setting the BOP_EN register bit high. The brownout supply source can be set

using BOP_SRC register bit to either PVDD (BOP_SRC =1) or VBAT1S (BOP_SRC =0) depending on

application need. It should be noted that the BOP feature is independent of the limiter and will function, if

enabled, even if the Supply Tracking Limiter is disabled.

The BOP can be configured to attack the gain through four levels as the supply voltage continues to drop. The

BOP threshold Level 3 is set using the BOP_TH3[7:0] register bits followed by threshold Level 2 using

BOP_TH2[7:0] register bits, Level 1 threshold set by BOP_TH1[7:0] bits and finally crossing Level 0 set by

BOP_TH0[7:0] register bits.

The BOP levels that are not used can be disabled individually using register bits BOP_DIS0, BOP_DIS1 ,

BOP_DIS2, BOP_DIS_3 and providing flexibility from one to four levels. Levels should be disabled in the order 3

to 1 for proper operation.

Each level has a separate Attack Rate (register bits BOP_ATK_RT0[2:0] to BOP_ATK_RT3[2:0]), Attack Step

Size (register bits BOP_ATK_ST0[2:0] to BOP_ATK_ST3[2:0]), Release Rate (register bits BOP_RLS_RT0[2:0]

to BOP_RLS_RT3[2:0]), Release Step Size (register bits BOP_RLS_ST0[3:0] to BOP_RLS_ST3[3:0]), Dwell

Time (register bits BOP_DT0[2:0] to BOP_DT3[2:0]), Hold Time (register bits BOP_HT0[2:0] to BOP_HT3[2:0]),

Maximum Attenuation and Shutdown.

When BOP supply source is set to PVDD input the SAR convertor will not digitize the VBAT1S voltage to reduce

latency in the first attack of the BOP engine.

For proper device operation the following conditions must be met:

●BOP_MAX_ATTN0 > BOP_MAX_ATTN1 > BOP_MAX_ATTN2 > BOP_MAX_ATTN3

●BOP_TH Level 3 > BOP_TH Level 2 > BOP_TH Level 1 > BOP_TH Level 0.

Use bits BOP_MAX_ATTN of registers BOP_CFG4, BOP_CFG9, BOP_CFG14, BOP_CFG20 from Register

Map to set attenuation levels. Registers BOP_CFG5, BOP_CFG10, BOP_CFG15, BOP_CFG21 will be used for

setting the BOP threshold levels.

The TAS2764 can also immediately mute and then shutdown the device when a BOP event occurs by reaching

Level 0 if the BOP_SHDN register bit is set high. For the device to continue playing audio again it must transition

through a SW/HW shutdown state. If the hold time set by BOP_HT3[2:0] , BOP_HT2[2:0], BOP_HT1[2:0],

BOP_HT0[2:0] register bits is at 7h (Infinite) the device needs to transition through a mute or SW/HW shutdown

state or the register bit BOP_HLD_CLR can be set to high (which will cause the device to exit the hold state and

begin releasing). This bit is self clearing and will always read-back low.

VBAT

BOP Thresh

BOP Active

BOP

Attacking

BOP

Holding

Limiter Releasing

(BOP Inactive)

BOP Inactive

BOP Mode

图8-10. Brownout Prevention Event

The TAS2764 BOP engine will keep track of the current level state, the lowest BOP level that has been engaged

and the lowest sensed BOP supply voltage. This information is continually updated until requested. When this

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information is polled the register BOP_STAT_HLD is set high. This will pause the updates of the current state

(BOP_STAT_STATE[3:0]) and lowest BOP level (BOP_STAT_LLVL[2:0]) registers bits allowing them to be read

back. Once the read is complete the register bit BOP_STAT_HLD should be set low again clearing the current

BOP status registers and re-enabling the updates based on current BOP state.

The lowest PVDD measurement since the last read is also available in register bits BOP_STAT_PVDD[9:0] if

BOP_STAT_HLD register bit is set high before reading.

BOP Level 0 cannot be disabled and BOP Level 0 thresholds will be fixed by values programmed in registers

0x2E to 0x32 of page 0x00.

8.4.2.9 Inter Chip Gain Alignment

The TAS2764 supports alignment of limiter and brownout prevention dynamics across devices using the

dedicated ICC pin (节 8.4.2.9.1) or across the TDM output bus. This ensures consistent gain between channels

during limiting or brownout events since these dynamics are dependent on audio content, which can vary across

channels. Each device can be configured to align to a specified number of other devices, which allows creation

of groupings of devices that align only to each other.

Limiter and brownout activity is optionally transmitted by each device on SDOUT or ICC pin in an 24-bit time slot.

When both limiter and brownout are enabled the 24-bit slot is comprised of 11-bit limiter and 13-bit brownout

data. If only the limiter is enabled the data will be only the 12-bit limiter data. Gain reduction should be

transmitted in adjacent time slots for all devices that are to be aligned beginning with the first slot that is specified

by the ICGA_SLOT[5:0] register bits. The order of the devices is not important as long as they are adjacent. The

time slot for limiter gain reduction is configured by the GAIN_SLOT[5:0] register bits and enabled by the

GAIN_TX register bit being set high. The ICGA_SEN[7:0] register bits specify which time slots should be listened

to for gain alignment. This allows any number of devices between two and eight to be grouped together. At least

two of these devices should be enabled for alignment to take place.

To enable the inter-chip limiter alignment the ICLA_EN register bit should be set to high. To enable the inter chip

BOP alignment the ICBA_EN register bit should be set to high. All devices should be configured with identical

limiter and brownout prevention settings.

8.4.2.9.1 Inter-Chip Communication (ICC) Pin

The TAS2764 has a dedicated ICC bus pin that can be used for the Inter Chip Gain Alignment (节 8.4.2.9). This

data pin enables gain alignment without consuming slots on the TDM Port (节 8.4.1). The ICC pin is connected

to all TAS2764 devices in the system and slots are configured using register bits GAIN_SLOT[5:0]. This bus

uses the TDM Port BCLK and FSYNC and requires all devices to be configured using the same sampling clock.

The ICC pin supports separate bus keeper configuration from the SDOUT pin on the TDM bus. If the ICC pin is

disabled or used for GPIO functionality the gain alignment (节 8.4.2.9) will occur on the TDM bus instead of the

ICC pin. Register bits ICC_MODE[2:0] are used to set the ICC pin functionality.

8.4.2.10 Class-D Settings

8.4.2.10.1 Synchronization and EMI

The TAS2764 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting

the AMP_SS register bit high. This can help reduce EMI in the system.

By default the Class-D amplifier switching frequency is based on the device trimmed internal oscillator. To

synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is

synchronized to the audio sample rate, the RAMP_RATE register bit must be set depending on the audio sample

rate based on either 44.1 kHz or 48 kHz frequency. For 44.1, 88.2 and 176.4 kHz, set RAMP_RATE bit high and

for 48, 96 and 192 kHz, set this bit low. This ensures that the internal ramp generator has the appropriate slope.

The TAS2764 supports closed loop edge-rate control on the class-D switching. This feature is enabled by

ERC_EN register bit. With a PVDD of less that 8 V the edge rate can slow down up to two times. A slower edge-

rate will reduce EMI and degrade efficiency. A faster edge-rate will improve efficiency but result in increased

EMI. The edge-rate of the class-D output can be set using EDGE_RATE[1:0] register bits.

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8.4.3 SAR ADC

An ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are

available via register readback (PVDD_CNV, VBAT1S_CNV and TMP_CNV registers). PVDD and VBAT1S

voltage conversions are also used by the limiter and brown out prevention blocks.

When BOP_SRC=1, VBAT1S conversion is not enabled and the ADC monitors only PVDD and temperature.

In order to prevent false triggering of BOP, limiter, thermal foldback, the initial values of SAR at power up are

VBAT1S = 6 V, PVDD = 16 V, TEMP = 2.6 ⁰C.

The ADC runs at a rate of 192 kHz with a conversion time of 5.2 μs.

Sampling rate for temperature is 10K samples/sec.

Actual PVDD and VBAT1S voltages are calculated by dividing the PVDD_CNV[11:0] and VBAT1S_CNV[11:0]

decimal values of register bits by 128. The die temperature is calculated by subtracting 93 from the decimal

value of TMP_CNV[7:0] register bits. The supply voltages PVDD and VBAT1S can be filtered using the proper

setting of the SAR_FLT[1:0] register bits but will increase measurement latency. The register bits content should

always be read from MSB to LSB.

8.4.4 Current and Voltage (IV) Sense

The TAS2764 provides speaker voltage and current sense measurements for real time monitoring of

loudspeaker behavior. The VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or

directly to the OUT_P and OUT_N connections if no EMI filter is used). The V-Sense connections eliminate

voltage drop error due to packaging, PCB interconnect or ferrite bead filter resistance. The V-sense connections

are also used for Post Filter Feed-Back (节 8.4.5) to correct for any voltage drop induced gain error or non-

linearity due to the ferrite bead. It should be noted that any interconnect resistance after the VSNS terminals will

not be corrected for, so it is advised to connect the sense connections as close to the load as possible.

The voltage and current sense ADCs have a DC blocking filter. This filter can be disabled using the

HPF_FREQ_REC[2:0] register bits.

I-Sense and V-Sense blocks can be powered down by asserting the ISNS_PD and VSNS_PD register bits

respectively. When powered down, the device will return null samples for the powered down block.

8.4.5 Post Filter Feed-Back (PFFB)

The device support post-filter feedback by closing the amplifier feedback loop after an external filter. The

feedback is applied using the VSNS_N and VSNS_P terminals of the device. This feature can be disabled using

the PFFB_EN register bit (if an external filter that violates the amplifier loop stability is implemented). When

PFFB is disabled, the feedback will be internally routed from the OUT_N and OUT_P pins of the device.

In the PFFB mode of operation the following conditions have to be met: f₀>10MHz and f₀/Q>2.5MHz (f₀and Q

are the cutoff frequency and the quality factor of the external filter).

When using PFFB with external LC filtering overshoot might occur at the speaker terminals. It is recommended

to connect resistors (see 节9.2) between speaker terninals and VSNS pins to protect internal diodes.

8.4.6 Load Diagnostics

The TAS2764 can check the speaker terminal for an open or short. This can be used to verify the continuity of

the speaker or the traces to the speaker. The entire operation is performed by the TAS2764 and result is

reported using the IRQZ pin or by reading over I²C bus on completion. The load diagnostics can be performed

using external audio clock (register bit LDG_CLK=0) or the internal oscillator (LDG_CLK=1).

The speaker open (UT) and short (LT) thresholds are configured using the LDG_RES_UT[31:0] and

LDG_RES_LT[31:0] register bits. The diagnostic is run by selecting one of the load diagnostic modes set by

MODE[2:0] register bits. The load diagnostic can be run before transitioning to active mode or stand-alone

returning to software shutdown when complete. When the load diagnostics is run it will play a 22kHz at -35dBFS

for 100ms and measure the resistance of the speaker trace. The result is averaged over the time specified by

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the LDG_AVG[1:0] register bits. The measured speaker impedance can be read from LDS_RES_VAL[31:0]

register bits.

8.4.7 Thermal Foldback

The TAS2764 monitors the die temperature and can automatically limit the audio signal when the die

temperature reaches a set threshold. It is recommended to use the thermal fold-back registers to configure this

protection mechanism as the internal DSP will perform the necessary calculation for each register.

Thermal fold-back can be disabled using TFB_EN register bit. If the die temperature reaches the value set by

TF_TEMP_TH[31:0] register bits this feature will begin to attenuate the audio signal to prevent the device from

shutting down due to over-temperature. It will attenuate the audio signal by a value set in TF_LIMS[31:0] register

bits over a range of temperature set by TF_TEMP_TH[31:0] register bits. The thermal fold-back attack is at a

fixed rate of 0.25dB per sample. A maximum attenuation can be specified using register bits

TF_MAX_ATTN[31:0]. However, if the device continues to heat up, eventually the device over-temperature will

be triggered. The attenuation will be held for a number of samples set by register bits TF_HOLD_CNT[31:0],

before the attenuation will begin releasing.

8.4.8 Over Power Protection

The TAS2764 monitors the temperature of the internal power FETs. If the maximum continue power is high and

power FETs temperature goes above a threshold, an in-built protection circuit will trigger a thermal foldback and,

if temperature still increases, shutdown the device.

The protection mechanism is based on two thresholds TH1 and TH2. The TH1 threshold is set at a temperature

116⁰C higher than the temperature measured by the internal bandgap but not less than 250⁰C. The TH1

threshold triggers a thermal foldback.

The TH2 threshold is 40⁰C above TH1 and triggers thermal shutdown.

The two detection mechanisms can be disabled by setting bits TH_DET_TH2_EN and TH_DET_TH1_EN of

register 0x47, page 0x01 to low.

8.4.9 Clocks and PLL

The device clocking is derived from the SBCLK input clock. The tables below show the valid SBCLK clock

frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies).

If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is

required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and

SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock

error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register

bits if CLK_HALT_EN bit is high. Additionally, the device can automatically power up and down on valid clock

signals if CLK_ERR_PWR_EN register bit is set to high. The device sampling rate should not be changed while

this feature is enabled. In this mode the CLK_HALT_EN bit register should be set high in order for this feature to

work properly.

表8-3. Supported SBCLK Frequencies (48 kHz based sample rates)

SBCLK to FSYNC Ratio

Sample Rate

(kHz)

16

24

32

48

2.304 MHz

64

96

125

48 kHz

96 kHz

768 kHz

1.536 MHz

1.152 MHz

2.304 MHz

1.536 MHz

3.072 MHz

6.144 MHz

4.608 MHz

9.216 MHz

6 MHz

12 MHz

4.608 MHz

SBCLK to FSYNC Ratio

256

Sample Rate

(kHz)

128

192

250

384

500

24 MHz

-

512

48 kHz

96 kHz

6.144 MHz

12.288 MHz

9.216 MHz

18.432 MHz

12 MHz

24 MHz

12.288 MHz

24.576 MHz

18.432 MHz

-

24.576 MHz

-

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表8-4. Supported SBCLK Frequencies (44.1 kHz based sample rates)

SBCLK to FSYNC Ratio

Sample Rate

(kHz)

16

24

32

48

64

96

125

44.1 kHz

88.2 kHz

705.6 kHz

1.4112 MHz

1.0584 MHz

2.1168 MHz

1.4112 MHz

2.8224 MHz

2.1168 MHz

4.2336 MHz

2.8224 MHz

5.6448 MHz

4.2336 MHz

8.4672 MHz

5.5125 MHz

11.025 MHz

SBCLK to FSYNC Ratio

256

Sample Rate

(kHz)

128

192

250

384

500

512

44.1 kHz

88.2 kHz

5.6448 MHz

11.2896 MHz

8.4672 MHz

16.9344 MHz

11.025 MHz

22.05 MHz

11.2896 MHz

22.5792 MHz

16.9344 MHz

-

22.05 MHz

-

22.5792 MHz

-

8.4.10 Echo Reference

The TAS2764 has a dedicated mode to loop back the DSP output.

This feature allows user to do noise cancellation or echo correction algorithms.

A block diagram is presented in the figure below.

图8-11. Echo Reference Loopback

The echo reference can be enabled by configuring AUDIO_TX bit in TDM_CFG12 register. The slot length and

the time slot can be selected using AUDIO_SLEN and AUDIO_SLOT bits in TDM_CFG12 register.

8.5 Operational Modes

8.5.1 Hardware Shutdown

The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the

device consumes the minimum quiescent current from AVDD, VBAT1S and PVDD supplies. All registers loose

state in this mode and I²C communication is disabled.

In normal shutdown mode if SDZ is asserted low while audio is playing, the device will ramp down volume on the

audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware

Shutdown mode. If configured in normal shutdown mode with timeout the device will force a hard shutdown after

a timeout set by the configurable shutdown timer (register bits SDZ_TIMEOUT[1:0]). The device can also be

configured for forced hard shutdown and in this case it will not attempt to gracefully disable the audio channel.

The shutdown mode can be controlled using SDZ_MODE[1:0] register bits.

When SDZ is released, the device will sample the ADDR pin and enter the software shutdown mode.

8.5.2 Mode Control and Software Reset

The TAS2764 mode can be configured by writing the MODE[2:0] register bits.

A software reset can be accomplished by setting high the SW_RESET register bit. This bit is self clearing. Once

enabled it will restore all registers to their default values.

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8.5.3 Software Shutdown

Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the

device to loose register state.

The registers are available through I²C interface.

Software Shutdown is enabled by asserting the MODE[2:0] register bits to 3'b010. If audio is playing when

Software Shutdown is asserted, the Class-D will volume ramp down before shutting down. When de-asserted,

the Class-D will begin switching and volume ramp back to the programmed digital volume setting.

8.5.4 Mute

The TAS2764 will ramp down volume of the Class-D amplifier to a mute state by setting the MODE[2:0] register

bits to 3'b001. During mute the Class-D still switches but transmits no audio content. If mute is de-asserted, the

device will ramp back the volume to the programmed digital setting.

8.5.5 Active

In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational

if enabled. PDM inputs are also active if enabled. Set the MODE[2:0] register bits to 3'b000 to enter active mode.

8.5.6 Diagnostic

The TAS2764 has a diagnostic generator that can be used without any clocking applied to the device. If

DG_CLK register bit is set low, an internal oscillator is used to generate the test patterns selected by

DG_SIG[4:0] register bits. For sine-wave generation the sampling frequency f_sshould be first set using the

SAMP_RATE[2:0] register bits.

The programable DC level for diagnostic mode can be set using the DG_DC[31:0] register bits.

To play a DC diagnostic tone set the bits HPF_FREQ_PB[2:0] in register 0x04 to 0h (disabled DC blocker).

8.5.7 Noise Gate

In this mode of operation (see section 节 8.4.2.7 ) the TAS2764 monitors the signal and powers down the class-

D when signal goes below a threshold.

8.6 Faults and Status

During the power-up sequence, the circuit monitoring the AVDD pin (UVLO) will hold the device in reset

(including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until

AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power

up, enabling detection of the operational mode. If AVDD dips below the UVLO threshold, the device will

immediately be forced into a reset state.

The device also monitors the PVDD supply and holds the analog core in power down if the supply is below the

UVLO threshold (set by register bits PVDD_UVLO_TH[5:0]). If the TAS2764 is in active operation and an UVLO

fault occurs, the analog blocks will immediately be powered down to protect the device. These faults are latched

and require a transition through HW/SW shutdown to clear the fault. The latched registers will report UVLO

faults.

The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:

•Invalid SBCLK to FSYNC ratio

•Invalid FSYNC frequency

•Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible

to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to

its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt

mask register bit IM_TDMCE is set low. The clock fault is also available for read-back in the latched fault status

registers (bits IL_TDMCE and IR_TDMCE]). Reading the latched fault status register clears the register.

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The TAS2764 also monitors die temperature and Class-D load current and will enter software shutdown mode if

either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if

the appropriate fault interrupt mask register bit is set low for over temperature and for over current. The fault

status can also be monitored in the latched fault registers as with the TDM clock error.

Over temperature warnings and flags are not raised if the device is in Idle or Noise Gate mode.

The status registers (and IRQZ pin if enabled via the status mask register) also indicate limiter behavior including

when the limiter is activated, when PVDD is below the inflection point, when maximum attenuation has been

applied, when the limiter is in infinite hold and when the limiter has muted the audio.

In the situations when the device operates in PWR_MODE2 or PWR_MODE4, the VBAT1S pin is supplied by an

internal LDO. Protection circuits monitor this block and generate faults in case of under voltage, over voltage or if

the LDO is over loaded. There is no re-try if one of these faults triggers; the device goes into shut down and the

IRQZ pin will go low.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be

pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2764 and can be accessed

by setting the IRQZ_PU register bit high. 图8-12 below highlights the IRQZ pin circuit.

IOVDD

IRQZ_PU

To

System

Master

IRQZ

Interrupt

图8-12. IRQZ Pin

The IRQZ interrupt configuration can be set using IRQZ_PIN_CFG[1:0] register bits. The IRQZ_POL register bit

sets the interrupt polarity and IRQZ_CLR register bit allows to clear the interrupt latch register bits.

Live flag registers are active only when the device is in active mode of operation. If the device is put in shutdown

by I²C command or due to any fault condition described below, the live flags will be reset. Latched flags will not

be reset in this condition and available for user to read their status.

表8-5. Fault Interrupt Mask

Interrupt

Live Register

Latch Register

IR_TO105

IR_TO115

IR_TO125

IR_TO135

IR_OT

Mask Register

IM_TO105

IM_TO115

IM_TO125

IM_TO135

IM_OT

Default (1 = Mask)

Temp Over 105C

Temp Over 115C

Temp Over 125C

Temp Over 135C

Over Temp Error

Over Current Error

TDM Clock Error

IL_TO105

1

0

1

IL_TO115

IL_TO125

IL_TO135

Device in shutdown

IL_TDMCE

IR_OC

IM_OC

IR_TDMCE

IR_TDMCEIR

IM_TDMCE

TDM Clock Error: Invalid SBCLK ratio or FS

rate

TDM Clock Error: FS changed on the fly

IR_TDNCEFC

IR_TDMCERC

TDM Clock Error: SBCLK FS ratio changed on

the fly

BOP Active

IL_BOPA

IL_BOPL0A

IL_BOPL1A

IL_BOPL2A

IR_BOPA

IR_BOPL0A

IR_BOPL1A

IR_BOPL2A

IM_BOPA

IM_BOPL0A

IM_BOPL1A

IM_BOPL2A

0

BOP Level 0 Active

BOP Level 1 Active

BOP Level 2 Active

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表8-5. Fault Interrupt Mask (continued)

Interrupt

BOP Level 3 Active

Live Register

Latch Register

IR_BOPL3A

IR_BOPIH

Mask Register

IM_BOPL3A

IM_BOPIH

Default (1 = Mask)

IL_BOPL3A

0

BOP Infinite Hold

IL_BOPIH

BOP Mute

IL_BOPM

IR_BOPM

IM_BOPM

PVDD Below LImiter Inflection

Limiter Active

IL_PBIP

IR_PBIP

IM_PBIP

IL_LIMA

IR_LIMA

IM_LIMA

Limiter Max Atten

IL_LIMMA

IR_LIMMA

IM_LIMMA

PVDD UVLO

Device in shutdown

IR_PUVLO

IR_VBAT1S_UVLO

IR_OTPCRC

IM_PUVLO

IM_VBAT1S_UVLO

VBAT1S UVLO

OTP CRC Error

Load Diagnostic Complete

Load Diagnostic Open/Short Load

Brownout Device Power Down

Internal PLL Clock Error

Noise Gate Active

IM_LDC

IM_SOL[1:0]

IM_BOPD

1

[11]

1

Device in shutdown

IL_NGA

IR_PLL_CLK

IM_PLL_CLK

1

PVDD-VBAT1S Below Threshold

Internal VBAT1S LDO Over Voltage

Internal VBAT1S LDO Under Voltage

Internal VBAT1S LDO Over Load

Thermal Detector Threshold 2

Thermal Detector Threshold 1

IL_PVBT

IR_PVBT

IR_LDO_OV

IR_LDO_UV

IR_LDO_OL

IR_TDTH2

IR_TDTH1

IM_PVBT

IM_LDO_OV

IM_LDO_UV

IM_LDO_OL

IM_TDTH2

IM_TDTH1

0

1

0

1

0

Device in shutdown

IL_TDTH2

IL_TDTH1

8.6.1 Faults and Status over TDM

Faults and device operation information can be sent over the TDM bus when STATUS_TX register bit is set high.

The slot position in TDM bus can be configured using STATUS_SLOT[5:0] register bits.

表8-6. TDM Information Bits

TDM_STATUS[7:0] Bit

Bit Information

Power up state

Y-Bridge

0 Value

1 Value

0

1

2

3

Powered down⁽¹⁾

Powered up

PVDD active

VBAT1S active

Noise gate active

Noise-Gate Status

Limiter Active

Normal operation

No Limiter or ICLA attenuation

applied

Limiter or ICLA attenuation

applied

4

5

6

7

BOP Active

Over Temperature Error

Over Current Error

PVDD Status

No BOP attenuation applied

No Over-temperature

No Over-current

BOP attenuation applied

Over-temperature detected⁽¹⁾

Over-current detected⁽¹⁾

PVDD UVLO detected⁽¹⁾

No PVDD UVLO

(1) Can be read only during the transient shutdown phase. After shutdown the TDM slots are not available.

8.7 Power Sequencing Requirements

There are no power sequencing requirements for order of the supplies other than PVDD and VBAT1S. During

power up and power down PVDD voltage must be greater than (VBAT1S-0.7V). See 节11 for details.

8.8 Digital Input Pull Downs

Each digital input and IO has an optional weak pull down to prevent the pin from floating. Register bits

DIN_PD[4:0] are used to enable/disable pull downs. The pull downs are not enabled during HW shutdown.

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8.9 Register Map

8.9.1 Register Summary Table Page=0x00

Addr

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

Register

Description

Section

节8.9.4

PAGE

Device Page

SW_RESET

MODE_CTRL

CHNL_0

Software Reset

节8.9.5

Device operational mode

Y Bridge and Channel settings

SAR Filter and DC Path Blocker

ERC and Record DC Blocke

Misc Configuration 1

Misc Configuration 2

TDM Configuration 0

TDM Configuration 1

TDM Configuration 2

Limiter

节8.9.6

节8.9.7

DC_BLK0

节8.9.8

DC_BLK1

节8.9.9

MISC_CFG1

MISC_CFG2

TDM_CFG0

TDM_CFG1

TDM_CFG2

LIM_MAX_ATTN

TDM_CFG3

TDM_CFG4

TDM_CFG5

TDM_CFG6

TDM_CFG7

TDM_CFG8

TDM_CFG9

TDM_CFG10

TDM_CFG11

ICC_CNFG2

TDM_CFG12

ICLA_CFG0

ICLA_CFG1

DG_0

节8.9.10

节8.9.11

节8.9.12

节8.9.13

节8.9.14

节8.9.15

节8.9.16

节8.9.17

节8.9.18

节8.9.19

节8.9.20

节8.9.21

节8.9.22

节8.9.23

节8.9.24

节8.9.25

节8.9.26

节8.9.27

节8.9.28

节8.9.29

节8.9.30

节8.9.31

节8.9.32

节8.9.33

节8.9.34

节8.9.35

节8.9.36

节8.9.37

节8.9.38

节8.9.39

节8.9.40

节8.9.41

节8.9.42

节8.9.43

节8.9.44

节8.9.45

节8.9.46

节8.9.47

节8.9.48

TDM Configuration 3

TDM Configuration 4

TDM Configuration 5

TDM Configuration 6

TDM Configuration 7

TDM Configuration 8

TDM Configuration 9

TDM Configuration 10

TDM Configuration 11

ICC Mode

TDM Configuration 12

Inter Chip Limiter Alignment 0

Inter Chip Gain Alignment 1

Diagnostic Signal

DVC

Digital Volume Control

Limiter Configuration 0

Limiter Configuration 1

Brown Out Prevention 0

Brown Out Prevention 1

Brown Out Prevention 2

Brown Out Prevention 3

Brown Out Prevention 4

BOP Configuration 5

Brown Out Prevention 6

Brown Out Prevention 7

Brown Out Prevention 8

Brown Out Prevention 9

BOP Configuration 10

Brown Out Prevention 11

Brown Out Prevention 12

Brown Out Prevention 13

Brown Out Prevention 14

BOP Configuration 15

LIM_CFG0

LIM_CFG1

BOP_CFG0

BOP_CFG1

BOP_CFG2

BOP_CFG3

BOP_CFG4

BOP_CFG5

BOP_CFG6

BOP_CFG7

BOP_CFG8

BOP_CFG9

BOP_CFG10

BOP_CFG11

BOP_CFG12

BOP_CFG13

BOP_CFG14

BOP_CFG15

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0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x40

0x41

0x42

0x43

0x44

0x47

0x48

0x49

0x4A

0x4B

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x5C

0x5D

0x60

0x63

0x65

0x67

0x68

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

BOP_CFG17

BOP_CFG18

BOP_CFG19

BOP_CFG20

BOP_CFG21

BOP_CFG22

BOP_CFG23

BOP_CFG24

NG_CFG0

Brown Out Prevention 17

Brown Out Prevention 18

Brown Out Prevention 19

Brown Out Prevention 20

BOP Configuration 21

Brown Out Prevention 22

Lowest PVDD Measured

Lowest BOP Attack Rate

Noise Gate 0

节8.9.49

节8.9.50

节8.9.51

节8.9.52

节8.9.53

节8.9.54

节8.9.55

节8.9.57

节8.9.58

节8.9.59

节8.9.60

节8.9.61

节8.9.62

节8.9.63

节8.9.64

节8.9.65

节8.9.66

节8.9.67

节8.9.68

节8.9.69

节8.9.70

节8.9.71

节8.9.72

节8.9.73

节8.9.74

节8.9.75

节8.9.76

节8.9.77

节8.9.78

节8.9.79

节8.9.80

节8.9.81

节8.9.82

节8.9.83

节8.9.84

节8.9.85

节8.9.86

节8.9.87

节8.9.88

节8.9.89

节8.9.90

节8.9.91

节8.9.92

节8.9.93

节8.9.94

节8.9.95

节8.9.96

节8.9.97

NG_CFG1

Noise Gate 1

LVS_CFG0

DIN_PD

Low Voltage Signaling

Digital Input Pin Pull Down

Output Driver Strength

Interrupt Mask 0

IO_DRV0

IO_DRV1

INT_MASK0

INT_MASK1

INT_MASK4

INT_MASK2

INT_MASK3

INT_LIVE0

INT_LIVE1

INT_LIVE1_0

INT_LIVE2

INT_LIVE3

INT_LTCH0

INT_LTCH1

INT_LTCH1_0

INT_LTCH2

INT_LTCH3

INT_LTCH4

VBAT_MSB

VBAT_LSB

PVDD_MSB

PVDD_LSB

TEMP

Interrupt Mask 1

Interrupt Mask 4

Interrupt Mask 2

Interrupt Mask 3

Live Interrupt Read-back 0

Live Interrupt Read-back 1

Live Interrupt Read-back 1_0

Live Interrupt Read-back 2

Live Interrupt Read-back 3

Latched Interrupt Read-back 0

Latched Interrupt Read-back 1

Latched Interrupt Read-back 1_0

Latched Interrupt Read-back 2

Latched Interrupt Read-back 3

Latched Interrupt Read-back 4

SAR VBAT1S 0

SAR VBAT1S 1

SAR PVDD 0

SAR PVDD 1

SAR ADC Conversion 2

Clock Setting and IRQZ

Misc Configuration 3

Clock Configuration

INT_CLK_CFG

MISC_CFG3

CLOCK_CFG

IDLE_IND

Idle channel current optimization

Misc Configuration 4

Idle Channel Hysterisis

Detect Clock Ration and Sample Rate

Class-D and LVS Delays

Noise Gate 2

MISC_CFG4

TG_CFG0

CLK_CFG

LV_EN_CFG

NG_CFG2

NG_CFG3

Noise Gate 3

NG_CFG4

Noise Gate 4

NG_CFG5

Noise Gate 5

NG_CFG6

Noise Gate 6

NG_CFG7

Noise Gate 7

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0x71

0x76

0x7D

0x7E

0x7F

PVDD_UVLO

DAC_MOD_RST

REV_ID

UVLO Threshold

DAC Modulator Reset

Revision and PG ID

I2C Checksum

节8.9.98

节8.9.99

节8.9.100

节8.9.101

节8.9.102

I2C_CKSUM

BOOK

Device Book

8.9.2 Register Summary Table Page=0x01

0x19

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x47

LSR

Modulation

节8.9.103

节8.9.104

节8.9.105

节8.9.106

节8.9.107

节8.9.108

节8.9.109

节8.9.110

节8.9.111

节8.9.112

节8.9.113

SDOUT_HIZ_1

SDOUT_HIZ_2

SDOUT_HIZ_3

SDOUT_HIZ_4

SDOUT_HIZ_5

SDOUT_HIZ_6

SDOUT_HIZ_7

SDOUT_HIZ_8

SDOUT_HIZ_9

TG_EN

Slots Control

Thermal Detection Enable

8.9.3 Register Summary Table Page=0x04

Addr

Register

DG_DC_VAL1

Description

Diagnostic DC Level

Section

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

节8.9.114

节8.9.115

节8.9.116

节8.9.117

节8.9.118

节8.9.119

节8.9.120

节8.9.121

节8.9.122

节8.9.123

节8.9.124

节8.9.125

节8.9.126

节8.9.127

节8.9.128

节8.9.129

节8.9.130

节8.9.131

节8.9.132

节8.9.133

节8.9.134

节8.9.135

节8.9.136

节8.9.137

节8.9.138

节8.9.139

节8.9.140

DG_DC_VAL2

DG_DC_VAL3

DG_DC_VAL4

LIM_TH_MAX1

LIM_TH_MAX2

LIM_TH_MAX3

LIM_TH_MAX4

LIM_TH_MIN1

LIM_TH_MIN2

LIM_TH_MIN3

LIM_TH_MIN4

LIM_INF_PT1

LIM_INF_PT2

LIM_INF_PT3

LIM_INF_PT4

LIM_SLOPE1

LIM_SLOPE2

LIM_SLOPE3

LIM_SLOPE4

TF_HLD1

Diagnostic DC Level

Limiter Maximum Threshold

Limiter Minimum Threshold

Limiter Inflection Point

Limiter Slope

TFB Maximum Hold

TFB Release Rate

TF_HLD2

TF_HLD3

TF_HLD4

TF_RLS1

TF_RLS2

TFB Release Rate

TF_RLS3

TFB Release Rate

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0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

TF_RLS4

TFB Release Rate

节8.9.141

节8.9.142

节8.9.143

节8.9.144

节8.9.145

节8.9.146

节8.9.147

节8.9.148

节8.9.149

节8.9.150

节8.9.151

节8.9.152

节8.9.153

节8.9.154

节8.9.155

节8.9.156

节8.9.157

节8.9.158

节8.9.159

节8.9.160

节8.9.161

节8.9.162

节8.9.163

节8.9.164

节8.9.165

节8.9.166

节8.9.167

节8.9.168

节8.9.169

TF_SLOPE1

TF_SLOPE2

TF_SLOPE3

TF_SLOPE4

TF_TEMP_TH1

TF_TEMP_TH2

TF_TEMP_TH3

TF_TEMP_TH4

TF_MAX_ATTN1

TF_MAX_ATTN2

TF_MAX_ATTN3

TF_MAX_ATTN4

LD_CFG0

TFB Limiter Slope

TFB Threshold

TFB Gain Reduction

Load Diagnostics Resistance Upper Threshold

Load Diagnostics Resistance Lower Threshold

Class D Efficiency

LD_CFG1

LD_CFG2

LD_CFG3

LD_CFG4

LD_CFG5

LD_CFG6

LD_CFG7

CLD_EFF_1

CLD_EFF_2

CLD_EFF_3

CLD_EFF_4

LDG_RES1

LDG_RES2

LDG_RES3

LDG_RES4

Class D Efficiency

Load Diagnostics Resistance Value

NOTE: all register bits described in italic font can be programmed in Active mode.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.9.4 PAGE (page=0x00 address=0x00) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

PAGE[7:0]

RW

0h

Sets the device page.

00h = Page 0

01h = Page 1

...

FFh = Page 255

8.9.5 SW_RESET (page=0x00 address=0x01) [reset=00h]

Bit

7-1

0

Field

Type

R

Reset

0h

Description

Reserved

SW_RESET

Reserved

RW

0h

Software reset. Bit is self clearing.

0b = De-asserted

1b = Asserted

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8.9.6 MODE_CTRL (page=0x00 address=0x02) [reset=1Ah]

Bit

Field

Type

Reset

Description

7

BOP_SRC

RW

0h

BOP input source and PVDD UVLO

0b = VBAT1S input and PVDD UVLO disabled.

* With this bit low at reset all BOP thresholds are by default at

2.75V

1b = PVDD input and PVDD UVLO enabled.

6-5

4

Reserved

RW

0h

1h

Reserved

ISNS_PD

Current sense is

0b = Active

1b = Powered down

3

VSNS_PD

MODE[2:0]

RW

1h

2h

Voltage sense is

0b = Active

1b = Powered down

2-0

Device operational mode.

000b = Active without Mute

001b = Active with Mute

010b = Software Shutdown

011b = Load Diagnostics followed by normal device power up

100b = Standalone Load Diagnostic, after completion these bits

are self reset to 010b

101b = Diagnostic Generator Mode

110b-111b = Reserved

8.9.7 CHNL_0 (page=0x00 address=0x03) [reset=28h]

Bit

Field

Type

Reset

Description

7-6

CDS_MODE[1:0]

RW

0h

Class-D switching mode

00b =Y-Bridge, high power on VBAT1S

01b = VBAT1S Only Supply of Class D

10b =PVDD Only Supply of Class D

11b=Y-Bridge, low power on VBAT1S

5-1

AMP_LEVEL[4:0]

RW

14h

Setting

00h

11 dBV

01h

11.5 dBV

12.0 dBV

12.5 dBV

….….….….….….

20 dBV

02h

03h

….….….….….….

12h

13h

20.5 dBV

21 dBV

14h

Others : Reserved

Reserved

0

Reserved

RW

0h

8.9.8 DC_BLK0 (page=0x00 address=0x04) [reset=21h]

Bit

Field

Type

Reset

Description

7

VBAT1S_MODE

RW

0h

VBAT1S supply

0b = Supplied externally

1b = Internal generated from PVDD

6

IRQZ_PU

RW

0h

IRQZ internal pull up enable.

0b = Disabled

1b = Enabled

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Bit

Field

Type

Reset

Description

5

AMP_SS

*When Spread Spectrum and Sync

RW

1h

Low EMI spread spectrum is

0b = Disabled

1b = Enabled

Mode are both enabled, Sync Mode

takes priority

4-3

2-0

SAR_FLT[1:0]

RW

0h

1h

VBAT1S and PVDD ADC filter frequency

00b = Disabled

01b = 300 KHz

10b = 150 KHz

11b = 50 KHz

HPF_FREQ_PB[2:0]

Forward Path DC blocker -3dB corner frequency for 48/96 kHz

sampling rates

0h = Disabled (filter bypassed)

1h = 2 Hz

2h = 50 Hz

3h = 100 Hz

4h = 200 Hz

5h = 400 Hz

6h = 800 Hz

7h = Reserved

* For 44.1/88.2 kHz sampling rates divide the values from above

by 1.0884

8.9.9 DC_BLK1 (page=0x00 address=0x05) [reset=41h]

Bit

7

Field

Type

RW

Reset

0h

Description

Reserved

ERC_EN

Reserved

6

RW

1h

Closed-loop edge rate control is

0b = Disabled

1b = Enabled

5-4

EDGE_RATE[1:0]

RW

0h

Class-D ERC control

0h = 1 V/ns

1h = 0.5 V/ns

2h = 0.35 V/ns

3h = 0.25 V/ns

3

TFB_EN

RW

0h

1h

Thermal Foldback is

0b = Disabled

1b = Enabled

2-0

HPF_FREQ_REC[2:0]

Record Path DC blocker -3dB corner frequency for 48/96 kHz

sampling rates

0h = Disabled (filter bypassed)

1h = 2 Hz

2h = 50 Hz

3h = 100 Hz

4h = 200 Hz

5h = 400 Hz

6h = 800 Hz

7h = Reserved

* For 44.1/88.2 kHz sampling rates divide the values from above

by 1.0884

8.9.10 MISC_CFG1 (page=0x00 address=0x06) [reset=00h]

表8-7.

Bit

7-6

5

Field

Type

RW

Reset

Description

Reserved

*OCE_RETRY

0h

Reserved

RW

0h

Retry after over current event.

0b = Disabled

1b = Enabled, retry after timer.

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表8-7. (continued)

Bit

Field

Type

Reset

Description

4

*OTE_RETRY

RW

0h

Retry after over temperature event.

0b = Disabled

1b = Enabled, retry after timer.

3

2

PFFB_EN

RW

0h

Post-Filter Feedback is

0b = Disabled (uses OUT)

1b = Enable (uses VSNS)

SMODE_EN

When safe mode is enabled adds 18dB attenuation on channel

gain. Safe mode is

0b = Disabled

1b = Enabled

1-0

Reserved

R

0h

Reserved

*Certain limitations applied. Contact TI if need to use this bit.

8.9.11 MISC_CFG2 (page=0x00 address=0x07) [reset=20h]

Bit

Field

Type

Reset

Description

7-6

SDZ_MODE[1:0]

RW

0h

SDZ Mode configuration.

00b = Shutdown after timeout

01b = Immediate forced shutdown

10b = Reserved

11b = Reserved

5-4

3-2

SDZ_TIMEOUT[1:0]

RW

2h

0h

SDZ Timeout value

00b = 2 ms

01b = 4 ms

10b = 6 ms

11b = 23.8 ms

DVC_RAMP_RATE[1:0]

Digital volume control ramp rate for low to high ramp

00b = 0.5 dB per 1 sample

01b = 0.5 dB per 4 samples

10b = 0.5 dB per 8 samples

11b = Volume ramping disabled

1

0

I2C_GBL_EN

I2C_AD_DET

RW

0h

I2c global address is

0b = Disabled

1b = Enabled

Re-detect I2C slave address (self clearing bit).

0b = Normal

1b = Re-detect address

8.9.12 TDM_CFG0 (page=0x00 address=0x08) [reset=09h]

Bit

Field

Type

Reset

Description

7

AMP_INV

RW

0h

Invert audio amplifier ouput

0b = Normal

1b = Invert

6

CLASSD_SYNC

RW

0h

Class-D synchronization mode.

0b = Not synchronized to audio clocks

1b = Synchronized to audio clocks

*When Spread Spectrum and Sync

Mode are both enabled, Sync Mode

takes priority

5

4

RAMP_RATE

AUTO_RATE

RW

0h

Sample rate based on 44.1kHz or 48 kHz when

CLASSD_SYNC=1.

0b = 48 kHz

1b = 44.1 kHz

Auto detection of TDM sample rate.

0b = Enabled

1b = Disabled

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Bit

Field

Type

Reset

Description

3-1

SAMP_RATE[2:0]

RW

4h

Sample rate of the TDM bus.

000b-011b = Reserved

100b = 44.1/48 kHz

101b = 88.2/96 kHz

110b-111b = Reserved

0

FRAME_START

RW

1h

TDM frame start polarity.

0b = Low to High on FSYNC

1b = High to Low on FSYNC

8.9.13 TDM_CFG1 (page=0x00 address=0x09) [reset=02h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

RX_JUSTIFY

Reserved

6

RW

0h

TDM RX sample justification within the time slot.

0b = Left

1b = Right

5-1

0

RX_OFFSET[4:0]

RX_EDGE

RW

1h

0h

TDM RX start of frame to time slot 0 offset (SBCLK cycles).

TDM RX capture clock polarity.

0b = Rising edge of SBCLK

1b = Falling edge of SBCLK

8.9.14 TDM_CFG2 (page=0x00 address=0x0A) [reset=0Ah]

Bit

Field

Type

Reset

Description

7-6

IVMON_LEN[1:0]

RW

0h

Sets the current and voltage data to length of

00b = 16 bits

01b = 12 bits

10b = 8 bits

11b = Reserved

5-4

3-2

1-0

RX_SCFG[1:0]

RX_WLEN[1:0]

RX_SLEN[1:0]

RW

0h

2h

TDM RX time slot select config.

00b = Mono with time slot equal to I2C address offset

01b = Mono left channel

10b = Mono right channel

11b = Stereo downmix (L+R)/2

TDM RX word length.

00b = 16-bits

01b = 20-bits

10b = 24-bits

11b = 32-bits

TDM RX time slot length.

00b = 16-bits

01b = 24-bits

10b = 32-bits

11b = Reserved

8.9.15 LIM_MAX_ATTN (page=0x00 address=0x0B) [reset=80h]

Bit

Field

Type

Reset

Description

7-4

LIM_MAX_ATTN[3:0]

RW

8h

Limiter Maximum Attenuation

0h = 1 dB

1h = 2 dB

2h = 3 dB

...

0Eh = 15 dB

0Fh = Reserved

3-0

Reserved

R

0h

Reserved

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8.9.16 TDM_CFG3 (page=0x00 address=0x0C) [reset=10h]

Bit

7-4

3-0

Field

Type

RW

Reset

1h

Description

RX_SLOT_R[3:0]

RX_SLOT_L[3:0]

TDM RX Right Channel Time Slot.

TDM RX Left Channel Time Slot.

RW

0h

8.9.17 TDM_CFG4 (page=0x00 address=0x0D) [reset=13h]

Bit

Field

Type

Reset

Description

7

TX_KEEPCY

RW

0h

TDM and ICC TX SDOUT LSB data will be driven for full/half

cycles when TX_KEEPEN is enabled

0b = Full-cycle

1b = Half-cycle

6

TX_KEEPLN

RW

0h

TDM and ICC TX SDOUT will hold the bus for the following

when TX_KEEPEN is enabled

0b = 1 LSB cycle

1b = Always

5

4

TX_KEEPEN

TX_FILL

RW

0h

1h

TDM and ICC TX SDOUT bus keeper enable.

0b = Disable bus keeper

1b = Enable bus keeper

TDM and ICC TX SDOUT unused bit field fill.

0b = Transmit 0

1b = Transmit Hi-Z

3-1

0

TX_OFFSET[2:0]

TX_EDGE

RW

1h

TDM TX start of frame to time slot 0 offset.

TDM TX launch clock polarity.

0b = Rising edge of SBCLK

1b = Falling edge of SBCLK

8.9.18 TDM_CFG5 (page=0x00 address=0x0E) [reset=42h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

VSNS_TX

Reserved

6

RW

1h

TDM TX voltage sense transmit

0b = Disabled

1b = Enabled

5-0

VSNS_SLOT[5:0]

RW

2h

TDM TX voltage sense time slot.

8.9.19 TDM_CFG6 (page=0x00 address=0x0F) [reset=40h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

ISNS_TX

Reserved

6

RW

1h

TDM TX current sense transmit

0b = Disabled

1b = Enabled

5-0

ISNS_SLOT[5:0]

RW

0h

TDM TX current sense time slot.

8.9.20 TDM_CFG7 (page=0x00 address=0x10) [reset=04h]

Bit

Field

Type

Reset

Description

7

VBAT1S_SLEN

RW

0h

TDM TX VBAT1S time slot length.

0b = Truncate to 8-bits

1b = Left justify to 16-bits

6

VBAT1S_TX

RW

0h

4h

TDM TX VBAT1S transmit enable.

0b = Disabled

1b = Enabled

5-0

VBAT1S_SLOT[5:0]

TDM TX VBAT1S time slot.

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8.9.21 TDM_CFG8 (page=0x00 address=0x11) [reset=05h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

TEMP_TX

Reserved

6

RW

0h

TDM TX temp sensor transmit enable.

0b = Disabled

1b = Enabled

5-0

TEMP_SLOT[5:0]

RW

5h

TDM TX temp sensor time slot.

8.9.22 TDM_CFG9 (page=0x00 address=0x12) [reset=06h]

Bit

Field

Type

Reset

Description

7

PVDD_SLEN

RW

0h

TDM TX PVDD time slot length.

0b = Truncate to 8-bits

1b = Left justify to 16-bits

6

PVDD_TX

RW

0h

6h

TDM TX PVDD transmit enable.

0b = Disabled

1b = Enabled

5-0

PVDD_SLOT[5:0]

TDM TX PVDD time slot.

8.9.23 TDM_CFG10 (page=0x00 address=0x13) [reset=08h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

STATUS_TX

Reserved

6

RW

0h

TDM TX status transmit enable.

0b = Disabled

1b = Enabled

5-0

STATUS_SLOT[5:0]

RW

8h

TDM TX status time slot.

Bit7- PVDD status(Cannot be read post analog blocks

shutdown)

0b = PVDD UVLO not detected

1b = PVDD UVLO detected

Bit6 -Over Current status(Cannot be read post analog blocks

shutdown)

0b = No OC detected

1b = OC detected

Bit5- Over Temp status(Cannot be read post analog blocks

shutdown)

0b = No OT detected

1b = OT detected

Bit4- BOP status

0b = BOP not detected

1b = BOP detected

Bit3- Signal distortion limiter status

0b = No distortion limiter or ICLA gain applied

1b = Gain attenuation done due to distortion limiter/ICLA

Bit2- Noise Gate status

0b = Device in normal mode

1b = Device in Noise Gate mode

Bit1- Class D Power Stage status

0b = Class D Power switch connected to VBAT1S

1b = Class D Power switch connected to PVDD

Bit0- Power Up state (Cannot be read post analog blocks

shutdown)

0b = Device is powered down

1b = Device is in active state

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8.9.24 TDM_CFG11 (page=0x00 address=0x14) [reset=0Ah]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

GAIN_TX

Reserved

6

RW

0h

TDM /ICC TX limiter gain reduction transmit enable.

0b = Disabled

1b = Enabled

5-0

GAIN_SLOT[5:0]

RW

Ah

TDM /ICC TX limiter gain reduction time slot.

00h = 0

01h = 1

........

3Eh = 62

3Fh = 63

8.9.25 ICC_CNFG2 (page=0x00 address=0x15) [reset=00h]

Bit

7-5

4-2

Field

Type

R

Reset

0h

Description

Reserved

ICC_MODE[2:0]

Reserved

RW

0h

Selects ICC pin function

0h = Gain alignment on ICC pin

1h = Reserved

2h = ICC pin buffers disabled

3h = ICC pin is a general purpose input

4h = ICC pin is a general purpose output

5h-7h = Reserved

1-0

Reserved

R

0h

Reserved

8.9.26 TDM_CFG12 (page=0x00 address=0x16) [reset=12h]

Bit

Field

Type

Reset

Description

7

AUDIO_SLEN

RW

0h

TDM audio slot length

0b = 16-bits

1b = 24-bits

6

AUDIO_TX

RW

0h

TDM audio output transmit is

0b = Disabled

1b = Enabled

5-0

AUDIO_SLOT[5:0]

12h

TDM TX status time slot.

8.9.27 ICLA_CFG0 (page=0x00 address=0x17) [reset=0Ch]

Bit

Field

Type

Reset

Description

7

ICBA_EN

RW

0h

Inter chip brownout gain alignment is

0b = Disabled

1b = Enabled

6-1

0

ICGA_SLOT[5:0]

ICLA_EN

RW

6h

0h

Inter chip gain alignment starting time slot.

Inter chip limiter alignment gain is

0b = Disabled

1b = Enabled

8.9.28 ICLA_CFG1 (page=0x00 address=0x18) [reset=00h]

Bit

Field

Type

Reset

Description

7

ICGA_SEN[7]

RW

0h

Time slot equals ICGA_SLOT[5:0]+7*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

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Bit

Field

Type

Reset

Description

6

ICGA_SEN[6]

RW

0h

Time slot equals ICGA_SLOT[5:0]+6*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

5

4

3

2

1

0

ICGA_SEN[5]

ICGA_SEN[4]

ICGA_SEN[3]

ICGA_SEN[2]

ICGA_SEN[1]

ICGA_SEN[0]

RW

0h

Time slot equals ICGA_SLOT[5:0]+5*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

Time slot equals ICGA_SLOT[5:0]+4*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

Time slot equals ICGA_SLOT[5:0]+3*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

Time slot equals ICGA_SLOT[5:0]+2*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

Time slot equals ICGA_SLOT[5:0]+1*3. When enabled, the

limiter will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

Time slot equals ICGA_SLOT[5:0]+0. When enabled, the limiter

will include this time slot in the alignment group.

0b = Disabled

1b = Enabled

8.9.29 DG_0 (page=0x00 address=0x19) [reset=0Dh]

Bit

Field

Type

Reset

Description

7

ICGA_NG_EN

RW

0h

Better and audio friendly ICGA feature (when Noise gate is

enabled)

0b = Feature disabled

1b = Feature enabled

6

5

DG_CLK

RW

0h

Dh

Diagnostic generate clock source is

0b = internal osscilator

1b = external SBCLK and FSYNC

ICG_MODE

DG_SIG[4:0]

Device attenuation is

0b = BOP and Limiter attenuation added together

1b = Max attenuation of either BOP or limiter

4-0

Selects Tone Freq for DG MODE

00h = Zero input (Idle channel)

01h = -6 dBFS positive DC

02h = -6 dBFS negative DC

03h = -12 dBFS positive DC

04h = -12 dBFS negative DC

05h = -18 dBFS positive DC

06h = -18 dBFS negative DC

07h = -24 dBFS positive DC

08h = -24 dBFS negative DC

09h = -30 dBFS positive DC

0Ah = -30 dBFS negative DC

0Bh = -6 dBFS f_s/4

0Ch = -4.8 dBFS f_s/6

0Dh = 0 dBFS 1KHz sine

0Eh = Programmable DC using B0_P4, registers 0x08 to 0x0B

0Fh-1Fh = Reserved

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8.9.30 DVC (page=0x00 address=0x1A) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

DVC_LVL[7:0]

RW

0h

00h = 0 dB

01h = -0.5 dB

02h = -1 dB

...

C8h = -100 dB

Others : Mute

8.9.31 LIM_CFG0 (page=0x00 address=0x1B) [reset=22h]

Bit

7-6

5

Field

Type

R

Reset

0h

Description

Reserved

LIM_DHYS_EN

Reserved

RW

1h

Limiter dynamic headroom is

0b = Disabled

1b = Enabled

4-1

LIM_ATK_RT[3:0]

RW

1h

00h = 20 us/dB

01h = 40 us/dB

02h = 80 us/dB

03h = 160 us/dB

04h = 320 us/dB

05h = 640 us/dB

06h = 1280 us/dB

07h = 2560 us/dB

08h = 5120 us/dB

09h = 10240 us/dB

Ah = 20480 us/dB

Bh = 40960 us/dB

Ch = 81920 us/dB

Others : Reserved

0

LIM_EN

RW

0h

Limiter is

0b = Disabled

1b = Enabled

8.9.32 LIM_CFG1 (page=0x00 address=0x1C) [reset=32h]

Bit

Field

Type

Reset

Description

7

LIM_PDB

RW

0h

During BOP the limiter will be

0b = Running

1b = Paused

6-3

LIM_RLS_RT[3:0]

RW

6h

00h = Reserved

01h = 4 ms/dB

02h = 8 ms/dB

03h = 16 ms/dB

04h = 32 ms/dB

05h = 64 ms/dB

06h = 128 ms/dB

07h = 256 ms/dB

08h = 512 ms/dB

09h = 1024 ms/dB

Ah = 2048 ms/dB

Bh = 4096 ms/dB

Ch = 8192 ms/dB

Others : reserved

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Bit

Field

Type

Reset

Description

2-0

LIM_HLD_TM[2:0]

RW

2h

Limiter hold time.

000b = 0 ms

001b = 10 ms

010b = 25 ms

011b = 50 ms

100b = 100 ms

101b = 250 ms

110b = 500 ms

111b = 1000 ms

8.9.33 BOP_CFG0 (page=0x00 address=0x1D) [reset=40h]

Bit

Field

Type

Reset

Description

7-3

LIM_DHR[4:0]

RW

8h

Limiter Maximum Headroom as % of PVDD

00h = -20 %

01h = -17.5 %

02h = -15 %

..

0Fh = 17.5 %

10h = 20 %

Others = Reserved

2

1

Reserved

R

0h

Reserved

BOP_SHDN

RW

When BOP level 0 is reached device

0b = Attenuates based on level 0 setttings

1b = Mutes followed by device shutdown

0

BOP_EN

RW

0h

Brown out prevention is

0b = Disabled

1b = Enabled

8.9.34 BOP_CFG1 (page=0x00 address=0x1E) [reset=32h]

Bit

Field

Type

Reset

Description

7

BOP_HLD_CLR

RW

0h

BOP infinite hold clear (self clearing).

0b = Don't clear

1b = Clear

6-0

DEV_MAX_ATTEN[6:0]

RW

32h

Device maximum attenuation of limiter and BOP combined.

00h = 0 dB

01h= -1 dB

02h = -2 dB

03h = -3 dB

..

2Eh = -46 dB

2Fh-7Fh = Reserved

8.9.35 BOP_CFG2 (page=0x00 address=0x1F) [reset=02h]

Bit

Field

Type

Reset

Description

7-5

BOP_DT3[2:0]

RW

0h

BOP level 3 dwell time

0h= 0 us

1h = 100 us

2h = 250 us

3h = 500 us

4h = 1000 us

5h = 2000 us

6h = 4000 us

7h = 8000 us

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Bit

Field

BOP_ATK_ST3[3:0]

Type

Reset

Description

4-1

RW

1h

BOP level 3 attack step size

0h = -0.0625 dB

1h = -0.5 dB

2h = -0.8958 dB

3h = -1.2916 dB

4h = -1.6874 dB

5h = -2.0832 dB

6h = -2.479 dB

7h = -2.8748 dB

8h = -3.2706 dB

9h = -3.6664 dB

Ah =-4.0622 dB

Bh = -4.458 dB

Ch = -4.8538 dB

Dh = -5.2496 dB

Eh = -5.6454 dB

Fh = -6dB

0

Reserved

R

0h

Reserved

8.9.36 BOP_CFG3 (page=0x00 address=0x20) [reset=06h]

Bit

Field

Type

Reset

Description

7-5

BOP_ATK_RT3[2:0]

RW

0h

BOP level 3 attack rate.

0h= 2.5 us

1h = 5 us

2h = 10 us

3h = 25 us

4h = 50 us

5h = 100 us

6h = 250 us

7h = 500 us

4-1

BOP_RLS_ST3[3:0]

RW

3h

BOP level 3 release step size.

0h = 0.0625 dB

1h = 0.5 dB

2h = 0.8958 dB

3h = 1.2916 dB

4h = 1.6874 dB

5h = 2.0832 dB

6h = 2.479 dB

7h = 2.8748 dB

8h = 3.2706 dB

9h = 3.6664 dB

0Ah =4.0622 dB

0Bh = 4.458 dB

0Ch = 4.8538 dB

0Dh = 5.2496 dB

0Eh = 5.6454 dB

0Fh = 6 dB

0

Reserved

R

0h

Reserved

8.9.37 BOP_CFG4 (page=0x00 address=0x21) [reset=2Ch]

Bit

Field

Type

Reset

Description

7-5

BOP_RLS_RT3[2:0]

RW

1h

BOP level 3 release rate time.

0h= 5 ms

1h = 10 ms

2h = 25 ms

3h = 50 ms

4h = 100 ms

5h = 250 ms

6h = 500 ms

7h = 1000 ms

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Bit

Field

Type

Reset

Description

4-0

BOP_MAX_ATTN3[4:0]

RW

Ch

BOP level 3 maximum attenuation.

00h = 0 dB

01h = -1 dB

02h = -2 dB

..

0Ch = -12 dB

..

1Eh = -30 dB

1Fh = -31 dB

8.9.38 BOP_CFG5 (page=0x00 address=0x22) [reset=4Ch]

Bit Field

Type Reset Description

7-0 BOP_TH3[7:0]

RW

4Ch

BOP level 3 threshold

Setting

BOP Threshold (V) -

BOP_SRC=0 (VBAT1S Source) BOP_SRC=1 (PVDD Source)

00h

01h

2.7

2.75

2.8

.....

5.5

0

5.5

5.55

5.6

.....

8.3

8.35

.....

10

02h

.....

38h

39h

.....

0

5Ah

.....

0

.....

15.95

16

D1h

D2h

D3h-FFh

0

8.9.39 BOP_CFG6 (page=0x00 address=0x23) [reset=20h]

Bit

Field

Type

Reset

Description

7-5

BOP_HT3[2:0]

RW

1h

BOP level 3 hold time.

0h = 0 ms

1h = 10 ms

2h = 100 ms

3h = 250 ms

4h = 500ms

5h = 1000 ms

6h = 2000 ms

7h = Infinite (This can be exited using BOP_HLD_CLR bit)

4

BOP_DIS3

RW

0h

BOP level 3 is

0b = Enabled

1b = Disabled

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Bit

Field

BOP_STAT_STATE[3:0]

Type

Reset

Description

3-0

R

0h

BOP current state. Set BOP_STAT_HLD high to hold for

readack.

0h = Idle

1h = Attacking Level 3

2h = Attacking Level 2

3h = Attacking Level 1

4h = Attacking Level 0

5h = Holding Level 3

6h = Holding Level 2

7h = Holding Level1

8h =Holding Level 0

9h = Releasing Level 3

Ah = Releasing Level 2

Bh = Releasing Level 1

Ch = Releasing Level 0

Dh-Fh = Reserved

8.9.40 BOP_CFG7 (page=0x00 address=0x24) [reset=02h]

Bit

Field

Type

Reset

Description

7-5

BOP_DT2[2:0]

RW

0h

BOP level 3 dwell time

0h= 0 us

1h = 100 us

2h = 250 us

3h = 500 us

4h = 1000 us

5h = 2000 us

6h = 4000 us

7h = 8000 us

4-1

BOP_ATK_ST2[3:0]

RW

1h

BOP level 2 attack step size

0h = -0.0625 dB

1h = -0.5 dB

2h = -0.8958 dB

3h = -1.2916 dB

4h = -1.6874 dB

5h = -2.0832 dB

6h = -2.479 dB

7h = -2.8748 dB

8h = -3.2706 dB

9h = -3.6664 dB

Ah =-4.0622 dB

Bh = -4.458 dB

Ch = -4.8538 dB

Dh = -5.2496 dB

Eh = -5.6454 dB

Fh = -6 dB

0

Reserved

R

0h

Reserved

8.9.41 BOP_CFG8 (page=0x00 address=0x25) [reset=06h]

Bit

Field

Type

Reset

Description

7-5

BOP_ATK_RT2[2:0]

RW

0h

BOP level 2 attack rate.

0h= 2.5 us

1h = 5 us

2h = 10 us

3h = 25 us

4h = 50 us

5h = 100 us

6h = 250 us

7h = 500 us

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Bit

Field

Type

Reset

Description

4-1

BOP_RLS_ST2[3:0]

RW

3h

BOP level 2 release step size.

0h = 0.0625 dB

1h = 0.5 dB

2h = 0.8958 dB

3h = 1.2916 dB

4h = 1.6874 dB

5h = 2.0832 dB

6h = 2.479 dB

7h = 2.8748 dB

8h = 3.2706 dB

9h = 3.6664 dB

Ah =4.0622 dB

Bh = 4.458 dB

Ch = 4.8538 dB

Dh = 5.2496 dB

Eh = 5.6454 dB

Fh = 6 dB

0

Reserved

R

0h

Reserved

8.9.42 BOP_CFG9 (page=0x00 address=0x26) [reset=32h]

Bit

Field

Type

Reset

Description

7-5

BOP_RLS_RT2[2:0]

RW

1h

BOP level 2 release rate time.

0h= 5 ms

1h = 10 ms

2h = 25 ms

3h = 50 ms

4h = 100 ms

5h = 250 ms

6h = 500 ms

7h = 1000 ms

4-0

BOP_MAX_ATTN2[4:0]

RW

12h

BOP level 2 maximum attenuation.

00h = 0 dB

01h = -1 dB

02h = -2 dB

..

0Ch = -12 dB

..

1Eh = -30 dB

1Fh = -31 dB

58

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8.9.43 BOP_CFG10 (page=0x00 address=0x27) [reset=46h]

Bit Field

Type Reset Description

7-0 BOP_TH2[7:0]

RW

46h

BOP level 2 threshold

Setting

BOP Threshold (V) -

BOP_SRC=0 (VBAT1S Source) BOP_SRC=1 (PVDD Source)

00h

01h

2.7

2.75

2.8

.....

5.5

0

5.5

5.55

5.6

.....

8.3

8.35

.....

10

02h

.....

38h

39h

.....

0

5Ah

.....

0

.....

15.95

16

D1h

D2h

D3h-FFh

0

8.9.44 BOP_CFG11 (page=0x00 address=0x28) [reset=20h]

Bit

Field

Type

Reset

Description

7-5

BOP_HT2[2:0]

RW

1h

BOP level 2 hold time.

0h = 0 ms

1h = 10 ms

2h = 100 ms

3h = 250 ms

4h = 500ms

5h = 1000 ms

6h = 2000 ms

7h = Infinite (This can be exited using BOP_HLD_CLR bit)

4

BOP_DIS2

Reserved

RW

R

0h

BOP level 2 is

0b = Enabled

1b = Disabled

3-0

Reserved

8.9.45 BOP_CFG12 (page=0x00 address=0x29) [reset=02h]

Bit

Field

Type

Reset

Description

7-5

BOP_DT1[2:0]

RW

0h

BOP level 1 dwell time

0h= 0 us

1h = 100 us

2h = 250 us

3h = 500 us

4h = 1000 us

5h = 2000 us

6h = 4000 us

7h = 8000 us

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Bit

Field

Type

Reset

Description

4-1

BOP_ATK_ST1[3:0]

RW

1h

BOP level 1 attack step size

0h = -0.0625 dB

1h = -0.5 dB

2h = -0.8958 dB

3h = -1.2916 dB

4h = -1.6874 dB

5h = -2.0832 dB

6h = -2.479 dB

7h = -2.8748 dB

8h = -3.2706 dB

9h = -3.6664 dB

Ah =-4.0622 dB

Bh = -4.458 dB

Ch = -4.8538 dB

Dh = -5.2496 dB

Eh = -5.6454 dB

Fh = -6 dB

0

Reserved

R

0h

Reserved

8.9.46 BOP_CFG13 (page=0x00 address=0x2A) [reset=06h]

Bit

Field

Type

Reset

Description

7-5

BOP_ATK_RT1[2:0]

RW

0h

BOP level 1 attack rate.

0h= 2.5 us

1h = 5 us

2h = 10 us

3h = 25 us

4h = 50 us

5h = 100 us

6h = 250 us

7h = 500 us

4-1

BOP_RLS_ST1[3:0]

RW

3h

BOP level 1 release step size.

0h = 0.0625 dB

1h = 0.5 dB

2h = 0.8958 dB

3h = 1.2916 dB

4h = 1.6874 dB

5h = 2.0832 dB

6h = 2.479 dB

7h = 2.8748 dB

8h = 3.2706 dB

9h = 3.6664 dB

Ah =4.0622 dB

Bh = 4.458 dB

Ch = 4.8538 dB

Dh = 5.2496 dB

Eh = 5.6454 dB

Fh = 6 dB

0

Reserved

R

0h

Reserved

8.9.47 BOP_CFG14 (page=0x00 address=0x2B) [reset=38h]

Bit

Field

Type

Reset

Description

7-5

BOP_RLS_RT1[2:0]

RW

1h

BOP level 1 release rate time.

0h= 5 ms

1h = 10 ms

2h = 25 ms

3h = 50 ms

4h = 100 ms

5h = 250 ms

6h = 500 ms

7h = 1000 ms

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Bit

Field

BOP_MAX_ATTN1[4:0]

Type

Reset

Description

4-0

RW

18h

BOP level 1 maximum attenuation.

0h = 0 dB

1h = -1 dB

2h = -2 dB

..

Ch = -12 dB

..

1Eh = -30 dB

1Fh = -31 dB

8.9.48 BOP_CFG15 (page=0x00 address=0x2C) [reset=40h]

Bit Field

Type Reset Description

7-0 BOP_TH1[7:0]

RW

40h

BOP level 1 threshold

Setting

BOP Threshold (V) -

BOP_SRC=0 (VBAT1S Source) BOP_SRC=1 (PVDD Source)

00h

01h

2.7

2.75

2.8

.....

5.5

0

5.5

5.55

5.6

.....

8.3

8.35

.....

10

02h

.....

38h

39h

.....

0

5Ah

.....

0

.....

15.95

16

D1h

D2h

D3h-FFh

0

8.9.49 BOP_CFG17 (page=0x00 address=0x2D) [reset=20h]

Bit

Field

Type

Reset

Description

7-5

BOP_HT1[2:0]

RW

1h

BOP level 1 hold time.

0h = 0 ms

1h = 10 ms

2h = 100 ms

3h = 250 ms

4h = 500ms

5h = 1000 ms

6h = 2000 ms

7h = Infinite (This can be exited using BOP_HLD_CLR bit)

4

BOP_DIS1

Reserved

RW

R

0h

BOP level 1 is

0b = Enabled

1b = Disabled

3-0

Reserved

8.9.50 BOP_CFG18 (page=0x00 address=0x2E) [reset=02h]

Bit

Field

Type

Reset

Description

7-5

BOP_DT0[2:0]

RW

0h

BOP level 0 dwell time locked

0h= 0 us

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Bit

Field

Type

Reset

Description

4-1

BOP_ATK_ST0[3:0]

RW

1h

BOP level 0 attack step size.

3h = -1.2916 dB

4h = -1.6874 dB

5h = -2.0832 dB

6h = -2.479 dB

7h = -2.8748 dB

8h = -3.2706 dB

9h = -3.6664 dB

Ah =-4.0622 dB

Bh = -4.458 dB

Ch = -4.8538 dB

Dh = -5.2496 dB

Eh = -5.6454 dB

Fh = -6 dB

0

Reserved

R

0h

Reserved

8.9.51 BOP_CFG19 (page=0x00 address=0x2F) [reset=06h]

Bit

Field

Type

Reset

Description

7-5

BOP_ATK_RT0[2:0]

RW

0h

BOP level 0 attack rate.

0h= 2.5 us

1h = 5 us

2h = 10 us

3h = 25 us

4h = 50 us

5h = 100 us

4-1

BOP_RLS_ST0[3:0]

RW

3h

BOP level 0 release step size.

0h = 0.0625 dB

1h = 0.5 dB

2h = 0.8958 dB

3h = 1.2916 dB

4h = 1.6874 dB

5h = 2.0832 dB

6h = 2.479 dB

7h = 2.8748 dB

8h = 3.2706 dB

9h = 3.6664 dB

Ah =4.0622 dB

Bh = 4.458 dB

Ch = 4.8538 dB

0Dh = 5.2496 dB

Eh = 5.6454 dB

Fh = 6 dB

0

Reserved

R

0h

Reserved

8.9.52 BOP_CFG20 (page=0x00 address=0x30) [reset=3Eh]

Bit

Field

Type

Reset

Description

7-5

BOP_RLS_RT0[2:0]

RW

1h

BOP level 0 release rate time.

0h= 5 ms

1h = 10 ms

2h = 25 ms

3h = 50 ms

4h = 100 ms

5h = 250 ms

6h = 500 ms

7h = 1000 ms

62

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Bit

Field

BOP_MAX_ATTN0[4:0]

Type

Reset

Description

4-0

RW

1Eh

BOP level 0 maximum attenuation.

0h - Bh= Reserved

Ch = -12 dB

..

1Eh = -30 dB

1Fh = -31 dB

8.9.53 BOP_CFG21 (page=0x00 address=0x31) [reset=37h]

Bit Field

Type Reset Description

7-0 BOP_TH0[7:0]

RW

37h

BOP level 0 threshold

Setting

BOP Threshold (V) -

BOP_SRC=0 (VBAT1S Source) BOP_SRC=1 (PVDD Source)

00h

01h

2.7

2.75

2.8

.....

5.45

5.5

0

5.5

5.55

5.6

02h

.....

37h

8.3

38h

8.35

8.4

39h

.....

0

.....

D1h

D2h

D3h-FFh

0

15.95

16

0

8.9.54 BOP_CFG22 (page=0x00 address=0x32) [reset=20h]

Bit

Field

Type

Reset

Description

7-5

BOP_HT0[2:0]

RW

1h

BOP level 0 hold time.

0h - 1h = Reserved

2h = 100 ms

3h = 250 ms

4h = 500ms

5h = 1000 ms

6h = 2000 ms

7h = Infinite (This can be exited using BOP_HLD_CLR bit)

4

BOP_DIS0

RW

0h

BOP level 0 is

0b = Enabled

1b = Disabled

3-1

0

Reserved

RW

0h

Reserved

BOP_STAT_HLD

Hold BOP status for BOP_STAT_STATE, BOP_STAT_LLVL, and

BOP_STAT_PVDD. When register is set back to low the status

registers will be reset and updating will resume.

0b= hold update disabled, status register readback invalid

1b= hold update enabled, status register readback valid

8.9.55 BOP_CFG23 (page=0x00 address=0x33) [reset=FFh]

Bit

Field

Type

Reset

Description

7-0

BOP_STAT_PVDD[9:2]

R

FFh

Lowest PVDD measured since last read. Set BOP_STAT_HLD

high before reading.Till the time SAR does not get enabled in

device, this register wll readback default value on PVDD (0xff) if

device is in PWR_MODE2, else it will readback default value on

VBAT (0xff) when device is in PWR_MODE1. Note: default of

PVDD is 16V and of VBAT is 6V.

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8.9.56 BOP_CFG24 (page=0x00 address=0x34) [reset=E6h]

Bit

Field

Type

Reset

Description

7-6

BOP_STAT_PVDD[1:0]

R

3h

Lowest PVDD measured since last read. Set BOP_STAT_HLD

high before reading.Till the time SAR does not get enabled in

device, this register wll readback default value on PVDD (2'b11)

if device is in PWR_MODE2, else it will readback default value

on VBAT (2'b11) when device is in PWR_MODE1. Note: default

of PVDD is 16V and of VBAT is 6V.

5-3

BOP_STAT_LLVL[2:0]

R

4h

Lowest BOP level attacked since last read. Set

BOP_STAT_HLD high before reading.

0h = Attack level 0 was lowest attack level

1h = Attack level 1 was lowest attack level

2h = Attack level 2 was lowest attack level

3h = Attack level 3 was lowest attack level

4h = No BOP attacked since last read

2-1

0

LVS_FTH_LOW[1:0]

Reserved

RW

R

3h

0h

Threshold for LVS when CDS_MODE=2'b11

0h = -121.5 dBFS

1h=- -101.5 dBFS (default)

2h= -81.5 dBFS

3h = -71.5 dBFS

Reserved

8.9.57 NG_CFG0 (page=0x00 address=0x35) [reset=BDh]

Bit

Field

Type

Reset

Description

7-5

NG_HSYT[2:0]

RW

5h

Noise Gate Entry hysteris timer

0h = 260us

1h = 500us

2h = 800us

3h = 2 ms

4h = 10 ms

5h = 50 ms

6h = 100 ms

7h = 1000 ms

4-3

NG_LVL[1:0]

RW

3h

Noise-gate audio threshold level

0h = -90 dBFS

1h= -100 dBFS

2h = -110 dBFS

3h = -120 dBFS

2

NG_EN

RW

1h

Noise gate

0b = Disabled

1b = Enabled

1-0

Reserved

8.9.58 NG_CFG1 (page=0x00 address=0x36) [reset=ADh]

Bit

7-6

5

Field

Type

RW

Reset

2h

Description

Reserved

NG_DVR_EN

Reserved

RW

1h

Volume ramping on noise-gate control is

0b = Enabled

1b = Disabled

4

Reserved

R

0h

Reserved

3-0

LVS_HYS[3:0]

RW

Dh

PVDD to VBAT1S hysteresis time

0h - 9h= Reserved

Ah = 1 ms

Bh = 10 ms

Ch = 20 ms

Dh = 50 ms

Eh = 75 ms

Fh = 100 ms

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8.9.59 LVS_CFG0 (page=0x00 address=0x37) [reset=A8h]

Bit

Field

Type

Reset

Description

7

LVS_TMODE

RW

1h

Low-Voltage signaling detection threshold is

0b = Fixed

1b = Relative to VBAT1S voltage

6

5

Reserved

RW

0h

1h

8h

Reserved

4-0

LVS_FTH[4:0]

Threshold for LVS when CDS_MODE=2'b00

0h = -18.5 dBFS

1h=-18.25 dBFS (default)

2h=-18 dBFS

3h = -17.75 dBFS

4h=-17.5 dBFS

..

8h=-16.5 dBFS

..

1Eh=-11 dBFS

1Fh=-10.75 dBFS

8.9.60 DIN_PD (page=0x00 address=0x38) [reset=03h]

Bit

7

Field

Type

RW

Reset

0h

Description

Reserved

DIN_PD[4]

Reserved

6

RW

0h

Weak pull down for ICC

0b = Disabled

1b = Enabled

5

4

DIN_PD[3]

DIN_PD[2]

DIN_PD[1]

DIN_PD[0]

Reserved

RW

0h

3h

Weak pull down for SDOUT.

0b = Disabled

1b = Enabled

Weak pull down for SDIN.

0b = Disabled

1b = Enabled

3

Weak pull down for FSYNC.

0b = Disabled

1b = Enabled

2

Weak pull down for SBCLK.

0b = Disabled

1b = Enabled

1-0

Reserved

8.9.61 IO_DRV0 (page=0x00 address=0x39) [reset=FFh]

Bit

Field

Type

Reset

Description

7-6

SDA_IO_DS[1:0]

RW

3h

SDA Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

5-4

3-2

Reserved

RW

3h

Reserved

SDOUT_IO_DS[1:0]

SDOUT Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

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Bit

Field

Type

Reset

Description

1-0

ICC_IO_DS[1:0]

RW

3h

ICC Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

8.9.62 IO_DRV1 (page=0x00 address=0x3A) [reset=FFh]

Bit

Field

Type

Reset

Description

7-6

SBCLK_IO_DS[1:0]

RW

3h

SBCLK Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

5-4

3-2

Reserved

RW

3h

Reserved

IRQZ_IO_DS[1:0]

IRQZ Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

1-0

BYP_EN_IO_DS[1:0]

RW

3h

Bypass Enable Drive Strength

00b = 2 mA

01b = 4 mA

10b = 6 mA

11b = 8 mA

8.9.63 INT_MASK0 (page=0x00 address=0x3B) [reset=FCh]

Bit

Field

Type

Reset

Description

7

IM_BOPM

RW

1h

BOP mute interrupt.

0b = Don't Mask

1b = Mask

6

5

4

3

2

1

0

IM_BOPIH

IM_LIMMA

IM_PBIP

IM_LIMA

IM_TDMCE

IM_OC

RW

1h

0h

Bop infinite hold interrupt.

0b = Don't Mask

1b = Mask

Limiter max attenuation interrupt.

0b = Don't Mask

1b = Mask

PVDD below limiter inflection point interrupt.

0b = Don't Mask

1b = Mask

Limiter active interrupt.

0b = Don't Mask

1b = Mask

TDM clock error interrupt.

0b = Don't Mask

1b = Mask

Over current error interrupt.

0b = Don't Mask

1b = Mask

IM_OT

Over temp error interrupt.

0b = Don't Mask

1b = Mask

8.9.64 INT_MASK1 (page=0x00 address=0x3C) [reset=BEh]

Bit

Field

Type

Reset

Description

7-6

Reserved

RW

2h

Reserved

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Bit

Field

Type

Reset

Description

5

IM_LDC

RW

1h

Load Diagnostic Completion Mask

0b = Don't Mask

1b = Masked

4

IM_SOL[1:0]

RW

3h

Load Mask

00b = Don't Mask

01b = Mask Open Load Detection

10b = Mask Short Load Detection

01b = Mask Open/Short Load Detection

2

IM_BOPSD

*If BOP_SHDN=1 and brownout is

RW

1h

2h

BOP Started Mask

0b = Don't Mask

1b = Mask

detected DSP shuts down if not

masked

1-0

Reserved

8.9.65 INT_MASK4 (page=0x00 address=0x3D) [reset=DFh]

Bit

Field

Type

Reset

Description

7

IM_PLL_CLK

RW

1h

Internal PLL Derived Clock Error Mask

0b = Don't Mask

1b = Mask

6

5

Reserved

RW

1h

0h

Reserved

IM_VBAT1S_UVLO

VBAT1S Under Voltage

0b = Don't Mask

1b = Mask

4-0

Reserved

RW

1Fh

Reserved

8.9.66 INT_MASK2 (page=0x00 address=0x40) [reset=F6h]

Bit

Field

Type

Reset

Description

7

IM_TO105

RW

1h

Temperature over 105C interrupt.

0b = Don't Mask

1b = Mask

6

5

4

3

2

1

0

IM_TO115

RW

1h

0h

1h

0h

Temperature over 115C interrupt.

0b = Don't Mask

1b = Mask

IM_TO125

IM_TO135

IM_LDO_UV

IM_LDO_OV

IM_LDO_OL

IM_PUVLO

Temperature over 125C interrupt.

0b = Don't Mask

1b = Mask

Temperature over 135C interrupt.

0b = Don't Mask

1b = Mask

Internal VBAT1S LDO Under Voltage

0b = Don't Mask

1b = Mask

Internal VBAT1S LDO Over Voltage

0b = Don't Mask

1b = Mask

Internal VBAT1S LDO Over Load

0b = Don't Mask

1b = Mask

PVDD UVLO interrupt.

0b = Don't Mask

1b = Mask

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8.9.67 INT_MASK3 (page=0x00 address=0x41) [reset=00h]

Bit

Field

Type

Reset

Description

7

IM_TDTH2

RW

0h

Thermal Detection Threshold 2 mask

0b = Don't Mask

1b = Mask

6

5

4

3

2

1

0

IM_TDTH1

IM_PVBT

RW

0h

Thermal Detection Threshold 1 mask

0b = Don't Mask

1b = Mask

PVDD - VBAT1S below threshold mask

0b = Don't Mask

1b = Mask

IM_BOPA

BOP active interrupt. Mask

0b = Don't mask

1b = Mask

IM_BOPL3A

IM_BOPL2A

IM_BOPL1A

IM_BOPL0A

BOP level 3 detected interrupt mask

0b = Don't mask

1b = Mask

BOP level 2 detected interrupt mask

0b = Don't mask

1b = Mask

BOP level 1 detected interrupt mask

0b = Don't mask

1b = Mask

BOP level 0 detected interrupt mask

0b = Don't mask

1b = Mask

8.9.68 INT_LIVE0 (page=0x00 address=0x42) [reset=00h]

Bit

Field

Type

Reset

Description

7

IL_BOPM

R

0h

Interrupt due to bop mute.

0b = No interrupt

1b = Interrupt

6

5

4

3

2

1

0

IL_BOPIH

IL_LIMMA

IL_PBIP

IL_LIMA

IL_TDMCE

IL_OC

R

0h

Interrupt due to bop infinite hold.

0b = No interrupt

1b = Interrupt

Interrupt due to limiter max attenuation.

0b = No interrupt

1b = Interrupt

Interrupt due to PVDD below limiter inflection point.

0b = No interrupt

1b = Interrupt

Interrupt due to limiter active.

0b = No interrupt

1b = Interrupt

Interrupt due to TDM clock error.

0b = No interrupt

1b = Interrupt - Device in shutdown

Interrupt due to over current error.

0b = No interrupt

1b = Interrupt - Device in shutdown

IL_OT

Interrupt due to over temp error.

0b = No interrupt

1b = Interrupt - Device in shutdown

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8.9.69 INT_LIVE1 (page=0x00 address=0x43) [reset=00h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

IL_OTPCRC

Reserved

6

R

0h

Interrupt due to OTP CRC Error Flag

0b = No interrupt

1b = Interrupt - Device in shutdown

5-3

2

Reserved

IL_NGA

R

0h

Reserved

Noise Gate Acive flag

0b = Noise gate not detected

1b = Noise gate detected

1-0

Reserved

R

0h

Reserved

8.9.70 INT_LIVE1_0 (page=0x00 address=0x44) [reset=00h]

Bit

Field

Type

Reset

Description

7

IL_PLL_CLK

R

0h

Internal PLL Clock Error

0b = No interrupt

1b = Interrupt - Device in shutdown

6

5

Reserved

R

0h

Reserved

IL_VBAT1S_UVLO

VBAT1S Under Voltage

0b = No interrupt

1b = Interrupt - Device in shutdown

4-0

Reserved

R

0h

Reserved

8.9.71 INT_LIVE2 (page=0x00 address=0x47) [reset=00h]

Bit

Field

Type

Reset

Description

7

IL_TO105

R

0h

Temperature over 105C

0b = No Interrupt

1b = Interrupt

6

5

4

3

2

1

0

IL_TO115

R

0h

Temperature over 115C

0b = No Interrupt

1b = Interrupt

IL_TO125

Temperature over 125C

0b = No Interrupt

1b = Interrupt

IL_TO135

Temperature over 135C

0b = No Interrupt

1b = Interrupt

IL_LDO_UV

IL_LDO_OV

IL_LDO_OL

IL_PUVLO

VBAT1S Internal LDO Under Voltage

0b = No Interrupt

1b = Interrupt - Device in shutdown

VBAT1S Internal LDO Over Voltage

0b = No Interrupt

1b = Interrupt - Device in shutdown

VBAT1S Internal LDO Over Load

0b = No Interrupt

1b = Interrupt - Device in shutdown

PVDD UVLO

0b = No Interrupt

1b = Interrupt - Device in shutdown

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8.9.72 INT_LIVE3 (page=0x00 address=0x48) [reset=00h]

Bit

Field

Type

Reset

Description

7

IL_TDTH2

R

0h

Thermal Detection Threshold 2 active flag

0b = No interrupt

1b = Interrupt

6

5

4

3

2

1

0

IL_TDTH1

IL_PVBT

R

0h

Thermal Detection Threshold 1 active flag

0b = No interrupt

1b = Interrupt

PVDD -VBAT1S going below the threshold flag

0b = No interrupt

1b = Interrupt

IL_BOPA

BOP active flag

0b = No interrupt

1b = Interrupt

IL_BOPL3A

IL_BOPL2A

IL_BOPL1A

IL_BOPL0A

BOP level 3 detected flag

0b = No interrupt

1b = Interrupt

BOP level 2 detected flag

0b = No interrupt

1b = Interrupt

BOP level 1 detected flag

0b = No interrupt

1b = Interrupt

BOP level 0 detected flag

0b = No interrupt

1b = Interrupt

8.9.73 INT_LTCH0 (page=0x00 address=0x49) [reset=00h]

Bit

Field

Type

Reset

Description

7

IR_BOPM

R

0h

Interrupt due to bop mute.

0b = No interrupt

1b = Interrupt

6

5

4

3

2

IR_BOPIH

IR_LIMMA

IR_PBIP

R

0h

Interrupt due to BOP infinite hold.

0b = No interrupt

1b = Interrupt

Interrupt due to limiter max attenuation.

0b = No interrupt

1b = Interrupt

Interrupt due to PVDD below limiter inflection point.

0b = No interrupt

1b = Interrupt

IR_LIMA

Interrupt due to limiter active

0b = No interrupt

1b = Interrupt

IR_TDMCE

Interrupt due to TDM clock error. Type of clock error can be

seen from INT_LTCH8

0b = No interrupt

1b = Interrupt

1

0

IR_OC

IR_OT

R

0h

Interrupt due to over current error

0b = No interrupt

1b = Interrupt

Interrupt due to over temp error

0b = No interrupt

1b = Interrupt

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8.9.74 INT_LTCH1 (page=0x00 address=0x4A) [reset=00h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

IR_OTPCRC

Reserved

6

R

0h

Interrupt due to OTP CRC Error Flag.

0b = No interrupt

1b = Interrupt

5

IR_LDC

R

0h

Interrupt due to load diagnostic completion.

0b = Not completed

1b = Completed

4-3

IR_LDSL IR_LDO

Interrupt due to Load Diagnostic Mode Fault Status

00b = Normal Load

01b = Open Load Detected

10b = Short Load Detected

11b = Reserved

2-0

Reserved

R

0h

Reserved

8.9.75 INT_LTCH1_0 (page=0x00 address=0x4B) [reset=00h]

Bit

7

Field

Type

R

Reset

0h

Description

IR_PLL_CLK

Reserved

Internal PLL Clock Error

Reserved

6

R

0h

5

IR_VBAT1S_UVLO

Reserved

R

0h

VBAT1S Under Voltage

Reserved

4-0

R

0h

8.9.76 INT_LTCH2 (page=0x00 address=0x4F) [reset=00h]

Bit

Field

Type

Reset

Description

7

IR_TO105

R

0h

Temperature over 105C

0b = No Interrupt

1b = Interrupt

6

5

4

3

2

1

0

IR_TO115

R

0h

Temperature over 115C

0b = No Interrupt

1b = Interrupt

IR_TO125

IR_TO135

IR_LDO_UV

IR_LDO_OV

IR_LDO_OL

IR_PUVLO

Temperature over 125C

0b = No Interrupt

1b = Interrupt

Temperature over 135C

0b = No Interrupt

1b = Interrupt

Internal VBAT1S LDO Under Voltage

0b = No Interrupt

1b = Interrupt

Internal VBAT1S LDO Over Voltage

0b = No Interrupt

1b = Interrupt

Internal VBAT1S LDO Over Load

0b = No Interrupt

1b = Interrupt

PVDD UVLO

0b = No Interrupt

1b = Interrupt

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8.9.77 INT_LTCH3 (page=0x00 address=0x50) [reset=00h]

Bit

Field

Type

Reset

Description

7

IR_TDTH2

R

0h

Thermal Detection Threshold 2

0b = No interrupt

1b = Interrupt

6

5

4

3

2

1

0

IR_TDTH1

IR_PVBT

R

0h

Thermal Detection Threshold 1

0b = No interrupt

1b = Interrupt

Interrupt due to PVDD-VBAT1S going below the threshold

0b = No interrupt

1b = Interrupt

IR_BOPA

BOP active flag

0b = No interrupt

1b = Interrupt

IR_BOPL3A

IR_BOPL2A

IR_BOPL1A

IR_BOPL0A

BOP level 3 detected sticky

0b = No interrupt

1b = Interrupt

BOP level 2 detected sticky

0b = No interrupt

1b = Interrupt

BOP level 1 detected sticky

0b = No interrupt

1b = Interrupt

BOP level 0 detected sticky

0b = No interrupt

1b = Interrupt

8.9.78 INT_LTCH4 (page=0x00 address=0x51) [reset=00h]

Bit

7-3

2

Field

Type

R

Reset

0h

Description

Reserved

IR_TDMCEIR

Reserved

R

0h

TDM clock error type = Invalid SBCLK ratio or FS rate

0b = Not detected during TDM clock error

1b = Detected during TDM clock error

1

0

IR_TDMCEFC

IR_TDMCERC

R

0h

TDM clock error type = FS changed on the fly

0b = Detected during TDM clock error

1b = Not detected during TDM clock error

TDM clock error type = SBCLK FS ratio changed on the fly

0b = Not detected during TDM clock error

1b = Detected during TDM clock error

8.9.79 VBAT_MSB (page=0x00 address=0x52) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

VBAT1S_CNV[11:4]

R

0h

Returns SAR ADC VBAT1S conversio:

VBAT1S=[hex2dec(VBAT1S_CNV<11:0>)]/128

8.9.80 VBAT_LSB (page=0x00 address=0x53) [reset=00h]

Bit

Field

Type

Reset

Description

7-4

VBAT1S_CNV[3:0]

R

0h

Returns SAR ADC VBAT1S conversio:

VBAT1S=[hex2dec(VBAT1S_CNV<11:0>)]/128

3-0

Reserved

R

0h

Reserved

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8.9.81 PVDD_MSB (page=0x00 address=0x54) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

PVDD_CNV[11:4]

R

0h

Returns SAR ADC PVDD conversio:

PVDD=[hex2dec(PVDD_CNV<11:0>)]/128

8.9.82 PVDD_LSB (page=0x00 address=0x55) [reset=00h]

Bit

Field

Type

Reset

Description

7-4

PVDD_CNV[3:0]

R

0h

Returns SAR ADC PVDD conversio:

PVDD=[hex2dec(PVDD_CNV<11:0>)]/128

3-0

Reserved

R

0h

Reserved

8.9.83 TEMP (page=0x00 address=0x56) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

TMP_CNV[7:0]

R

0h

Returns SAR ADC temp sensor conversion:

TEMP(⁰C)=[hex2dec(TEMP_CNV(7:0)]-93

8.9.84 INT_CLK_CFG (page=0x00 address=0x5C) [reset=19h]

Bit

Field

Type

Reset

Description

7

*CLK_ERR_PWR_EN

RW

0h

Clock based device power up/power down feature enable

0b = Enable clk halt detection after clock error detection

1b = Disable clock halt detection, after clock error is detected

6

*DIS_CLK_HALT

RW

0h

3h

Clock halt timer enable

0b = Feature disabled

1b = Feature enabled

5-3

CLK_HALT_TIMER[2:0]

Clock halt timer values

0b = 820 us

1b = 3.27ms

2b = 26.21ms

3b =52.42ms

4b = 104.85ms

5b = 209.71ms

6b = 419.43ms

7b = 838.86 ms

2

IRQZ_CLR

RW

0h

1h

Clear INT_LATCH registers

0b = Don't clear

1b = Clear (self clearing bit)

1-0

IRQZ_PIN_CFG[1:0]

IRQZ interrupt configuration. IRQZ will assert

00b = On any unmasked live interrupts

01b = On any unmasked latched interrupts

10b = For 2-4ms one time on any unmasked live interrupt event

11b = For 2-4ms every 4ms on any unmasked latched interrupts

* Certain limitations applied. Contact TI if need to use this bit.

8.9.85 MISC_CFG3 (page=0x00 address=0x5D) [reset=80h]

Bit

Field

Type

Reset

Description

7

IRQZ_POL

RW

1h

IRQZ pin polarity for interrupt.

0b = Active high

1b = Active low

6-4

Reserved

RW

0h

Reserved

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Bit

Field

Type

Reset

Description

3-2

YB_BOP_CTRL

RW

0h

This register selects on which BOP level, Y-bridge and BYP_EN

pad need to shift to PVDD when PVDD_SELECTION = 0.

0h = Shift to PVDD when BOP LVL0 is detected

1h = Shift to PVDD when BOP LVL1 or LVL0 is detected

2h = Shift to PVDD when BOP LVL2 or LVL1 or LVL0 is detected

3h = Shift to PVDD when BOP LVL3 or LVL2 or LVL1 or LVL0 is

detected

1

0

Reserved

RW

R

0h

Reserved

8.9.86 CLOCK_CFG (page=0x00 address=0x60) [reset=0Dh]

Bit

7-6

5-2

Field

Type

R

Reset

0h

Description

Reserved

SAMP_RATIO[3:0]

RW

3h

SBCLK to FS ratio when AUTO_RATE=1 (disabled)

00h = 16

01h = 24

02h = 32

03h = 48

04h = 64

05h = 96

06h = 128

07h = 192

08h = 256

09h = 384

0Ah = 512

0Bh = 125

0Ch = 250

0Dh = 500

0Eh-0Fh = Reserved

1-0

Reserved

RW

1h

Reserved

8.9.87 IDLE_IND (page=0x00 address=0x63) [reset=48]

Bit

Field

Type

Reset

Description

7

IDLE_IND

RW

0h

Idle channel Class D output current optimization

0b = Used for inductors 15uH and higher

1b = Used for 5uH inductors

6-0

Reserved

RW

48h

Reserved

8.9.88 MISC_CFG4 (page=0x00 address=0x65) [reset=08]

Bit

7-4

3

Field

Type

RW

Reset

0h

Description

Reserved

LDG_CLK

Reserved

RW

1h

Clock source for load diagnostic

0b = External TDM

1b = Internal oscillator

2-1

0

LDG_IVSNS_AVG

Reserved

0h

Duration on averaging on V/I data

0h = 5 ms

1h = 10 ms

2h = 50 ms

3h =100 ms

RW

Reserved

8.9.89 TG_CFG0 (page=0x00 address=0x67) [reset=00h]

Bit

Field

Type

Reset

Description

7-2

Reserved

R

0h

Reserved

74

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Bit

Field

ID_CH_HYST_TIME[1:0]

Type

Reset

Description

1-0

RW

0h

Idle channel hysteresis timer.

00h = 50 ms

01h = 100 ms

02h = 200 ms

03h = 1000 ms

8.9.90 CLK_CFG (page=0x00 address=0x68) [reset=7Fh]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

FS_RATIO[3:0]

Reserved

6-3

R

Fh

Detected SBCLK to FSYNC ratio.

00h = 16

01h = 24

02h = 32

03h = 48

04h = 64

05h = 96

06h = 128

07h = 192

08h = 256

09h = 384

0Ah = 512

0Bh = 125

0Ch = 250

0Dh = 500

0Eh = Reserved

0F = Invalid ratio

2-0

FS_RATE[2:0]

R

7h

Detected sample rate of TDM bus.

000b = Reserved

001b = Reserved

010b = Reserved

011b = Reserved

100b = 44.1/48 kHz

101b = 88.2/96 kHz

110b = Reserved

111b = Error condition

8.9.91 LV_EN_CFG (page=0x00 address=0x6A) [reset=12h]

Bit

Field

Type

Reset

Description

7-6

CDS_DLY[1:0]

RW

0h

Delay (1/f_s) of the Class-D Y-bridge switching with respect to the

input signal

00b = 8.1(NG enabled,48ksps), 6.1(NG disabled,48ksps)

00b = 12.6(NG enabled,96ksps), 9.6(NG disabled,96ksps)

01b = 7.1(NG enabled,48ksps), 5.1(NG disabled,48ksps),

01b = 10.6(NG enabled,96ksps), 7.6(NG disabled,96ksps)

10b = 6.1(NG enabled,48ksps), 4.1(NG disabled,48ksps)

10b = 8.5(NG enabled,96ksps), 5.6(NG disabled,96ksps)

11b = 5.6(NG enabled,48ksps), 3.6(NG disabled,48ksps

11b = 7.6(NG enabled,96ksps), 4.6(NG disabled,96ksps)

5-4

LVS_DLY[1:0]

RW

1h

Delay (1/f_s) of the BYP_EN signaling with respect to the input

signal

00b = 7.8(NG enabled,48ksps), 5.8(NG disabled,48ksps)

00b = 12.1(NG enabled,96ksps), 9.1(NG disabled,96ksps)

01b = 6.8(NG enabled,48ksps), 4.8(NG disabled,48ksps),

01b = 10.1(NG enabled,96ksps), 7.1(NG disabled,96ksps)

10b = 5.8(NG enabled,48ksps), 3.8(NG disabled,48ksps)

10b = 8.1(NG enabled,96ksps), 5.1(NG disabled,96ksps)

11b = 5.1(NG enabled,48ksps), 3.1(NG disabled,48ksps

11b = 6.6(NG enabled,96ksps), 3.6(NG disabled,96ksps)

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Bit

Field

Type

Reset

Description

3-0

LVS_RTH[3:0]

RW

2h

Relative threshold for Low-Voltage Signaling. Headroom is from

current VBAT1S voltage.

00h = 0.5 V

01h = 0.6 V

02h = 0.7 V

...

0Eh = 1.9 V

0Fh = 2 V

8.9.92 NG_CFG2 (page=0x00 address=0x6B) [reset=01h]

Bit

7

Field

Type

R

Reset

0h

Description

Reserved

6

CONV_VBAT_PVDD_MODE

RW

0h

Convert the VBAT1S in PVDD Only Mode

0b=No VBAT1S conversion

1b=VBAT1S conversion will show the value of internal LDO

supplying VBAT1S pin

5-3

2

Reserved

R

0h

Reserved

NGFR_EN

RW

Noise-gate fine resolution register mode

0b = Disabled

1b = Enabled

1-0

Reserved

RW

1h

Reserved

8.9.93 NG_CFG3 (page=0x00 address=0x6C) [reset=00h]

Programmable bits for Noise Gate fine resolution threshold to a level -NGLVL(dBFS)

Bit

Field

Type

Reset

Description

7-0

NGFR_LVL[23:16]

RW

0h

dec2hex{round{ 10^(-NGLVL)/20)]*2^23}

8.9.94 NG_CFG4 (page=0x00 address=0x6D) [reset=00h]

Programmable bits for Noise Gate fine resolution threshold to a level -NGLVL(dBFS)

Bit

Field

Type

Reset

Description

7-0

NGFR_LVL[15:8]

RW

0h

dec2hex{round{ 10^(-NGLVL)/20)]*2^23}

8.9.95 NG_CFG5 (page=0x00 address=0x6E) [reset=1Ah]

Programmable bits for Noise Gate fine resolution threshold to a level -NGLVL(dBFS)

Bit

Field

Type

Reset

Description

7-0

NGFR_LVL[7:0]

RW

1Ah

dec2hex{round{ 10^(-NGLVL)/20)]*2^23}

8.9.96 NG_CFG6 (page=0x00 address=0x6F) [reset=00h]

Programmable bits for Noise Gate fine resolution threshold to a level -NGLVL(dBFS)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-8. Noise Gate 6 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

NGFR_HYST[18:11]

RW

0h

dec2bin[(NGHYS*f_s),19]

f_s=sampling rate in kHz

8.9.97 NG_CFG7 (page=0x00 address=0x70) [reset=96h]

Programmable bits for Noise Gate fine resolution threshold to a level -NGLVL(dBFS)

76

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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-9. Noise Gate 7 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

NGFR_HYST[10:3]

RW

96h

dec2bin[(NGHYS*f_s),19]

f_s=sampling rate in kHz

Example

NGFR_HYST[15:0] is the result of 19 bits processing with last three bits thrown away (000)

For 50 ms and 48ksps formula is: dec2bin[50*48,19]=dec2bin[2400,19]=0000000100101100000

Result: 01h in register 0x6F and 2Ch in register 0x70.

8.9.98 PVDD_UVLO (page=0x00 address=0x71) [reset=00h]

Bit

7-6

5-0

Field

Type

RW

Reset

00h

Description

Reserved

PVDD_UVLO_TH[5:0]

RW

00h

PVDD UVLO Thresholds.

00h = 2.2 V

01h = 2.419 V

02h = 2.638 V

...........

3Fh= 16 V

8.9.99 DAC_MOD_RST (page=0x00 address=0x76) [reset=02h]

Bit

7-2

1

Field

Type

RW

Reset

0h

Description

Reserved

DIS_DMOD_RST

RW

1h

Reset of DAC Modulator when DSP is OFF:

0= Enable reset of DAC Modulator when DSP is OFF

1= Disable reset of DAC Modulator when DSP is OFF

0

Reserved

R

0h

Reserved

Reset value can change when read back .

8.9.100 REV_ID (page=0x00 address=0x7D) [reset=30h]

Bit

7-4

3-0

Field

Type

R

Reset

3h

Description

REV_ID[3:0]

PG_ID[3:0]

Returns the revision ID.

Returns the PG ID.

R

0h

8.9.101 I2C_CKSUM (page=0x00 address=0x7E) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

I2C_CKSUM[7:0]

RW

0h

Returns I2C checksum. Writing to this register will reset the

checksum to the written value. This register is updated on writes

to other registers on all books and pages.

8.9.102 BOOK (page=0x00 address=0x7F) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

BOOK[7:0]

RW

0h

Sets the device book.

00h = Book 0

01h = Book 1

...

FFh = Book 255

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8.9.103 LSR (page=0x01 address=0x19) [reset=40h]

Bit

7

Field

Type

R

Reset

0b

Description

Reserved

EN_LLSR

6

RW

1b

Modulation

0b = LSR

1b = Linear LSR

Reserved

5-0

Reserved

R

0h

8.9.104 SDOUT_HIZ_1 (page=0x01 address=0x3D) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ1[7:0]

RW

0h

Force '0' output control for slots 7 down to 0. This register to be

programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.105 SDOUT_HIZ_2 (page=0x01 address=0x3E) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ2[7:0]

RW

0h

Force '0' output control for slots 15 down to 8. This register to be

programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.106 SDOUT_HIZ_3 (page=0x01 address=0x3F) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ3[7:0]

RW

0h

Force '0' output control for slots 23 down to 16. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.107 SDOUT_HIZ_4 (page=0x01 address=0x40) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ4[7:0]

RW

0h

Force '0' output control for slots 31 down to 24. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.108 SDOUT_HIZ_5 (page=0x01 address=0x41) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ5[7:0]

RW

0h

Force '0' output control for slots 39 down to 32. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.109 SDOUT_HIZ_6 (page=0x01 address=0x42) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ6[7:0]

RW

0h

Force '0' output control for slots 47 down to 40. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.110 SDOUT_HIZ_7 (page=0x01 address=0x43) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ7[7:0]

RW

0h

Force '0' output control for slots 55 down to 48. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

78

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8.9.111 SDOUT_HIZ_8 (page=0x01 address=0x44) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

SDOUT_HIZ8[7:0]

RW

0h

Force '0' output control for slots 63 down to 56. This register to

be programmed as zero in case the slot is not valid as per valid

FSRATIO

8.9.112 SDOUT_HIZ_9 (page=0x01 address=0x45) [reset=00h]

Bit

Field

Type

Reset

Description

7

SDOUT_FORCE_0_CNT_EN

RW

0h

Control over sending "0" to un-used slots

0b = All unused slots will have 'Hi-Z' transmitted

1b = Unused slots can transmit '0' base on programming in

registers 0x44 to 0x3D

6-0

Reserved

RW

0h

Reserved

8.9.113 TG_EN (page=0x01 address=0x47) [reset=ABh]

Bit

Field

Type

Reset

Description

7-2

Reserved

R

6'b101010 Reserved

Reset value can change when read back .

1

0

TG_TH2

TG_TH1

RW

1'b1

Thermal threshold 2

1=Enabled

0=Disabled

1'b1

Thermal threshold 1

1=Enabled

0=Disabled

8.9.114 DG_DC_VAL1 (page=0x04 address=0x08) [reset=40h]

Programmable Diagnostic bits for a DC_VAL (dBFS) desired level.

Bit

Field

Type

Reset

Description

7-0

DG_DC_VAL [31:24]

RW

40h

dec2hex{256*round[10^(DC_VAL/20)*2^23]}

8.9.115 DG_DC_VAL2 (page=0x04 address=0x09) [reset=26h]

Programmable Diagnostic bits for a DC_VAL (dBFS) desired level.

Bit

Field

Type

Reset

Description

7-0

DG_DC_VAL [23:16]

RW

26h

dec2hex{256*round[10^(DC_VAL/20)*2^23]}

8.9.116 DG_DC_VAL3 (page=0x04 address=0x0A) [reset=40h]

Bit

Field

Type

Reset

Description

7-0

DG_DC_VAL [15:8]

RW

40h

dec2hex{256*round[10^(DC_VAL/20)*2^23]}

8.9.117 DC_DG_VAL4 (page=0x04 address=0x0B) [reset=00h]

Programmable Diagnostic bits for a DC_VAL (dBFS) desired level.

Bit

Field

Type

Reset

Description

7-0

DG_DC_VAL [7:0]

RW

00h

dec2hex{256*round[10^(DC_VAL/20)*2^23]}

8.9.118 LIM_TH_MAX1 (page=0x04 address=0x0C) [reset=68h]

Programmable bits to set limiter maximum threshold to a LIM_TH_MAX (V).

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Bit

Field

Type

Reset

Description

7-0

LIM_TH_MAX[31:24]

RW

68h

dec2hex{256*round [LIM_TH_MAX*2^19]}

8.9.119 LIM_TH_MAX2 (page=0x04 address=0x0D) [reset=00h]

Programmable bits to set limiter maximum threshold to a LIM_TH_MAX (V).

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MAX[23:16]

RW

00h

dec2hex{256*round [LIM_TH_MAX*2^19]}

8.9.120 LIM_TH_MAX3 (page=0x04 address=0x0E) [reset=00h]

Programmable bits to set limiter maximum threshold to a LIM_TH_MAX (V).

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MAX[15:8]

RW

00h

dec2hex{256*round [LIM_TH_MAX*2^19]}

8.9.121 LIM_TH_MAX4 (page=0x04 address=0x0F) [reset=00h]

Programmable bits to set limiter maximum threshold to a LIM_TH_MAX (V).

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MAX[7:0]

RW

00h

dec2hex{256*round [LIM_TH_MAX*2^19]}

8.9.122 LIM_TH_MIN1 (page=0x04 address=0x10) [reset=28h]

Sets limiter minimum threshold to a LIM_TH_MIN (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MIN[31:24]

RW

28h

dec2hex{256*round [LIM_TH_MIN*2^19]}

8.9.123 LIM_TH_MIN2 (page=0x04 address=0x11) [reset=00h]

Sets limiter minimum threshold to a LIM_TH_MIN (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MIN[23:16]

RW

00h

dec2hex{256*round [LIM_TH_MIN*2^19]}

8.9.124 LIM_TH_MIN3 (page=0x04 address=0x12) [reset=00h]

Sets limiter minimum threshold to a LIM_TH_MIN (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MIN[15:8]

RW

00h

dec2hex{256*round [LIM_TH_MIN*2^19]}

8.9.125 LIM_TH_MIN4 (page=0x04 address=0x13) [reset=00h]

Sets limiter minimum threshold to a LIM_TH_MIN (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_TH_MIN[7:0]

RW

0h

dec2hex{256*round [LIM_TH_MIN*2^19]}

8.9.126 LIM_INF_PT1 (page=0x04 address=0x14) [reset=56h]

Sets limiter inflection point to a value of LIM_INF_PT (V).

Bit

Field

Type

Reset

Description

7-0

LIM_INF_PT[31:24]

RW

56h

dec2hex{256*round [LIM_INF_PT*2^19]}

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8.9.127 LIM_INF_PT2 (page=0x04 address=0x15) [reset=66h]

Sets limiter inflection point to a value of LIM_INF_PT (V).

Bit

Field

Type

Reset

Description

dec2hex{256*round [LIM_INF_PT*2^19]}

7-0

LIM_INF_PT[23:16]

RW

66h

8.9.128 LIM_INF_PT3 (page=0x04 address=0x16) [reset=66h]

Sets limiter inflection point to a value of LIM_INF_PT (V).

Bit

Field

Type

Reset

Description

7-0

LIM_INF_PT[15:8]

RW

66h

dec2hex{256*round [LIM_INF_PT*2^19]}

8.9.129 LIM_INF_PT4 (page=0x04 address=0x17) [reset=00h]

Sets limiter inflection point to a value of LIM_INF_PT (V).

Bit

Field

Type

Reset

Description

7-0

LIM_INF_PT[7:0]

RW

0h

dec2hex{256*round [LIM_INF_PT*2^19]}

8.9.130 LIM_SLOPE1 (page=0x04 address=0x18) [reset=10h]

Sets limiter slope to a LIM_SLOPE (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_SLOPE[31:24]

RW

10h

dec2hex{256*round [LIM_SLOPE*2^20]}

8.9.131 LIM_SLOPE2 (page=0x04 address=0x19) [reset=00h]

Sets limiter slope to a LIM_SLOPE (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_SLOPE[23:16]

RW

00h

dec2hex{256*round [LIM_SLOPE*2^20]}

8.9.132 LIM_SLOPE3 (page=0x04 address=0x1A) [reset=00h]

Sets limiter slope to a LIM_SLOPE (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_SLOPE[15:8]

RW

00h

dec2hex{256*round [LIM_SLOPE*2^20]}

8.9.133 LIM_SLOPE4 (page=0x04 address=0x1B) [reset=00h]

Sets limiter slope to a LIM_SLOPE (V) value.

Bit

Field

Type

Reset

Description

7-0

LIM_SLOPE[7:0]

RW

00h

dec2hex{256*round [LIM_SLOPE*2^20]}

8.9.134 TF_HLD1 (page=0x04 address=0x1C) [reset=00h]

Thermal fold-back hold count set to a TF_HLD (s) value.

Bit

Field

Type

Reset

Description

7-0

TF_ HOLD_CNT[31:24]

RW

00h

dec2hex [256*round (TF_HLD*9600)]

8.9.135 TF_HLD2 (page=0x04 address=0x1D) [reset=03h]

Thermal fold-back hold count set to a TF_HLD (s) value.

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Bit

Field

Type

Reset

Description

7-0

TF_HOLD_CNT23:16]

RW

03h

dec2hex [256*round (TF_HLD*9600)]

8.9.136 TF_HLD3 (page=0x04 address=0x1E) [reset=E8h]

Thermal fold-back hold count set to a TF_HLD (s) value.

Bit

Field

Type

Reset

Description

7-0

TF_HOLD_CNT[15:8]

RW

E8h

dec2hex [256*round (TF_HLD*9600)]

8.9.137 TF_HLD4 (page=0x04 address=0x1F) [reset=00h]

Thermal fold-back hold count set to a TF_HLD (s) value.

Bit

Field

Type

Reset

Description

7-0

TF_HOLD_CNT[7:0]

RW

00h

dec2hex [256*round (TF_HLD*9600)]

8.9.138 TF_RLS1 (page=0x04 address=0x20) [reset=40h]

Thermal fold-back limiter release rate set to a value TF_RLS (dB/100us).

Bit

Field

Type

Reset

Description

7-0

TF_REL_RATE[31:24]

RW

40h

dec2hex{256*round[10^(TF_RLS/20)*2^22]}

8.9.139 TF_RLS2 (page=0x04 address=0x21) [reset=12h]

Thermal fold-back limiter release rate set to a value TF_RLS (dB/100us).

Bit

Field

Type

Reset

Description

7-0

TF_REL_RATE[23:16]

RW

12h

dec2hex{256*round[10^(TF_RLS/20)*2^22]}

8.9.140 TF_RLS3 (page=0x04 address=0x22) [reset=E0h]

Thermal fold-back limiter release rate set to a value TF_RLS (dB/100us).

Bit

Field

Type

Reset

Description

7-0

TF_REL_RATE[15:8]

RW

E0h

dec2hex{256*round[10^(TF_RLS/20)*2^22]}

8.9.141 TF_RLS4 (page=0x04 address=0x23) [reset=00h]

Thermal fold-back limiter release rate set to a value TF_RLS (dB/100us).

Bit

Field

Type

Reset

Description

7-0

TF_REL_RATE[7:0]

RW

0h

dec2hex{256*round[10^(TF_RLS/20)*2^22]}

8.9.142 TF_SLOPE1 (page=0x04 address=0x24) [reset=04h]

Thermal fold-back limiter attenuation slope set to a value TF_SLOPE (V/⁰C).

Input level is assumed 0dB and gain is 21dB. Extra 3dB (from 24dB) is due to rms to peak conversion.

Bit

Field

Type

Reset

Description

7-0

TF_LIMS[31:24]

RW

04h

dec2hex {256*round[TF_SLOPE/10^(24/20)]*2^23}

8.9.143 TF_SLOPE2 (page=0x04 address=0x25) [reset=08h]

Thermal fold-back limiter attenuation slope set to a value TF_SLOPE (V/⁰C).

Input level is assumed 0dB and gain is 21dB. Extra 3dB (from 24dB) is due to rms to peak conversion.

82

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Bit

Field

TF_LIMS[23:16]

Type

Reset

Description

dec2hex {256*round[TF_SLOPE/10^(24/20)]*2^23}

7-0

RW

08h

8.9.144 TF_SLOPE3 (page=0x04 address=0x26) [reset=89h]

Thermal fold-back limiter attenuation slope set to a value TF_SLOPE (V/⁰C).

Input level is assumed 0dB and gain is 21dB. Extra 3dB (from 24dB) is due to rms to peak conversion.

Bit

Field

Type

Reset

Description

7-0

TF_LIMS[15:8]

RW

89h

dec2hex {256*round[TF_SLOPE/10^(24/20)]*2^23}

8.9.145 TF_SLOPE4 (page=0x04 address=0x27) [reset=00h]

Thermal fold-back limiter attenuation slope set to a value TF_SLOPE (V/⁰C).

Input level is assumed 0dB and gain is 21dB. Extra 3dB (from 24dB) is due to rms to peak conversion.

Bit

Field

Type

Reset

Description

7-0

TF_LIMS[7:0]

RW

0h

dec2hex {256*round[TF_SLOPE/10^(24/20)]*2^23}

8.9.146 TF_TEMP_TH1 (page=0x04 address=0x28) [reset=39h]

Thermal fold-back temperature threshold set to TF_TEMP (⁰C) value.

Bit

Field

Type

Reset

Description

7-0

TF_TEMP_TH[31:24]

RW

39h

dec2hex{256*round[TF_TEMP*(2^15)]}

8.9.147 TF_TEMP_TH2 (page=0x04 address=0x29) [reset=80h]

Thermal fold-back temperature threshold set to TF_TEMP (⁰C) value.

Bit

Field

Type

Reset

Description

7-0

TF_TEMP_TH[23:16]

RW

80h

dec2hex{256*round[TF_TEMP*(2^15)]}

8.9.148 TF_TEMP_TH3 (page=0x04 address=0x2A) [reset=00h]

Thermal fold-back temperature threshold set to TF_TEMP (⁰C) value.

Bit

Field

Type

Reset

Description

7-0

TF_TEMP_TH[15:8]

RW

00h

dec2hex{256*round[TF_TEMP*(2^15)]}

8.9.149 TF_TEMP_TH4 (page=0x04 address=0x2B) [reset=00h]

Thermal fold-back temperature threshold set to TF_TEMP (⁰C) value.

Bit

Field

Type

Reset

Description

7-0

TF_TEMP_TH[7:0]

RW

00h

dec2hex{256*round[TF_TEMP*(2^15)]}

8.9.150 TF_MAX_ATTN1 (page=0x04 address=0x2C) [reset=2Dh]

Thermal fold-back maximum gain reduction set to TF_ATTN (dB) value.

Bit

Field

Type

Reset

Description

7-0

TF_MAX_ATTN[31:24]

RW

2Dh

dec2hex{256*round[10^(-TF_ATTN/20)*2^ 23]}

8.9.151 TF_MAX_ATTN2 (page=0x04 address=0x2D) [reset=6Ah]

Thermal fold-back maximum gain reduction set to TF_ATTN (dB) value.

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Bit

Field

Type

Reset

Description

7-0

TF_MAX_ATTN(23:16]

RW

6Ah

dec2hex{256*round[10^(-TF_ATTN/20)*2^ 23]}

8.9.152 TF_MAX_ATTN3 (page=0x04 address=0x2E) [reset=86h]

Thermal fold-back maximum gain reduction set to TF_ATTN (dB) value.

Bit

Field

Type

Reset

Description

7-0

TF_MAX_ATTN[15:8]

RW

86h

dec2hex{256*round[10^(-TF_ATTN/20)*2^ 23]}

8.9.153 TF_MAX_ATTN4 (page=0x04 address=0x2F) [reset=00h]

Thermal fold-back maximum gain reduction set to TF_ATTN (dB) value.

Bit

Field

Type

Reset

Description

7-0

TF_MAX_ATTN[7:0]

RW

0h

dec2hex{256*round[10^(-TF_ATTN/20)*2^ 23]}

8.9.154 LD_CFG0 (page=0x04 address=0x40) [reset=02h]

Load diagnostic resistance upper threshold value set to LDG_RES_UT (Ω).

Bit

Field

Type

Reset

Description

dec2hex {256*round[LDG_RES_UT*(3.75/14)*2^14]}

7-0

LDG_RES_UT[31:24]

RW

02h

8.9.155 LD_CFG1 (page=0x04 address=0x41) [reset=ADh]

Load diagnostic resistance upper threshold value set to LDG_RES_UT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_UT[23:16]

RW

ADh

dec2hex {256*round[LDG_RES_UT*(3.75/14)*2^14]}

8.9.156 LD_CFG2 (page=0x04 address=0x42) [reset=B7h]

Load diagnostic resistance upper threshold value set to LDG_RES_UT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_UT[15:8]

RW

B7h

dec2hex {256*round[LDG_RES_UT*(3.75/14)*2^14]}

8.9.157 LD_CFG3 (page=0x04 address=0x43) [reset=00h]

Load diagnostic resistance upper threshold value set to LDG_RES_UT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_UT[7:0]

RW

0h

dec2hex {256*round[LDG_RES_UT*(3.75/14)*2^14]}

8.9.158 LD_CFG4 (page=0x04 address=0x44) [reset=00h]

Load diagnostics resistance lower threshold value set to LDG_RES_LT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_LT[31:24]

RW

0h

dec2hex {256*round[LDG_RES_LT*(3.75/14)*2^14]}

8.9.159 LD_CFG5 (page=0x04 address=0x45) [reset=1Bh]

Load diagnostics resistance lower threshold value set to LDG_RES_LT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_LT[23:16]

RW

1Bh

dec2hex {256*round[LDG_RES_LT*(3.75/14)*2^14]}

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8.9.160 LD_CFG6 (page=0x04 address=0x46) [reset=6Eh]

Load diagnostics resistance lower threshold value set to LDG_RES_LT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_LT[15:8]

RW

6Eh

dec2hex {256*round[LDG_RES_LT*(3.75/14)*2^14]}

8.9.161 LD_CFG7 (page=0x04 address=0x47) [reset=00h]

Load diagnostics resistance lower threshold value set to LDG_RES_LT (Ω).

Bit

Field

Type

Reset

Description

7-0

LDG_RES_LT[7:0]

RW

0h

dec2hex {256*round[LDG_RES_LT*(3.75/14)*2^14]}

8.9.162 CLD_EFF_1 (page=0x04 address=0x48) [reset=6Ch]

Class D efficiency for LVS relative threshold expressed as a fraction (EFF). Default is 0.85.

Bit

Field

Type

Reset

Description

7-0

ClassD Efficiency [31:24]

RW

6Ch

dec2hex[256*round(EFF*2^23)]

8.9.163 CLD_EFF_2 (page=0x04 address=0x49) [reset=CCh]

Class D efficiency for LVS relative threshold expressed as a fraction (EFF). Default is 0.85.

Bit

Field

Type

Reset

Description

7-0

ClassD Efficiency [23:16]

RW

CCh

dec2hex[256*round(EFF*2^23)]

8.9.164 CLD_EFF_3 (page=0x04 address=0x4A) [reset=CDh]

Class D efficiency for LVS relative threshold expressed as a fraction (EFF). Default is 0.85.

Bit

Field

Type

Reset

Description

7-0

ClassD Efficiency [15:8]

RW

CDh

dec2hex[256*round(EFF*2^23)]

8.9.165 CLD_EFF_4 (page=0x04 address=0x4B) [reset=00h]

Class D efficiency for LVS relative threshold expressed as a fraction (EFF). Default is 0.85.

Bit

Field

Type

Reset

Description

7-0

ClassD Efficiency [7:0]

RW

00h

dec2hex[256*round(EFF*2^23)]

8.9.166 LDG_RES1 (page=0x04 address=0x4C) [reset=00h]

Diagnostic Mode load resistance measured value in Ω. Read value is 0xUUVVXXYY and the last byte to be

dropped.

Bit

Field

Type

Reset

Description

7-0

LDG_RES_VAL[32:24]

R

0h

(14/3.75)*{[hex2dec(0xUUVVXX)]/2^14)

8.9.167 LDG_RES2 (page=0x04 address=0x4D) [reset=00h]

Diagnostic Mode load resistance measured value in Ω. Read value is 0xUUVVXXYY and the last byte to be

dropped.

Bit

Field

Type

Reset

Description

7-0

LDG_RES_VAL[23:16]

R

0h

(14/3.75)*{[hex2dec(0xUUVVXX)]/2^14)

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8.9.168 LDG_RES3 (page=0x04 address=0x4E) [reset=00h]

Diagnostic Mode load resistance measured value in Ω. Read value is 0xUUVVXXYY and the last byte to be

dropped.

Bit

Field

Type

Reset

Description

7-0

LDG_RES_VAL[15:8]

R

0h

(14/3.75)*{[hex2dec(0xUUVVXX)]/2^14)

8.9.169 LDG_RES4 (page=0x04 address=0x4F) [reset=00h]

Bit

Field

Type

Reset

Description

7-0

LDG_RES_VAL[7:0]

R

0h

Drop this byte.

8.10 SDOUT Equations

The following equations will alow to convert data read on SDOUT.

PVDD (V)= 16* [Hex2Dec(SDOUTdata)]/2^PVDDSlotLength

By default, PVDDSlotLength=8.

VBAT (V)= 8* [Hex2Dec(SDOUTdata)]/2^VBATSlotLength

By default,VBATSlotLength=8.

TEMP (⁰C)= [Hex2Dec(SDOUTdata)] -93

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TAS2764 is a digital input Class-D audio power amplifier with integrated current and voltage sense. I²S

audio data is supplied by host processor. TAS2764 sends to the host processor current and voltage data in I²S

format. I²C bus is used for configuration and control.

9.2 Typical Application

图9-1. Typical Application - Digital Audio Input

表9-1. Recommended External Components

COMPONENT

DESCRIPTION

SPECIFICATION

MIN

TYP

MAX

UNIT

Type

X7R

10

VBAT1S Decoupling Capacitor - VBAT1S

External Supply (PWR_MODE1)

Capacitance, 20% Tolerance

Rated Voltage

µF

V

6

C1

Type

X7R

0.68

6

VBAT1S Decoupling Capacitor - VBAT1S

Internally Generated (PWR_MODE2)

Capacitance, 20% Tolerance

Rated Voltage

1

1.5

µF

V

Type

X7R

C2

C3

C4

VBAT1S Decoupling Capacitor

PVDD Decoupling Capacitor

Capacitance, 20% Tolerance

Rated Voltage

100

nF

V

6

Type

X7R

10

Capacitance, 20% Tolerance

Rated Voltage

µF

V

20

Type

X7R

Capacitance, 20% Tolerance

Rated Voltage

100

nF

V

20

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表9-1. Recommended External Components (continued)

COMPONENT

DESCRIPTION

SPECIFICATION

MIN

TYP

MAX

Type

X7R

4.7

6

C5

AVDD Decoupling Capacitor

Capacitance, 20% Tolerance

Rated Voltage

µF

V

Type

X7R

0.68

6

C6

C7

DREG Decoupling Capacitor

IOVDD Decoupling Capacitor

High-side Boost Capacitors

Capacitance, 20% Tolerance

Rated Voltage

1

1.5

µF

V

Type

X7R

1

Capacitance, 20% Tolerance

Rated Voltage

µF

V

6

Type

X7R

68

C8, C9

Capacitance, 20% Tolerance

Rated Voltage

100

120

150

nF

V

6

EMI Filter Inductors (optional). These are

not recommended as it degrades THD+N

performance. The TAS2764 device is a

filter-less Class-D and does not require

these bead inductors.

Impedance at 100MHz

DC Resistance

Ω

0.095

Lf1, Lf2

DC Current

Capacitance

5

A

EMI Filter Capacitors (optional, must use

Lf2, Lf3 if Cf1, Cf2 used)

Cf1, Cf2

R_F1, R_F2

1

5

nF

Feedback resistor to be connected if L_f, C_f

filters are used

1

kΩ

R_P1, R_P2

Pull up resistors to IOVDD

For minimum driving capability of

2mA

10

kΩ

9.3 Design Requirements

For this design example, use the parameters shown in 节9.2.

表9-2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Digital Audio, I²S

Mono

Audio Input

Current and Voltage Data Stream

Mono or Stereo Configuration

Max Output Power at 1% THD+N,

over temperature and frequency

range, R_L= 4 Ω

≥10 W

9.4 Detailed Design Procedure

9.4.1 Mono/Stereo Configuration

In this application, the device is assumed to be operating in mono mode. See 节 8.3.1 for information on

changing the I²C address of the TAS2764 to support stereo operation. Mono or stereo configuration does not

impact the device performance.

9.4.2 EMI Passive Devices

The TAS2764 supports spread spectrum to minimize EMI. It is allowed to include passive devices on the Class-

D outputs. The passive devices Lf1, Lf2, Cf1 and Cf2 from 图 9-1 have recommended specifications provided in

表 9-1. The passive devices Lf1, Lf2, Cf1 and Cf2 have to be properly selected to maintain the stability of the

output stage. See 节8.4.5 for details.

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9.5 Application Curves

0

-65

-70

-75

-80

-85

-90

-95

-100

VBAT = 2.95 V, PVDD = 6.5 V

VBAT = 4.2 V, PVDD = 8.4 V

VBAT = 3.8 V, PVDD = 12 V

VBAT = 3.8 V, PVDD = 16 V

-10

-20

-30

-40

-50

-60

-70

-80

-90

VBAT = 4.2 V, PVDD = 8.4 V

VBAT = 3.8 V, PVDD = 12 V

VBAT = 3.8 V, PVDD = 16 V

20

100

1000

Frequency (Hz)

10K 20K

0.001

0.01

0.1

P_OUT(W)

1

10 25

PWR_MODE2

f=1kHz

PWR_MODE2

f=1kHz

RL=4Ω

图9-3. THDN vs Frequency

图9-2. THDN vs Pout

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10 Initialization Set Up

10.1 Recommended Configuration at Power Up

The following configuration is recommended after power up.

w 70 00 00 # Page-0

w 70 7F 00 # Book-0

w 70 01 01 # SW reset

d 1 # 1mS Delay

w 70 0E 44 # TDM TX voltage sense transmit enable with slot 4,

w 70 0F 40 # TDM TX current sense transmit enable with slot 0

w 70 00 00 # Page-0

w 70 7F 00 # Book-0

w 70 00 06 # Switch to Page-6

#250C # Write quadratic without additional TCO and ratio of 1.7

w 70 14 00 13 52 00 E4 0C AA 00 12 A0 D8 00

w 70 00 01 # Page-01

w 70 47 AA # Threshold-1 disabled

w 70 19 40 # Linear LSR mode

w 70 37 AA # Linear LSR deglitch disabled

w 70 33 80 # SAR reaction on noise gate

w 70 00 00 # Page-0

w 70 76 00 # DAC mod reset for reduced POP

w 70 02 00 # Power up audio playback with I,V enabled

10.2 Initial Device Configuration - 4 Channel Power Up (Default Mode - PWR_MODE1)

The following I²C sequence is an example of initializing four TAS2764 devices. This sequence contains a 1 ms

delay required after a software or hardware reset as illustrated in 节11.

###### Configure Channel 1

w 70 60 11 # sbclk to fs ratio = 64

w 70 0D 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge

w 70 0E 42 # TDM TX voltage sense transmit enable with slot 2,

w 70 0F 40 # TDM TX current sense transmit enable with slot 0

w 70 03 14 # 21 dB gain

w 70 02 00 # power up audio playback with I,V enabled

###### Configure Channel 2

w 72 60 11 # sbclk to fs ratio = 64

w 72 0D 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge

w 72 0E 46 # TDM TX voltage sense transmit enable with slot 6,

w 72 0F 44 # TDM TX current sense transmit enable with slot 4

w 72 03 14 # 21 dB gain

w 72 02 00 # power up audio playback with I,V enabled

###### Configure Channel 3

w 74 60 11 # sbclk to fs ratio = 64

w 74 0D 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge

w 74 0E 4A # TDM TX voltage sense transmit enable with slot 10,

w 74 0F 48 # TDM TX current sense transmit enable with slot 8

w 74 03 14 # 21 dB gain

w 74 02 00 # power up audio playback with I,V enabled

###### Configure Channel 4

w 76 60 11 # sbclk to fs ratio = 64

w 76 0D 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge

w 76 0E 4E # TDM TX voltage sense transmit enable with slot 14,

w 76 0F 4C # TDM TX current sense transmit enable with slot 12

w 76 03 14 # 21 dB gain

w 76 02 00 # power up audio playback with I,V enabled

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10.3 Initial Device Configuration - 44.1 kHz

The following I²C sequence is an example of initializing a TAS2764 device into 44.1 kHz sampling rate. This

sequence contains a 1 ms delay required after a software or hardware reset as illustrated in 节11.

###### Configure Channel 1

w 70 60 21 # sbclk to fs ratio = 256 / 8 TDM Slots

w 70 08 39 # 44.1KHz, Auto TDM off, Frame start High to Low

w 70 09 03 # Offset = 1, Sync on BCLK falling edge

w 70 0a 0a # TDM slot by address, Word = 24 bit, Frame = 32 bit

w 70 0c 20 # Right Ch = TDM slot 2, Left Ch = TDM slot 0

w 70 0d 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge

w 70 0e 42 # TDM TX voltage sense transmit enable with slot 2,

w 70 0f 40 # TDM TX current sense transmit enable with slot 0

w 70 03 14 # 21 dB gain

w 70 02 00 # power up audio playback with I,V enabled

10.4 Sample Rate Change - 48 kHz to 44.1kHz

The following I2C sequence is an example of changing the sampling rate from 48 kHz to 44.1 kHz .

w 70 07 28 #Set DVC Ramp Rate to 0.5 dB / 8 samples

w 70 02 01 #Mute

d 1

w 70 02 02 #Software shutdown

w 70 08 39 #44.1KHz, Auto TDM off, Frame start High to Low

### change source sample rate now

w 70 02 01 #Take device out of low-power shutdown

d 1

w 70 02 00 #Un-mute

10.5 Idle Channel Hysterisis

Recommended to set hysterisis to 1s to ensure gain release operation gets maximum time.

w 70 00 00 #Page 0x00

w 70 67 03 #IC histeresis at 1s

10.6 DSP Loopback

The following I²C sequence will enable the DSP loopback for echo reference.

#####DSP Echo Reference Loopback

w 70 00 00 #Page -0

w 70 7F 00

w 70 16 C0 #Audio TX slot programmed to 0

w 70 0E 00 #Disable Vsense

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11 Power Supply and I²C Recommendations

During power up and power down PVDD voltage must be greater than (VBAT1S-0.7V)

Once all supplies are stable the SDZ pin can be set high to initialize the part. After a hardware or software reset

additional commands to the device should be delayed for at least 1 mS to allow the OTP memory to load.

If the TDM clocks are sent to TAS2764 after the part is programmed through I²C to go to Active Mode the TDM

clock interrupts will be triggered.

When VBAT1S is internally generated (see below 节 11.1) it is recommended that the device enters Software

Shutdown mode before entering Hardware Shutdown mode. This ensures that VBAT1S pin is discharged using

the internal 5 kOhms pull down resistor (not present in HW shutdown mode).

图11-1. Power Supply Sequence for Power-Up and Power-Down

11.1 Power Supply Modes

The TAS2764 can operate with both VBAT1S and PVDD as supplies or with only PVDD as supply. The table

below shows different power supply modes of operation depending on the customer need.

表11-1. Device Configuration and Power Supply Modes

Output

Supply Power Mode

PWR_MODE1

Switching

Mode

Supply Condition

Device Configurations

Use Case and Device Functionality

VBAT1S is used to deliver output power

based on level and headroom configured.

When audio signal crosses a programmed

threshold Class-D output is switched over

PVDD.

BOP source is VBAT1S. PVDD UVLO is

disabled. SAR conversion done for VBAT1S,

PVDD and temperature.

Y Bridge High

Power on

VBAT1S_MODE=0

BOP_SRC=0

CDS_MODE[1:0]=00

PVDD>VBAT1S

VBAT1S

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表11-1. Device Configuration and Power Supply Modes (continued)

Output

Switching

Mode

Supply Power Mode

Supply Condition

Device Configurations

Use Case and Device Functionality

PVDD is the only supply. VBAT1S is

delivered by an internal LDO and used to

supply at signals close to idle channel levels.

When audio signal levels crosses -100dBFS

(default), Class_D output switches to PVDD.

BOP source is PVDD. PVDD UVLO is

enabled. SAR conversion done for PVDD

and temperature.

Y Bridge Low

Power on

VBAT1S

VBAT1S_MODE=1

BOP_SRC=1

CDS_MODE[1:0]=11

PWR_MODE2

PVDD>VBAT1S+2.5V

VBAT1S is used to deliver output power

based on level and headroom configured.

When audio signal crosses a programmed

threshold Class-D output is switched over

PVDD.

BOP source is PVDD. PVDD UVLO is

enabled. SAR conversion done for PVDD

and temperature.

Y Bridge High

Power on

VBAT1S_MODE=0

BOP_SRC=1

CDS_MODE[1:0]=00

PWR_MODE3

PWR_MODE4

PVDD>VBAT1S

VBAT1S

Class-D power supplied by PVDD branch of

Y bridge. VBAT1S is delivered by an

internal LDO.

BOP source is PVDD. PVDD UVLO is

enabled. SAR conversion done for PVDD

and temperature.

VBAT1S_MODE=1

BOP_SRC=1

CDS_MODE[1:0]=10

PVDD

PVDD>VBAT1S+2.5V

For PWR_MODE2 and PWR_MODE4, by default, the internal ADC samples only the PVDD pin in order to meet

the stringent requirement on brownout latency. If the monitoring of VBAT1S pin is needed the register bit

CONV_VBAT_PVDD_MODE should be set to high. The additional monitoring of VBAT1S will come at the cost of

losing brownout latency.

If VBAT1S is generated by internal LDO, customer needs to ensure that PVDD supply level is at least 2.5V

above the VBAT1S voltage generated internally. To enable voltage protection the UVLO of PVDD supply should

be set above 7.3V by using register bits PVDD_UVLO[5:0]. This will ensure that, with an internally generated

VBAT1S of 4.8V, PVDD supply is at least 2.5V higher than VBAT1S.

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12 Layout

12.1 Layout Guidelines

All supply rails should be bypassed by low-ESR ceramic capacitors as shown in 图9-1 and described in 表9-1.

Place the decoupling capacitors as close as possible to the respective power supply pins. Do not place vias

between the decoupling capacitors and the device pin. Connect the vias to the ground or power planes on the

far side of the capacitor.

Ground plane in the adjacent layer is recommended. It is required to maintain a single solid ground plane

underneath the IC and its decoupling caps. Solid ground plane is the best option, providing continuous

(uninterrupted) and low-impedance path for return currents back to the source. Fill the device side layer of the

system board with ground copper and connect it to main ground plane using lots of vias. Each ground pin (GND,

PGND) should directly shorted to the ground plane in the same layer as device as well as to the main solid

ground plane in the adjacent layer through vias.

Specific layout design recommendations should be followed for this device:

• Do not use vias for traces that carry high current: PVDD, VBAT1S, PGND, GND and the speaker OUT_P,

OUT_N.

• Connect VSNS_P and VSNS_N as close as possible to the speaker.

• VSNS_P and VSNS_N should be connected between the EMI ferrite filter and the speaker if EMI ferrites are

used at the outputs.

• VSNS_P and VSNS_N routing should be separated and shielded from switching signals (interface signals,

speaker outputs, bootstrap pins).

• Place bootstrap capacitors as close as possible to the BST pins.

12.2 Layout Example

The figure below describes the placement of critical components as presented in 图9-1.

图12-1. Component Placement

For the component placement from 图12-1 an example of layout of top layer is presented below.

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图12-2. Layout Design - Top Copper Layer

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13 Device and Documentation Support

13.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

YBH0030-C01

DSBGA - 0.4 mm max height

SCALE 7.000

DIE SIZE BALL GRID ARRAY

2.147

2.107

A

B

BALL A1

CORNER

2.502

2.462

C

0.4 MAX

SEATING PLANE

0.05 C

BALL TYP

1.6 TYP

0.16

0.10

(0.1939)

0.0696

(0.3331)

(0.2313)

F

E

BALL ARRAY

0.0097

2

D

TYP

PKG

C

B

A

0.4

TYP

(0.2507)

2

3

4

5

1

0.225

0.185

30X

0.015

PKG

C A B

0.4 TYP

4224895/B 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

YBH0030-C01

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

(0.0696)

30X ( 0.2)

1

4

5

2

A

(0.4) TYP

B

C

SYMM

BALL ARRAY

PKG

D

E

(0.0097)

F

SYMM

BALL ARRAY

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 30X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

( 0.2)

METAL

(

0.2)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4224895/B 04/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN

YBH0030-C01

DSBGA - 0.4 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(0.0696)

4

30X ( 0.21)

(R0.05) TYP

2

3

5

1

A

(0.4) TYP

B

C

SYMM

BALL ARRAY

PKG

(0.0097)

D

E

METAL

TYP

F

SYMM

BALL ARRAY

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE: 30X

4224895/B 04/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release.

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS2764
厂家：	TEXAS INSTRUMENTS
描述：	具有 I/V 感应功能、用于扬声器保护和多级电源的 13W 数字输入 2.3V 至 16V 智能放大器放大器
文件：	总103页 (文件大小：2772K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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