TAS2770 [TI]
具有 I/V 感应扬声器保护的 20W 数字输入 4.5V 至 18V 智能放大器;
| 型号： | TAS2770 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I/V 感应扬声器保护的 20W 数字输入 4.5V 至 18V 智能放大器 放大器 |
| 文件： | 总102页 (文件大小：3654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS2770
ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TAS2770 具有扬声器I/V 感应20W 数字输入单声道D 类音频放大器
欠压保护器跟踪峰值电压，并自动将增益限制为可用电
压。该硬件实现的功能降低了放大器对系统电源的需
1 特性
求，从而防止音频中断和系统关断。
• 高性能单声道D 类放大器
– 1% THD+N 时的功率为20W（4Ω，16V）
– 1% THD+N 时的功率为15.4W（4Ω，12.6V）
• 1W 时的THD+N 为0.03%（4Ω，VBAT =
12.6V）
TAS2770 可用作常规放大器或与基于主机的扬声器保
护算法配合使用。集成的扬声器电压和电流感应功能可
通过 I2S 返回路径将扬声器状况实时反馈到保护算
法。
• 8.4V Vbat 时的A 加权空闲通道噪声为32µVrms
• 20Hz 至20kHz 内具有90dB PSRR、200mVPP 纹
波
最多有8 个器件可以通过任意一个I2S/TDM + I2C 共享
一个公共总线。
• 1W（4Ω，VBAT = 12.6V）下的效率为82.5%
• < 1µA HW 关断VBAT 电流
• 42mW / 63mW 空闲损耗(8.4V / 12.6V)
• 扬声器电压和电流感测
TAS2770 器件采用 26 引脚、0.4mm 间距 QFN 封
装，实现紧凑的PCB 空间。
器件信息
封装尺寸（标称值）
器件型号
TAS2770
封装
• 使用I/V 扬声器感测进行实时诊断
QFN
4mm × 3.5mm
2mm × 2.52mm
4mm x 3.5mm
2mm × 2.52mm
2mm × 2.52mm
– 过流
– 短路（电源短路、接地短路和终端至终端短路）
– 过热
TAS2770
DSBGA
QFN
SNP002770
SNP002770
TAS5770LC0
• VBAT 跟踪峰值电压限制器提供欠压保护
• 44.1kHz 至192kHz 采样速率
• 灵活的用户界面
DSBGA
DSBGA
– I2S/TDM：8 通道（32 位/96kHz）
– I2C：8 个可选择地址
• 无MCLK 运行
• 低噗声和嘀哒声
• 电源
1.8 V
1.8 V
4.5-16 V
VREG
SDZ
SDA
SAR
ADC
BST_P
SCL
OUT_P
– VBAT：4.5V 至16V
– AVDD：1.8V
• 扩频频谱低EMI 模式
• 热保护和过流保护
IRQZ
MODE
fb
fb
Class-D
Amplifier
TMP SNS
DAC
OUT_N
BST_N
SDIN
SDOUT
FSYNC
SBCLK
System
Interface
+
Limiter
with
VSNS_P
VSNS_N
IV-Sense
IV-SNS
ADCs
2 应用
Pop/Click
Over Current
Over Temp
Protection
VREG
• 笔记本电脑
• 蓝牙扬声器
• 家庭自动化
• 智能扬声器/物联网
Copyright © 2016, Texas Instruments Incorporated
功能方框图
3 说明
TAS2770 是一款经优化后可高效驱动小型扬声器的单
声道数字输入 D 类音频放大器。凭借出色的输出功
率、保护功能和封装，TAS2770 成为智能扬声器、蓝
牙扬声器、家庭自动化设备、笔记本电脑和平板电脑的
理想选择。
该 D 类放大器能够在 16V 电压下向 4Ω 的负载提供
20W 的连续功率，在 16V 电压下向 8Ω 的负载提供
15W 的连续功率，两种情况下的 THD 都为 1%。4.5V
至 16V 的宽输入电压范围和高输出功率使该放大器具
有出色的通用性，能够与电池电源或线路供电系统配合
使用。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEM6
TAS2770
www.ti.com.cn
ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
Table of Contents
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................24
8.5 Register Maps...........................................................50
9 Application and Implementation..................................77
9.1 Application Information............................................. 77
9.2 Typical Application.................................................... 77
9.3 Initialization Set Up................................................... 81
10 Power Supply Recommendations..............................84
11 Layout...........................................................................85
11.1 Layout Guidelines................................................... 85
11.2 Layout Example...................................................... 85
12 Device and Documentation Support..........................90
12.1 Receiving Notification of Documentation Updates..90
12.2 Community Resources............................................90
12.3 Trademarks.............................................................90
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 I2C Timing Requirements..........................................12
6.7 TDM Port Timing Requirements................................13
6.8 PDM Port Timing Requirements............................... 13
6.9 Typical Characteristics..............................................14
7 Parameter Measurement Information..........................20
8 Detailed Description......................................................21
8.1 Overview...................................................................21
Information.................................................................... 91
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (August 2022) to Revision E (April 2023)
Page
• Updated 表8-70 .............................................................................................................................................. 45
• Updated 图8-64 .............................................................................................................................................. 74
Changes from Revision C (October 2020) to Revision D (August 2022)
Page
• 向数据表添加了 TAS5770LC0 器件....................................................................................................................1
Changes from Revision B (October 2018) to Revision C (October 2020)
Page
• 更改了首页中的信息........................................................................................................................................... 1
• Changed VBAT Max in 节6.3 from 16 V to 18 V................................................................................................ 5
• Changed REV_ID............................................................................................................................................. 75
Changes from Revision A (December 2017) to Revision B (October 2018)
Page
• Changed From: Efficiency (%) To: VDD PSRR (dB) in 图6-15 ....................................................................... 14
• Changed From: Efficiency (%) To: VBAT PSRR (dB) in 图6-16 ......................................................................14
Changes from Revision * (October 2017) to Revision A (December 2017)
Page
• 将 TAS2770 发布为“量产数据”.......................................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEM6
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
5 Pin Configuration and Functions
MODE
PDMD
PDMCK
GND
BST_N
PGND
OUT_P
BST_P
Preliminary
GND
VSNS_P
FSYNC
Drawing is Preliminary.
图5-1. QFN Package 26-Pin RJQ Top View
1
2
3
4
5
VSNS_P
BST_N
OUT_P
PGND
OUT_N
A
B
C
D
E
F
VSNS_N
BST_P
OUT_P
PGND
VBAT
IRQZ
GND
SCL
OUT_N
VBAT
AVDD
GND
SDZ
DREG
IOVDD
FSYNC
SDIN
MODE
AREG
PDMD
SDOUT
SBCLK
GND
SDA
PDMCK
Not to scale
图5-2. WCSP 30-Ball Top View
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English Data Sheet: SLASEM6
TAS2770
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
DSBGA
QFN
NAME
Gate drive voltage regulator output. Decouple with cap to GND. Do not connect
to external load.
D5
24
AREG
O
C1
A2
B2
9
1
4
AVDD
BST_N
BST_P
P
I
Analog power input. Connect to 1.8V supply and decouple to GND with cap.
Class-D negative bootstrap. Connect a cap between BST_N and OUT_N.
Class-D positive bootstrap. Connect a cap between BST_P and OUT_P.
I
Digital core voltage regulator output. Bypass to GND with a cap. Do not
connect to external load.
D1
E2
7
DREG
FSYNC
GND
O
I
14
TDM Frame Sync.
C2, E3,
E4
10, 15,
16
P
Analog GND. Connect to PCB GND Plane.
Digital IO Supply. Connect to the same 1.8 V supply that powers AVDD and
decouple with a cap to GND.
D2
D4
8
IOVDD
IRQZ
P
Open drain, actve low interrupt pin. Pull up to IOVDD with resistor if optional
internal pull up is not used.
20
O
Mode detect pin. This pin can detect a short to IOVDD or GND, a 470 Ω
connection to IOVDD or GND, a 2.2 kΩconnection to IOVDD or GND, a 10
kΩconnection to IOVDD or GND and a 47 kΩconnection to IOVDD. Minimize
capacitive loading on this pin and do not connect to any other load.
D3
19
MODE
I
A5, B5
A3, B3
F5
26
3
OUT_N
OUT_P
PDMCK
PDMD
PGND
SBCLK
SCL
O
O
IO
I
Class-D negative output.
Class-D positive output.
17
18
2
PDM Clock.
E5
PDM Digital Input.
A4, B4
F1
P
I
Class-D GND. Connect to PCB GND Plane.
TDM Serial Bit Clock in TDM/I2C Mode.
I2C Clock Pin. Pull up to IOVDD with a resistor.
I2C Data Pin. Pull up to IOVDD with a resistor.
TDM Serial Data Input.
13
23
22
11
12
21
25
F4
I
F3
SDA
IO
I
F2
SDIN
E1
SDOUT
SDZ
IO
I
TDM Serial Data Output in TDM/I2C Mode.
C3
Active low hardware shutdown.
C4, C5
VBAT
P
Class-D power supply input. Connect to VBAT supply and decouple with a cap.
Voltage Sense negative input. Connect to Class-D negative output after Ferrite
bead filter.
B1
A1
6
5
VSNS_N
VSNS_P
I
I
Voltage Sense positive input. Connect to Class-D positive output after Ferrite
bead filter.
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English Data Sheet: SLASEM6
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
2
UNIT
AVDD
V
V
V
V
–0.3
–0.3
–0.3
–0.3
Supply Voltage
Input voltage(2)
IOVDD
2
VBAT
18
2.3
Digital IOs referenced to IOVDD supply
Operating free-air temperature, TA ; Device is functional and reliable, some performance
characteristics may be degraded.
85
°C
–40
Performance free-air temperature, TP ; All performance characteristics are met.
Operating junction temperature, TJ
70
°C
°C
°C
–20
–40
–65
150
150
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Procedures. Exposure to absolute-maximum-rated conditions for extended periods can affect device
reliability.
(2) All digital inputs and IOs are failsafe.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
1.65
4.5
NOM
1.8
MAX
1.95
1.95
16
UNIT
AVDD
IOVDD
VBAT
VIH
Supply voltage
V
V
V
V
V
Supply voltage
1.8
Supply voltage
High-level digital input voltage
Low-level digital input voltage
Minimum speaker impedance
Minimum speaker inductance
IOVDD
0
VIL
RSPK
LSPK
3.2
10
Ω
µH
6.4 Thermal Information
TAS2770
THERMAL METRIC(1)
QFN (RJQ)
26 PINS
57.0
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.3
8.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
8.7
ψJB
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English Data Sheet: SLASEM6
TAS2770
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TAS2770
QFN (RJQ)
26 PINS
NA
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT and OUTPUT
High-level digital input logic voltage All digital pins except SDA and SCL;
0.65 ×
IOVDD
VIH
V
V
threshold
IOVDD = 1.8 V.
Low-level digital input logic voltage
threshold
All digital pins except SDA and SCL;
IOVDD = 1.8 V.
0.35 ×
IOVDD
VIL
High-level digital input logic voltage
threshold
0.7 x
IOVDD
VIH(I2C)
VIL(I2C)
VOH
SDA and SCL; IOVDD = 1.8 V.
SDA and SCL; IOVDD = 1.8 V.
V
Low-level digital input logic voltage
threshold
0.3 x
IOVDD
V
All digital pins except SDA, SCL and
IRQZ; IOVDD = 1.8 V; IOH = 2 mA.
IOVDD –
High-level digital output voltage
Low-level digital output voltage
Low-level digital output voltage
V
0.45 V
All digital pins except SDA, SCL and
IRQZ; IOVDD = 1.8 V; IOL = –2 mA.
VOL
0.45
V
SDA and SCL; IOVDD = 1.8 V;
IOL(I2C) = –2 mA.
0.2 x
IOVDD
VOL(I2C)
VOL(IRQZ)
IIH
V
Low-level digital output voltage for
IRQZ open drain Output
IRQZ; IOVDD = 1.8 V; IOL(IRQZ) = –2
mA.
0.45
5
V
Input logic-high leakage for digital
inputs
All digital pins; Input = IOVDD.
0.1
µA
–5
–5
Input logic-low leakage for digital
inputs
IIL
All digital pins; Input = GND.
All digital pins
0.1
5
5
µA
pF
CIN
RPD
Input capacitance for digital inputs
Pull down resistance for digital
input/IO pins when asserted on
SDOUT, SDIN, FSYNC, SBCLK,
PDMD, PDMCK
18
kΩ
TDM SERIAL AUDIO PORT
Single Speed, I2S/TDM Operation
48
96
PCM Sample Rates & FSYNC Input Double Speed, I2S/TDM Operation
kHz
Frequency
Quadruple Speed, I2S/TDM
Operation
192
SBCLK Input Frequency
I2S/TDM Operation
2.54
27.1
MHz
RMS Jitter below 40 kHz that can be
tolerated without performance
degradation
1
SBCLK Maximum Input Jitter
ns
RMS Jitter above 40 kHz that can be
tolerated without performance
degradation
10
SBCLK Cycles per FSYNC in I2S
and TDM Modes
Values: 64, 96, 128, 192, 256, 384
and 512
64
512
Cycles
MHz
PDM AUDIO PORT
Single Rate PDM
Double Rate PDM
3.072
6.144
PDM clock input frequency
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLASEM6
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Single Speed PCM. Values: 64X and
128X.
64
128
PDM sensor clock rate to PCM
sample rate oversampling ratios
Double Speed PCM. Values: 32X
and 64X.
32
16
64
32
Quadruple Speed PCM. Values: 16X
and 32X.
PROTECTION CIRCUITRY
Thermal shutdown temperature
Thermal shutdown retry
140
1.5
°C
s
VBAT undervoltage lockout threshold
(UVLO)
UVLO is asserted
OVLO is asserted
4
V
V
VBAT overvoltage lockout threshold
(OVLO)
18
AMPLIFIER PERFORMANCE
RL = 8 Ω+ 33 µH, THD+N = 0.1 %,
fin = 1 kHz, VBAT = 8.4 V
3.7
6.6
RL = 4 Ω+ 33 µH, THD+N = 0.1 %,
fin = 1 kHz, VBAT = 8.4 V
Maximum Continuous Output Power
0.1% THD+N
RL = 8 Ω+ 33 µH, THD+N = 0.1 %,
fin = 1 kHz, VBAT = 12.6 V
8.5
RL = 4 Ω+ 33 µH, THD+N = 0.1 %,
fin = 1 kHz, VBAT = 12.6 V
14.2
4
POUT
W
RL = 8 Ω+ 33 µH, THD+N = 1 %, fin
= 1 kHz, VBAT = 8.4 V
RL = 4 Ω+ 33 µH, THD+N = 1 %, fin
= 1 kHz, VBAT = 8.4 V
7.1
Maximum Continuous Output Power
1% THD+N
RL = 8 Ω+ 33 µH, THD+N = 1 %, fin
= 1 kHz, VBAT = 12.6 V
9.1
RL = 4 Ω+ 33 µH, THD+N = 1 %, fin
= 1 kHz, VBAT = 12.6 V
15.4
89 %
84 %
87.5 %
82.7 %
92 %
87 %
92 %
86 %
RL = 8 Ω+ 33 µH, fin = 1 kHz, VBAT
= 8.4 V
RL = 4 Ω+ 33 µH, fin = 1 kHz, VBAT
= 8.4 V
System efficiency at POUT = 1 W
RL = 8 Ω+ 33 µH, fin = 1 kHz, VBAT
= 12.6 V
RL = 4 Ω+ 33 µH, fin = 1 kHz, VBAT
= 12.6 V
RL = 8 Ω+ 33 µH, POUT = 3. 7W, fin
= 1 kHz, VBAT = 8.4 V
RL = 4 Ω+ 33 µH, POUT = 6.6 W, fin
= 1 kHz, VBAT = 8.4 V
System efficiency at 0.1% THD+N
power level
RL = 8 Ω+ 33 µH, POUT = 8.5 W, fin
= 1 kHz, VBAT = 12.6 V
RL = 4 Ω+ 33 µH, POUT = 14.2 W, fin
= 1 kHz, VBAT = 12.6 V
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English Data Sheet: SLASEM6
TAS2770
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POUT = 1 W, RL = 8 Ω+ 33 µH, fin
20 Hz - 20 kHz, VBAT = 8.4 V
=
=
=
=
0.01 %
POUT = 1 W, RL = 4 Ω+ 33 µH, fin
20 Hz - 20 kHz, VBAT = 8.4 V
0.01 %
0.01 %
0.01 %
31
THD+N
Total harmonic distortion + noise
POUT = 1 W, RL = 8 Ω+ 33 µH, fin
20 Hz - 20 kHz, VBAT = 12.6 V
POUT = 1 W, RL = 4 Ω+ 33 µH, fin
20 Hz - 20 kHz, VBAT = 12.6 V
A-Weighted, 20 Hz - 20 kHz, DAC
Modulator Running
µV
VN
Idle channel noise
VBAT = 8.4 V
32
36
µV
µV
VBAT = 12.6 V
Average frequency in Spread
Spectrum Mode, CLASSD_SYNC=0
384
384
Fixed Frequency Mode,
CLASSD_SYNC=0
345.6
422.4
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 44.1, 88.2,
174.6 kHz
FPWM
Class-D PWM switching frequency
kHz
44.1·8
48·8
Fixed Frequency Mode,
CLASSD_SYNC=1, fs = 48, 96, 192
kHz
VOS
Output offset voltage
Dynamic range
-1
1
mV
dB
DNR
A-Weighted, -60 dBFS Method
108
108
A-Weighted, Referenced to 1 %
THD+N Output Level
SNR
KCP
Signal to noise ratio
dB
Into and out of Mute, Shutdown,
Power Up, Power Down and audio
clocks starting and stopping. A-
weighted
Click and pop performance
5
mV
Programmable output level range
Programmable output level step size
Amplifier gain error
12.5
21
dBV
dB
0.5
±0.1
±0.1
AVERROR
ARIPPLE
POUT=1W
dB
Frequency response passband ripple 20 Hz - 20 kHz
dB
Device in Shutdown or Muted in
Normal Operation
Mute attenuation
110
6
dB
A
VBAT = 12.6 V, Output to Output,
Output to GND or Output to VBAT
Short
Output short circuit limit
Power stage on-resistance (high-
side + low-side + sense resistor)
RDS(ON)FET
TA = 25 °C
510
105
86
mΩ
VBAT = 12.6 V + 200 mVpp, fripple
217 Hz
=
VBAT power-supply rejection ratio
AVDD power-supply rejection ratio
dB
VBAT = 12.6 V + 200 mVpp, fripple
20 kHz
=
AVDD = 1.8 V + 200 mVpp, fripple
217 Hz
=
95
dB
ms
AVDD = 1.8 V + 200 mVpp, fripple
20 kHz
=
88
No Volume Ramping
Volume Ramping
1.2
5.3
Turn on time from release of SW
shutdown
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TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No Volume Ramping
0.3
Turn off time from assertion of SW
shutdown to amp Hi-Z
ms
Volume Ramping
4.7
PCM PLAYBACK CHARACTERISTICS
Single Speed, I2S/TDM
Double Speed, I2S/TDM
Quadruple Speed, I2S/TDM
Single Speed, I2S/TDM
Double Speed, I2S/TDM
Quadruple Speed, I2S/TDM
Single Speed, I2S/TDM
Double Speed, I2S/TDM
Quadruple Speed, I2S/TDM
3.5
3.5
3.5
Playback latency from latched input
sample to speaker terminals
samples
kHz
23.06
21.79
21.69
24
Playback –0.1 dB bandwidth
23
kHz
Playback –3 dB bandwidth
27.26
PDM PLAYBACK CHARACTERISTICS
Single Rate PDM, PDMD input
Double Rate PDM, PDMD input
Single Rate PDM, PDMD input
Double Rate PDM, PDMD input
Single Rate PDM, PDMD input
Double Rate PDM, PDMD input
7.07
5.02
41.5
88
Playback latency from latched data
bit to speaker terminals
µs
kHz
kHz
Playback –0.1 dB bandwidth
77.5
143
Playback –3 dB bandwidth
SPEAKER CURRENT SENSE
DNR
Dynamic range
Un-Weighted, Relative to 0 dBFS
69
dB
dB
A
RL = 8 Ω+ 33 µH, fin = 1 kHz, POUT
= 5 W
–60
THD+N
Total harmonic distortion + noise
RL = 4 Ω+ 33 µH, fin = 1 kHz, POUT
= 7.5 W
–60
3.75
Full-scale input current
Current-sense accuracy
RL = 8 Ω+ 33 µH, IOUT = 354
mARMS (POUT = 1 W)
±1 %
Current-sense gain error over
temperature
±0.75%
±0.75%
±0.2
–20°C to 70°C, POUT = 1 W
50 mW to 0.1 % THD+N level, fin = 1
kHz, 4 Ω, using a 40Hz-34dB pilot
tone
Current-sense gain error over output
power
Max deviation above and below
passband gain
Current-sense frequency response
dB
SPEAKER VOLTAGE SENSE
DNR
Dynamic range
Un-Weighted, Relative 0 dBFS
69
dB
dB
RL = 8 Ω+ 33 µH, fin = 1 kHz, POUT
= 5 W
–60
THD+N
Total harmonic distortion + noise
RL = 4 Ω+ 33 µH, fin = 1 kHz, POUT
= 7.5 W
–60
14
Full-scale input voltage
Voltage-sense accuracy
VPK
RL = 8 Ω+ 33 µH, IOUT = 354
mARMS (POUT = 1 W)
±1%
Voltage-sense gain error over
temperature
±0.75%
–20°C to 70°C, POUT = 1 W
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50 mW to 0.1 % THD+N level, fin = 1
kHz, 4 Ω, using a 40Hz-34dB pilot
tone
Voltage-sense gain error over output
power
±0.75%
Max deviation above and below
passband gain
Voltage-sense frequency response
±0.2
dB
SPEAKER VOLTAGE/CURRENT SENSE RATIO
50 mW to 0.1 % THD+N level, fin = 1
kHz, 4 Ω, using a 40Hz-34dB pilot
tone
Gain ratio error over output power
±0.75%
±0.5%
Gain ratio error over temperature
–20°C to 70°C
TYPICAL CURRENT CONSUMPTION
SDZ = 0, VBAT
0.1
1
Current consumption in hardware
shutdown
SDZ = 0, AVDD
µA
µA
SDZ = 0, IOVDD
0.1
10
All Clocks Stopped, VBAT
All Clocks Stopped, AVDD
All Clocks Stopped, IOVDD
fs = 48 kHz, VBAT
Current consumption in software
shutdown
10
1
3.1
10
Current consumption during active
operation with IV sense disabled
fs = 48 kHz, AVDD
fs = 48 kHz, IOVDD
fs = 48 kHz, VBAT
mA
mA
0.1
3.1
12.5
0.1
Current consumption during active
operation with IV sense enabled
fs = 48 kHz, AVDD
fs = 48 kHz, IOVDD
PEAK VOLTAGE LIMITER
Limiter maximum threshold
Limiter minimum threshold
Limiter inflection point
2
2
2
1
1
14.7
14.7
14.7
4
V
V
V
Limiter VBAT tracking slope
Limiter max attenuation
V/V
dB
16.5
Time from VBAT dipping below
threshold to initial gain reduction
Limiter latency
23
µs
Limiter attack rate
Limiter attack step size
5
0.25
0
640 µs/step
2
dB/step
ms
Limiter hold time
1000
Limiter release rate
10
1500 ms/step
Limiter release step size
BROWN OUT PREVENTION LIMITER
Brownout prevention threshold
0.25
2
dB/step
4.5
10.875
V
Brownout prevention threshold step
size
25
mV
Brownout prevention threshold
tolerance
Measured at VBAT of 5V and 10V
±25
mV
µs
Time from VBAT dipping below
threshold to initial gain reduction
Brownout prevention latency
20
Brownout prevention attack rate
Brownout prevention attack step size
Brownout prevention hold time
5
0.5
0
640 µs/step
2
dB/step
ms
1000
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω+ 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ =
1, Measured filter free using 节7 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Brownout prevention release rate
10
1500 ms/step
Brownout prevention release step
size
0.25
2
dB/step
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
6.6 I2C Timing Requirements
TA = 25 °C, AVDD = IOVDD = 1.8 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
Standard-Mode
fSCL
SCL clock frequency
0
4
100
kHz
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
μs
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
tLOW
4.7
4
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
0
3.45
250
SDA and SCL rise time
1000
300
ns
tf
SDA and SCL fall time
ns
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
tSU;STO
tBUF
4
μs
μs
pF
4.7
Cb
400
400
Fast-Mode
fSCL
SCL clock frequency
0
kHz
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
0.6
μs
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
tLOW
1.3
0.6
40.6
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
0.9
100
SDA and SCL rise time
20 + 0.1 ×
Cb
tr
tf
300
300
ns
ns
SDA and SCL fall time
20 + 0.1 ×
Cb
Set-up time for STOP condition
tSU;STO
0.26
1.3
μs
μs
pF
Bus free time between a STOP and START condition
Capacitive load for each bus line
tBUF
Cb
400
Fast-Mode Plus
fSCL
SCL clock frequency
0
1000
kHz
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
tHD;STA
0.26
μs
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
0.5
0.26
0.26
0
μs
μs
μs
μs
ns
50
SDA and SCL Rise Time
120
120
ns
tf
SDA and SCL Fall Time
ns
tSU;STO
tBUF
Set-up time for STOP condition
Bus free time between a STOP and START condition
μs
μs
0.5
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TA = 25 °C, AVDD = IOVDD = 1.8 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
Cb
Capacitive load for each bus line
550
pF
6.7 TDM Port Timing Requirements
TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MIN
40
40
8
NOM
MAX
UNIT
ns
tH(SBCLK)
tL(SBCLK)
SBCLK high period
SBCLK low period
ns
tSU(FSYNC) FSYNC setup time
tHLD(FSYNC) FSYNC hold time
tSU(FSYNC) SDIN setup time
ns
8
ns
8
ns
tHLD(SDIN)
SDIN hold time
8
ns
td(DO-
FSYNC)
FSYNC to SDOUT delay (tx_offset
= 0 only)
50% of FSYNC to 50% of SDOUT
50% of FSYNC to 50% of SDOUT
35
35
ns
ns
td(DO-
SBCLK)
SBCLK to SDOUT delay
tr(SBCLK)
tf(SBCLK)
SBCLK rise time
SBCLK fall time
10 % - 90 % Rise Time
90 % - 10 % Fall Time
8
8
ns
ns
6.8 PDM Port Timing Requirements
TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MIN
20
3
NOM
MAX
UNIT
ns
tSU(PDM) PDM IN setup time
tHLD(PDM) PDM IN hold time
ns
tr(PDM)
tf(PDM)
PDM IN rise time
PDM IN fall time
10 % - 90 % Rise Time
90 % - 10 % Fall Time
4
4
ns
ns
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
6.9 Typical Characteristics
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
100
100
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
10
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
0.001
0.01
0.1
POUT (W)
1
10
0.001
0.01
0.1
POUT (W)
1
10
D001
D002
FIN = 1 kHz
FS = 1 kHz
FIN = 1 kHz
RL = 4 Ω
RL = 8 Ω
图6-1. THD+N vs Output Power
图6-2. THD+N vs Output Power
100
10
100
10
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
1
1
0.1
0.1
0.01
0.001
0.01
0.001
0.001
0.01
0.1
POUT (W)
1
10
0.001
0.01
0.1
POUT (W)
1
10
D003
D004
FIN = 6.667 kHz
图6-3. THD+N vs Output Power
FIN = 6.667 kHz
图6-4. THD+N vs Output Power
RL = 4 Ω
RL = 8 Ω
10
1
10
1
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.1
0.1
0.01
0.001
0.01
0.001
20
200
2000
Frequency (Hz)
20000
20
200
2000
Frequency (Hz)
20000
D005
D006
POUT = 0.1 W
POUT = 1 W
FIN = 20 Hz –20
RL = 4 Ω+ 30 µH
FIN = 20 Hz –20
RL = 4 Ω+ 30 µH
kHz
kHz
图6-5. THD+N vs Frequency
图6-6. THD+N vs Frequency
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6.9 Typical Characteristics (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
10
10
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
1
1
0.1
0.1
0.01
0.001
0.01
0.001
20
200
2000
Frequency (Hz)
20000
20
200
2000
Frequency (Hz)
20000
D007
D008
POUT = 5 W
POUT = 1 W
FIN = 20 Hz –20
RL = 4 Ω+ 30 µH
FIN = 20 Hz –20
RL = 8 Ω+ 30 µH
kHz
kHz
图6-7. THD+N vs Frequency
图6-8. THD+N vs Frequency
38
36
34
32
30
28
6.13
6.11
6.09
6.07
6.05
6.03
6.01
VBAT = 12.6 V
4
6
8
10
VBAT (V)
12
14
16
20
200
2000
Frequency (Hz)
20000
D009
D010
FS = 48 kHz
POUT = 1 W
VBAT = 4.5 V –16 V
图6-9. Idle Channel Noise (A-Weighted) vs VBAT
图6-10. Amplitude vs Frequency
20
12
10
8
18
16
14
12
10
8
6
4
6
4
2
VBAT = 8.4
VBAT = 12.6
VBAT = 8.4 V
VBAT = 12.6 V
2
0
0
0.1
1
THDN (%)
10
0.1
1
THDN (%)
10
D011
D012
RL = 4 Ω
RL = 8 Ω
图6-11. Max Output Power vs THD+N
图6-12. Max Output Power vs THD+N
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ZHCSHK8E –OCTOBER 2017 –REVISED JULY 2023
6.9 Typical Characteristics (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.0001
0.001
0.1
POUT (W)
1
10
0.0001
0.001
0.1
POUT (W)
1
10
D013
D014
FIN = 1 kHz
FIN = 1 kHz
RL = 4 Ω
RL = 8 Ω
图6-13. Efficiency vs Output Power
图6-14. Efficiency vs Output Power
140
140
120
100
80
60
40
20
0
120
100
80
60
40
20
0
VBAT = 4.6 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 15.9 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
20
200
2000
Frequency (Hz)
20000
20
200
2000
Frequency (Hz)
20000
D015
D016
图6-15. VDD PSRR vs Frequency
图6-16. VBAT PSRR vs Frequency
0.004
0.0035
0.003
0.0128
0.01275
0.0127
0.0025
0.002
0.01265
0.0126
0.0015
0.01255
4
6
8
10
VBAT (V)
12
14
16
1.6
1.65
1.7
1.75
1.8
AVDD (V)
1.85
1.9
1.95
2
D017
D018
A.
IV Sense Enabled
VBAT = 4.5 V –16
AVDD = 1.65 V –1.95
V
V
图6-17. VBAT Idle Current vs VBAT
图6-18. AVDD Idle Current vs AVDD
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6.9 Typical Characteristics (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
100
100
10
10
1
1
0.1
0.01
0.1
0.01
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.001
0.01
0.1
POUT (W)
10
0.001
0.01
0.1
POUT (W)
10
D019
D020
FIN = 1 kHz
FIN = 1 kHz
RL = 4 Ω
RL = 8 Ω
图6-19. ISENSE THD+N vs Output Power
图6-20. ISENSE THD+N vs Output Power
1
0.8
0.6
0.4
0.2
0
10
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
1
-0.2
-0.4
-0.6
-0.8
-1
0.1
0.01
0.001
0.01
0.1
Power (W)
1
10
30
20
200
2000
Frequency (Hz)
20000
D021
D023
Pilot tone = 40 Hz, 34 dB
POUT = 1 W
RL = 4 Ω
FIN = 20 Hz –20 kHz
图6-21. ISENSE Gain Linearity vs Output Power
图6-22. ISENSE THD+N vs Frequency
10
100
10
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
1
1
0.1
0.1
0.01
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.01
20
200
2000
Frequency (Hz)
20000
0.001
0.1
POUT (W)
1
10
D024
D025
POUT = 1 W
FIN = 20 Hz –20
RL = 4 Ω
图6-24. VSENSE THD+N vs Output Power
kHz
图6-23. ISENSE THD+N vs Frequency
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6.9 Typical Characteristics (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
100
1
0.8
0.6
0.4
0.2
0
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
10
1
-0.2
-0.4
-0.6
-0.8
-1
0.1
0.01
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.001
0.1
POUT (W)
1
10
0.001
0.01
0.1
VSENSE Linearity (%)
1
10
D026
D027
Pilot tone = 40 Hz, 34 dB
RL = 8 Ω
RL = 4 Ω
图6-25. VSENSE THD+N vs Output Power
图6-26. Output Power vs VSENSE Linearity
10
10
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
1
1
0.1
0.01
0.1
0.01
20
200
2000
Frequency (Hz)
20000
20
200
2000
Frequency (Hz)
20000
D028
D029
POUT = 1 W
POUT = 1 W
FIN = 20 Hz –20
FIN = 20 Hz –20
kHz
kHz
图6-27. VSENSE THD+N vs Frequency
图6-28. VSENSE THD+N vs Frequency
1
0.8
0.6
0.4
0.2
0
2
1.5
1
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
-1.5
-2
0.001
0.01
0.1
Power (W)
1
10
-30
-10
10
30
50
70
Temperature (èC)
D030
D031
Pilot tone = 40 Hz, 34 dB
Pilot tone = 40 Hz, 34 dB
RL = 4 Ω+ 30 µH
TA = –20°C –
70°C
图6-29. V/ISENSE Gain Linearity vs Output Power
图6-30. ISENSE Gain Deviation vs Temperature
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6.9 Typical Characteristics (continued)
At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30
µH, unless otherwise noted.
2
1.5
1
2
1.5
1
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
VBAT = 4.5 V
VBAT = 8.4 V
VBAT = 12.6 V
VBAT = 16 V
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-30
-10
10
30
50
70
-30
-10
10
30
50
70
Temperature (èC)
Temperature (èC)
D032
D033
Pilot tone = 40 Hz, 34 dB
Pilot tone = 40 Hz, 34 dB
TA = –20°C –
TA = –20°C –
70°C
70°C
图6-31. VSENSE Gain Deviation vs Temperature
图6-32. V/ISENSE Gain Deviation vs Temperature
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7 Parameter Measurement Information
All typical characteristics for the devices are measured using the Bench EVM and an Audio Precision SYS-2722
Audio Analyzer. A PSIA interface is used to allow the I2S interface to be driven directly into the SYS-2722.
Speaker output terminals are connected to the Audio-Precision analyzer analog inputs through a differential-to-
single ended(D2S) filter as shown below. The D2S filter contains a 1st order Passive pole at 120 kHz. The D2S
filter ensures the TAS2770 high performance class-D amplifier sees a fully differential matched loading at its
outputs. This prevents measurement errors due to loading effects of AUX-0025 filter on the class-D outputs.
1kΩ
0.01%
1kΩ
0.01%
-
1kΩ
SPK_P
+
-
AP
680pF
AUX-0025
SYS-2722
+
SPK_N
1kΩ
0.01%
+
-
1kΩ
1kΩ
0.01%
图7-1. Differential To Single Ended (D2S) Filter
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8 Detailed Description
8.1 Overview
The TAS2770 is a mono digital input Class-D amplifier optimized for mobile applications where efficient battery
operation and small solution size are crucial. It integrates speaker voltage and current sensing and battery
tracking limiting with brown out prevention. The device can operate in either TDM/I2C mode. Both modes support
two PDM inputs that can be used for low latency playback or sensor aggregation.
8.2 Functional Block Diagram
1.8 V
1.8 V
4.5-16 V
VREG
SDZ
SDA
SAR
ADC
BST_P
OUT_P
SCL
IRQZ
fb
fb
Class-D
Amplifier
TMP SNS
DAC
MODE
SDIN
OUT_N
BST_N
System
Interface
+
Limiter
SDOUT
FSYNC
SBCLK
with
VSNS_P
VSNS_N
IV-Sense
IV-SNS
ADCs
Pop/Click
VREG
Over Current
Over Temp
Protection
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Device Mode and Address Selection
The TAS2770 can operate in two distinct operational modes, each with eight selectable device addresses. In
TDM/I2C Mode, audio input and output are provided through the FSYNC, SBCLK, SDIN and SDOUT pins using
formats including I2S, Left Justified and TDM. Configuration and status are provided through the SDA and SCL
pins using the I2C protocol.
The PDM input can be used for a low latency playback path or as a sensor input.
表 8-1 below illustrates how to configure the device for TDM/I2C Mode. I2C slave addresses are shown left
shifted by one bit with the R/W bit set to 0 (i.e. {ADDR[6:0],1b0}). 5% or better tolerance resistors should be used
for setting the mode configuration.
表8-1. TDM/I2C Mode Address Selection
MODE PIN
I2C SLAVE ADDRESS
TAS5770LC0
0x62
TAS2770
0x82
Short to GND
470 Ωto GND
470 Ωto IOVDD
2.2 KΩto GND
2.2 KΩto IOVDD
10 KΩto GND
10 KΩto IOVDD
0x64
0x84
0x66
0x86
0x68
0x88
0x6A
0x8A
0x8C
0x8E
0x6C
0x6E
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表8-1. TDM/I2C Mode Address Selection (continued)
MODE PIN
I2C SLAVE ADDRESS
TAS5770LC0
TAS2770
0x70
0x90
47 KΩto IOVDD
8.3.2 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system using serial data transmission. The address and data 8-bit bytes are transferred most-significant bit
(MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an
acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and
ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal
(SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA
indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the
low time of the clock period. shows a typical sequence.
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock
period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bi-directional bus using a wired-AND connection.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up
resistors between 2 kΩ and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device supply
voltage, IOVDD.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
图8-1. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. 图 8-1shows a generic data transfer
sequence.
8.3.3 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the TAS2770 responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
The TAS2770 supports sequential I2C addressing. For write transactions, if a register is issued followed by data
for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For
I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
8.3.4 Single-Byte Write
As shown in 图 8-2, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C device
address and the read/write bit, the TAS2770 responds with an acknowledge bit. Next, the master transmits the
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register byte corresponding to the device internal memory address being accessed. After receiving the register
byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to
complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
图8-2. Single-Byte Write Transfer
8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TAS2770 as shown in 图 8-3. After receiving each data byte, the
device responds with an acknowledge bit.
Register
图8-3. Multi-Byte Write Transfer
8.3.6 Single-Byte Read
As shown in 图 8-4, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a
read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be
read. As a result, the read/write bit is set to a 0.
After receiving the TAS2770 address and the read/write bit, the device responds with an acknowledge bit. The
master then sends the internal memory address byte, after which the device issues an acknowledge bit. The
master device transmits another start condition followed by the TAS2770 address and the read/write bit again.
This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2770 transmits the data byte from
the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
图8-4. Single-Byte Read Transfer
8.3.7 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS2770 to the master device as shown in 图 8-5. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
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Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Condition
图8-5. Multi-Byte Read Transfer
8.3.8 Register Organization
Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes
and each book contains 256 pages. All device configuration registers are stored in book 0, page 0, which is the
default setting at power up (and after a software reset). The book and page can be set by the BOOK[7:0] and
PAGE[7:0] registers respectively.
8.4 Device Functional Modes
8.4.1 PDM Input
The TAS2770 provides one PDM input that can be used for low latency audio playback or sensor aggregation in
TDM/I2C mode. 图 8-6 below illustrates the double data rate nature of the PDM inputs. Each input has two
interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of the clock.
PDM CLK
PDM DATA
Rising
Channel
Falling
Channel
图8-6. PDM Waveform
The PDM inputs are sampled by the PDMCK pin, which can be independently configured as either a PDM clock
slave input or a PDM clock master output. The PDM_EDGE[1:0] and PDM_SLV[1:0] register bits select the
sample clock edge and master/slave mode for each of the two PDM inputs. In master mode the PDMCK pin can
disable the clocks (and drive a logic 0) by setting the PDM_GATE[1:0] register bits low. The PDM_CLK[1:0]
register bits select which clock is used to sample each PDM input.
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PDM
GND
CLK GEN
PDM_SLV[1]
PDM_GATE[1]
PDMCK
GND
d
PDMD
q
PDM_EDGE[1]
PDM_CLK[1]
图8-7. PDM Data and Clock Input Block Diagram
When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the
system clock (SBCLK in TDM/I2C Mode), but must have an exact frequency relationship to the audio sample
rate. This is equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed
sample rate. The PDM rate is set by the PDM_RATE1[1:0] register bits.
When the PDMCK pin is configured as a clock master, the TAS2770 will output a 50% duty cycle clock of
frequency that is set by the PDM_RATE1[1:0] register bits (64/32/16 or 128/64/32 times a single/double/
quadruple speed sample rate).
The PDM_MAP register bit selects which PDM pin is used for audio playback input and which is used for PDM
sensor input. The PDM sensor input can be decimated (time aligned with the IV sense) and transmitted on the
SDOUT pin when the device is in TDM/I2C mode.
表8-2. PDM Input Capture Edge
PDM Input Pin
Register Bit
Value
Capture Edge
Rising (default)
0
PDMD
PDM_EDGE[1]
Falling
1
表8-3. PDM Clock Slave
PDM Input Pin
Register Bit
Value
Master/Slave
Slave (default)
0
PDMD
PDM_SLV[1]
Master
1
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表8-4. PDM Clock Select
PDM Input Pin
Register Bit
Value
Clock Source
GND
0
PDMD
PDM_CLK[1]
PDMCK
(default)
1
表8-5. PDM Master Mode Clock Gate
PDM Clock Pin Register Bit
Value
Gating
Gated Off
(default)
0
PDMCK
PDM_GATE[1]
Active
1
表8-6. PDM Input Sample Rate
PDM Input Pin Register Bits
Value
Sample Rate
2.54 - 3.38 MHz
(default)
00
5.08 - 6.76 MHz
Reserved
01
10
11
PDM_RATE
PDMD
1[1:0]
Reserved
表8-7. PDM Pin Mapping
PDM_MAP
Mapping
PDMD pin for sensor input
(default)
0
PDMD pin for playback
1
8.4.2 TDM Port
The TAS2770 provides a flexible TDM serial audio port for use in TDM/I2C Mode. The port can be configured to
support a variety of formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via
the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense,
VBAT voltage, die temperature and channel gain.
The TDM serial audio port supports up to 8 32-bit time slots at 44.1/48 kHz, 4 32-bit time slots at a 88.2/96 kHz
sample rate and 2 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in
width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, and
256.. Note that the device will automatically detect the number of time slots and this does not need to be
programmed.
By default, the TAS2770 will automatically detect the PCM playback sample rate. This can be disabled by setting
the AUTO_RATE register bit high.
The SAMP_RATE[2:0] register bits set the PCM audio sample rate when AUTO_RATE = 1. The TAS2770
employs a robust clock fault detection engine that will automatically volume ramp down the playback path if
FSYNC does not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not
supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and
ratio, the device will automatically volume ramp the playback path back to the configured volume and resume
playback.
表8-8. PCM Auto Sample Rate Detection
AUTO_RATE
Setting
Enabled (default)
0
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表8-8. PCM Auto Sample Rate Detection (continued)
AUTO_RATE
Setting
Disabled
1
表8-9. PCM Audio Sample Rates
SAMP_RATE[1:0]
Sample Rate
Reserved
000
001
010
011
100
101
110
111
Reserved
Reserved
44.1 kHz / 48 kHz (default)
88.2 kHz / 96 kHz
176.4 kHz / 192 kHz
Reserved
Reserved
图 8-8 and 图 8-9 below illustrates the receiver frame parameters required to configure the port for playback. A
frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START
register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the
RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the
transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format
and 1 for an I2S format.
SBCLK
FSYNC
MSB
MSB-1
LSB+1
LSB
SDIN
RX_OFFSET
RX_WLEN
RX_SLEN
图8-8. TDM RX Time Slot with Left Justification
SBCLK
FSYNC
SDIN
Slot 0
Bit 31
Slot0
Bit 0
Slot 1
Bit 31
Slot1
Bit 0
Slot2
Bit 31
RX_OFFSET
Time Slot 0
Time Slot 1
图8-9. TDM RX Time Slots
表8-10. TDM Start of Frame Polarity
FRAME_START
Polarity
Low to High on FSYNC
0
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表8-10. TDM Start of Frame Polarity (continued)
FRAME_START
Polarity
High to Low on FSYNC (default)
1
表8-11. TDM RX Capture Polarity
RX_EDGE
FSYNC and SDIN Capture Edge
Rising edge of SBCLK (default)
Falling edge of SBCLK
0
1
表8-12. TDM RX Start of Frame to Time Slot 0 Offset
RX_OFFSET[4:0]
SBCLK Cycles
0
0x00
1 (default)
0x01
0x02
...
2
...
30
31
0x1E
0x1F
The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within
the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within
the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The
TAS2770 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time
slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default
the device will playback mono from the time slot equal to the I2C base address offset (set by the MODE pin) for
playback. The RX_SCFG [1:0] register bits can be used to override the playback source to the left time slot, right
time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.
If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return
a null sample equivalent to a digitally muted sample.
表8-13. TDM RX Time Slot Length
RX_SLEN[1:0]
Time Slot Length
16-bits
00
24-bits
32-bits (default)
reserved
01
10
11
表8-14. TDM RX Sample Word Length
RX_WLEN[1:0]
Length
16-bits
00
20-bits
24-bits (default)
32-bits
01
10
11
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表8-15. TDM RX Sample Justification
RX_JUSTIFY
Justification
Left (default)
Right
0
1
表8-16. TDM RX Time Slot Select Configuration
RX_SCFG[1:0]
Config Origin
Mono with Time Slot equal to I2C
Address Offset (default)
00
Mono Left Channel
Mono Right Channel
Stereo Down Mix [L+R]/2
01
10
10
表8-17. TDM RX Left Channel Time Slot
RX_SLOT_L[3:0]
Time Slot
0 (default)
0x0
1
0x1
...
0xE
0xF
...
14
15
表8-18. TDM RX Right Channel Time Slot
RX_SLOT_R[3:0]
Time Slot
0 (default)
0x0
1
0x1
...
0xE
0xF
...
14
15
The TDM port can transmit a number sample streams on the SDOUT pin including speaker voltage sense,
speaker current sense, decimated PDM input, VBAT voltage, die temperature and channel gain. 图 8-10 below
illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to
time slots. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can
be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK
cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for
Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the
setting of the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all
devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the
TX_KEEPER register bit.
Each sample stream is composed of either one or two 8-bit time slots. Speaker voltage sense, speaker current
sense and decimated PDM sample streams are 16-bit precision, so they will always utilize two TX time slots.
The VBAT voltage stream is 12-bit precision, and can either be transmitted left justified in a 16-bit word (using
two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is
configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are
transmitted in a single time slot.
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SBCLK
FSYNC
Slot 0
Bit 7
Slot0
Bit 0
Slot 1
Bit 7
Slot1
Bit 0
Slot2
Bit 7
SDOUT
TX_OFFSET
Time Slot 0
Time Slot 1
Ex: V_SENSE[15:0]
图8-10. TDM Port TX Diagram
表8-19. TDM TX Transmit Polarity
TX_EDGE
SDOUT Transmit Edge
Rising edge of SBCLK
0
1
Falling edge of SBCLK (default)
表8-20. TDM TX Start of Frame to Time Slot 0 Offset
TX_OFFSET[2:0]
SBCLK Cycles
0
0x0
1 (default)
0x1
0x2
...
0x6
0x7
2
...
6
7
表8-21. TDM TX Unused Bit Field Fill
TX_FILL
SDOUT Unused Bit Fields
Transmit 0
0
Transmit Hi-Z (default)
1
表8-22. TDM TX SDOUT Bus Keeper Enable
TX_KEEPER
SDOUT Bus Keeper
Disable bus keeper
0
Enable bus keeper (default)
1
The time slot register for each sample stream defines where the MSB transmission begins. For instance, if
VSNS_SLOT[5:0] is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be
transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage
limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.
It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For
instance, if VSNS_SLOT[5:0] is set to 2 and ISNS_SLOT[5:0] is set to 3, the lower 8 LSBs of voltage sense will
conflict with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the
conflicting bit slots (i.e. the priority is not defined).
If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at
the frame boundary.
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表8-23. TDM Voltage Sense Time Slot
VSNS_SLOT[5:0]
Slot
0 (default)
0x00
1
2
0x01
0x02
...
...
62
63
0x3E
0x3F
表8-24. TDM Voltage Sense Transmit Enable
VSNS_TX
State
Disabled (default)
0
Enabled
1
表8-25. TDM Current Sense Time Slot
ISNS_SLOT[5:0]
Slot
0
0x00
1
0x01
0x02
...
2 (default)
...
62
63
0x3E
0x3F
表8-26. TDM Current Sense Transmit Enable
ISNS_TX
State
Disabled (default)
0
Enabled
1
表8-27. TDM Decimated PDM Input Time Slot
PDM_SLOT[5:0]
Slot
0
0x00
1
0x01
...
...
4 (default)
0x04
...
...
62
63
0x3E
0x3F
表8-28. TDM Decimated PDM Input Transmit Enable
PDM_TX
State
Disabled (default)
0
Enabled
1
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表8-29. TDM VBAT Time Slot
VBAT_SLOT[5:0]
Slot
0
0x00
0x01
...
1
...
6 (default)
0x06
...
...
62
63
0x3E
0x3F
表8-30. TDM VBAT Time Slot Length
VBAT_SLEN
Slot Length
Truncate to 8-bits (default)
0
Left justify to 16-bits
1
表8-31. TDM VBAT Transmit Enable
VBAT_TX
State
Disabled (default)
0
Enabled
1
表8-32. TDM Temp Sensor Time Slot
TEMP_SLOT[5:0]
Slot
0
0x00
1
0x01
...
...
7 (default)
0x07
...
...
62
63
0x3E
0x3F
表8-33. TDM Temp Sensor Transmit Enable
TEMP_TX
State
Disabled (default)
0
Enabled
1
表8-34. TDM Limiter Gain Reduction Time Slot
GAIN_SLOT[5:0]
Slot
0
0x00
1
0x01
...
...
8 (default)
...
0x08
...
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表8-34. TDM Limiter Gain Reduction Time Slot
(continued)
GAIN_SLOT[5:0]
Slot
62
0x3E
63
0x3F
表8-35. TDM Limiter Gain Reduction Transmit
Enable
GAIN_TX
State
Disabled (default)
0
Enabled
1
8.4.3 Playback Signal Path
8.4.3.1 High Pass Filter
Excessive DC and low frequency content in audio playback signal can damage loudspeakers, so the TAS2770
employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. No HPF is available
in the PDM playback path. 表 8-36 below shows the -3 dB corner frequencies available for each sample rate set
by register bits HPF_FREQ[2:0]. The filter can be bypassed by setting the HPF_FREQ[2:0] register to 3'b000.
The HPF Bi-Quad filter coefficients can also be directly programmed via the TBD register bits.
表8-36. HPF Filter Settings
-3 dB FREQUENCY (Hz)
HPF_FREQ[2:0]
44.1/88.2/176.4 kHz
48/96/192 kHz
bypass
bypass
000
001
010
011
100
101
110
111
1.8 (default)
46
2 (default)
50
92
100
184
200
368
400
735
800
Reserved
Reserved
8.4.3.2 Digital Volume Control and Amplifier Output Level
The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital
volume control (DVC). A separate DVC is provided for PDM (available from the PDM input pins) and PCM
(available from the TDM ports pins) playback paths.
Amplifier output level settings are presented in dBV (dB relative to 1 Vrms) with a full scale digital audio input (0
dBFS) and the digital volume control set to 0 dB. It should be noted that these levels may not be achievable
because of analog clipping in the amplifier, so they should be used to convey gain only. 表 8-37 below shows
analog gain settings that can be programmed via the AMP_LEVEL[4:0] register bits.
表8-37. Amplifier Output Level Settings
FULL SCALE OUTPUT
AMP_LEVEL[4:0]
dBV
VPEAK (V)
11.0
5.02
0x00
0x01
11.5
5.32
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表8-37. Amplifier Output Level Settings (continued)
FULL SCALE OUTPUT
AMP_LEVEL[4:0]
dBV
VPEAK (V)
12.0
12.5
5.63
0x02
0x03
5.96
6.32
13.0
0x04
13.5
6.69
0x05
14.0
7.09
0x06
14.5
7.51
0x07
15.0
7.95
0x08
15.5
8.42
0x09
16.0
8.92
0x0A
16.5
9.45
0x0B
17.0
10.0
0x0C
17.5
10.6
0x0D
18.0
11.2
0x0E
18.5
11.9
0x0F
19.0 (default)
19.5
12.6 (default)
13.4
0x10
0x11
20.0
14.1
0x12
20.5
14.98
15.87
Reserved
0x13
21.0
0x14
Reserved
0x15 - 0x1F
方程式1 calculates the amplifiers output voltage.
V
= Input + A
+ A
dBV
AMP
AMP
dvc
(1)
where
• VAMP is the amplifier output voltage in dBV
• Input is the digital input amplitude in dB with respect to 0 dBFS
• Advc is the digital volume control setting, 0 dB to -100 dB in 0.5 dB steps
• AAMP is the amplifier output level setting in dBV
The digital volume control (DVC) is independently configurable for PCM and PDM streams from 0 dB to -100 dB
in 0.5 dB steps by setting the DVC_PCM[7:0] and PVC_PDM[7:0] register bits respectively. Settings greater than
0xC8 are interpreted as mute. When a change in digital volume control occurs, the device ramps the volume to
the new setting based on the DVC_RATE[1:0] register bits. If DVC_RATE[1:0] is set to 2'b11, volume ramping is
disabled. This can be used to speed up startup, shutdown and digital volume changes when volume ramping is
handled by the system master.
表8-38. PCM Digital Volume Control
DVC_PCM[7:0]
Volume (dB)
0 (default)
0x00
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表8-38. PCM Digital Volume Control (continued)
DVC_PCM[7:0]
Volume (dB)
-0.5
-1
0x01
0x02
...
...
-100
Mute
0xC8
0xC9 - 0xFF
表8-39. PDM Digital Volume Control
DVC_PDM[7:0]
Volume (dB)
0 (default)
0x00
-0.5
-1
0x01
0x02
...
...
-100
Mute
0xC8
0xC9 - 0xFF
表8-40. Digital Volume Ramp Rate
DVC_RAMP[1:0]
Ramp Rate
0.5 dB per 1 Sample (default)
00
0.5 dB per 4 Samples
0.5 dB per 8 Samples
01
10
11
Volume Ramping Disabled
The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on VBAT. The approximate
threshold for the onset of analog clipping is calculated in 方程式2.
≈
’
RL
VPK(max,preclip)= VBAT ×
V
∆
∆
«
÷
÷
◊
RFET(tot) + Rinterconnect + RL
(2)
where
• VPK(max,preclip) is the maximum peak unclipped output voltage in V
• VBAT is the power supply voltage
• RL is the speaker load in Ω
• Rinterconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
• RFET(on) is the power stage total on resistance (HS FET+LS FET+Sense Resistor+bonding+packaging) in Ω
The effective on-resistance for this device (including HS+LS FET, Sense Resistor and bonding and packaging
leads) is approximately 510 mΩ at room temperature. 表 8-41 shows approximate maximum unclipped peak
output voltages at room temperature (excluding interconnect resistances).
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表8-41. Approximate Maximum Unclipped Peak
Output Voltage at Room Temperature
MAXIMUM UNCLIPPED
PEAK VOLTAGE
SUPPLY VOLTAGE
VPK (V)
VBAT (V)
RL = 4 Ω
7.45
RL = 8 Ω
7.90
8.4
12.6
11.18
11.84
8.4.3.3 Audio Playback Selection
Audio playback can be sourced from either PCM (through the TDM) or PDM (through the PDMD PDM Inputs)
input sources through the PB_SRC register bit. The PB_PDM_SRC register bit determines the source of the
PDM source.
表8-42. Audio Playback Source
PB_SRC
Source
PCM (default)
0
PDM
1
表8-43. PDM Playback Source
PB_PDM_SRC
Source
PDM input pin defined by
PDM_MAP register bit (default)
0
1
Reserved
8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
The TAS2770 monitors battery voltage (VBAT) and the audio signal to automatically decrease gain when the
audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time
through end of charge battery conditions. The limiter threshold can be configured to track VBAT below a
programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold
reduction from VBAT tracking. Configurable attack rate, hold time and release rate are provided to shape the
dynamic response of the limiter (through the LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0]
register bits).
BOP ACTIVE PHASE (BOP_GAIN ≠ 0dB)
PAUSE LIMITER UPDATES
ICLA_MODE
LIMITER
ICLA
CALC
ATTACK/
RELEASE
ICLA
1
0
LIMITER
ATTACK/
RELEASE
ICLA_EN
LIMITER
PUBLISHED ON
ICLA
LIM_MAX_ATN
LIM_MAX_ATN
+
+
ATTNUATION
APPLIED
BOP ATTACK/
RELEASE
VBATT<BOP_TH
BOP
ATTN
图8-11. Limiter and Brown Out Prevention Interaction Diagram
A Brown Out Prevention (BOP) feature provides a priority input to the limiter to provide very fast response to
transient dips in VBAT at end of charge conditions that can cause system level brown out. When VBAT dips
below the BOP threshold, the limiter begins reducing gain with an attack latency of less than 10 µs and a
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configurable attack rate. When VBAT rises above the BOP threshold, the limiter will begin to release after the
programmed hold time.
The limiter is enabled by setting the LIM_EN bit register bit high.
表8-44. Battery Tracking Limiter Enable
LIM_EN
Value
Disabled (default)
0
Enabled
1
The limiter has configurable attack rate, hold time and release rate, which are available through the
LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0] register bits respectively. The limiter attack and
release step size can be set by configuring the LIM_ATK_ST[1:0] and LIM_RLS_ST[1:0] register bits
respectively.
表8-45. Limiter Attack Rate
LIM_ATK_RT[2:0]
Attack Rate (µs)
5
0x0
10
20 (default)
40
0x1
0x2
0x3
0x4
0x5
0x6
0x7
80
160
320
640
表8-46. Limiter Hold Time
LIM_HLD_TM[2:0]
Hold Time (ms)
0
0x0
10
25
0x1
0x2
0x3
0x4
0x5
0x6
0x7
50
100
250
500 (default)
1000
表8-47. Limiter Release Rate
LIM_RLS_RT[2:0]
Release Time (ms)
10
0x0
50
0x1
0x2
0x3
0x4
100
250
500
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表8-47. Limiter Release Rate (continued)
LIM_RLS_RT[2:0]
Release Time (ms)
750
0x5
0x6
0x7
1000 (default)
1500
表8-48. Limiter Attack Step Size
LIM_ATK_ST[1:0]
Step Size (dB)
0.25
00
01
10
11
0.5 (default)
1
2
表8-49. Limiter Release Step Size
LIM_RLS_ST[1:0]
Step Size (dB)
0.25
00
0.5 (default)
01
10
11
1
2
A maximum level of attenuation applied by the limiter and brown out prevention feature is configurable through
the LIM_MAX_ATN[4:0] register bits. This attenuation limit is shared between the features. For instance, if the
maximum attenuation is set to 6 dB and the limiter has reduced gain by 4 dB, the brown out prevention feature
will only be able to reduce the gain further by another 2 dB. If the limiter or brown out prevention feature is
attacking and it reaches the maximum attenuation, gain will not be reduced any further.
表8-50. Limiter Max Attenuation
LIM_MAX_ATN[4:0]
Attenuation (dB)
1
0x00
1.5
0x01
...
...
9 (default)
...
0x10
...
16
0x1E
0x1F
16.5
The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can
be configured to track VBAT below a programmable inflection point with a minimum threshold value. 图 8-12
below shows the limiter configured to limit to a constant level regardless of VBAT level. To achieve this behavior,
set the limiter maximum threshold to the desired level through the LIM_TH_MAX[6:0] register bits. Set the limiter
inflection point (through the LIM_INF_PT[6:0] register bits) below the minimum allowable VBAT setting. The
limiter minimum threshold register bits (LIM_TH_MIN[6:0]) do not impact limiter behavior in this use case.
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LIM_TH_MAX
Brown
Out
BOP_TH
VBAT (V)
图8-12. Limiter with Fixed Threshold
表8-51. Limiter Maximum Threshold
LIM_TH_MAX[6:0]
Threshold (V)
2
0x00
2.1
...
0x01
...
13 (default)
...
0x6E
...
14.6
0x7E
0x7F
14.7
表8-52. Limiter Minimum Threshold
LIM_TH_MIN[6:0]
Threshold (V)
2
0x00
2.1
...
0x01
...
5 (default)
...
0x1E
...
14.6
0x7E
0x7F
14.7
表8-53. Limiter Inflection Point
LIM_INF_PT[6:0]
Inflection Point (V)
2
0x00
2.1
...
0x01
...
10.8 (default)
0x58
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表8-53. Limiter Inflection Point (continued)
LIM_INF_PT[6:0]
Inflection Point (V)
...
...
0x7E
0x7F
14.6
14.7
图8-13 shows how to configure the limiter to track VBAT below a threshold without a minimum threshold. Set the
LIM_TH_MAX[6:0] register bits to the desired threshold and LIM_INF_PT[6:0] register bits to the desired
inflection point where the limiter will begin reducing the threshold with VBAT. The LIM_SLOPE[1:0] register bits
can be used to change the slope of the limiter tracking with VBAT. The default value of 1 V/V will reduce the
threshold 1 V for every 1 V of drop in VBAT. More aggressive tracking slopes can be programmed if desired.
Program the LIM_TH_MIN[6:0] below the minimum VBAT to prevent the limiter from having a minimum threshold
reduction when tracking VBAT.
Inflection
Point
LIM_TH_MAX
slope
Brown
Out
BOP_TH LIM_INF_PT
VBAT (V)
图8-13. Limiter with Inflection Point
表8-54. Limiter VBAT Tracking Slope
LIM_SLOPE[1:0]
Slope (V/V)
1 (default)
00
1.5
2
01
10
11
4
To achieve a limiter that tracks VBAT below a threshold, configure the limiter as explained in the previous
example, except program the LIM_TH_MIN[6:0] register bits to the desired minimum threshold. This is shown in
图8-14 below.
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Inflection
Point
LIM_TH_MAX
LIM_TH_MIN
slope
Brown
Out
BOP_TH LIM_INF_PT
VBAT (V)
图8-14. Limiter with Inflection Point and Minimum Threshold
The TAS2770 also employs a Brown Out Prevention (BOP) feature that serves as a low latency priority input to
the limiter engine that begins attacking within 10 µs of VBAT dipping below the programmed BOP threshold. This
feature can be enabled by setting the BOP_EN register bit high. It should be noted that the BOP feature is
independent of the limiter and will function if enabled even if the limiter is disabled. The BOP threshold is
configured by setting the threshold with register bits BOP_TH[7:0].
AUDIO_IN
AUDIO_OUT
Limiter
&
Brown
Out
Prevention
Temp
Sensor
SAR
ADC
12-bit
12
VBAT
SETTINGS
图8-15. Limiter Block Diagram
表8-55. Brown Out Prevention Enable
BOP_EN
Value
Disabled
0
Enabled (default)
1
表8-56. Brown Out Prevention Threshold
BOP_TH[7:0]
Threshold (V)
4.5
0x00
4.525
4.55
0x01
0x02
...
...
5.0 (default)
0x14
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表8-56. Brown Out Prevention Threshold
(continued)
BOP_TH[7:0]
Threshold (V)
...
...
10.85
0xFE
0xFF
10.875
The BOP feature has a separate attack rate, attack step size and hold time from the battery tracking limiter
(register bits BOP_ATK_RT[2:0], BOP_ATK_ST[1:0] and BOP_HLD_TM[2:0] respectively). The BOP feature
uses the LIM_RLS_RT[2:0] register setting to release after a brown out event.
表8-57. Brown Out Prevention Attack Rate
BOP_ATK_RT[2:0]
Attack Rate (µs)
5
0x0
10
20 (default)
40
0x1
0x2
0x3
0x4
0x5
0x6
0x7
80
160
320
640
表8-58. Brown Out Prevention Attack Step Size
BOP_ATK_ST[1:0]
Step Size (dB)
0.5
00
1 (default)
01
10
11
1.5
2
表8-59. Brown Out Prevention Hold Time
BOP_HLD_TM[2:0]
Hold Time (ms)
0
0x0
10
25
0x1
0x2
0x3
0x4
0x5
0x6
0x7
50
100
250
500 (default)
1000
The TAS2770 can also shutdown the device when a brown out event occurs if the BOP_SHUTDOWN register bit
is set high. For the device to continue playing audio again, the device must transition through a SW/HW
shutdown state. Setting the BOP_INF_HLD high will cause the limiter to stay in the hold state (i.e. never release)
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after a cleared brown out event until either the device transitions through a mute or SW/HW shutdown state or
the register bit BOP_HLD_CLR is written to a high value (which will cause the device to exit the hold state and
begin releasing). This bit is self clearing and will always readback low. 图 8-16 below illustrates the entering and
exiting from a brown out event.
VBAT
BOP Thresh
BOP Active
BOP
Attacking
BOP
Holding
Limiter Releasing
(BOP Inactive)
BOP Inactive
BOP Inactive
BOP Mode
图8-16. Brown Out Prevention Event
表8-60. Shutdown on Brown Out Event
BOP_SHUTDOWN
Value
Don't Shutdown (default)
0
Shutdown
1
表8-61. Infinite Hold on Brown Out Event
BOP_INF_HLD
Value
Use BOP_HLD_TM after Brown
0
Out event (default)
Do not release until
1
BOP_HLD_CLR is asserted high
表8-62. BOP Infinite Hold Clear
BOP_HLD_CLR
Value
Don't clear (default)
0
Clear event (self clearing)
1
8.4.3.5 Inter Chip Limiter Alignment
8.4.3.5.1 TDM Mode
The TAS2770 supports alignment of limiter (including brown out prevention) dynamics across devices that share
the same TDM bus. This ensures consistent gain between channels during limiting or brown out events since
these dynamics are dependent on audio content, which can vary across channels. Each device can be
configured to align to a specified number of other devices, which allows creation of groupings of devices that
align only to each other.
Limiter activity is communicated through the limiter gain reduction parameter that can be optionally transmitted
by each device on SDOUT in an 8-bit time slot. Gain reduction should be transmitted in adjacent time slots for all
devices that are to be aligned beginning with the first slot that is specified by the ICLA_SLOT[5:0] register bits.
The order of the devices is not important as long as they are adjacent. The time slot for limiter gain reduction is
configured by the GAIN_SLOT[5:0] register bits and enabled by the GAIN_TX register bit.
The ICLA_SEN[7:0] register bits specify which time slots should be listened to for gain alignment. This allows
any number of devices between two and eight to be grouped together. At least two of these bits should be
enabled for alignment to take place. The ICLA_USE_MAX register bit determines whether alignment is based on
the maximum or minimum gain reduction value from the group of enabled devices.
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To enable the inter chip limiter alignment feature, the ICLA_EN register bit should be asserted high and all
devices should be configured with identical limiter and brown out prevention settings. Limiter gain reduction
transmission should be enabled on all devices as described above.
表8-63. Inter Chip Limiter Alignment
ICLA_EN
Value
Disabled (default)
0
Enabled
1
表8-64. ICLA Alignment Configuration
ICLA_MODE
Value
Use the minimum gain reduction
of the ICLA group including 0dB
(default)
00
Use the maximum gain reduction
of the ICLA group
01
10
11
Use the minimum gain reduction
of the ICLA group that is non-0dB
Reserved
表8-65. Inter Chip Limiter Alignment Starting Time
Slot
ICLA_SLOT[5:0]
Starting Time Slot
Time Slot 0 (default)
0x00
Time Slot 1
Time Slot 2
...
0x01
0x02
...
Time Slot 63
0x3F
表8-66. Inter Chip Limiter Alignment Time Slot Enable
Register Bit
Description
Bit Value
State
Disabled (default)
0
Time Slot = ICLA_SLOT[5:0]. When enabled, the limiter will
ICLA_SEN[0]
include this time slot in the alignment group.
Enabled
Disabled (default)
Enabled
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot = ICLA_SLOT[5:0] + 1. When enabled, the limiter
ICLA_SEN[1]
ICLA_SEN[2]
ICLA_SEN[3]
ICLA_SEN[4]
ICLA_SEN[5]
ICLA_SEN[6]
will include this time slot in the alignment group.
Disabled (default)
Enabled
Time Slot = ICLA_SLOT[5:0] + 2. When enabled, the limiter
will include this time slot in the alignment group.
Disabled (default)
Enabled
Time Slot = ICLA_SLOT[5:0] + 3. When enabled, the limiter
will include this time slot in the alignment group.
Disabled (default)
Enabled
Time Slot = ICLA_SLOT[5:0] + 4. When enabled, the limiter
will include this time slot in the alignment group.
Disabled (default)
Enabled
Time Slot = ICLA_SLOT[5:0] + 5. When enabled, the limiter
will include this time slot in the alignment group.
Disabled (default)
Enabled
Time Slot = ICLA_SLOT[5:0] + 6. When enabled, the limiter
will include this time slot in the alignment group.
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表8-66. Inter Chip Limiter Alignment Time Slot Enable (continued)
Register Bit
ICLA_SEN[7]
Description
Bit Value
State
Disabled (default)
0
Time Slot = ICLA_SLOT[5:0] + 7. When enabled, the limiter
will include this time slot in the alignment group.
Enabled
1
8.4.3.6 Class-D Settings
The TAS2770 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting
the AMP_SS register bit high. This can help reduce EMI in some systems.
表8-67. Low EMI Spread Spectrum Mode
AMP_SS
Spread Spectrum
Disabled
0
Enabled (default)
1
By default the Class-D amplifier's switching frequency is based on the device's trimmed internal oscillator. To
synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is
synchronized to the audio sample rate, the RATE_RAMP register bit must be set based whether the audio
sample rate is based on a 44.1 kHz or 48 kHz frequency. For 44.1, 88.2 and 176.4 kHz, set this bit high. for 48,
96 and 192 kHz, set this bit low. This ensures that the internal ramp generator has the appropriate slope.
表8-68. Class-D Synchronization Mode
CLASSD_SYNC
Synchronization Mode
Not synchronized to audio clocks
(default)
0
Synchronized to audio clocks
1
表8-69. Sample Rate for Class-D Synchronized
Mode
RAMP_RATE
Playback Sample Rate
48, 96 and 192 kHz (default)
0
44.1, 88.2 and 174.6 kHz
1
8.4.4 SAR ADC
A 12-bit SAR ADC monitors VBAT voltage and die temperature. The results of these conversions are available
through the register readback (VBAT_CNV[11:0] and TMP_CNV[7:0] registers respectively). VBAT voltage
conversions are also used by the limiter and brown out prevention features.
The ADC runs at a fixed 667 kHz sample rate (1.5 µs per conversion) interleaved between VBAT voltage and die
temperature measurements. This gives an effective sample rate of 333 kHz (3 µs per conversion) with a latency
of 1 sample (1.5 µs). This gives a worst case measurement latency of 4.5 µs. Actual VBAT voltage is calculated
by dividing the VBAT_CNV[11:0] register by 256. Actual die temperature is calculated by dividing the
TMP_CNV[11:0] register by 16 and then subtracting 93.
表8-70. ADC VBAT Voltage Conversion
VBAT_CNV[11:0]
VBAT Voltage (V)
0 V
0x000
0.0039 V
...
0x001
...
12.6016 V
0xC9A
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表8-70. ADC VBAT Voltage Conversion (continued)
VBAT_CNV[11:0]
VBAT Voltage (V)
...
...
14.0000 V
0xE00
表8-71. ADC Die Temperature Conversion
TMP_CNV[11:0]
Die Temperature (°C)
-93 °C
0x000
-92.9375 °C
...
0x001
...
25 °C
0x760
...
...
162.8750 °C
162.9375 °C
0xFFE
0xFFF
8.4.5 IV Sense
The TAS2770 provides speaker voltage and current sense for real time monitoring of loudspeaker behavior. The
VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or directly to the OUT_P and
OUT_N connections if no EMI filter is used). The V-Sense connections eliminate IR drop error due to packaging,
PCB interconnect or ferrite bead filter resistance. It should be noted that any interconnect resistance after the V-
Sense terminals will not be corrected for, so it is advised to connect the sense connections as close to the load
as possible.
BST_P
OUT_P
fb
OUT_N
fb
BST_N
VSNS_P
VSNS_N
图8-17. V-Sense Connections
I-Sense and V-Sense can be powered down by asserting the ISNS_PD and VSNS_PD register bits respectively.
When powered down, the device will return null samples for the powered down block.
表8-72. I-Sense Power Down
ISNS_PD
Setting
I-Sense is active (default)
0
I-Sense is powered down
1
表8-73. V-Sense Power Down
VSNS_PD
Setting
V-Sense is active (default)
0
V-Sense is powered down
1
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8.4.6 Clocks and PLL
In TMD/I2C Mode, the device operates from SBCLK. 表 8-74 and 表 8-75 below shows the valid SBCLK
frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies
respectively.
If the sample rate is properly configured through the SAMP_RATE[1:0] bits, no additional configuration is
required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and
SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts.
表8-74. Supported SBCLK Frequencies (48 kHz based sample rates)
SBCLK to FSYNC Ratio
Sample Rate
(kHz)
64
96
128
192
256
384
512
48 kHz
96 kHz
192 kHz
3.072 MHz
6.144 MHz
12.288 MHz
4.608 MHz
9.216 MHz
18.432 MHz
6.144 MHz
12.288 MHz
24.576 MHz
9.216 MHz
18.432 MHz
-
12.288 MHz
24.576 MHz
-
18.432 MHz
24.576 MHz
-
-
-
-
表8-75. Supported SBCLK Frequencies (44.1 kHz based sample rates)
SBCLK to FSYNC Ratio
Sample Rate
(kHz)
64
96
128
192
8.4672 MHz
16.9344 MHz
-
256
11.2896 MHz
22.5792 MHz
-
384
512
44.1 kHz
88.2 kHz
176.4 kHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
4.2336 MHz
8.4672 MHz
16.9344 MHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
16.9344 MHz
22.5792 MHz
-
-
-
-
8.4.7 Operational Modes
8.4.7.1 Hardware Shutdown
The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the
device consumes the minimum quiescent current from AVDD and VBAT supplies. All registers loose state in this
mode and communication is disabled (through the I2C).
If SDZ is asserted low while audio is playing, the device will ramp down volume on the audio, stop the Class-D
switching, power down analog and digital blocks and finally put the device into Hardware Shutdown mode.
When SDZ is released, the device will sample the MODE pin and enter the selected operational mode (i.e. either
TDM/I2C).
8.4.7.2 Software Shutdown
Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the
device to loose register state. Software Shutdown is enabled by asserting the MODE[1:0] register bits to 2'b10. If
audio is playing when Software Shutdown is asserted, the Class-D will volume ramp down before shutting down.
When deasserted, the Class-D will begin switching and volume ramp back to the programmed digital volume
setting.
8.4.7.3 Mute
The TAS2770 will volume ramp down the Class-D amplifier to a mute state by setting the MODE[1:0] register bits
to 2'b01. During mute the Class-D still switches, but transmits no audio content. If mute is deasserted, the device
will volume ramp back to the programmed digital volume setting.
8.4.7.4 Active
In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational
if enabled. PDM inputis also active if enabled. Set the MODE[1:0] register bits to 2'b00 to enter active mode.
8.4.7.5 Mode Control and Software Reset
The TAS2770 mode can be configured by writing the MODE[1:0] bits.
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表8-76. Mode Control
MODE[1:0]
Setting
Active
Mute
00
01
10
11
Software Shutdown (default)
Reserved
A software reset can be accomplished by asserting the SW_RESET bit, which is self clearing. This will restore all
registers to their default values.
表8-77. Software Reset
SW_RESET
Setting
Don't reset (default)
0
Reset
1
8.4.8 Faults and Status
During the power-up sequence, the power-on-reset circuit (POR) monitoring the AVDD pin will hold the device in
reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown
until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will
power up, enabling detection of the operational mode. If AVDD dips below the POR threshold, the device will
immediately be forced into a reset state.
The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the
UVLO threshold or above the OVLO threshold. If the TAS2770 is in active operation and a UVLO or OVLO fault
occurs, the analog supplies will immediately power down to protect the device. These faults are latching and
require a transition through HW/SW shutdown to clear the fault. The live and latched registers will report UVLO/
OVLO faults.
The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:
•Invalid SBCLK to FSYNC ratio
•Invalid FSYNC frequency
•Halting of SBCLK or FSYNC clocks
Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible
to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to
its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt
mask register bit is set low (INT_MASK[2]). The clock fault is also available for readback in the live or latched
fault status registers (INT_LIVE[2] and INT_LTCH[2]). Reading the latched fault status register (INT_LTCH[7:0])
clears the register.
The TAS2770 also monitors die temperature and Class-D load current and will enter software shutdown mode if
either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if
the appropriate fault interrupt mask register bit is set low (INT_MASK[0] for over temp and INT_MASK[1] for over
current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.
Die over temp and Class-D over current errors can either be latching (i.e. the device will enter software
shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a
prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over
temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over
temp or over current error until the retry time period (1.5s) has elapsed. This prevents applying repeated stress
to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW
shutdown, the device will only begin to operate after the retry time period.
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The status registers (and IRQZ pin if enabled through the status mask register) also indicates limiter behavior
including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has
been applied, when the limiter is in infinite hold and when the limiter has muted the audio.
The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be
pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2770 and can be accessed
by setting the IRQZ_PU register bit high. 图8-18 below highlights the IRQZ pin circuit.
IOVDD
IOVDD
IRQZ_PU
To
System
Master
IRQZ
Interrupt
图8-18. IRQZ Pin
表8-78. Fault Interrupt Mask
INT_MASK[10:0] Bit
Interrupt
Default (1 = Mask)
0
1
Over Temp Error
0
0
1
1
1
1
1
1
1
1
1
1
Over Current Error
TDM Clock Error
Limiter Active
2
3
4
VBAT < Inf Point
Limiter Max Atten
Limiter Inf Hold
Limiter Mute
5
6
7
8
PDM Clock Error
VBAT Brown Out
VBAT UVLO
9
10
11
VBAT OVLO
表8-79. IRQZ Internal Pull Up Enable
IRQZ_PU
State
Disabled (default)
0
Enabled
1
表8-80. IRQZ Interrupt Configuration
IRQZ_PIN_CFG[1:0]
Value
IRQZ will assert on any
unmasked live interrupts
00
IRQZ will assert on any
unmasked latched interrupts
(default)
01
10
Reserved
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表8-80. IRQZ Interrupt Configuration (continued)
IRQZ_PIN_CFG[1:0]
Value
Reserved
11
8.4.9 Power Sequencing Requirements
AVDD and IOVDD pins should be connected to the same 1.8 V supply domain. There are no other power
sequencing requirements for order of rate of ramping up or down.
8.4.10 Digital Input Pull Downs
Each digital input and IO has an optional weak pull down to prevent the pin from floating. Pull downs are not
enabled during HW shutdown.
表8-81. Digital Input Pull Down Enables
Register Bit
Description
Bit Value
State
Disabled
0
DIN_PD[0]
Weak pull down for PDMCK.
Enabled (default)
Disabled
1
0
1
0
1
0
1
0
1
DIN_PD[2]
DIN_PD[5]
DIN_PD[6]
DIN_PD[7]
Weak pull down for PDMD.
Weak pull down for FSYNC.
Weak pull down for SDIN.
Weak pull down for SDOUT.
Enabled (default)
Disabled
Enabled (default)
Disabled
Enabled (default)
Disabled
Enabled (default)
8.5 Register Maps
8.5.1 Register Summary Table Book=0x00 Page=0x00
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Register
Description
Section
PAGE
Device Page
节8.5.2.1
节8.5.2.2
节8.5.2.3
节8.5.2.4
节8.5.2.5
节8.5.2.6
节8.5.2.7
节8.5.2.8
节8.5.2.9
节8.5.2.10
节8.5.2.11
节8.5.2.12
节8.5.2.13
节8.5.2.14
节8.5.2.15
节8.5.2.16
节8.5.2.17
节8.5.2.18
SW_RESET
PWR_CTL
PB_CFG0
Software Reset
Power Control
Playback Configuration 0
Playback Configuration 1
Playback Configuration 2
Playback Configuration 3
Misc Configuration
PB_CFG1
PB_CFG2
PB_CFG3
MISC_CFG
PDM_CFG0
PDM_CFG1
TDM_CFG0
TDM_CFG1
TDM_CFG2
TDM_CFG3
TDM_CFG4
TDM_CFG5
TDM_CFG6
TDM_CFG7
PDM Input Register 0
PDM Configuration 1
TDM Configuration 0
TDM Configuration 1
TDM Configuration 2
TDM Configuration 3
TDM Configuration 4
TDM Configuration 5
TDM Configuration 6
TDM Configuration 7
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0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x27
0x28
0x29
0x2A
0x30
0x31
0x32
0x3C
0x77
0x7D
0x7E
0x7F
TDM_CFG8
TDM_CFG9
TDM_CFG10
LIM_CFG0
LIM_CFG1
LIM_CFG2
LIM_CFG3
LIM_CFG4
LIM_CFG5
BOP_CFG0
BOP_CFG1
BOP_CFG2
ICLA_CFG0
ICLA_CFG1
INT_MASK0
INT_MASK1
INT_LIVE0
INT_LIVE1
INT_LTCH0
INT_LTCH1
VBAT_MSB
VBAT_LSB
TEMP_MSB
TEMP_LSB
INT_CFG
TDM Configuration 8
节8.5.2.19
节8.5.2.20
节8.5.2.21
节8.5.2.22
节8.5.2.23
节8.5.2.24
节8.5.2.25
节8.5.2.26
节8.5.2.27
节8.5.2.28
节8.5.2.29
节8.5.2.30
节8.5.2.31
节8.5.2.32
节8.5.2.33
节8.5.2.34
节8.5.2.35
节8.5.2.36
节8.5.2.37
节8.5.2.38
节8.5.2.40
节8.5.2.41
节8.5.2.42
节8.5.2.43
节8.5.2.44
节8.5.2.45
节8.5.2.46
节8.5.2.47
节8.5.2.48
节8.5.2.49
节8.5.2.50
节8.5.2.51
TDM Configuration 9
TDM Configuration 10
Limiter Configuration 0
Limiter Configuration 1
Limiter Configuration 2
Limiter Configuration 3
Limiter Configuration 4
Limiter Configuration 5
Brown Out Prevention 0
Brown Out Prevention 1
Brown Out Prevention 2
Inter Chip Limiter Alignment 0
Inter Chip Limiter Alignment 1
Interrupt Mask 0
Interrupt Mask 1
Live Interrupt Readback 0
Live Interrupt Readback 1
Latched Interrupt Readback 0
Latched Interrupt Readback 1
SAR ADC Conversion 0
SAR ADC Conversion 1
SAR ADC Conversion 2
SAR ADC Conversion 2
Interrupt Configuration
Digital Input Pin Pull Down
Misc Configuration
DIN_PD
MISC_IRQ
CLOCK_CFG
TDM_DET
REV_ID
Clock Configuration
TDM Clock detection monitor
Revision and PG ID
I2C_CKSUM
BOOK
I2C Checksum
Device Book
8.5.2 Register Maps
8.5.2.1 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
The device's memory map is divided into pages and books. This register sets the page.
图8-19. PAGE Register Address: 0x00
7
6
5
4
3
2
1
0
PAGE[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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表8-82. Device Page Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
RW
0h
Sets the device page.
00h = Page 0
01h = Page 1
...
FFh = Page 255
8.5.2.2 SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
Asserting Software Reset will place all register values in their default POR (Power on Reset) state.
图8-20. SW_RESET Register Address: 0x01
7
6
5
4
3
2
1
0
Reserved
RW-0h
SW_RESET
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-83. Software Reset Field Descriptions
Bit
7-1
0
Field
Type
Reset
Description
Reserved
SW_RESET
RW
0h
Reserved
RW
0h
Software reset. Bit is self clearing.
0b = Don't reset
1b = Reset
8.5.2.3 PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
Sets device's mode of operation and power down of IV sense blocks.
图8-21. PWR_CTL Register Address: 0x02
7
6
5
4
3
2
1
0
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
ISNS_PD
RW-1h
VSNS_PD
RW-1h
MODE[1:0]
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-84. Power Control Field Descriptions
Bit
7-6
5
Field
Type
RW
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ISNS_PD
0h
0h
4
0h
3
1h
Current sense power down.
0b = Current sense active
1b = Current sense is powered down
2
VSNS_PD
MODE[1:0]
RW
RW
1h
2h
Voltage sense power down.
0b = voltage sense is active
1b = Voltage sense is powered down
1-0
Device operational mode.
00b = Active
01b = Mute
10b = Software Shutdown
11b = Reserved
8.5.2.4 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
Sets playback source, including PDM input and amplifier output level setting.
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图8-22. PB_CFG0 Register Address: 0x03
7
6
5
4
3
2
1
0
PDM_MAP
RW-0h
PB_PDM_SRC
RW-0h
PB_SRC
RW-0h
AMP_LEVEL[4:0]
RW-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-85. Playback Configuration 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
PDM_MAP
RW
0h
PDM Pin Mapping
0b = PDMD1 for sensor input.
1b = PDMD1 for playback.
6
5
PB_PDM_SRC
PB_SRC
RW
RW
RW
0h
PDM playback source.
0b = PDM input pin defined by PDM_MAP.
1b = Reserved.
0h
Playback source.
0b = PCM
1b = PDM
4-0
AMP_LEVEL[4:0]
10h
Amplifier output level setting.
00h = 11.0 dBV (5.02 Vpk)
01h = 11.5 dBV (5.32 Vpk)
02h = 12.0 dBV (5.63 Vpk)
03h = 12.5 dBV (5.96 Vpk)
04h = 13.0 dBV (6.32 Vpk)
05h = 13.5 dBV (6.69 Vpk)
06h = 14.0 dBV (7.09 Vpk)
07h = 14.5 dBV (7.51 Vpk)
08h = 15.0 dBV (7.95 Vpk)
09h = 15.5 dBV (8.42 Vpk)
0Ah = 16.0 dBV (8.92 Vpk)
0Bh = 16.5 dBV (9.45 Vpk)
0Ch = 17.0 dBV (10.01 Vpk)
0Dh = 17.5 dBV (10.61 Vpk)
0Eh = 18.0 dBV (11.23 Vpk)
0Fh = 18.5 dBV (11.90 Vpk)
10h = 19.0 dBV (12.60 Vpk)
11h = 19.5 dBV (13.35 Vpk)
12h = 20.0 dBV (14.14 Vpk)
13h = 20.5 dBV (14.98 Vpk)
14h = 21.0 dBV (15.87 Vpk)
15h - 1Fh = Reserved
8.5.2.5 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
Sets playback high pass filter corner (PCM playback only).
图8-23. PB_CFG1 Register Address: 0x04
7
6
5
4
3
2
1
0
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
HPF_FREQ[2:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-86. Playback Configuration 1 Field Descriptions
Bit
7
Field
Type
RW
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0h
6
0h
5
0h
4
0h
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表8-86. Playback Configuration 1 Field Descriptions (continued)
Bit
3
Field
Type
Reset
Description
Reserved
HPF_FREQ[2:0]
RW
0h
Reserved
2-0
RW
1h
High Pass Filter Corner Frequency.
000b = Bypass
001b = 2 Hz
010b = 50 Hz
011b = 100 Hz
100b = 200 Hz
101b = 400 Hz
110b = 800 Hz
111b = Reserved
8.5.2.6 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
Sets playback volume for PCM playback path.
图8-24. PB_CFG2 Register Address: 0x05
7
6
5
4
3
2
1
0
DVC_PCM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-87. Playback Configuration 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DVC_PCM[7:0]
RW
0h
PCM digital volume control.
00h = 0 dB
01h = -0.5 dB
02h = -1 dB
....
C7h = -99.5 dB
C8h = -100dB
C9h - FFh = Mute
8.5.2.7 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
Sets playback volume for PDM playback path.
图8-25. PB_CFG3 Register Address: 0x06
7
6
5
4
3
2
1
0
DVC_PDM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-88. Playback Configuration 3 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DVC_PDM[7:0]
RW
0h
PDM digital volume control.
00h = 0 dB
01h = -0.5 dB
02h = -1 dB
....
C7h = -99.5 dB
C8h = -100dB
C9h - FFh = Mute
8.5.2.8 MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
Sets DVC Ramp Rate, IRQZ pull up, amp spread spectrum and I-Sense current range.
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7
6
5
4
3
2
1
0
DVC_RAMP_RATE[1:0]
RW-0h
Reserved
RW-0h
IRQZ_PU
RW-0h
AMP_SS
RW-1h
Reserved
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-89. Misc Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7-6
DVC_RAMP_RATE[1:0]
RW
0h
Digital volume control ramp rate.
00b = 0.5 dB per 1 sample
01b = 0.5 dB per 4 samples
10b = 0.5 dB per 8 samples
11b = Volume ramping disabled
5-4
3
Reserved
IRQZ_PU
RW
RW
0h
0h
Reserved
IRQZ internal pull up enable.
0b = Disabled
1b = Enabled
2
AMP_SS
Reserved
RW
RW
1h
2h
Low EMI spread spectrum enable.
0b = Disabled
1b = Enabled
1-0
Reserved
8.5.2.9 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
Sets Class-D sync mode and PDM sample rates.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
图8-26. PDM_CFG0 Register Address: 0x08
7
6
5
4
3
2
1
0
Reserved
CLASSD_SYN
C
Reserved
RW-0h
PDM_RATE1[1:0]
RW-0h
Reserved
RW-0h
RW-0h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-90. PDM Input Register 0 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
CLASSD_SYNC
RW
0h
Reserved
6
RW
0h
Class-D synchronization mode.
0b = Not synchronized to audio clocks
1b = Synchronized to audio clocks
5-4
3-2
Reserved
RW
RW
0h
0h
Reserved
PDM_RATE1[1:0]
PDMD1 input sample rate.
00b = 2.54 - 3.38 MHz
01b = 5.08 - 6.76 MHz
10b = Reserved
11b = Reserved
1-0
Reserved
RW
0h
Reserved
8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
Sets PDM capture edge, master/slave, clock source and gating.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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图8-27. PDM_CFG1 Register Address: 0x09
7
6
5
4
3
2
1
0
PDM_EDGE1
RW-0h
Reserved
RW-0h
PDM_SLV1
RW-0h
Reserved
RW-0h
PDM_CLK1
RW-1h
Reserved
RW-0h
PDM_GATE1
RW-0h
Reserved
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-91. PDM Configuration 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
PDM_EDGE1
RW
0h
PDMD1 input capture edge.
0b = Rising
1b = Falling
6
5
Reserved
RW
RW
0h
0h
Reserved
PDM_SLV1
PDMD1 input master or slave.
0b = Slave
1b = Master
4
3
Reserved
RW
RW
0h
1h
Reserved
PDM_CLK1
PDMD1 clock select.
0b = GND
1b = PDMCK1
2
1
Reserved
RW
RW
0h
0h
Reserved
PDM_GATE1
PDMD1 clock gate.
0b = Gated Off
1b = Active
0
Reserved
RW
0h
Reserved
8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
Sets the TDM frame start, TDM sample rate, TDM auto rate detection and whether rate is based on 44.1 kHz or
48 kHz frequency.
图8-28. TDM_CFG0 Register Address: 0x0A
7
6
5
4
3
2
1
0
Reserved
RW-0h
RATE_RAMP
RW-0h
AUTO_RATE
RW-0h
SAMP_RATE[2:0]
RW-3h
FRAME_START
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-92. TDM Configuration 0 Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
Reserved
RATE_RAMP
RW
0h
Reserved
RW
0h
Sample rate based on 44.1kHz or 48kHz when
CLASSD_SYNC=1.
0b = 48kHz
1b = 44.1kHz
4
AUTO_RATE
RW
RW
0h
3h
Auto detection of TDM sample rate.
0b = Enabled
1b = Disabled
3-1
SAMP_RATE[2:0]
Sample rate of the TDM bus.
000b = Reserved
001b = Reserved
010b = Reserved
011b = 44.1/48 kHz
100b = 88.2/96 kHz
101b = 176.4/192 kHz
110b = Reserved
111b = Reserved
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表8-92. TDM Configuration 0 Field Descriptions (continued)
Bit
Field
FRAME_START
Type
Reset
Description
0
RW
1h
TDM frame start polarity.
0b = Low to High on FSYNC
1b = High to Low on FSYNC
8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
Sets TDM RX justification, offset and capture edge.
图8-29. TDM_CFG1 Register Address: 0x0B
7
6
5
4
3
2
1
0
Reserved
RW-0h
RX_JUSTIFY
RW-0h
RX_OFFSET[4:0]
RW-1h
RX_EDGE
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-93. TDM Configuration 1 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
RX_JUSTIFY
RW
0h
Reserved
6
RW
0h
TDM RX sample justification within the time slot.
0b = Left
1b = Right
5-1
0
RX_OFFSET[4:0]
RX_EDGE
RW
RW
1h
0h
TDM RX start of frame to time slot 0 offset (SBCLK cycles).
TDM RX capture clock polarity.
0b = Rising edge of SBCLK
1b = Falling edge of SBCLK
8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
Sets TDM RX time slot select, word length and time slot length.
图8-30. TDM_CFG2 Register Address: 0x0C
7
6
5
4
3
2
1
0
Reserved
RW-0h
RX_SCFG[1:0]
RW-0h
RX_WLEN[1:0]
RW-2h
RX_SLEN[1:0]
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-94. TDM Configuration 2 Field Descriptions
Bit
7-6
5-4
Field
Type
Reset
Description
Reserved
RX_SCFG[1:0]
RW
0h
Reserved
RW
0h
TDM RX time slot select config.
00b = Mono with time slot equal to I2C address offset
01b = Mono left channel
10b = Mono right channel
11b = Stereo downmix (L+R)/2
3-2
1-0
RX_WLEN[1:0]
RX_SLEN[1:0]
RW
RW
2h
2h
TDM RX word length.
00b = 16-bits
01b = 20-bits
10b = 24-bits
11b = 32-bits
TDM RX time slot length.
00b = 16-bits
01b = 24-bits
10b = 32-bits
11b = Reserved
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8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
Sets TDM RX left and right time slots.
图8-31. TDM_CFG3 Register Address: 0x0D
7
6
5
4
3
2
1
0
RX_SLOT_R[3:0]
RW-1h
RX_SLOT_L[3:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-95. TDM Configuration 3 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RX_SLOT_R[3:0]
RX_SLOT_L[3:0]
RW
1h
TDM RX Right Channel Time Slot.
TDM RX Left Channel Time Slot.
RW
0h
8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
Sets TDM TX bus keeper, fill, offset and transmit edge.
图8-32. TDM_CFG4 Register Address: 0x0E
7
6
5
4
3
2
1
0
TX_LSB_CFG TX_KEEPER_C TX_KEEPER
FG
TX_FILL
TX_OFFSET[2:0]
TX_EDGE
RW-0h
RW-0h
RW-0h
RW-1h
RW-1h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-96. TDM Configuration 4 Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_LSB_CFG
RW
0h
TDM TX SDOUT LSB data option
0b = TX SDOUT LSB is driven for full-cycle (provided
TX_KEEPER is '0')
1b = TX SDOUT LSB is driven for half-cycle
6
TX_KEEPER_CFG
RW
0h
TDM TX SDOUT bus keeper configuration.
0b = Bus keeper is enabled only for 1 LSB bit cycle & SDOUT
LSB driven for half cycle (provided TX_KEEPER is '1')
1b = Bus keeper is always enabled & SDOUT LSB driven for
half cycle (provided TX_KEEPER is '1')
5
4
TX_KEEPER
TX_FILL
RW
RW
0h
1h
TDM TX SDOUT bus keeper enable.
0b = Disable bus keeper
1b = Enable bus keeper
TDM TX SDOUT unused bitfield fill.
0b = Transmit 0
1b = Transmit Hi-Z
3-1
0
TX_OFFSET[2:0]
TX_EDGE
RW
RW
1h
1h
TDM TX start of frame to time slot 0 offset.
TDM TX launch clock polarity.
0b = Rising edge of SBCLK
1b = Falling edge of SBCLK
8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
Sets TDM TX V-Sense time slot and enable.
图8-33. TDM_CFG5 Register Address: 0x0F
7
6
5
4
3
2
1
0
Reserved
VSNS_TX
VSNS_SLOT[5:0]
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图8-33. TDM_CFG5 Register Address: 0x0F (continued)
RW-0h
RW-0h
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-97. TDM Configuration 5 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
VSNS_TX
RW
0h
Reserved
6
RW
0h
TDM TX voltage sense transmit enable.
0b = Disabled
1b = Enabled
5-0
VSNS_SLOT[5:0]
RW
2h
TDM TX voltage sense time slot. It is recommended to maintain
the following order:
ISNS_SLOT<VSNS_SLOT<PDM_SLOT<VBAT_SLOT<TEMP_
SLOT<GAIN_SLOT
8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
Sets TDM TX I-Sense time slot and enable.
图8-34. TDM_CFG6 Register Address: 0x10
7
6
5
4
3
2
1
0
Reserved
RW-0h
ISNS_TX
RW-0h
ISNS_SLOT[5:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-98. TDM Configuration 6 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
ISNS_TX
RW
0h
Reserved
6
RW
0h
TDM TX current sense transmit enable.
0b = Disabled
1b = Enabled
5-0
ISNS_SLOT[5:0]
RW
0h
TDM TX current sense time slot. It is recommended to maintain
the following order:
ISNS_SLOT<VSNS_SLOT<PDM_SLOT<VBAT_SLOT<TEMP_
SLOT<GAIN_SLOT
8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
Sets TDM TX time slot and transmit enable for decimated PDM.
图8-35. TDM_CFG7 Register Address: 0x11
7
6
5
4
3
2
1
0
Reserved
RW-0h
PDM_TX
RW-0h
PDM_SLOT[5:0]
RW-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-99. TDM Configuration 7 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
PDM_TX
RW
0h
Reserved
6
RW
0h
TDM TX decimated PDM transmit enable.
0b = Disabled
1b = Enabled
5-0
PDM_SLOT[5:0]
RW
4h
TDM TX decimated PDM time slot.
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8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
Sets TDM TX VBAT time slot and enable.
图8-36. TDM_CFG8 Register Address: 0x12
7
6
5
4
3
2
1
0
VBAT_SLEN
RW-0h
VBAT_TX
RW-0h
VBAT_SLOT[5:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-100. TDM Configuration 8 Field Descriptions
Bit
Field
Type
Reset
Description
7
VBAT_SLEN
RW
0h
TDM TX VBAT time slot length.
0b = Truncate to 8-bits
1b = Left justify to 16-bits
6
VBAT_TX
RW
RW
0h
6h
TDM TX VBAT transmit enable.
0b = Disabled
1b = Enabled
5-0
VBAT_SLOT[5:0]
TDM TX VBAT time slot.
8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
Sets TDM TX temp time slot and enable.
图8-37. TDM_CFG9 Register Address: 0x13
7
6
5
4
3
2
1
0
Reserved
RW-0h
TEMP_TX
RW-0h
TEMP_SLOT[5:0]
RW-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-101. TDM Configuration 9 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
TEMP_TX
RW
0h
Reserved
6
RW
0h
TDM TX temp sensor transmit enable.
0b = Disabled
1b = Enabled
5-0
TEMP_SLOT[5:0]
RW
7h
TDM TX temp sensor time slot.
8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
Sets TDM TX limiter gain reduction time slot and enable.
图8-38. TDM_CFG10 Register Address: 0x14
7
6
5
4
3
2
1
0
Reserved
RW-0h
GAIN_TX
RW-0h
GAIN_SLOT[5:0]
RW-8h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-102. TDM Configuration 10 Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
RW
0h
Reserved
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表8-102. TDM Configuration 10 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
GAIN_TX
RW
0h
TDM TX limiter gain reduction transmit enable.
0b = Disabled
1b = Enabled
5-0
GAIN_SLOT[5:0]
RW
8h
TDM TX limiter gain reduction time slot.
8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
Sets Limiter attack step size, attack rate and enable.
图8-39. LIM_CFG0 Register Address: 0x15
7
6
5
4
3
2
1
0
Reserved
RW-0h
LIM_ATK_ST[1:0]
RW-1h
LIM_ATK_RT[2:0]
RW-2h
LIM_EN
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-103. Limiter Configuration 0 Field Descriptions
Bit
7-6
5-4
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
LIM_ATK_ST[1:0]
RW
1h
Limiter/ICLA attack step size.
00b = 0.25 dB
01b = 0.5 dB
10b = 1 dB
11b = 2 dB
3-1
LIM_ATK_RT[2:0]
RW
2h
Limiter/ICLA attack rate.
000b = 5 us/step
001b = 10 us/step
010b = 20 us/step
011b = 40 us/step
100b = 80 us/step
101b = 160 us/step
110b = 320 us/step
111b = 640 us/step
0
LIM_EN
RW
0h
Limiter enable.
0b = Disabled
1b = Enabled
8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
Sets limiter release step size, release rate and hold time.
图8-40. LIM_CFG1 Register Address: 0x16
7
6
5
4
3
2
1
0
LIM_RLS_ST[1:0]
RW-1h
LIM_RLS_RT[2:0]
RW-6h
LIM_HLD_TM[2:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-104. Limiter Configuration 1 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
LIM_RLS_ST[1:0]
RW
1h
Limiter/BOP/ICLA release step size.
00b = 0.25 dB
01b = 0.5 dB
10b = 1 dB
11b = 2 dB
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表8-104. Limiter Configuration 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-3
LIM_RLS_RT[2:0]
RW
6h
Limiter/BOP/ICLA release rate.
000b = 10 ms/step
001b = 50 ms/step
010b = 100 ms/step
011b = 250 ms/step
100b = 500 ms/step
101b = 750 ms/step
110b = 1000 ms/step
111b = 1500 ms/step
2-0
LIM_HLD_TM[2:0]
RW
6h
Limiter hold time.
000b = 0 ms
001b = 10 ms
010b = 25 ms
011b = 50 ms
100b = 100 ms
101b = 250 ms
110b = 500 ms
111b = 1000 ms
8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
Sets limiter VBAT tracking slope and max attenuatio.
图8-41. LIM_CFG2 Register Address: 0x17
7
6
5
4
3
2
1
0
Reserved
RW-0h
LIM_MAX_ATN[4:0]
RW-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-105. Limiter Configuration 2 Field Descriptions
Bit
7-5
4-0
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
LIM_MAX_ATN[4:0]
RW
10h
Limiter max attenuation.
00h = 1 dB
01h = 1.5 dB
...
10h = 9 dB
...
1Eh = 16 dB
1Fh = 16.5 dB
8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
Sets Limiter max threshold.
图8-42. LIM_CFG3 Register Address: 0x18
7
6
5
4
3
2
1
0
Reserved
RW-0h
LIM_TH_MAX[6:0]
RW-6Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-106. Limiter Configuration 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
RW
0h
Reserved
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表8-106. Limiter Configuration 3 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-0
LIM_TH_MAX[6:0]
RW
6Eh
Limiter max threshold.
00h = 2 V
01h = 2.1 V
...
6Eh = 13 V
...
7Eh = 14.6 V
7Fh = 14.7 V
8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
Sets limiter min threshold.
图8-43. LIM_CFG4 Register Address: 0x19
7
6
5
4
3
2
1
0
Reserved
RW-0h
LIM_TH_MIN[6:0]
RW-1Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-107. Limiter Configuration 4 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
6-0
LIM_TH_MIN[6:0]
RW
1Eh
Limiter min threshold.
00h = 2 V
01h = 2.1 V
...
1Eh = 5 V
...
7Eh = 14.6 V
7Fh = 14.7 V
8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
Sets limiter inflection point.
图8-44. LIM_CFG5 Register Address: 0x1A
7
6
5
4
3
2
1
0
Reserved
RW-0h
LIM_INF_PT[6:0]
RW-58h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-108. Limiter Configuration 5 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
6-0
LIM_INF_PT[6:0]
RW
58h
Limiter inflection point.
00h = 2 V
01h = 2.1 V
...
58h = 10.8 V
...
7Eh = 14.6 V
7Fh = 14.7 V
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8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
Sets BOP infinite hold clear, infinite hold enable, mute on brown out and enable.
图8-45. BOP_CFG0 Register Address: 0x1B
7
6
5
4
3
2
1
0
Reserved
EN_BO_RECO
VERY_HYSTE
RSIS
LIM_SLOPE[1:0]
BOP_HLD_CLR BOP_INF_HLD
BOP_MUTE
BOP_EN
RW-0h
RW-0h
RW-0h
RW-0h
RW-0h
RW-0h
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-109. Brown Out Prevention 0 Field Descriptions
Bit
7
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
6
EN_BO_RECOVERY_HYSTERSIS RW
0h
5-4
LIM_SLOPE[1:0]
RW
0h
Limiter VBAT tracking slope.
00b = 1 V/V
01b = 1.5 V/V
10b = 2 V/V
11b = 4 V/V
3
2
1
0
BOP_HLD_CLR
BOP_INF_HLD
BOP_MUTE
BOP_EN
RW
RW
RW
RW
0h
0h
0h
1h
BOP infinite hold clear (self clearing).
0b = Don't clear
1b = Clear
Infinite hold on brown out event.
0b = Use BOP_HLD_TM after brown out event
1b = Don't release until BOP_HLD_CLR is asserted high
Mute on brown out event.
0b = Don't mute
1b = Mute followed by device shutdown
Brown out prevention enable.
0b = Disabled
1b = Enabled
8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
BOP threshold.
图8-46. BOP_CFG1 Register Address: 0x1C
7
6
5
4
3
2
1
0
BOP_TH[7:0]
RW-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-110. Brown Out Prevention 1 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BOP_TH[7:0]
RW
14h
Brown out prevention threshold.
00h = 4.5 V
01h = 4.525 V
...
14h = 5.0 V
...
FEh = 10.85 V
FFh = 10.875 V
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8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
BOP attack rate, attack step size and hold time.
图8-47. BOP_CFG2 Register Address: 0x1D
7
6
5
4
3
2
1
0
BOP_ATK_RT[2:0]
RW-2h
BOP_ATK_ST[1:0]
RW-1h
BOP_HLD_TM[2:0]
RW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-111. Brown Out Prevention 2 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
BOP_ATK_RT[2:0]
RW
2h
Brown out prevention attack rate.
000b = 5 us/step
001b = 10 us/step
010b = 20 us/step
011b = 40 us/step
100b = 80 us/step
101b = 160 us/step
110b = 320 us/step
111b = 640 us/step
4-3
2-0
BOP_ATK_ST[1:0]
BOP_HLD_TM[2:0]
RW
RW
1h
6h
Brown out prevention attack step size.
00b = 0.5 dB
01b = 1 dB
10b = 1.5 dB
11b = 2 dB
Brown out prevention hold time.
000b = 0 ms
001b = 10 ms
010b = 25 ms
011b = 50 ms
100b = 100 ms
101b = 250 ms
110b = 500 ms
111b = 1000 ms
8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
ICLA starting time slot and enable.
图8-48. ICLA_CFG0 Register Address: 0x1E
7
6
5
4
3
2
1
0
ICLA_USE_MA
X
ICLA_SLOT[5:0]
RW-0h
ICLA_EN
RW-0h
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-112. Inter Chip Limiter Alignment 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
ICLA_USE_MAX
RW
0h
Inter chip limiter alignment min/max config
0b = Use the maximum of the ICLA group gain reduction
1b = Use the minimum of the ICLA group gain reduction
6-1
0
ICLA_SLOT[5:0]
ICLA_EN
RW
RW
0h
0h
Inter chip limiter alignment starting time slot.
Inter chip limiter alignment enable.
0b = Disabled
1b = Enabled
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8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
ICLA time slot enables.
图8-49. ICLA_CFG1 Register Address: 0x1F
7
6
5
4
3
2
1
0
ICLA_SEN[7]
RW-0h
ICLA_SEN[6]
RW-0h
ICLA_SEN[5]
RW-0h
ICLA_SEN[4]
RW-0h
ICLA_SEN[3]
RW-0h
ICLA_SEN[2]
RW-0h
ICLA_SEN[1]
RW-0h
ICLA_SEN[0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-113. Inter Chip Limiter Alignment 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
ICLA_SEN[7]
RW
0h
Time slot equals ICLA_SLOT[5:0]+7. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
6
5
4
3
2
1
0
ICLA_SEN[6]
ICLA_SEN[5]
ICLA_SEN[4]
ICLA_SEN[3]
ICLA_SEN[2]
ICLA_SEN[1]
ICLA_SEN[0]
RW
RW
RW
RW
RW
RW
RW
0h
0h
0h
0h
0h
0h
0h
Time slot equals ICLA_SLOT[5:0]+6. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]+5. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]+4. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]+3. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]+2. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]+1. When enabled, the limiter
will include this time slot in the alignment group.
0b = Disabled
1b = Enabled
Time slot equals ICLA_SLOT[5:0]. When enabled, the limiter will
include this time slot in the alignment group.
0b = Disabled
1b = Enabled
8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
Interrupt masks.
图8-50. INT_MASK0 Register Address: 0x20
7
6
5
4
3
2
1
0
INT_MASK[7]
RW-1h
INT_MASK[6]
RW-1h
INT_MASK[5]
RW-1h
INT_MASK[4]
RW-1h
INT_MASK[3]
RW-1h
INT_MASK[2]
RW-1h
INT_MASK[1]
RW-0h
INT_MASK[0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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表8-114. Interrupt Mask 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK[7]
INT_MASK[6]
INT_MASK[5]
INT_MASK[4]
INT_MASK[3]
INT_MASK[2]
INT_MASK[1]
INT_MASK[0]
RW
1h
Limiter mute mask.
0b = Don't Mask
1b = Mask
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
1h
1h
1h
1h
1h
0h
0h
Limiter infinite hold mask.
0b = Don't Mask
1b = Mask
Limiter max attenuation mask.
0b = Don't Mask
1b = Mask
VBAT <N521 Inflection Point mask.
0b = Don't Mask
1b = Mask
Limiter active mask.
0b = Don't Mask
1b = Mask
TDM clock error mask.
0b = Don't Mask
1b = Mask
Over current error mask.
0b = Don't Mask
1b = Mask
Over temp error mask.
0b = Don't Mask
1b = Mask
8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
Interrupt masks.
图8-51. INT_MASK1 Register Address: 0x21
7
6
5
4
3
2
1
0
INT_MASK[14]
RW-1h
Reserved
RW-0h
Reserved
RW-1h
Reserved
RW-1h
INT_MASK[11] INT_MASK[10] INT_MASK[9]
RW-0h RW-0h RW-0h
INT_MASK[8]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-115. Interrupt Mask 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK[14]
RW
1h
PDM audio data invalid mask.
0b = Don't Mask
1b = Mask
6
5
4
3
Reserved
RW
RW
RW
RW
0h
1h
1h
0h
Reserved
Reserved
Reserved
Reserved
Reserved
INT_MASK[11]
VBAT OVLO mask.
0b = Don't Mask
1b = Mask
2
1
INT_MASK[10]
INT_MASK[9]
RW
RW
0h
0h
VBAT UVLO mask.
0b = Don't Mask
1b = Mask
VBAT Brown out mask
0b = Don't Mask
1b = Mask
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表8-115. Interrupt Mask 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
INT_MASK[8]
RW
1h
PDM clock error mask.
0b = Don't Mask
1b = Mask
8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
Live interrupt readback.
图8-52. INT_LIVE0 Register Address: 0x22
7
6
5
4
3
2
1
0
INT_LIVE[7]
R-0h
INT_LIVE[6]
R-0h
INT_LIVE[5]
R-0h
INT_LIVE[4]
R-0h
INT_LIVE[3]
R-0h
INT_LIVE[2]
R-0h
INT_LIVE[1]
R-0h
INT_LIVE[0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-116. Live Interrupt Readback 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE[7]
R
0h
Interrupt due to limiter mute.
0b = No interrupt
1b = Interrupt
6
5
4
3
2
1
0
INT_LIVE[6]
INT_LIVE[5]
INT_LIVE[4]
INT_LIVE[3]
INT_LIVE[2]
INT_LIVE[1]
INT_LIVE[0]
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
Interrupt due to limiter infinite hold.
0b = No interrupt
1b = Interrupt
Interrupt due to limiter max attenuation.
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT below limiter inflection point.
0b = No interrupt
1b = Interrupt
Interrupt due to limiter active.
0b = No interrupt
1b = Interrupt
Interrupt due to TDM clock error.
0b = No interrupt
1b = Interrupt
Interrupt due to over current error.
0b = No interrupt
1b = Interrupt
Interrupt due to over temp error.
0b = No interrupt
1b = Interrupt
8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
Live interrupt readback.
图8-53. INT_LIVE1 Register Address: 0x23
7
6
5
4
3
2
1
0
INT_LIVE[15]
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
INT_LIVE[11]
R-0h
INT_LIVE[10]
R-0h
INT_LIVE[9]
R-0h
INT_LIVE[8]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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表8-117. Live Interrupt Readback 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE[15]
R
0h
Interrupt due to PDM audio data invalid
0b = No interrupt
1b = Interrupt
6
5
4
3
Reserved
Reserved
Reserved
INT_LIVE[11]
R
R
R
R
0h
0h
0h
0h
Reserved
Reserved
Reserved
Interrupt due to VBAT OVLO flag.
0b = No interrupt
1b = Interrupt
2
1
0
INT_LIVE[10]
INT_LIVE[9]
INT_LIVE[8]
R
R
R
0h
0h
0h
Interrupt due to VBAT UVLO flag.
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT brown out flag.
0b = No interrupt
1b = Interrupt
Interrupt due to PDM clock error.
0b = No interrupt
1b = Interrupt
8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
Latched interrupt readback.
图8-54. INT_LTCH0 Register Address: 0x24
7
6
5
4
3
2
1
0
INT_LTCH[7]
R-0h
INT_LTCH[6]
R-0h
INT_LTCH[5]
R-0h
INT_LTCH[4]
R-0h
INT_LTCH[3]
R-0h
INT_LTCH[2]
R-0h
INT_LTCH[1]
R-0h
INT_LTCH[0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-118. Latched Interrupt Readback 0 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH[7]
R
0h
Interrupt due to limiter mute (read to clear).
0b = No interrupt
1b = Interrupt
6
5
4
3
2
1
INT_LTCH[6]
INT_LTCH[5]
INT_LTCH[4]
INT_LTCH[3]
INT_LTCH[2]
INT_LTCH[1]
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
Interrupt due to limiter infinite hold (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to limiter max attenuation (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT < limiter inflection point (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to limiter active (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to TDM clock error (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to over current error (read to clear).
0b = No interrupt
1b = Interrupt
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表8-118. Latched Interrupt Readback 0 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
INT_LTCH[0]
R
0h
Interrupt due to over temp error (read to clear).
0b = No interrupt
1b = Interrupt
8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
Latched interrupt readback.
图8-55. INT_LTCH1 Register Address: 0x25
7
6
5
4
3
2
1
0
INT_LTCH[15]
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
INT_LTCH[11] INT_LTCH[10]
R-0h R-0h
INT_LTCH[9]
R-0h
INT_LTCH[8]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-119. Latched Interrupt Readback 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH[15]
R
0h
Interrupt due to PDM audio data invalid. (read to clear).
0b = No interrupt
1b = Interrupt
6
5
4
3
Reserved
R
R
R
R
0h
0h
0h
0h
Reserved
Reserved
Reserved
Reserved
Reserved
INT_LTCH[11]
Interrupt due to VBAT OVLO flag (read to clear).
0b = No interrupt
1b = Interrupt
2
1
0
INT_LTCH[10]
INT_LTCH[9]
INT_LTCH[8]
R
R
R
0h
0h
0h
Interrupt due to VBAT UVLO flag (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to VBAT brown out flag (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to PDM clock error (read to clear).
0b = No interrupt
1b = Interrupt
8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
表8-120. INT_LTCH2 Register Address: 0x26
7
6
5
4
3
2
1
0
INT_LTCH[23] INT_LTCH[22] INT_LTCH[21] INT_LTCH[20] INT_LTCH[19] INT_LTCH[18] INT_LTCH[17] INT_LTCH[16]
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-121. INT_LTCH2 Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH[23]
R
0h
Interrupt due to clock halt flag (read to clear)
0b = No interrupt
1b = Interrupt
6
INT_LTCH[22]
R
0h
Interrupt due to DMA Request to DSP lost flag (read to clear)
0b = No interrupt
1b = Interrupt
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表8-121. INT_LTCH2 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
INT_LTCH[21]
INT_LTCH[20]
INT_LTCH[19]
INT_LTCH[18]
INT_LTCH[17]
INT_LTCH[16]
R
0h
Interrupt due to Auto Trim converged status (read to clear)
0b = No interrupt
1b = Interrupt
4
3
2
1
0
R
R
R
R
R
0h
0h
0h
1h
0h
Interrupt due to Class D Clamp status flag (read to clear)
0b = No interrupt
1b = Interrupt
Interrupt due to HIGH SIDE OC flag (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to LOW SIDE OC flag (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to LDO 5 V PG flag (read to clear).
0b = No interrupt
1b = Interrupt
Interrupt due to LDO 5 V OL (read to clear).
0b = No interrupt
1b = Interrupt
8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
MSBs of SAR ADC VBAT conversion.
图8-56. VBAT_MSB Register Address: 0x27
7
6
5
4
3
2
1
0
VBAT_CNV[11:4]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-122. SAR ADC Conversion 0 Field Descriptions
Bit
Field
Type
Reset
Description
7--4
VBAT_CNV[11:0]
R
0h
Returns SAR ADC VBAT conversion MSBs.
8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
LSBs of SAR ADC VBAT conversion.
图8-57. VBAT_LSB Register Address: 0x28
7
6
5
4
3
2
1
0
VBAT_CNV[3:0]
R-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-123. SAR ADC Conversion 1 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
VBAT_CNV[3:0]
Reserved
R
0h
Returns SAR ADC VBAT conversion LSBs.
Reserved
R
0h
8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
SARD ADC Temp conversion.
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图8-58. TEMP_MSB Register Address: 0x29
7
6
5
4
3
2
1
0
TMP_CNV[11:4]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-124. SAR ADC Conversion 2 Field Descriptions
Bit
Field
Type
Reset
Description
7--4
TMP_CNV[11:0]
R
0h
Returns SAR ADC temp sensor conversion.
8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
SARD ADC Temp conversion.
图8-59. TEMP_LSB Register Address: 0x2A
7
6
5
4
3
2
1
0
TMP_CNV[3:0]
-0h
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-125. SAR ADC Conversion 2 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
TMP_CNV[3:0]
Reserved
0h
Returns SAR ADC temp sensor conversion.
Reserved
R
0h
8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
Sets whether latched or live interrupts will trigger IRQZ pin.
图8-60. INT_CFG Register Address: 0x30
7
6
5
4
3
2
1
0
Reserved
RW-0h
IRQZ_PIN_CFG[1:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-126. Interrupt Configuration Field Descriptions
Bit
7-2
1-0
Field
Type
Reset
Description
Reserved
RW
0h
Reserved
IRQZ_PIN_CFG[1:0]
RW
1h
IRQZ interrupt configuration.
00b = IRQZ will assert on any unmasked live interrupts
01b = IRQZ will assert on any unmasked latched interrupts
10b = IRQZ will assert for 2ms one time on any unmasked live
interrupt event
11b = IRQZ will assert for 2ms every 4ms on any unmasked
latched interrupts
8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
Sets enables of input pin weak pull down.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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图8-61. DIN_PD Register Address: 0x31
7
6
5
4
3
2
1
0
DIN_PD[7]
RW-0h
DIN_PD[6]
RW-0h
DIN_PD[5]
RW-0h
DIN_PD[4]
RW-0h
Reserved
RW-0h
DIN_PD[2]
RW-0h
Reserved
RW-0h
DIN_PD[0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-127. Digital Input Pin Pull Down Field Descriptions
Bit
Field
Type
Reset
Description
7
DIN_PD[7]
RW
0h
Weak pull down for SDOUT
0b = Disabled
1b = Enabled
6
5
4
DIN_PD[6]
DIN_PD[5]
DIN_PD[4]
RW
RW
RW
0h
0h
0h
Weak pull down for SDIN.
0b = Disabled
1b = Enabled
Weak pull down for FSYNC.
0b = Disabled
1b = Enabled
Weak pull down for SBCLK.
0b = Disabled
1b = Enabled
3
2
Reserved
RW
RW
0h
0h
Reserved
DIN_PD[2]
Weak pull down for PDMD1.
0b = Disabled
1b = Enabled
0
0
Reserved
RW
RW
0h
0h
Reserved
DIN_PD[0]
Weak pull down for PDMCK1.
0b = Disabled
1b = Enabled
8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
Set IRQZ pin active state
图8-62. MISC_IRQ Register Address: 0x32
7
6
5
4
3
2
1
0
IRQZ_POL
RW-1h
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
Reserved
RW-0h
IRQZ_VAL
R-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-128. Misc Configuration Field Descriptions
Bit
Field
Type
Reset
Description
7
IRQZ_POL
RW
1h
IRQZ pin polarity for interrupt.
0b = Active high (IRQ)
1b = Active low (IRQZ)
6-4
3
Reserved
Reserved
Reserved
Reserved
IRQZ_VAL
RW
RW
RW
RW
R
0h
0h
0h
0h
1h
Reserved
Reserved
Reserved
Reserved
2
1
0
IRQZ bit bang in read value. Default is 1b'1 if there are no
interupts/errors
0b = IRQZ Input Buffer Value=0
1b = IRQZ Input Buffer Value=1
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8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
Can override audio configure and set the clocking ratio
图8-63. CLOCK_CFG Register Address: 0x3C
7
6
5
4
3
2
1
0
Reserved
RW-0h
Reserved
RW-0h
SBCLK_FS_RATIO[3:0]
RW-3h
AUTO_CLK[1:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-129. Clock Configuration Field Descriptions
Bit
7
Field
Type
RW
RW
RW
Reset
Description
Reserved
Reserved
Reserved
0h
6
Reserved
0h
5-2
SBCLK_FS_RATIO[3:0]
3h
Program manually SBCLK to FS ratio when auto clock detection
is disabled
00h = 16
01h = 24
02h = 32
03h = 48
04h = 64
05h = 96
06h = 128
07h = 192
08h = 256
09h = 384
0Ah = 512
1-0
AUTO_CLK[1:0]
RW
1h
Clocking automatic configuraiton
00b = Auto configure clock dividers based on SBCLK to FSYNC
ratio
01b = Manually configure clock dividers by programming
SBCLK_FS_RATIO
8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
Readback of internal auto-rate detection.
图8-64. TDM_DET Register Address: 0x77
7
6
5
4
3
2
1
0
Reserved
R-0h
FS_RATIO[3:0]
R-Fh
FS_RATE_V[2:0]
R-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-130. TDM Clock detection monitor Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
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表8-130. TDM Clock detection monitor Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-3
FS_RATIO[3:0]
R
Fh
Detected SBCLK to FSYNC ratio.
00h = 16
01h = 24
02h = 32
03h = 48
04h = 64
05h = 96
06h = 128
07h = 192
08h = 256
09h = 384
0Ah = 512
0Bh-0Eh = Reserved
0F = Invalid ratio
2-0
FS_RATE_V[2:0]
R
7h
Detected sample rate of TDM bus.
000b = Reserved
001b = Reserved
010b = Reserved
011b = 44.1/48 KHz
100b = 88.2/96 kHz
101b = 176.4/192 kHz
110b = Reserved
111b = Error condition
8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
Returns REV and PG ID.
图8-65. REV_ID Register Address: 0x7D
7
6
5
4
3
2
1
0
REV_ID[3:0]
PG_ID[3:0]
R-0h
R-1h ( TAS2770 QFN Rev A)
R-2h ( TAS2770 QFN Rev B)
R- 4h ( TAS2770 WCSP Rev B)
R- 5h ( TAS2770 WCSP Rev C)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-131. Revision and PG ID Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
REV_ID[3:0]
PG_ID[3:0]
R
(see above table)
0h
Returns the revision ID.
Returns the PG ID.
R
8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
Returns I2C checksum.
图8-66. I2C_CKSUM Register Address: 0x7E
7
6
5
4
3
2
1
0
I2C_CKSUM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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表8-132. I2C Checksum Field Descriptions
Bit
Field
Type
Reset
Description
7-0
I2C_CKSUM[7:0]
RW
0h
Returns I2C checksum. Writing to this register will reset the
checksum to the written value. This register is updated on writes
to other registers on all books and pages.
8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
Device's memory map is divided into pages and books. This register sets the book.
图8-67. BOOK Register Address: 0x7F
7
6
5
4
3
2
1
0
BOOK[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-133. Device Book Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BOOK[7:0]
RW
0h
Sets the device book.
00h = Book 0
01h = Book 1
...
FFh = Book 255
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TAS2770 is a digital input Class-D audio power amplifier with integrated I/V sense. I2S audio data is
supplied by host processor. It also accepts I/V data in I2S format. I2C bus is used for configuration and control.
9.2 Typical Application
图9-1 below shows a typical configuration of the TAS2770.
1.65 VÀ
1.95 V
2.9 V À
16 V
C7
1 mF
C8
0.1 mF
C6
0.1 mF
C4
0.1 mF
C2
0.1 mF
C1
10 mF
C3
10 mF
C5
1 mF
AREG
AVDD
VBAT
DREG
IOVDD
1.65 V À
1.95 V
C10
0.1 mF
C9
1 mF
VSENSE_P
VSENSE_M
C11
0.1 mF
TAS2770
BST_P
SPK_P
SPK_M
BST_M
L1 (opt.)
L2 (opt.)
+
-
Enable
SDZ
2
To
Speaker
2
I2C Address Select
I2C Interface
MODE
I2C
C14
(opt.)
C13
(opt.)
C12
0.1 mF
2
5
I2S Interface
I2S
GND
PGND
2
Copyright © 2016, Texas Instruments Incorporated
图9-1. TAS2770 Typical Application
表9-1. Recommended External Components
COMPONENT DESCRIPTION SPECIFICATIO MIN
N
TYP
MAX
UNIT
NOTES
µF
V
C1
VBAT
Capacitance
10
25
22
Decoupling
Capacitor
Rated Voltage
µF
V
C2
VBAT
Capacitance
0.1
25
Decoupling
Capacitor
Rated Voltage
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表9-1. Recommended External Components (continued)
COMPONENT DESCRIPTION SPECIFICATIO MIN
N
TYP
MAX
UNIT
NOTES
µF
V
C3
C4
C5
C6
AVDD
Capacitance
1
10
Decoupling
Capacitor
Rated Voltage
10
µF
V
AVDD
Capacitance
0.1
10
Decoupling
Capacitor
Rated Voltage
µF
V
AREG
Capacitance
0.68
10
1
1.5
Decoupling
Capacitor
Rated Voltage
µF
AREG
Capacitance
0.1
C5 + C6 <
1.5µF
Decoupling
Capacitor
Rated Voltage
10
V
µF
C7
C8
DREG
Capacitance
0.68
10
1
1.5
Decoupling
Capacitor
Rated Voltage
V
µF
DREG
Capacitance
0.1
C7 + C8 <
1.5µF
Decoupling
Capacitor
Rated Voltage
10
1
V
µF
C9
IOVDD
Capacitance
Decoupling
Capacitor
Rated Voltage
10
V
µF
V
C10
C11
IOVDD
Capacitance
0.1
10
Decoupling
Capacitor
Rated Voltage
µF
V
Class-D
Positive
Boostrap
Capacitor
Capacitance
0.1
0.12
0.12
Rated Voltage
25
Class-D
µF
V
C12
Capacitance
0.1
1
Negative
Boostrap
Capacitor
Rated Voltage
25
25
C13, C14
EMI Filter
Capacitance
nF
V
Capacitors
(optional).
Rated Voltage
Optional
inductors L1
and L2 must be
connected
when the EMI
Filter capacitors
are placed
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表9-1. Recommended External Components (continued)
COMPONENT DESCRIPTION SPECIFICATIO MIN
N
TYP
MAX
UNIT
NOTES
Ω
L1, L2
EMI Filter
Impedance at
100MHz
120
Inductors
(optional).
Ω
A
DC Resistance
DC Current
Size
0.095
6
SPK_P pin
4
must be directly
connected to
VSENSE_P
when the
0402
EIA
inductors are
used. Optional
capacitors C13
and C14 must
be connected
when the EMI
filter inductors
are placed
9.2.1 Design Requirements
表9-2 shows the design parameters.
表9-2. Recommended Component Selection
PARAMETER
Amplifier power supply (VBAT)
EVM power supply
EXAMPLE VALUE
4.5 V to 16 V
4.5 V to 16 V
1.65 V to 1.95 V
18.3 W
IO power supply (IOVDD)
Output Power
USB, USB class-audio
Micro-USB B
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9.2.2 Detailed Design Procedure
9.2.2.1 Overview
The TAS2770 is a flexible and easy-to-use Class D amplifier. Therefore, the design process is straightforward.
Before beginning the design, gather the following information regarding the audio system:
• VBAT rail planned for the design
• Speaker or load impedance
• Audio sample rate
• Maximum output power requirement
9.2.2.2 Select Input Capacitance
Select the bulk capacitors at the VBAT inputs for proper voltage margin and adequate capacitance to support the
power requirements. The TAS2770 has very good PSRR, so the capacitor is more about limiting the ripple and
droop for the rest of system than preserving good audio performance. The amount of bulk decoupling can be
reduced as long as the droop and ripple is acceptable. One capacitor should be placed near the VBAT pin.
VBATY capacitors should be a low ESR type because they are being used in a high-speed switching application.
9.2.2.3 Select Decoupling Capacitors
Good quality decoupling capacitors should be added at each of the VBAT input to provide good reliability, good
audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, the decoupling capacitors should be located near the VBAT and GND connections to the device to
minimize series inductances.
9.2.2.4 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.1-µF, 25-V capacitors of X5R quality or better.
9.2.3 Application Curves
40
20
10
5
50
10
VBAT = 12.6 V
VBAT = 8.4
VBAT = 4.5
VBAT = 12.6 V
VBAT = 8.4
VBAT = 4.5
2
1
0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
0.005
0.01
0.002
0.001
0.004
10
100
1k
Frequency (%)
10k
20k
0.00001 0.0001
0.001
0.01
Output Power (W)
0.1
1
10 20
D002
D002
图9-2. THD+N vs Frequency
图9-3. THD+N vs Output Power (W)
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9.3 Initialization Set Up
9.3.1 Initial Device Configuration - Auto Rate
The following I2C sequence is an example of initializing four TAS5770LC0 devices. The devices will be
configured to use the TDM auto-rate detection feature. This sequence contains a 1 ms delay required after a
software or hardware reset as illustrated in 节10.
备注
For TAS2770 the device I2C address needs to be changed. See 表8-1.
w 62 00 00 # Page-0
w 62 7f 00 # Book-0
w 62 01 01 # Software Reset
w 64 00 00 # Page-0
w 64 7f 00 # Book-0
w 64 01 01 # Software Reset
w 66 00 00 # Page-0
w 66 7f 00 # Book-0
w 66 01 01 # Software Reset
w 68 00 00 # Page-0
w 68 7f 00 # Book-0
w 68 01 01 # Software Reset
d 1 # 1mS Delay
###### Configure Channel 1
w 62 3c 11 # sbclk to fs ratio = 64
w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 62 0f 42 # TDM TX voltage sense transmit enable with slot 2,
w 62 10 40 # TDM TX current sense transmit enable with slot 0
w 62 03 14 # 21 dB gain
w 62 02 00 # power up audio playback with I,V enabled
###### Configure Channel 2
w 64 3c 11 # sbclk to fs ratio = 64
w 64 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 64 0f 46 # TDM TX voltage sense transmit enable with slot 6,
w 64 10 44 # TDM TX current sense transmit enable with slot 4
w 64 03 14 # 21 dB gain
w 64 02 00 # power up audio playback with I,V enabled
###### Configure Channel 3
w 66 3c 11 # sbclk to fs ratio = 64
w 66 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 66 0f 4A # TDM TX voltage sense transmit enable with slot 10,
w 66 10 48 # TDM TX current sense transmit enable with slot 8
w 66 03 14 # 21 dB gain
w 66 02 00 # power up audio playback with I,V enabled
###### Configure Channel 4
w 68 3c 11 # sbclk to fs ratio = 64
w 68 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 68 0f 4E # TDM TX voltage sense transmit enable with slot 14,
w 68 10 4C # TDM TX current sense transmit enable with slot 12
w 68 03 14 # 21 dB gain
w 68 02 00 # power up audio playback with I,V enabled
9.3.2 Initial Device Configuration - 48 kHz
The following I2C sequence is an example of initializing a TAS5770LC0 device into 48 kHz sampling rate. This
sequence contains a 1 ms delay required after a software or hardware reset as illustrated in 节10.
备注
For TAS2770 the device I2C address needs to be changed. See 表8-1.
w 62 00 00 # Page-0
w 62 7f 00 # Book-0
w 62 01 01 # Software Reset
d 1 # 1mS Delay
###### Configure Channel 1
w 62 3c 21 # sbclk to fs ratio = 256 / 8 TDM Slots
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w 62 0a 17 # 48KHz, Auto TDM off, Frame start High to Low
w 62 0b 03 # Offset = 1, Sync on BCLK falling edge
w 62 0c 0a # TDM slot by address, Word = 24 bit, Frame = 32 bit
w 62 0d 20 # Right Ch = TDM slot 2, Left Ch = TDM slot 0
w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 62 0f 42 # TDM TX voltage sense transmit enable with slot 2,
w 62 10 40 # TDM TX current sense transmit enable with slot 0
w 62 03 14 # 21 dB gain
w 62 02 00 # power up audio playback with I,V enabled
9.3.3 Initial Device Configuration - 44.1 kHz
The following I2C sequence is an example of initializing a TAS5770LC0 device into 48 kHz sampling rate. This
sequence contains a 1 ms delay required after a software or hardware reset as illustrated in 节10.
备注
For TAS2770 the device I2C address needs to be changed. See 表8-1.
w 62 00 00 # Page-0
w 62 7f 00 # Book-0
w 62 01 01 # Software Reset
d 1 # 1mS Delay
###### Configure Channel 1
w 62 3c 21 # sbclk to fs ratio = 256 / 8 TDM Slots
w 62 0a 37 # 44.1KHz, Auto TDM off, Frame start High to Low
w 62 0b 03 # Offset = 1, Sync on BCLK falling edge
w 62 0c 0a # TDM slot by address, Word = 24 bit, Frame = 32 bit
w 62 0d 20 # Right Ch = TDM slot 2, Left Ch = TDM slot 0
w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edge
w 62 0f 42 # TDM TX voltage sense transmit enable with slot 2,
w 62 10 40 # TDM TX current sense transmit enable with slot 0
w 62 03 14 # 21 dB gain
w 62 02 00 # power up audio playback with I,V enabled
9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
The following I2C sequence is an example of changing the sampling rate from 48 kHz to 44.1 kHz .
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 01 #Mute
d 1
w 62 02 02 #Software shutdown
w 62 0a 37 #44.1KHz, Auto TDM off, Frame start High to Low
### change source sample rate now
w 62 02 01 #Take device out of low-power shutdown
d 1
w 62 02 00 #Un-mute
9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
The following I2C sequence is an example of changing the sampling rate from 44.1 kHz to 48 kHz .
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 01 #Mute
d 1
w 62 02 02 #Software shutdown
w 62 0a 17 #44.1KHz, Auto TDM off, Frame start High to Low
### change source sample rate now
w 62 02 01 #Take device out of low-power shutdown
d 1
w 62 02 00 #Un-mute
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9.3.6 Device Mute
The following I2C sequence will mute one device at address 62 using a digital volume ramp rate of 0.5 dB per 8
samples.
备注
For TAS2770 the device I2C address is 82
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 01 #Mute
9.3.7 Device Un-Mute
The following I2C sequence will un-mute one device at address 62 using a digital volume ramp rate of 0.5 dB per
8 samples.
备注
For TAS2770 the device I2C address is 82
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 00 #Un-Mute
9.3.8 Device Sleep
The following I2C sequence will mute the device and put it into low power mode for one device at address 62
using a digital volume ramp rate of 0.5 dB per 8 samples.
备注
For TAS2770 the device I2C address is 82
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 01 #Mute
d 1 # 1mS Delay
w 62 02 02 #Software shutdown
9.3.9 Device Wake
The following I2C sequence will wake the device from low power mode (sleep) and un-mute one device at
address 62 using a digital volume ramp rate of 0.5 dB per 8 samples.
备注
For TAS2770 the device I2C address is 82
w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samples
w 62 02 01 #Take device out of low-power shutdown
d 1 # 1mS Delay
w 62 02 00 #Un-mute TAS2770
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10 Power Supply Recommendations
The power sequence between the supply rails can be applied in any order as long as SDZ pin is held low.
Generally VBAT would be applied before IOVDD and AVDD in most system applications. Once all supplies are
stable the SDZ pin can be set high to initialize the part. After a hardware or software reset additional commands
to the device should be delayed for 1 mS to allow the OTP to load.
VBAT
IOVDD
AVDD
Tdelay >= 50us (from stable supply)
Tdelay >= 50us
SDZ
I2C
Tdelay >= 1ms (reset to first I2C command)
图10-1. Power Supply Sequence for Power-Up and Power-Down
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11 Layout
11.1 Layout Guidelines
Pay special attention to the power stage power supply layout.
• Use 4.7 µf for decoupling of VBAT supply.
• Keep the current circulating loops containing the supply decoupling capacitors, the H-bridges in the device
and the connections to the speakers as tight as possible to reduce emissions.
• Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. The area directly under the device should be treated as a central ground area for the
device, and all device grounds must be connected directly to that area.
• Use a via pattern to connect the area directly under the device to the ground planes in copper layers below
the surface. This connection helps to dissipate heat from the device.
• Avoid interrupting the ground plane with circular traces around the device. Interruption disconnects the
copper and interrupt flow of heat and current. Radial copper traces are better to use if necessary.
11.2 Layout Example
图11-1. Stereo EVM Layout Diagram
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图11-2. Stereo EVM Layout Reference Design - 01
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图11-3. Stereo EVM Layout Reference Design - 02
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图11-4. Layout Reference –TAS2770RJQ
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图11-5. Layout Reference –TAS2770YFF
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
12.3 Trademarks
所有商标均为其各自所有者的财产。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS2770RJQR
TAS2770RJQT
TAS2770YFFR
TAS2770YFFT
TAS5770LC0YFFR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
DSBGA
RJQ
RJQ
YFF
YFF
YFF
26
26
30
30
30
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2770
2770
2770
2770
Samples
Samples
Samples
Samples
Samples
NIPDAU
SNAGCU
SNAGCU
SNAGCU
DSBGA
DSBGA
TAS5770LC0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS2770RJQR
TAS2770RJQT
VQFN-
HR
RJQ
RJQ
26
26
3000
250
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q2
VQFN-
HR
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q2
TAS2770YFFR
TAS2770YFFT
DSBGA
DSBGA
YFF
YFF
30
30
3000
250
180.0
180.0
8.4
8.4
2.13
2.13
2.66
2.66
0.69
0.69
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS2770RJQR
TAS2770RJQT
TAS2770YFFR
TAS2770YFFT
VQFN-HR
VQFN-HR
DSBGA
RJQ
RJQ
YFF
YFF
26
26
30
30
3000
250
346.0
210.0
182.0
182.0
346.0
185.0
182.0
182.0
33.0
35.0
20.0
20.0
3000
250
DSBGA
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0030
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
F
E
D: Max = 2.549 mm, Min =2.489 mm
E: Max = 2.038 mm, Min =1.977 mm
D
C
SYMM
2
TYP
B
A
0.4 TYP
1
2
4
5
3
0.3
30X
0.4 TYP
0.2
0.015
C A B
4219433/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
30X ( 0.23)
(0.4) TYP
2
4
5
1
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219433/A 03/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
30X ( 0.25)
(R0.05) TYP
1
3
2
4
5
A
B
(0.4)
TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219433/A 03/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJQ0026A
A
4.1
3.9
B
PIN 1 INDEX AREA
3.6
3.4
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.8
PKG
(0.24)
0.8
0.6
1.35
1.15
(0.76)
13
2X
3X
0.1 (TYP)
(0.06)
6
(0.572)
0.95
0.75
2X
14
(1.049)
5
(0.201)
1.02
0.82
PKG
2
1.6
(0.278)
22X 0.4
19
1
0.25
0.15
0.25
0.15
(0.728)
(0.651)
26X
0.1
C A B
C
20
0.56
0.36
26
(0.226)
1.22
1.02
0.05
0.33
0.23
0.5
14X
(0.926)
0.3
2.4
1.2
1
(0.474)
2X
4223791/C 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJQ0026A
(1.12)
(0.66)
(0.28)
PKG
20
26
(0.9)
(1.05)
(0.2)
1.01
(1.32)
1
19
0.93
0.61
0.21
0.53
(1.3)
(1.3)
PKG
0.13
(3.3)
0.27
22X (0.4)
0.67
0.19
5
0.59
1.07
2X
(1.45)
14
26X (0.2)
2X
(0.9)
(1.05)
14X (0.6)
13
6
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223791/C 05/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJQ0026A
(0.28)
PKG
2X (0.75)
(0.66)
26
20
(0.66)
(0.2)
4X (0.56)
1
19
1.01
0.93
(0.76)
0.61
0.21
0.53
2X
(0.55)
PKG
0.13
(3.3)
0.27
0.19
0.59
22X (0.4)
2X (0.83)
0.67
5
1.07
14
15X (0.2)
2X (0.63)
3X (0.55)
14X (0.6)
13
6
4X (0.625)
4X (0.425)
(R0.05) TYP
6X (0.35)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
84% PRINTED COVERAGE BY AREA
SCALE: 20X
4223791/C 05/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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