TAS5111DAD [TI]
DIGITAL AMPLIFIER POWER STAGE; 数字放大器功率级
| 型号： | TAS5111DAD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL AMPLIFIER POWER STAGE |
| 文件： | 总16页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLES049D − JULY 2003 − REVISED MARCH 2004
www.ti.com
TM
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D
Home Theatre
FEATURES
D
Mini/Micro Component Systems
Internet Music Appliance
D
D
D
70-W RMS Power (BTL) Into 4 Ω With Less
Than 0.2% THD+N
D
95-dB Dynamic Range (TDAA System With
TAS5026)
DESCRIPTION
Power Efficiency Greater Than 90% Into 4-Ω
and 8-Ω Loads
− Smaller Power Supplies
The TAS5111 is a high-performance digital amplifier power
stage designed to drive a 4-Ω speaker up to 70 W with
0.2% distortion plus noise. The device incorporates TI’s
PurePath Digital technology and is used with a digital
audio PWM processor (TAS50XX) and a simple passive
demodulation filter to deliver high-quality, high-efficiency
digital audio amplification.
D
D
D
D
Self-Protecting Design With Autorecovery
32-Pin TSSOP (DAD) PowerPAD Package
3.3-V Digital Interface
EMI-Compliant When Used With
Recommended System Design
The efficiency of this digital amplifier can be greater than
90%, depending on the system design. Overcurrent
protection, overtemperature protection, and undervoltage
protection are built into the TAS5111, safeguarding the
device and speakers against fault conditions that could
damage the system.
APPLICATIONS
D
DVD Receiver
THD + NOISE vs OUTPUT POWER
THD + NOISE vs FREQUENCY
1
1
R
= 4 Ω
= 75°C
R
= 4 Ω
= 75°C
L
L
T
C
T
C
P
O
= 70 W
0.1
P
O
= 1 W
0.1
P
O
= 10 W
0.01
0.01
0.001
100m
1
10
100
20
100
1k
f − Frequency − Hz
10k 20k
P
− Output Power − W
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
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Copyright 2004, Texas Instruments Incorporated
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SLES049D − JULY 2003 − REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
Terminal Assignment
TAS5111
DVDD TO DGND
UNITS
–0.3 V to 4.2 V
33.5 V
33.5 V
48 V
The TAS5111 is offered in a thermally enhanced 32-pin
TSSOP surface-mount package (DAD), which has the
thermal pad on top.
GVDD TO GND
PVDD_X TO GND (dc voltage)
PVDD_X TO GND (spike voltage
OUT_X TO GND (dc voltage)
DAD PACKAGE
(TOP VIEW)
(2)
)
)
33.5 V
48 V
(2)
OUT_X TO GND (spike voltage
BST_X TO GND (dc voltage)
BST_X TO GND (spike voltage
PWM_BP
GND
GVDD
GND
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
48 V
RESET
DREG_RTN
GREG
M3
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
3
(2)
)
53 V
4
(3)
GREG TO GND
14.2 V
5
PWM_XP, RESET, M1, M2, M3, SD,
OTW
6
–0.3 V to DVDD + 0.3 V
DREG
DGND
M1
7
Maximum operating junction
8
–40°C to 150°C
–40°C to 125°C
temperature, T
J
GND
9
Storage temperature
M2
DVDD
SD
DGND
OTW
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GND
10
11
12
13
14
15
16
(1)
Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-
maximum-ratedconditions for extended periods may affect device
reliability.
PWM_AP
GVDD
(2)
(3)
The duration of a voltage spike should be less than 100 ns.
GREG is treated as an input when the GREG pin is overdriven by
a GVDD voltage of 12 V.
PACKAGE DISSIPATION RATINGS
R
R
θJC
θJA
PACKAGE
(°C/W)
(°C/W)
32-Pin DAD TSSOP
1.69
See Note 1
(1)
The TAS5111 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only means for
heat dissipation.
For this reason, R
thermaltreatment, is provided in theApplication Information section
a system parameter that characterizes the
θJA,
of the data sheet. An example and discussion of typical system
R
θJA
values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipationratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed. Also, for additional general information on
PowerPad packages, see TI document SLMA002.
ORDERING INFORMATION
T
A
PACKAGE
DESCRIPTION
0°C to 70°C
TAS5111DAD
32-pin small TSSOP
For the most current specification and package
information, refer to the TI Web site at www.ti.com.
2
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TERMINAL
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SLES049D − JULY 2003 − REVISED MARCH 2004
Terminal Functions
(1)
FUNCTION
DESCRIPTION
NAME
BST_A
NO.
19
30
8, 13
7
P
P
P
P
P
P
P
High side bootstrap supply (BST), external capacitor to OUT_A required
High side bootstrap supply (BST), external capacitor to OUT_B required
I/O reference ground
BST_B
DGND
DREG
Digital supply voltage regulator decoupling pin, capacitor connected to DREG_RTN
Decoupling return pin
DREG_RTN
DVDD
4
11
I/O reference supply input (3.3 V): 100 Ω to DREG
Power ground
GND
2,15, 18,
24, 25,
31
GREG
GVDD
M1
5
17, 32
9
P
P
I
Gate drive voltage regulator decoupling pin, capacitor to GND
Voltage supply to on-chip gate drive and digital supply voltage regulators
Mode selection pin
M2
10
I
Mode selection pin
M3
6
I
Mode selection pin
OTW
14
O
O
O
P
P
I
Overtemperature warning output, open drain with internal pullup resistor
Output, half-bridge A
OUT_A
OUT_B
PVDD_A
PVDD_B
PWM_AP
PWM_BP
RESET
SD
22, 23
26, 27
20, 21
28, 29
16
Output, half-bridge B
Power supply input for half-bridge A
Power supply input for half-bridge B
Input signal, half-bridge A
1
I
Input signal, half-bridge B
3
I
Reset signal, active low
12
O
Shutdown signal for half-bridges A and B
(1)
I = input, O = Output, P = Power
3
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SLES049D − JULY 2003 − REVISED MARCH 2004
FUNCTIONAL BLOCK DIAGRAM
BST_A
GREG
PVDD_A
Gate
Drive
OUT_A
GND
PWM_AP
PWM
Timing
Control
Receiver
Gate
Drive
Protection A
BST_B
RESET
GREG
PVDD_B
Protection B
Gate
Drive
PWM_BP
OUT_B
GND
PWM
Receiver
Timing
Control
Gate
Drive
To Protection
Blocks
DREG
DREG
GVDD
OTW
SD
GREG
OT
Protection
UVP
GREG
GREG
DREG
GREG
DREG_RTN
DREG_RTN
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SLES049D − JULY 2003 − REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
(1)
DVDD
GVDD
Digital supply
Relative to DGND
Relative to GND
3
3.3
3.6
V
Supply for internal gate drive and logic
regulators
16
29.5
29.5
30.5
V
PVDD_x Half-bridge supply
Junction temperature
Relative to GND, R = 4 Ω to 8 Ω
0
0
30.5
125
V
L
T
J
_C
(1)
It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, R = 4 Ω, 8X f = 384 kHz, unless otherwise noted
L
s
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
T
= 40°C
MIN/TYP/
MAX
A
T
A
= 25°C
T
A
= 25°C
T = 75°C
C
UNITS
to 85°C
AC PERFORMANCE, BTL Mode, 1 kHz
R
= 8 Ω, THD = 0.2%,
L
40
53
53
68
74
93
W
W
W
W
W
W
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
AES17 filter
R
filter
= 8 Ω, THD = 10%, AES17
L
R
L
= 6 Ω, THD = 0.2%,
AES17 filter
Po
Output power
R
filter
= 6 Ω, THD = 10%, AES17
L
R
L
= 4 Ω, THD = 0.2%,
AES17 filter
R
filter
= 4 Ω, THD = 10%, AES17
L
Po = 1 W/ channel, R = 4 Ω,
AES17 filter
L
0.05%
0.03%
0.2%
Po = 10 W/channel, R = 4 Ω,
AES17 filter
Total harmonic
distortion + noise
L
THD+N
Po = 70 W/channel, R = 4 Ω,
AES17 filter
L
Output integrated
voltage noise
A-weighted, mute, R = 4 Ω,
20 Hz to 20 kHz, AES17 filter
L
V
295
95
µV
dB
dB
Max
Typ
Typ
n
SNR
DR
Signal-to-noise ratio
A-weighted, AES17 filter
f = 1 kHz, A-weighted,
AES17 filter
Dynamic range
95
INTERNAL VOLTAGE REGULATOR
V
V
V
V
Min
Max
Min
I
= 1 mA,
o
DREG
Voltage regulator
Voltage regulator
3.1
PVDD = 18 V−30.5 V
I
o
= 1.2 mA,
GREG
IVGDD
IDVDD
13.4
PVDD = 18 V−30.5 V
f = 384 kHz, no load,
S
Max
GVDD supply current,
operating
27
5
mA
mA
Max
Max
50% duty cycle
DVDD supply current,
operating
f
S
= 384 kHz, no load
1
OUTPUT STAGE MOSFETs
Forward on-resistance,
low side
R
T = 25°C
120
120
132
132
mΩ
mΩ
Max
Max
on,LS
on,HS
J
Forward on-resistance,
high side
R
T = 25°C
J
5
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SLES049D − JULY 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, connected to DREG via a 100-Ω resistor, R = 4 Ω, 8X f = 384 kHz, unless otherwise noted
L
s
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
T
= 40°C
MIN/TYP/
MAX
A
T
A
= 25°C
T
A
= 25°C
T = 75°C
C
UNITS
to 85°C
INPUT/OUTPUT PROTECTION
Set the DUT in normal
operation mode with all the
protections enabled. Sweep
GVDD up and down. Monitor
SD output. Record the
GREG reading when SD is
triggered.
6.9
7.9
V
Min
Undervoltage protection
limit, GVDD
V
7.4
uvp,G
V
Max
Typ
Overtemperature
warning
OTW
125
°C
OTE
OC
Overtemperature error
Overcurrent protection
150
8
°C
Typ
Typ
See Note 1.
A
STATIC DIGITAL SPECIFICATION
PWM_AP, PWM_BP,
M1, M2, M3, SD, OTW
2
V
V
Min
Max
Max
Min
V
V
High-level input voltage
Low-level input voltage
IH
DVDD
0.8
−10
10
V
IL
µA
µA
Leakage
Input leakage current
Max
OTW/SHUTDOWN (SD)
Internally pull up R from
28
22
kΩ
Min
OTW/SD to DVDD
V
OL
Low-level output voltage
I
O
= 4 mA
0.4
V
Max
(1)
To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See
DemodulationFilter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for
optimalperformance. It is also important to consider PCB design and layout for optimum performance of the TAS5111. It is recommended to follow
the TAS5026-5111KEVM (S/N 001) design and layout guidelines for best performance.
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SLES049D − JULY 2003 − REVISED MARCH 2004
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
Gate-Drive
Power Supply
External Power Supply
H-Bridge
Power Supply
1000 µF
TAS5111DAD
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
PWM_AP_1
PWM_AM_1
PWM_BP
GND
GVDD
GND
100 nF
100 nF
1.5 Ω
RESET
DREG_RTN
GREG
M3
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
VALID_1
1.5 Ω
33 nF
L
100 nF
100 nF
PCB
10 µH
4.7 kΩ
DREG
DGND
M1
PWM PROCESSOR
TAS5026
10 kΩ
{
{
470 nF
100 nF
100 nF
GND
10
11
12
13
14
15
16
10 µH
4.7 kΩ
10 kΩ
M2
OUT_A
OUT_A
100 Ω
22
21
20
19
DVDD
L
PCB
SD
PVDD_A
PVDD_A
BST_A
100 nF
DGND
OTW
33 nF
1.5 Ω
ERR_RCVY
100 nF
1.5 Ω
18
17
GND
GND
PWM_AP
GVDD
100 nF
L
: TRACK IN THE PCB (1,0 mm wide and 50 mm long)
PCB
{
Voltage suppressor diodes: 1SMA33CAT
7
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SLES049D − JULY 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE
OF TAS5111 EVM WITH TAS5026 PROCESSOR
TOTAL HARMONIC DISTORTION + NOISE
NOISE AMPLITUDE
vs
vs
FREQUENCY
FREQUENCY
1
0
−20
R
T
= 4 Ω
= 75°C
−60 dB Input
= 75°C
L
C
T
C
TAS5026 Front End Device
−40
P
O
= 70 W
0.1
−60
P
O
= 1 W
−80
−100
−120
−140
−160
P
O
= 10 W
0.01
0.001
0
2
4
6
8
10 12 14 16 18 20 22
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − kHz
Figure 1
Figure 2
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
vs
OUTPUT POWER
H-BRIDGE VOLTAGE
1
90
80
70
60
50
40
30
20
10
0
R
T
= 4 Ω
= 75°C
T
A
= 75°C
L
C
R
L
= 4 Ω
0.1
R
L
= 6 Ω
R
L
= 8 Ω
0.01
0
4
8
12
16
20
24
28
32
100m
1
10
100
P
O
− Output Power − W
VDD − Supply Voltage − V
Figure 3
Figure 4
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SLES049D − JULY 2003 − REVISED MARCH 2004
SYSTEM OUTPUT STAGE EFFICIENCY
POWER LOSS
vs
vs
OUTPUT POWER
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
14
12
10
8
f = 1 kHz
R
= 4 Ω
= 75°C
L
T
C
6
4
f = 1 kHz
2
R
= 4 Ω
= 75°C
L
T
C
0
0
10
20
30
40
50
60
70
80
0
10
20
30
P − Output Power − W
O
40
50
60
70
80
P
O
− Output Power − W
Figure 5
Figure 6
OUTPUT POWER
vs
ON-STATE RESISTANCE
vs
CASE TEMPERATURE
JUNCTION TEMPERATURE
90
85
80
75
70
65
60
200
190
180
170
160
150
140
130
120
110
100
PVDD = 29.5 V
R
L
= 4 Ω
0
20
40
60
80
100
120
140
0
25
50
75
100
125
T
C
− Case Temperature − °C
T
J
− Junction Temperature − °C
Figure 7
Figure 8
9
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SLES049D − JULY 2003 − REVISED MARCH 2004
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor (see the Typical
TAS5111 Application Configuration section).
THEORY OF OPERATION
POWER SUPPLIES
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
back-end bootstrap capacitor is charged.
The power device only requires two supply voltages,
GVDD and PVDD_X.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turnon
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal LDRs to 3.3 V.
RESET can now be released if the modulator is powered
up and streaming valid PWM signals to the back-end
PWM_xP. Valid means a switching PWM signal which
complies with the frequency and duty cycle ranges stated
in the Recommended Operating Conditions.
A constant HIGH dc level on the PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually runs out of BST capacitor energy and might
damage the device.
The gate-driver LDR can be bypassed for reducing idle
loss in the device by shorting GREG to GVDD and directly
feeding in 12 V. This can be useful in an application where
thermal conduction of heat from the device is difficult.
Bypassing the LDR reduces dissipation by approximately
1 W at 30-V GVDD input.
An unknown state of the PWM output signals from the
modulator is not permitted, which in practice means that
the PWM processor must be powered up and initialized
before RESET is de-asserted HIGH to the back end.
PVDD_X is the H-bridge power supply pin. Two power
pins exist for each half-bridge to handle the current density.
It is important that the circuitry recommendations around
the PVDD_X pins are followed carefully both topology-
and layout-wise. For topology recommendations, see the
Typical System Configuration section. For layout
recommendations, see the reference design layout for the
TAS5111. Following these recommendations is important
for parameters like EMI, reliability, and performance.
POWERING DOWN
For power down of the back end, an opposite approach is
necessary. The RESET must be asserted LOW before the
valid PWM signal is removed.
When TI TDAA modulators are used with TI TDAA back
ends, the correct timing control of RESET and PWM_xP
is performed by the modulator.
POWERING UP
PRECAUTION
> 1 ms
The TAS5111 must always start up in the high-impedance
(Hi-Z) state. In this state, the bootstrap (BST) capacitor is
precharged by a resistor on each PWM output node to
ground. See the system configuration. This ensures that
the back end is ready for receiving PWM pulses, indicating
either HIGH- or LOW-side turnon after RESET is
de-asserted to the back end.
> 1 ms
RESET
GVDD
With the following pulldown resistor and BST capacitor
size, the charge time is:
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
PVDD_x
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the
back-end BST is charged and ready. RESET can now be
released if the PWM modulator is ready and is streaming
valid PWM signals to the back end. Valid PWM signals are
switching PWM signals with a frequency between
350−400 kHz. A constant HIGH level on the PWM+ would
force the high side MOSFET ON until it eventually ran out
of BST capacitor energy. Putting the device in this
condition should be avoided.
PWM_xP
NOTE: PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are at this point
not charged. To comply with the click and pop scheme and
use of non-TI TDAA modulators, it is recommended to use
a 4-kΩ pulldown resistor on each PWM output node to
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In practice, this means that the DVDD-to-PWM processor
(front-end) should be stable and initialization should be
completed before RESET is de-asserted to the back end.
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
Overcurrent (OC) Protection
CONTROL I/O
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Filter Demodulation Design in the
Application Information section of the data sheet for design
constraints.
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other front-end device. The pin is open-drain with an
internal pullup to DVDD.
Overtemperature (OT) Protection
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125°C. The OT protection circuit is shared by all
half-bridges.
SD
0
RESET
DESCRIPTION
0
1
Not used
0
Device in protection mode, i.e., UVP and/or OC
and/or OT error
Undervoltage (UV) Protection
(1)
1
1
0
1
Device set high-impedance (Hi-Z), SD forced high
Normal operation
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
(1)
SD is pulled high when RESET is asserted low independent of chip
state (i.e., protection mode). This is desirable to maintain
compatibilitywith some TI PWM front ends.
Temperature Warning Pin: OTW
Reset Function
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup to DVDD.
The function of the reset input is twofold:
D
D
Reset is used for re-enabling operation after a
latching error event.
OTW
DESCRIPTION
0
1
Junction temperature higher than 125°C
Junction temperature lower than 125°C
Reset is used for disabling output stage
switching (mute function).
Overall Reporting
In PMODEs where the reset input functions as the means
to re-enable operation after an error event, the error latch
is cleared on the falling edge of reset and normal operation
is resumed when reset goes high.
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
Table 1. Error Signal Decoding
OTW
SD
0
DESCRIPTION
PROTECTION MODE
0
0
1
1
Overtemperatureerror (OTE)
1
Overtemperature warning (OTW)
Overcurrent (OC) or undervoltage (UVP) error
Normal operation, no errors/warnings
Autorecovery (AR) After Errors (PMODE0)
0
1
In autorecovery mode (PMODE0) the TAS5111 is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time the
device autorecovers, i.e., operation is automatically
resumed provided that the system is fully operational.
Chip Protection
The TAS5111 protection function is implemented in a
closed loop with, for example, a system controller or other
TI PWM processor (front-end) device. The TAS5111
contains three individual systems protecting the device
against misuse. All of the error events covered result in the
output stage being set in a high-impedance state (Hi-Z) for
maximum protection of the device and connected
equipment.
The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.
The AR system is common to both half-bridges.
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Timing and Function
Table 3. Output Mode Selection
M3
0
OUTPUT MODE
Bridge-tied load output stage (BTL)
Reserved
The function of the autorecovery circuit is as follows:
1. An error event occurs and sets the
protection latch (output stage goes Hi-Z).
1
2. The counter is started.
APPLICATION INFORMATION
3. After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).
DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS
The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application note
SLEA025.
4. After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).
Error
Protection
Latch
The TDAA amplifier outputs are driven by heavy-duty
DMOS transistors in an H-bridge configuration. These
transistors are either off or fully on, which reduces the
DMOS transistor on-state resistance, R(DMOSon), and
the power dissipated in the device, thereby increasing
efficiency.
Shutdown
SD
Autorecovery
PWM
The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 10.
Counter
AR-RESET
Figure 9. Autorecovery Function
TAS51xx
Latching Shutdown on All Errors (PMODE1)
L
Output A
In latching shutdown mode, all error situations result in a
power down (output stage Hi-Z). Re-enabling can be done
by toggling the RESET pin.
R
(Load)
C1A
All Protection Systems Disabled (PMODE2)
C2
C1B
In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.
L
Output B
MODE Pins Selection
Figure 10. Demodulation Filter
The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.
The main purpose of the output filter is to attenuate the
high-frequency switching component of the TDAA
amplifier while preserving the signals in the audio band.
Table 2. Protection Mode Selection
Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance
should remain stable within the range of peak current seen
at maximum output power and deliver at least 5 µH of
inductance at 15 A.
M1 M2
PROTECTION MODE
Autorecovery after errors (PMODE 0)
Latching shutdown on all errors (PMODE 1)
All protection systems disabled (PMODE 2)
Reserved
0
0
1
1
0
1
0
1
The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.
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If this rule is observed, the TAS5111 does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.
THERMAL INFORMATION
The thermally augmented package provided with the
TAS5111 is designed to be interfaced directly to a heatsink
using a thermal interface compound (for example,
Wakefield Engineering type 126 thermal grease.) The
heatsink then absorbs heat from the ICs and couples it to
the local air. If the heatsink is carefully designed, this
process can reach equilibrium and heat can be continually
removed from the ICs. Because of the efficiency of the
TAS5111, heatsinks are smaller than those required for
linear amplifiers of equivalent performance.
Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.
In general, 10-µH inductors suffice for most applications.
The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10 µH.
R
is a system thermal resistance from junction to
θ
JA
ambient air. As such, it is a system parameter with roughly
the following components:
The graph in Figure 11 displays the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5111.
D
R
(the thermal resistance from junction to
JC
θ
case, or in this case the metal pad)
Thermal grease thermal resistance
Heatsink thermal resistance
D
D
INDUCTANCE
vs
CURRENT
R
has been provided in the General Information
θ
JC
section.
11
The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer’s area thermal resistance (expressed in
DBF1310A
10
2
°C-in /W). The area thermal resistance of the example
9
thermal grease with a 0.001-inch thick layer is about
DASL983XX−1023
8
2
0.054°C-in /W. The approximate exposed pad area is
2
0.0164 in .
Dividing the example thermal grease area resistance by
the area of the pad gives the actual resistance through the
thermal grease, 3.3°C/W.
7
6
5
4
Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Thus, for a single monaural IC, the system R
= R
+
JC
θ
θ
JA
thermal grease resistance + heatsink resistance.
0
5
10
I − Current − A
15
The following table indicates modeled parameters for one
TAS5111 IC on a heatsink. The junction temperature is set
at 110°C in both cases while delivering 70 W RMS into 4-Ω
loads with no clipping. It is assumed that the thermal
grease is about 0.001 inch thick (this is critical).
Figure 11. Inductance Saturation
The selection of the capacitor that is placed across the
output of each inductor (C2 in Figure 10) is simple. To
complete the output filter, use a 0.47-µF capacitor with a
voltage rating at least twice the voltage applied to the
output stage (PVDD).
32-Pin TSSOP
Ambient temperature
25°C
Power to load
70 W
Delta T inside package
Delta T through thermal grease
Required heatsink thermal resistance
Junction temperature
12.3°C
21.1°C
8.2°C/W
110°C
13.2°C/W
85°C
This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.
In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-µF, 50-V, SMD capacitors (X7R
or better) (C1A and C1B in Figure 10) should be added
from the output of each inductor to ground.
System R
θJA
R
θJA
× power dissipation
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As an indication of the importance of keeping the thermal
grease layer thin, if the thermal grease layer increases to
0.002 inches thick, the required heatsink thermal
resistance changes to 2.4°C/W.
Other things that can affect the audible click level:
D
The spectrum of the click seems to follow the
speaker impedance vs. frequency curve—the
higher the impedance, the higher the click
energy.
D
Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.
Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click is.
3,91 mm
3,31 mm
Thermal
Pad
The following mode transitions feature click and pop
reduction.
CLICK AND
POP REDUCED
STATE
(1)
Normal
→
→
Mute
Yes
Yes
(1)
Mute
Normal
Error recovery
(ERRCVY)
(1)
Normal
→
Yes
(1)
Error recovery
→
→
→
Normal
Yes
No
(1)
Normal
4,11 mm
3,35 mm
Hard Reset
(1)
Normal
Hard Reset
Yes
(1)
Normal = switching
REFERENCES
1. TAS5000 Digital Audio PWM Processor data
manual—TI (SLAS270)
CLICK AND POP REDUCTION
2. True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet—TI (SLES009)
Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.
3. True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet—TI (SLAS328)
4. True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet—TI (SLES006)
To make this system work properly, the following design
rules must be followed when using the TAS5111 back end:
5. TAS5026 Six-Channel Digital Audio PWM
Processor data manual—TI (SLES041)
D
The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.
6. TAS5036A Six-Channel Digital Audio PWM
Processor data manual—TI (SLES061)
7. TAS3103 Digital Audio Processor With 3D Effects
data manual—TI (SLES038)
8. Digital Audio Measurements application report—TI
D
The output stage must start switching from a
fully discharged output filter capacitor. Because
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
(SLAA114)
9. PowerPAD Thermally Enhanced Package
technical brief—TI (SLMA002)
10. System Design Considerations for True Digital
Audio Power Amplifiers application report—TI
(SLAA117)
output to GND
(see Typical System
Configuration).
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15
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