TAS5112ADFDG4 [TI]
DIGITAL AMPLIIFIER POWER STAGE; 数字AMPLIIFIER功率级型号: | TAS5112ADFDG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | DIGITAL AMPLIIFIER POWER STAGE |
文件: | 总22页 (文件大小:535K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
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TM
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FEATURES
APPLICATIONS
D
D
D
D
DVD Receiver
Home Theatre
Mini/Micro Component Systems
Internet Music Appliance
D
D
D
D
D
D
50 W per Channel (BTL) Into 6 Ω (Stereo)
95-dB Dynamic Range With TAS5026
Less Than 0.1% THD+N (1 W RMS Into 6 Ω)
Less Than 0.2% THD+N (50 W RMS into 6 Ω)
DESCRIPTION
Power Efficiency Typically 90% Into 6-Ω Load
The TAS5112A is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-Ω
speakers at up to 50 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.
Self-Protecting Design (Undervoltage,
Overtemperature and Short Conditions) With
Error Reporting
D
D
Internal Gate Drive Supply Voltage Regulator
EMI Compliant When Used With
Recommended System Design
The efficiency of this digital amplifier is typically 90%,
reducing the size of both the power supplies and heatsinks
needed. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5112A, safeguarding the device and speakers against
fault conditions that could damage the system.
THD + NOISE vs OUTPUT POWER
1
THD + NOISE vs FREQUENCY
1
R
= 6 Ω
= 75°C
R
= 6 Ω
= 75°C
L
L
T
C
T
C
P
O
= 50 W
0.1
P
O
= 10 W
0.1
P
O
= 1 W
0.01
0.01
0.001
100m
1
10
100
20
100
1k
f - Frequency - Hz
10k 20k
P
- Output Power - W
O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
ꢋꢎ ꢏ ꢆꢑ ꢒ ꢀꢇ ꢏꢓ ꢆ ꢁꢀꢁ ꢔꢕ ꢖꢗ ꢘ ꢙꢚ ꢛꢔꢗꢕ ꢔꢜ ꢝꢞ ꢘ ꢘ ꢟꢕꢛ ꢚꢜ ꢗꢖ ꢠꢞꢡ ꢢꢔꢝ ꢚꢛꢔ ꢗꢕ ꢣꢚ ꢛꢟꢤ ꢋꢘ ꢗꢣꢞ ꢝꢛꢜ
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ꢋꢘ ꢗ ꢣꢞꢝ ꢛ ꢔꢗ ꢕ ꢠꢘ ꢗ ꢝ ꢟ ꢜ ꢜ ꢔꢕ ꢩ ꢣꢗ ꢟ ꢜ ꢕꢗꢛ ꢕꢟ ꢝꢟ ꢜꢜ ꢚꢘ ꢔꢢ ꢨ ꢔꢕꢝ ꢢꢞꢣ ꢟ ꢛꢟ ꢜꢛꢔ ꢕꢩ ꢗꢖ ꢚꢢ ꢢ ꢠꢚ ꢘ ꢚꢙ ꢟꢛꢟ ꢘ ꢜꢤ
Copyright 2004, Texas Instruments Incorporated
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
Absolute Maximum Ratings
(1)
over operating free-air temperature range unless otherwise noted
The TAS5112A is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top), shown as follows.
TAS5112A
DVDD TO DGND
UNITS
–0.3 V to 4.2 V
33.5 V
33.5 V
48 V
DFD PACKAGE
(TOP VIEW)
GVDD TO GND
PVDD_X TO GND (dc voltage)
PVDD_X TO GND (spike voltage
OUT_X TO GND (dc voltage)
GND
GND
GND
GVDD
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
(2)
)
)
2
33.5 V
48 V
GREG
3
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND
(2)
OUT_X TO GND (spike voltage
BST_X TO GND (dc voltage)
BST_X TO GND (spike voltage
OTW
4
48 V
SD_CD
SD_AB
PWM_DP
PWM_DM
RESET_CD
PWM_CM
PWM_CP
DREG_RTN
M3
5
(2)
6
)
53 V
7
(3)
GREG TO GND
14.2 V
8
PWM_XP, RESET, M1, M2, M3, SD,
OTW
–0.3 V to DVDD + 0.3 V
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
Maximum operating junction
–40°C to 150°C
–40°C to 125°C
temperature, T
J
Storage temperature
(1)
Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-
maximum-ratedconditions for extended periods may affect device
reliability.
M2
M1
DREG
PWM_BP
PWM_BM
RESET_AB
PWM_AM
PWM_AP
GND
(2)
(3)
The duration of voltage spike should be less than 100 ns; see
applicationnote SLEA025.
GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V.
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
DGND
GND
DVDD
GREG
GND
GND
Package Dissipation Ratings
R
R
θJC
θJA
PACKAGE
(°C/W)
(°C/W)
56-pin DFD TSSOP
(4)
1.14
See Note 4
GND
The TAS5112A package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, R
thermaltreatment, is provided in theApplication Information section
a system parameter that characterizes the
θJA,
of the data sheet. An example and discussion of typical system
R
θJA
values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipationratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.
Ordering Information
T
A
PACKAGE
DESCRIPTION
0°C to 70°C
TAS5112ADFD
56-pin small TSSOP
For the most current specification and package
information, refer to our Web site at www.ti.com.
2
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
Terminal Functions
TERMINAL
NAME
BST_A
(1)
FUNCTION
DESCRIPTION
NO.
31
42
43
54
23
16
12
25
P
P
P
P
P
P
P
P
P
High-side bootstrap supply (BST), external capacitor to OUT_A required
High-side bootstrap supply (BST), external capacitor to OUT_B required
HS bootstrap supply (BST), external capacitor to OUT_C required
HS bootstrap supply (BST), external capacitor to OUT_D required
Digital I/O reference ground
BST_B
BST_C
BST_D
DGND
DREG
Digital supply voltage regulator decoupling pin, capacitor connected to GND
Digital supply voltage regulator decoupling return pin
I/O reference supply input (3.3 V)
DREG_RTN
DVDD
GND
1, 2, 22, 24,
27, 28, 29, 36,
37, 48, 49, 56
Power ground
GREG
3, 26
30, 55
15
P
P
I
Gate drive voltage regulator decoupling pin, capacitor to REG_GND
Voltage supply to on-chip gate drive and digital supply voltage regulators
Mode selection pin
GVDD
M1 (TST0)
M2
14
I
Mode selection pin
M3
13
I
Mode selection pin
OTW
4
O
O
O
O
O
P
P
P
P
I
Overtemperature warning output, open drain with internal pullup resistor
Output, half-bridge A
OUT_A
34, 35
38, 39
46, 47
50, 51
32, 33
40, 41
44, 45
52, 53
20
OUT_B
Output, half-bridge B
OUT_C
Output, half-bridge C
OUT_D
Output, half-bridge D
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PWM_AM
PWM_AP
PWM_BM
PWM_BP
PWM_CM
PWM_CP
PWM_DM
PWM_DP
RESET_AB
RESET_CD
SD_AB
Power supply input for half-bridge A
Power supply input for half-bridge B
Power supply input for half-bridge C
Power supply input for half-bridge D
Input signal (negative), half-bridge A
Input signal (positive), half-bridge A
Input signal (negative), half-bridge B
Input signal (positive), half-bridge B
Input signal (negative), half-bridge C
Input signal (positive), half-bridge C
Input signal (negative), half-bridge D
Input signal (positive), half-bridge D
Reset signal, active low
21
I
18
I
17
I
10
I
11
I
8
I
7
I
19
I
9
I
Reset signal, active low
6
O
O
Shutdown signal for half-bridges A and B, active-low
Shutdown signal for half-bridges C and D, active-low
SD_CD
5
(1)
I = input, O = Output, P = Power
3
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
FUNCTIONAL BLOCK DIAGRAM
BST_A
GREG
PVDD_A
Gate
Drive
OUT_A
GND
PWM_AP
PWM
Timing
Control
Receiver
Gate
Drive
Protection A
BST_B
RESET
GREG
PVDD_B
Protection B
Gate
Drive
PWM_BP
OUT_B
GND
PWM
Receiver
Timing
Control
Gate
Drive
To Protection
Blocks
DREG
DREG
GVDD
OTW
SD
GREG
OT
Protection
UVP
GREG
GREG
DREG
GREG
DREG_RTN
DREG_RTN
This diagram shows one channel.
4
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
(1)
DVDD
GVDD
Digital supply
Relative to DGND
Relative to GND
3
3.3
3.6
V
Supply for internal gate drive and logic
regulators
16
29.5
29.5
30.5
V
PVDD_x Half-bridge supply
Junction temperature
It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
Relative to GND, R = 6 Ω to 8 Ω
0
0
30.5
125
V
L
T
J
_C
(1)
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, R = 6 Ω, 8X f = 384 kHz, unless otherwise noted
L
s
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
T
75°C
=
T =40°C
TO 85°C
MIN/TYP/
MAX
Case
A
T =25°C
A
T =25°C
A
UNITS
AC PERFORMANCE, BTL Mode, 1 kHz
R
= 8 Ω, THD = 0.2%,
L
40
50
50
62
W
W
W
W
Typ
Typ
Typ
Typ
Typ
Typ
Typ
AES17 filter, 1 kHz
R
L
= 8 Ω, THD = 10%, AES17
filter, 1 kHz
Po
Output power
R
L
= 6 Ω, THD = 0.2%,
AES17 filter, 1 kHz
R
L
= 6 Ω, THD = 10%, AES17
filter, 1 kHz
Po = 1 W/ channel, R = 6 Ω,
AES17 filter
L
0.03%
0.04%
0.2%
Po = 10 W/channel, R = 6 Ω,
AES17 filter
Total harmonic distortion
+ noise
L
THD+N
Po = 50 W/channel, R = 6 Ω,
AES17 filter
L
Output integrated voltage A-weighted, mute, R = 6 Ω,,
L
V
260
96
µV
dB
dB
Max
Typ
Typ
n
noise
20 Hz to 20 kHz, AES17 filter
SNR
DR
Signal-to-noise ratio
A-weighted, AES17 filter
f = 1 kHz, A-weighted,
AES17 filter
Dynamic range
96
INTERNAL VOLTAGE REGULATOR
I
= 1 mA,
o
DREG
GREG
IVGDD
IDVDD
Voltage regulator
Voltage regulator
3.1
V
Typ
Typ
PVDD = 18 V-30.5 V
I
o
= 1.2 mA,
13.4
V
PVDD = 18 V-30.5 V
f = 384 kHz, no load, 50%
S
GVDD supply current,
operating
24
5
mA
mA
Max
Max
duty cycle
DVDD supply current,
operating
f
S
= 384 kHz, no load
1
OUTPUT STAGE MOSFETs
Forward on-resistance,
R
T = 25°C
155
155
mΩ
mΩ
Typ
Typ
DSon,LS
J
low side
Forward on-resistance,
high side
R
T = 25°C
J
DSon,HS
5
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, R = 6 Ω, 8X f = 384 kHz, unless otherwise noted
L
s
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
T
=
T =40°C
TO 85°C
MIN/TYP/
MAX
Case
75°C
A
T =25°C
A
T =25°C
A
UNITS
INPUT/OUTPUT PROTECTION
Set the DUT in normal
operation mode with all the
protections enabled. Sweep
GVDD up and down. Monitor
SD output. Record the
GREG reading when SD is
triggered.
6.9
7.9
V
Min
Undervoltage protection
limit, GVDD
V
7.4
uvp,G
V
Max
Typ
Overtemperature warning,
junction temperature
OTW
125
°C
Overtemperature error,
junction temperature
OTE
OC
150
6.7
°C
Typ
Typ
Overcurrent protection
See Note 1.
A
STATIC DIGITAL SPECIFICATION
PWM_AP, PWM_BP, M1,
M2, M3, SD, OTW
2
DVDD
0.8
V
V
Min
Max
Max
Min
V
V
High-level input voltage
Low-level input voltage
IH
V
IL
-10
µA
µA
Leakage
Input leakage current
10
Max
OTW/SHUTDOWN (SD)
Internally pull up R from
30
22.5
0.4
kΩ
Min
OTW/SD to DVDD
V
OL
Low-level output voltage
I
O
= 4 mA
V
Max
(1)
To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care.
See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors
for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended
to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.
6
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
Gate-Drive
Power Supply
External Power Supply
H-Bridge
Power Supply
TAS5112ADFD
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
47
GND
GND
GVDD
1 µF
GND
1.5 Ω
100 nF
GREG
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND
‡
L
33 nF
PCB
OTW
SD_CD
SD_AB
PWM_DP
PWM_DM
RESET_CD
PWM_CM
PWM_CP
100 nF
ERR_RCVY
PWM_AP_1
PWM_AM_1
VALID_1
10 µH
470 nF
†
4.7 kΩ
4.7 kΩ
1.5 Ω
100 nF
100 nF
GND
10
11
12
13
14
15
1.5 Ω
10 µH
OUT_C
OUT_C
46
45
44
43
†
100 nF
DREG_RTN
PVDD_C
PVDD_C
BST_C
100 nF
‡
L
PWM PROCESSOR
TAS5026
M3
M2
PCB
33 nF
33 nF
1000 µF
1.5 Ω
42
41
40
39
38
37
36
35
34
33
32
M1
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
‡
16
17
L
PCB
DREG
PWM_BP
PWM_AP_2
PWM_AM_2
VALID_2
100 nF
18
19
20
21
PWM_BM
RESET_AB
PWM_AM
PWM_AP
GND
10 µH
470 nF
†
4.7 kΩ
4.7 kΩ
1.5 Ω
100 nF
100 nF
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
22
23
1.5 Ω
100 Ω
10 µH
†
DGND
100 nF
100 nF
24
25
GND
‡
L
DVDD
PCB
33 nF
31
30
29
26
27
1000 µF
GREG
1 µF
1.5 Ω
GND
28
100 nF
GND
GND
†
‡
Voltage suppressor diodes: 1SMA33CAT
: Track in the PCB (1,0 mm wide and 50 mm long)
L
PCB
7
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE
OF TAS5112A EVM WITH TAS5026 PWM PROCESSOR
TOTAL HARMONIC DISTORTION + NOISE
NOISE AMPLITUDE
vs
vs
FREQUENCY
FREQUENCY
1
0
−20
R
T
= 6 Ω
= 75°C
R
= 6Ω
L
C
L
FFT = -60 dB
T
C
= 75°C
TAS5026 Front End Device
P
O
= 50 W
−40
0.1
−60
P
O
= 10 W
−80
P
O
= 1 W
−100
−120
−140
−160
0.01
0.001
0
2
4
6
8
10 12 14 16 18 20 22
20
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - kHz
Figure 1
Figure 2
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
vs
OUTPUT POWER
H-BRIDGE VOLTAGE
10
60
50
40
30
20
10
0
R
= 6 Ω
= 75°C
T
A
= 75°C
L
T
C
1
R
L
= 6 Ω
R
L
= 8 Ω
0.1
0.01
0
4
8
12
16
20
24
28
32
100m
1
10
100
P
O
- Output Power - W
VDD - Supply Voltage - V
Figure 3
Figure 4
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004
SYSTEM OUTPUT STAGE EFFICIENCY
POWER LOSS
vs
vs
OUTPUT POWER
OUTPUT POWER
11
10
9
100
90
80
70
60
50
40
30
20
10
0
f = 1 kHz
R
T
= 6 Ω
= 75°C
L
C
8
7
6
5
4
3
2
f = 1 kHz
R
T
= 6 Ω
= 75°C
L
1
C
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
P
O
- Output Power - W
P
O
- Output Power - W
Figure 5
Figure 6
OUTPUT POWER
vs
AMPLITUDE
vs
CASE TEMPERATURE
FREQUENCY
60
58
56
54
52
50
48
46
44
42
40
3.0
2.5
PVDD = 29.5 V
R
L
= 6 Ω
2.0
1.5
1.0
R
L
= 8 Ω
0.5
0.0
Channel 1
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
Channel 2
R
L
= 6 Ω
0
20
40
60
80
100
120
140
10
100
1k
10k
50k
T
C
- Case Temperature - °C
f - Frequency - Hz
Figure 7
Figure 8
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ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
200
190
180
170
160
150
140
130
120
0
10 20 30 40 50 60 70 80 90 100
T
J
- Junction Temperature - °C
Figure 9
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4.7-kΩ pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor.
THEORY OF OPERATION
POWER SUPPLIES
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
back-end bootstrap capacitor is charged.
The power device only requires two supply voltages,
GVDD and PVDD_X.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turn-on
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal circuitry to
3.3 V.
RESET can now be released if the modulator is powered
up and streaming valid PWM signals to the back-end
PWM_xP. Valid means a switching PWM signal which
complies with the frequency and duty cycle ranges stated
in the Recommended Operating Conditions.
A constant HIGH dc level on the PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.
The gate-driver regulator can be bypassed for reducing
idle loss in the device by shorting GREG to GVDD and
directly feeding in 12.0 V. This can be useful in an
application where thermal conduction of heat from the
device is difficult.
An unknown state of the PWM output signals from the
modulator is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is de-asserted HIGH to
the back end.
PVDD_X is the H-bridge power supply pin. Two power pins
exists for each half-bridge to handle the current density. It
is important that the circuitry recommendations around the
PVDD_X pins are followed carefully both topology- and
layout-wise. For topology recommendations, see the
System Configuration Used for Characterization section.
Following these recommendations is important for
parameters like EMI, reliability, and performance.
POWERING DOWN
For power down of the back end, an opposite approach is
necessary. The RESET must be asserted LOW before the
valid PWM signal is removed.
When PWM processors are used with TI PurePath Digital
amplifiers, the correct timing control of RESET and
PWM_xP is performed by the modulator.
POWERING UP
PRECAUTION
> 1 ms
> 1 ms
The TAS5112A must always start up in the
high-impedance (Hi-Z) state. In this state, the bootstrap
(BST) capacitor is precharged by a resistor on each PWM
output node to ground. See the system configuration. This
ensures that the back end is ready for receiving PWM
pulses, indicating either HIGH- or LOW-side turnon after
RESET is de-asserted to the back end.
RESET
GVDD
With the following pulldown resistor and BST capacitor
size, the charge time is:
PVDD_X
PWM_xP
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms the
back end BST is charged and ready. RESET can now be
released if the PWM modulator is ready and is streaming
valid PWM signals to the back end. Valid PWM signals are
switching PWM signals with a frequency between 350-400
kHz. A constant HIGH level on the PWM+ would force the
high-side MOSFET ON until it eventually ran out of BST
capacitor energy. Putting the device in this condition
should be avoided.
NOTE:
PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are not charged
at this point. To comply with the click and pop scheme and
use of non-TI modulators, it is recommended to use a
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In practice this means that the DVDD-to-PWM processor
(front-end) should be stable and initialization should be
completed before RESET is de-asserted to the back end.
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
Overcurrent (OC) Protection
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Demodulation Filter Design in the
Application Information section of the data sheet for design
constraints.
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other front-end device. The pin is open-drain with an
internal pullup resistor to DVDD.
Overtemperature (OT) Protection
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125°C. The OT protection circuit is shared by all
half-bridges.
SD
0
RESET
DESCRIPTION
0
1
Reserved
0
Device in protection mode, i.e., UVP and/or OC
and/or OT error
Undervoltage (UV) Protection
(2)
1
1
0
1
Device set high-impedance (Hi-Z), SD forced high
Normal operation
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
(2)
SD is pulled high when RESET is asserted low independent
of chip state (i.e., protection mode). This is desirable to
maintaincompatibility with some TI PWM front ends.
Temperature Warning Pin: OTW
Reset Function
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup resistor to DVDD.
The reset has two functions:
D
D
Reset is used for re-enabling operation after a
latching error event.
OTW
DESCRIPTION
0
1
Junction temperature higher than 125°C
Junction temperature lower than 125°C
Reset is used for disabling output stage
switching (mute function).
Overall Reporting
The error latch is cleared on the falling edge of reset and
normal operation is resumed when reset goes high.
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
Table 1. Error Signal Decoding
PROTECTION MODE
OTW
SD
0
DESCRIPTION
0
0
1
1
Overtemperatureerror (OTE)
Autorecovery (AR) After Errors (PMODE0)
1
Overtemperature warning (OTW)
Overcurrent (OC) or undervoltage (UVP) error
Normal operation, no errors/warnings
0
In autorecovery mode (PMODE0) the TAS5112A is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time period
the device autorecovers, i.e., operation is automatically
resumed provided that the system is fully operational.
1
Chip Protection
The TAS5112A protection function is implemented in a
closed loop with, for example, a system controller and TI
PWM processor. The TAS5112A contains three individual
systems protecting the device against error conditions. All
of the error events covered result in the output stage being
set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.
The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.
The AR system is common to both half-bridges.
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Timing and Function
Table 3. Output Mode Selection
The function of the autorecovery circuit is as follows:
M3
0
OUTPUT MODE
Bridge-tied load output stage (BTL)
Reserved
1. An error event occurs and sets the
protection latch (output stage goes Hi-Z).
1
2. The counter is started.
APPLICATION INFORMATION
3. After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).
DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS
4. After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).
The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application note
SLEA025.
Error
Protection
Latch
Shutdown
SD
The PurePath Digital amplifier outputs are driven by
heavy-duty DMOS transistors in an H-bridge
configuration. These transistors are either off or fully on,
which reduces the DMOS transistor on-state resistance,
Autorecovery
PWM
R
, and the power dissipated in the device, thereby
DSon
increasing efficiency.
The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 11.
Counter
AR-RESET
Figure 10. Autorecovery Function
Latching Shutdown on All Errors (PMODE1)
TAS51xx
In latching shutdown mode, all error situations result in a
power down (output stage Hi-Z). Re-enabling can be done
by toggling the RESET pin.
L
Output A
R
(Load)
C1A
C1B
All Protection Systems Disabled (PMODE2)
C2
In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.
L
Output B
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.
Figure 11. Demodulation Filter
The main purpose of the output filter is to attenuate the
high-frequency switching component of the PurePath
Digital amplifier while preserving the signals in the audio
band.
Table 2. Protection Mode Selection
M1 M2
PROTECTION MODE
Autorecovery after errors (PMODE 0)
Latching shutdown on all errors (PMODE 1)
All protection systems disabled (PMODE 2)
Reserved
0
0
1
1
0
1
0
1
Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance
The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.
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should remain stable within the range of peak current seen
at maximum output power and deliver at least 5 µH of
inductance at 15 A.
In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-µF 50-V SMD capacitors (X7R or
better) (C1A and C1B in Figure 11) should be added from
the output of each inductor to ground.
If this rule is observed, the TAS5112A does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.
THERMAL INFORMATION
The thermally augmented package provided with the
TAS5112A is designed to be interfaced directly to
heatsinks using a thermal interface compound (for
example, Wakefield Engineering type 126 thermal
grease.) The heatsink then absorbs heat from the ICs and
couples it to the local air. If the heatsink is carefully
designed, this process can reach equilibrium and heat can
be continually removed from the ICs. Because of the
efficiency of the TAS5112A, heatsinks can be smaller than
those required for linear amplifiers of equivalent
performance.
Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.
In general, 10-µH inductors suffice for most applications.
The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10 µH.
The graphs in Figure 12 display the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5112A.
R
is a system thermal resistance from junction to
θ
JA
ambient air. As such, it is a system parameter with roughly
the following components:
D
R
(the thermal resistance from junction to
JC
θ
INDUCTANCE
vs
CURRENT
case, or in this case the metal pad)
Thermal grease thermal resistance
Heatsink thermal resistance
D
D
11
DFB1310A
R
has been provided in the General Information
θ
JC
10
section.
The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer’s area thermal resistance (expressed in
9
DASL983XX-1023
8
2
°C-in /W). The area thermal resistance of the example
thermal grease with a 0.002-inch thick layer is about 0.1
2
°C-in /W. The approximate exposed pad area is as
7
6
5
4
follows:
2
56-pin HTSSOP
0.045 in
Dividing the example thermal grease area resistance by
the surface area gives the actual resistance through the
thermal grease for both ICs inside the package:
0
5
10
15
I - Current - A
56-pin HTSSOP
2.27 °C/W
Figure 12. Inductance Saturation
The thermal resistance of thermal pads is generally
considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance.
Neither pads nor tape should be used with either of these
two packages. A thin layer of thermal grease with careful
clamping of the heatsink is recommended. It may be
difficult to achieve a layer 0.001-inch thick or less, so the
modeling below is done with a 0.002-inch thick layer,
which may be more representative of production thermal
grease thickness.
The selection of the capacitor that is placed across the
output of each inductor (C2 in Figure 11) is simple. To
complete the output filter, use a 0.47-µF capacitor with a
voltage rating at least twice the voltage applied to the
output stage (PVDD).
This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.
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Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Table 5. Case 2 (2 × 50 W Unclipped Into 6 Ω,
(1)
Channels in Separate Packages)
56-Pin HTSSOP
Ambient temperature
25°C
Thus, for a single monaural IC, the system R
thermal grease resistance + heatsink resistance.
= R
+
JC
θ
θ
JA
Power to load (per channel)
Power dissipation
50 W (unclipped)
4.5 W
Delta T inside package
5.1°C
Table 4, Table 5, and Table 6 indicate modeled
parameters for one or two TAS5112A ICs on a single
heatsink. The final junction temperature is set at 110°C in
all cases. It is assumed that the thermal grease is 0.002
inch thick and that it is similar in performance to Wakefield
Type 126 thermal grease. It is important that the thermal
grease layer is ≤0.002 inches thick and that thermal pads
or tape are not used in the pad-to-heatsink interface due
to the high power density that results in these extreme
power cases.
Delta T through thermal grease
Required heatsink thermal resistance
Junction temperature
18.6°C
6.9°C/W
110°C
System R
19°C/W
θJA
R
* power dissipation
85°C
θJA
Junction temperature
(1)
85°C + 25°C = 110°C
In this case, the power is separated into two packages. Note that
this allows a considerably smaller heatsink because twice as much
area is available for heat transfer through the thermal grease. For
this reason, separating the stereo channels into two ICs is
recommended in full-power stereo tests made on multichannel
systems.
Table 4. Case 1 (2 × 50 W Unclipped Into 6 Ω,
Table 6. Case 2A (2 × 60 W Into 6 Ω, Channels in
(1)
Both Channels in Same IC)
(1)
Separate IC Packages)
56-Pin HTSSOP
56-Pin HTSSOP
Ambient temperature
25°C
Ambient temperature
Power to load (per channel)
Power dissipation
25°C
Power to load (per channel)
Power dissipation per channel
60 W (10% THD)
5.4 W
50 W (unclipped)
4.5 W
6.1°C, note 2 ×
channel dissipation
Delta T inside package
10.2°C, note 2 ×
channel dissipation
Delta T inside package
22.3°C, note 2 ×
channel dissipation
Delta T through thermal grease
37.1°C, note 2 ×
channel dissipation
Delta T through thermal grease
Required heatsink thermal resistance
Junction temperature
5.3°C/W
Required heatsink thermal resistance
Junction temperature
4.2°C/W
110°C
110°C
System R
θJA
15.9°C/W
85°C
System R
θJA
19°C/W
R
* power dissipation
θJA
Junction temperature
(1)
R
* power dissipation
85°C
θJA
Junction temperature
85°C + 25°C = 110°C
85°C + 25°C = 110°C
In this case, the power is also separated into two packages, but
overdriving causes clipping to 10% THD. In this case, the high
power requires extreme care in attachment of the heatsink to
ensure that the thermal grease layer is ≤ 0.002 inches thick. Note
that this power level should not be attempted with both channels in
a single IC because of the high power density through the thermal
grease layer.
(1)
This case represents a stereo system with only one package. See
Case 2 and Case 2A if doing a full-power, 2-channel test in a
multichannelsystem.
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Other things that can affect the audible click level:
D
The spectrum of the click seems to follow the
speaker impedance vs. frequency curve—the
higher the impedance, the higher the click
energy.
D
Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.
Thermal
Pad
8,20 mm
7,20 mm
Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click will be.
The following mode transitions feature click and pop
reduction.
CLICK AND
POP REDUCED
STATE
(1)
Normal
→
→
Mute
Yes
Yes
(1)
Mute
Normal
Error recovery
(ERRCVY)
(1)
Normal
→
Yes
(1)
Error recovery
→
→
→
Normal
Yes
No
3,90 mm
2,98 mm
(1)
Normal
Hard Reset
(1)
Normal
Hard Reset
Yes
(1)
Normal = switching
REFERENCES
CLICK AND POP REDUCTION
1. TAS5000 Digital Audio PWM Processor data
manual—TI (SLAS270)
TI modulators feature a pop and click reduction system
that controls the timing when switching starts and stops.
2. True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet—TI (SLES009)
Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.
3. True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet—TI (SLAS328)
4. True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet—TI (SLES006)
To make this system work properly, the following design
rules must be followed when using the TAS5112A back
end:
5. TAS5026 Six-Channel Digital Audio PWM
Processor data manual—TI (SLES041)
6. TAS5036A Six-Channel Digital Audio PWM
Processor data manual—TI (SLES061)
D
The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.
7. TAS3103 Digital Audio Processor With 3D Effects
data manual—TI (SLES038)
8. Digital Audio Measurements application report—TI
D
The output stage must start switching from a
fully discharged output filter capacitor. Because
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
output to GND (see System Configuration Used
for Characterization).
(SLAA114)
9. PowerPAD Thermally Enhanced Package
technical brief—TI (SLMA002)
10. System Design Considerations for True Digital
Audio Power Amplifiers application report—TI
(SLAA117)
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MECHANICAL DATA
17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
TAS5112ADCA
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
DCA
56
56
56
56
56
56
56
56
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5112ADCAG4
TAS5112ADCAR
TAS5112ADCARG4
TAS5112ADFD
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
DCA
DCA
DCA
DFD
DFD
DFD
DFD
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5112ADFDG4
TAS5112ADFDR
TAS5112ADFDRG4
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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