TAS5121DKDE4_技术文档

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

TM

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FEATURES

APPLICATIONS

D

DVD Receiver

Home Theatre

Mini/Micro Component Systems

Internet Music Appliance

D

100-W RMS Power (BTL) Into 4 Ω With Less

Than 10% THD+N

80-W RMS Power (BTL) Into 4 Ω With Less

Than 0.2% THD+N

DESCRIPTION

The TAS5121 is a high-performance digital amplifier

power stage designed to drive a 4-Ω speaker up to 100 W.

The device incorporates PurePath Digital technology

and can be used with a TI audio PWM processor and a

simple passive demodulation filter to deliver high-quality,

high-efficiency digital audio amplification.

D

0.05% THD+N at 1 W Into 4 Ω

Power Stage Efficiency Greater Than 90%

Into 4 Ω Load

D

Self-Protecting Design

36-Pin PSOP3 Package

3.3-V Digital Interface

The efficiency of this digital amplifier can be greater than

90%, depending on the system design. Overcurrent

protection, overtemperature protection, and undervoltage

protection are built into the TAS5121, safeguarding the

device and speakers against fault conditions that could

damage the system.

EMI Compliant When Used With

Recommended System Design

TOTAL HARMONIC DISTORTION + NOISE

UNCLIPPED OUTPUT POWER

vs

POWER

H-BRIDGE VOLTAGE

10

90

80

R

= 4 Ω

= 75°C

L

T

C

Gain = 3 dB

70

4 Ω

60

1

6 Ω

50

40

30

0.1

8 Ω

20

10

0

0.01

0

4

8

12

16

20

24

28

32

0.1

1

10

100

P − Power − W

PVDD_X − H-Bridge Voltage − V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital and PowerPAD are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

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Copyright  2004, Texas Instruments Incorporated

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

Terminal Assignment

TAS5121

DVDD TO DGND

UNITS

–0.3 V to 4.2 V

14.2 V

33.5 V

48 V

The TAS5121 is offered in a thermally enhanced 36-pin

PSOP3 (DKD) package. The DKD package has the

thermal pad on top.

GVDD_x TO GND

PVDD_X TO GND (dc voltage)

DKD PACKAGE

(TOP VIEW)

(2)

)

PVDD_X TO GND

OUT_X TO GND (dc voltage)

(2)

33.5 V

48 V

OUT_X TO GND

BST_X TO GND (DC voltage)

(2)

)

GND

PWM_BP

GND

GVDD_B

GND

BST_B

PVDD_B

OUT_B

GND

1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

46 V

2

BST_X TO GND

)

53 V

3

PWM_XP, RESET, M1, M2, M3, SD,

OTW

RESET

DREG_RTN

GVDD

M3

4

–0.3 V to DVDD + 0.3 V

5

Maximum junction temperature range,

6

–40°C to 150°C

–40°C to 125°C

T

J

7

Storage temperature

8

DREG

DGND

M1

M2

DVDD

SD

DGND

OTW

GND

9

(1)

Stresses beyond those listed under “absolute maximum ratings”

may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any

other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-

maximum-ratedconditions for extended periods may affect device

reliability.

10

11

12

13

14

15

16

17

18

GND

OUT_A

PVDD_A

BST_A

GND

(2)

The duration should be less than 100 ns (see application note

SLEA025).

PWM_AP

GND

GVDD_A

ORDERING INFORMATION

TRANSPORT

MEDIA

T

A

PACKAGE

DESCRIPTION

0°C to 70°C

TAS5121DKD

Tube

36-pin PSOP3

0°C to 70°C TAS5121DKDR Tape and reel

PACKAGE DISSIPATION RATINGS

R

θJC

θJA

PACKAGE

(°C/W)

36-Pin DKD PSOP3

0.85

See Note 1

(1)

The TAS5121 package is thermally enhanced for conductive

cooling using an exposed metal pad area. It is impractical to use the

devices with the pad exposed to ambient air as the only heat sinking

of the device.

For this reason, R

thermaltreatment, is provided in theApplication Information section

a system parameter that characterizes the

θJA,

of the data sheet. An example and discussion of typical system

R

values are provided in the Thermal Information section. This

θJA

example provides additional information regarding the power

dissipationratings. This example should be used as a reference to

calculate the heat dissipation ratings for a specific application.

2

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TERMINAL

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

Terminal Functions

(1)

FUNCTION

DESCRIPTION

NAME

BST_A

DKD

22

33

9, 14

8

P

High-side bootstrap supply (BST), external resistor and capacitor to OUT_A required

High-side bootstrap supply (BST), external resistor and capacitor to OUT_B required

I/O reference ground

BST_B

DGND

DREG

Digital supply voltage regulator decoupling pin, 1-µF capacitor connected to DREG_RTN

Decoupling return pin

DREG_RTN

DVDD

5

12

I/O reference supply input: 100 Ω to DREG, decoupled to GND, 0.1-µF capacitor connected to

GND

1, 3, 16,

18, 21,

27, 28,

34

P

Power ground, connected to system GND

GVDD

GVDD_A

GVDD_B

M1

6

19, 20

35, 36

10

P

I

Local GVDD decoupling \pin

Gate drive input voltage

Protection mode selection pin, connect to GND

Protection mode selection pin, connect to DREG

Output mode selection pin; connect to GND

M2

11

I

M3

7

I

OTW

15

O

Overtemperature warning output, open drain with internal pullup resistor, active-low when temper-

ature exceeds 115°C

OUT_A

OUT_B

PVDD_A

PVDD_B

PWM_AP

PWM_BP

RESET

SD

25, 26

29, 30

23, 24

31, 32

17

O

P

I

Output, half-bridge A

Output, half-bridge B

Power supply input for half-bridge A

Power supply input for half-bridge B

PWM input signal, half-bridge A

2

I

PWM input signal, half-bridge B

4

I

Reset signal, active-low

13

O

Shutdown signal for half-bridges A and B (open drain with internal pullup resistor), active-low

(1)

I = input, O = Output, P = Power

3

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

FUNCTIONAL BLOCK DIAGRAM

GVDD_A

BST_A

GVDD_A

PVDD_A

OCH

DREG

Gate

DVDD DREG

Drive

Timing

Control

and

PWM_AP

DGND

OUT_A

PWM

Receiver

GVDD_A

Protection

Gate

Drive

GND

OCL

OCH

GVDD_B

BST_B

RESET

GVDD_B

PVDD_B

DREG

DVDD

Gate

DREG

Drive

Timing

Control

and

PWM_BP

DGND

OUT_B

PWM

Receiver

GVDD_B

Protection

Gate

Drive

GND

OCL

GVDD

DREG

OTW

SD

DREG

Protection

Logic

DREG

M1

M2

M3

OT

and

UVP

Internally

Connected

to GVDD_x

DREG_RTN

4

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

(1)

DVDD

Digital supply

Relative to DGND

Relative to GND

3

3.3

3.6

V

Supply for internal gate drive and logic

regulators

GVDD_x

10.8

12

13.2

V

PVDD_x Half-bridge supply

Junction temperature

It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

Relative to GND, R = 4 Ω

0

30.5

32

V

L

T

125

_C

J

(1)

ELECTRICAL CHARACTERISTICS

PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, R = 4 Ω, 8X f = 384 kHz, TAS5026 PWM processor,

L

s

unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

MIN/TYP/

MAX

T =25°C T =25°C T =75°C UNITS

A

C

AC PERFORMANCE, BTL Mode, 1 kHz

R

filter

= 4 Ω, THD = 10%, AES17

L

100

W

%

Typ

R

L

= 4 Ω, THD = unclipped,

80

44

Po

Output power

AES17 filter

R

L

= 8 Ω, THD =unclipped,

AD mode

Po = 1 W/ channel, R = 4 Ω,

AES17 filter

L

0.05

0.1

0.2

Po = 10 W/channel, R = 4 Ω,

AES17 filter

L

THD+N

Total harmonic distortion + noise

Po = 80 W/channel, R = 4 Ω,

AES17 filter

L

A-weighted, R = 4 Ω,

20 Hz to 20 kHz, AES17 filter

L

V

Output integrated noise voltage

Signal-to-noise ratio

300

95

µV

dB

Max

Typ

n

SNR

DR

A-weighted, AES17 filter

f = 1 kHz, −60 dB,

A-weighted, AES17 filter

Dynamic range

95

5

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS

PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, R = 4 Ω, 8X f = 384 kHz, TAS5026 PWM processor,

L

s

unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

MIN/TYP/

MAX

T =25°C T =25°C T =75°C UNITS

A

C

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

V

Min

DREG

Voltage regulator

I

f

= 1 mA

3.3

o

Max

= 384 kHz, no load,

S

IGVDD_x Total GVDD supply current, operating

24

1

30

5

mA

Max

50% duty cycle

IDVDD

DVDD supply current, operating

f = 384 kHz, no load

S

OUTPUT STAGE MOSFETs

R

Forward on-resistance, low side

Forward on-resistance, high side

T = 25°C

120

132

mΩ

Max

DSon,LS

J

R

T = 25°C

J

DSon,HS

INPUT/OUTPUT PROTECTION

7

V

Min

Max

Typ

Min

V

Undervoltage protection limit, GVDD

7.6

uvp,G

8.2

OTW

OTE

OC

Overtemperature warning

Overtemperature error

Overcurrent protection

Static

115

150

9.5

°C

A

Static

See Note 1.

STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS AND OUTPUT MODE SELECTION PINS

2

DVDD

0.8

V

Min

Max

Min

V

High-level input voltage

Low-level input voltage

IH

V

IL

−10

10

µA

Leakage

Input leakage current

Max

OTW/SHUTDOWN (SD)

Internal pullup resistor from OTW and

32

22

kΩ

Min

SD to DVDD

V

OL

Low-level output voltage

I

O

= 1 mA

0.4

V

Max

(1)

To optimize device performance and prevent overcurrent (OC) protection activation, the demodulation filter must be designed with special care.

See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors

for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5121.

6

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

TYPICAL APPLICATION AND CHARACTERIZATION CONFIGURATION USED WITH TAS5026

PWM PROCESSOR

TAS5121DKD

1 µF

Gate-Drive

Power Supply

1

2

36

35

34

33

32

31

30

29

28

27

26

GND

GVDD_B

GND

22 Ω

PWM_AP_1

PWM_BP

GND

3

1 Ω

4

100 nF

2.7 Ω

RESET

DREG_RTN

GVDD

M3

BST_B

PVDD_B

OUT_B

GND

5

6

‡

75 nH L

PCB

33 nF

7

10 µH

100

nF

8

H-Bridge

Power Supply

DREG

DGND

M1

4.7 kΩ

1 µF

9

†

TVS Zener

1 µF

10

TVS Zener

GND

1000 µF

1 µF

11

12

13

14

15

16

17

18

10 µH

M2

OUT_A

100 Ω

25

24

23

22

DVDD

33 nF

75 nH L

‡

PCB

SD

PVDD_A

BST_A

100 nF

DGND

OTW

2.7 Ω

100 nF

1 Ω

21

20

19

GND

22 Ω

PWM_BP_1

GVDD_A

PWM_AP

GND

33 µF

GVDD_A

1 µF

Micro-

controller

†

‡

Voltage suppressor diodes: 1SMA33CAT3

: Track in the PCB 1,0 mm wide and 50 mm long)

L

PCB

7

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

TOTAL HARMONIC DISTORTION + NOISE

UNCLIPPED OUTPUT POWER

vs

POWER

H-BRIDGE VOLTAGE

10

90

80

70

60

50

40

30

20

10

0

R

= 4 Ω

= 75°C

L

T

C

Gain = 3 dB

4 Ω

6 Ω

1

0.1

8 Ω

0.01

0

4

8

12

16

20

24

28

32

0.1

1

10

100

P − Power − W

PVDD_X − H-Bridge Voltage − V

Figure 1

Figure 2

POWER LOSS

vs

UNCLIPPED OUTPUT POWER

vs

TOTAL OUTPUT POWER

CASE TEMPERATURE

14

12

10

8

100

90

80

70

60

50

40

30

20

10

0

6

4

2

0

10

20

30

40

50

60

70

80

−30

0

30

60

90

120

P

− Total Output Power − W

T

C

− Case Temperature − °C

O(Total)

Figure 3

Figure 4

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

EFFICIENCY

vs

TOTAL HARMONIC DISTORTION + NOISE

vs

TOTAL OUTPUT POWER

FREQUENCY

100

90

80

70

60

50

40

30

20

10

0

1

R

T

= 4 Ω

= 75°C

L

C

75 W

0.1

10 W

1 W

0.01

0.001

0

10

20

30

40

50

60

70

80

20

100

1k

10k 20k

P

− Total Output Power − W

f − Frequency − Hz

O(Total)

Figure 5

Figure 6

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0.5

0.4

0.3

0.2

0.1

0

−20

P

T

= 1 W

= 75°C

O

C

8 Ω

6 Ω

−40

−60

−

−80

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

−100

−120

−140

−160

4 Ω

0

2

4

6

8

10 12 14 16 18 20 22

10

100

1k

10k 20k

f − Frequency − Hz

f − Frequency − kHz

Figure 7

Figure 8

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THEORY OF OPERATION

RECOMMENDATIONS FOR POWERING UP

> 1 ms

POWER SUPPLIES

> 1 ms

This power device requires only two power supply

voltages, GVDD_x and PVDD_x.

RESET

GVDD

GVDD_x is the gate drive supply for the device, which is

usually supplied from an external 12-V power supply.

GVDD_x is also connected to an internal LDR that

regulates the GVDD_x voltage down to the logic power

supply, 3.3 V, for the TAS5121 internal logic blocks. Each

GVDD_x pin is decoupled to system ground by a 1-µF

capacitor.

PVDD_X

PWM_xP

PVDD_x is the H-bridge power supply. Two power pins are

provided for each half-bridge due to the high current

density. It is important to follow the circuit and PCB layout

recommendations for the design of the PVDD_x

connection. For component suggestions, see the Typical

System Configuration section in this document. For layout

guidelines, see the reference design layout for the

TAS5121. Following these recommendations is important

because they influence key system parameters such as

EMI, idle current, and audio performance.

The following table describes the input conditions and the

output states of the device:

INPUTS

OUTPUTS

Condition

Description

RESET PWM PWM SHUT- OUT_ OUT_

_AP _BP DOWN

A

B

X

0

1

X

0

1

X

0

1

0

1

Hi-Z

Shutdown

Reset

When GVDD_x is applied, while RESET is held low, the

error latches are cleared, SHUTDOWN is set high, and the

outputs are held in a high-impedance state. The bootstrap

capacitor is charged by the current path through the

internal bootstrap diode and external resistors placed on

the PCB from each OUT_x pin to ground. A subsequent

section describes the charging of the bootstrap capacitor.

GND GND

PVDD PVDD

GND PVDD

PVDD PVDD

Normal

Reserved

After the previously mentioned conditions are met, the

device output begins. If PWM_AP is equal to a high and

PMW_BP is equal to a low, the high-side MOSFET in the

A half-bridge of the output H-bridge conducts while the

low-side MOSFET in the A half-bridge is not conducting.

Because the source of the high-side MOSFET is

referenced to the drain of the low-side MOSFET, a

bootstrapped gate drive is used to eliminate the need for

additional high-voltage power supplies. Under the above

condition, the opposite is true for the B half-bridge of the

output H-bridge. The low-side MOSFET in B half-bridge

conducts while the high-side MOSFET is not conducting;

therefore, the load connected between the OUT_A and

OUT_B pins has PVDD applied to it from the A side while

ground is applied from the B side for the period of time

PWM_AP is high and PWM_BP is low. Furthermore, when

the PWM signals change to the condition where PWM_AP

is low and PWM_BP is high, the opposite condition exists.

Ideally, PVDD_x is applied after GVDD_x. When GVDD_x

and PVDD_x are applied, the TAS5121 is ready for

operation. PWM input signals can then be applied any time

during the power-on sequence, but they must be active

and stable before RESET is set high.

A constant high level is not permitted on the PWM inputs.

This condition causes the bootstrap capacitors to

discharge and can cause device damage.

10

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A digitally controlled dead-time circuit controls the

transitions between the high-side and low-side MOSFETs

to ensure that both devices in each half-bridge are not

conducting simultaneously.

SD

0

RESET

DESCRIPTION

0

1

Reserved

0

Device in protection mode, i.e., UVP and/or OC

and/or OT error

(2)

1

0

1

Device set high-impedance (Hi-Z), SD forced high

Normal operation

POWERING DOWN

(2)

SD is pulled high when RESET is asserted low independent of chip

state (i.e., protection mode). This is desirable to maintain

compatibilitywith some TI PWM front ends.

For power down of the TAS5121, an opposite approach is

necessary. The RESET must be asserted LOW before the

valid PWM signal is removed.

Overtemperature Warning Pin: OTW

The OTW pin gives a temperature warning signal when

temperature exceeds the set limit. The pin is of the

open-drain type with an internal pullup resistor to DVDD.

PRECAUTION

The TAS5121 must always start up in the high-impedance

(Hi-Z) state. In this state, the bootstrap (BST) capacitor is

precharged by a resistor on each PWM output node to

ground. See the system configuration. This ensures that

the TAS5121 is ready for receiving PWM pulses, indicating

either HIGH- or LOW-side turnon after RESET is

de-asserted to the back end.

OTW

DESCRIPTION

0

1

Junction temperature higher than 115°C

Junction temperature lower than 115°C

Overall Reporting

The SD pin, together with the OTW pin, gives chip state

information as described in Table 1.

With the following pulldown resistor and BST capacitor

size, the BST charge time is:

Table 1. Error Signal Decoding

C = 33 nF, R = 4.7 kΩ

R × C × 5 = 775.5 µs

OTW

SD

0

DESCRIPTION

0

1

Overtemperatureerror (OTE)

After GVDD has been applied, it takes approximately 800

µs to fully charge the BST capacitor. During this time,

RESET must be kept low. After approximately 1 ms the

back end BST is charged and ready. RESET can now be

released if the PWM modulator is ready and is streaming

valid PWM signals to the device. Valid PWM signals are

switching PWM signals with a frequency between

350−400 kHz. A constant HIGH level on the PWM+ forces

the high-side MOSFET ON until it eventually runs out of

BST capacitor energy. Putting the device in this condition

should be avoided.

1

Overtemperature warning (OTW)

Overcurrent (OC) or undervoltage (UVP) error

Normal operation, no errors/warnings

0

1

Chip Protection

The TAS5121 protection function is generally

implemented in a closed loop control system with, for

example, a system controller. The TAS5121 contains three

individual systems protecting the device against fault

conditions. All of the error events result in the output stage

being set in a high-impedance state (Hi-Z) for maximum

protection of the device and connected equipment.

In practice this means that the DVDD-to-PWM processor

(front-end) should be stable and initialization should be

completed before RESET is de-asserted to the TAS5121.

The device can be recovered by toggling RESET low and

then high, after all errors are cleared. It is recommended

that if the error persists, the device is held in reset until user

intervention clears the error.

CONTROL I/O

Shutdown Pin: SD

Overcurrent (OC) Protection

The SD pin functions as an output pin and is intended for

protection-mode signaling to, for example, a controller or

other front-end device. The pin is open-drain with an

internal pullup resistor to DVDD.

The device has individual current protection on both

high-side and low-side power stage FETs. The OC

protection works only with the demodulation filter present

at the output. See Filter Demodulation Design in the

Application Information section of the data sheet for design

constraints.

The logic output is, as shown in the following table, a

combination of the device state and RESET input:

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Overtemperature (OT) Protection

Timing and Function

The function of the autorecovery circuit is as follows:

A dual temperature protection system asserts a warning

signal when the device junction temperature exceeds

115°C and shuts down the device when the junction

temperature exceeds 150°C. The OT protection circuit is

shared by both half-bridges.

1. An error event occurs and sets the

protection latch (output stage goes Hi-Z).

2. The counter is started.

3. After n/2 cycles, the protection latch is

cleared but the output stage remains Hi-Z

(identical to pulling RESET low).

Undervoltage Protection (UVP)

4. After n cycles, operation is resumed

(identical to pulling RESET high) (n = 512).

Undervoltage lockout occurs when GVDD is insufficient

for proper device operation. The UV protection system

protects the device under fault power-up and power-down

situations by shutting the device down. The UV protection

circuits are shared by both half-bridges.

Error

Protection

Latch

Shutdown

SD

Reset Function

The reset has two functions:

Autorecovery

PWM

D

Reset is used for re-enabling operation after a

latched error event.

Counter

Reset is used for disabling output stage

switching, hard mute function. Use modulator

control for soft mute.

AR-RESET

Figure 9. Autorecovery Function

In protection modes where the reset input functions as the

means to re-enable operation after an error event, the error

latch is cleared on the falling edge of reset and normal

operation is resumed on the rising edge of RESET.

Latching Shutdown on All Errors (PMODE1)

In latching shutdown mode, all error situations result in a

power down (output stage Hi-Z). Re-enabling can be done

by toggling the RESET pin.

All Protection Systems Disabled (PMODE2)

In PMODE2, all protection systems are disabled. This

mode is purely intended for testing and characterization

purposes and thus not recommended for normal device

operation.

PROTECTION MODE

Autorecovery (AR) After Errors (PMODE0)

MODE Pins Selection

The protection mode is selected by connecting M1/M2 to

DREG or DGND according to Table 2.

In autorecovery mode (PMODE0) the TAS5121 is

self-supported in handling of error situations. All protection

systems are active, setting the output stage in the

high-impedance state to protect the output stage and

connected equipment. However, after a short time the

device autorecovers, i.e., operation is automatically

resumed provided that the system is fully operational.

Table 2. Protection Mode Selection

M1 M2

PROTECTION MODE

Autorecovery after errors (PMODE 0)

Latched shutdown on all errors

Reserved

0

1

0

1

0

1

The autorecovery timing is set by counting PWM input

cycles, i.e., the timing is relative to the switching frequency.

Reserved

The output configuration mode is selected by connecting

the M3 pin to DREG or DGND according to Table 3.

The AR system is common to both half-bridges.

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In general, 10-µH inductors suffice for most applications.

The frequency response of the amplifier is slightly altered

by the change in output load resistance; however, unless

tight control of frequency response is necessary (better

than 0.5 dB), it is not necessary to deviate from 10 µH.

Table 3. Output Mode Selection

M3

0

OUTPUT MODE

Bridge-tied load output stage (BTL)

Reserved

1

The graphs in Figure 11 display the inductance vs current

characteristics of two inductors that are suggested for use

with the TAS5121.

APPLICATION INFORMATION

DEMODULATION FILTER DESIGN

INDUCTANCE

vs

CURRENT

The TAS5121 amplifier outputs are driven by high-current

DMOS transistors in an H-bridge configuration. These

transistors are either off or fully on.

11

The result is a square-wave output signal with a duty cycle

that is proportional to the amplitude of the audio signal. It

is recommended that a second-order LC filter be used to

recover the audio signal.

DBF1310A

10

9

DASL983XX−1023

8

TAS5121

L

Output A

7

6

5

4

R

(Load)

C1

C2

L

Output B

0

5

10

I − Current − A

15

Figure 10. Demodulation Filter

Figure 11. Inductance Saturation

The main purpose of the demodulation filter is to attenuate

the high-frequency components of the output signals that

are out of the audio band.

The selection of the capacitors that are placed from the

output of each inductor to ground is simple. To complete

the output filter, use a 1-µF capacitor with a voltage rating

at least twice the voltage applied to the output stage

(PVDD_x).

Design of the demodulation filter affects the audio

performance of the power amplifier significantly. As a

result, to ensure proper operation of the overcurrent (OC)

protection circuit and meet the device THD+N

specifications, the selection of the inductors used in the

output filter must be considered according to the following.

The rule is that the inductance should remain stable within

the range of peak current seen at maximum output power

and deliver approximately 5 µH of inductance at 15 A.

This capacitor should be a good quality polyester

dielectric.

THERMAL INFORMATION

The following is provided as an example.

The thermally enhanced package provided with the

TAS5121 are designed to be interfaced directly to

heatsinks using a thermal interface compound (for

example, Wakefield Engineering type 126 thermal

grease.) The heatsink then absorbs heat from the ICs and

transfers it to the ambient air. If the heatsink is carefully

designed, this process can reach equilibrium and heat can

be continually removed from the ICs without device

overtemperature shutdown. Because of the efficiency of

the TAS5121, heatsinks are smaller than those required

for linear amplifiers of equivalent performance.

If this rule is observed, the TAS5121 should not have

distortion issues due to the output inductors. This prevents

device damage due to overcurrent conditions because of

inductor saturation in the output filter.

Another parameter to be considered is the idle current loss

in the inductor. This can be measured or specified as

inductor dissipation (D). The target specification for

dissipation is less than 0.05. If this specification is not met,

idle current increases.

13

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

R

is a system thermal resistance from junction to

The following table indicates modeled parameters for one

TAS5121 IC on a heatsink. The junction temperature is set

at 110°C while delivering 70 W RMS into 4-Ω loads with no

clipping. It is assumed that the thermal grease is about

0.001 inch thick (this is critical).

θ

JA

ambient air. As such, it is a system parameter with roughly

the following components:

D

R

(the thermal resistance from junction to

JC

θ

case, or in this case the metal pad)

Heatsink compound thermal resistance

Heatsink thermal resistance

Table 4. Example of Thermal Simulation

D

36-Pin PSOP3

Ambient temperature

25°C

Power to load

70 W

The thermal grease thermal resistance can be calculated

from the exposed pad area and the thermal grease

manufacturer’s area thermal resistance (expressed in

°C-in /W). The area thermal resistance of the example

thermal grease with a 0.001-inch thick layer is about 0.054

Delta T inside package

Delta T through thermal grease

Required heatsink thermal resistance

Junction temperature

5.5°C

3.2°C

2

11.0°C/W

110°C

2

°C-in /W. The approximate exposed pad area is as

follows:

System R

θJA

12.3°C/W

85°C

R

* power dissipation

θJA

θJC

2

R

0.85°C/W

36-pin PSOP3

0.116 in

As an indication of the importance of keeping the thermal

grease layer thin, if the thermal grease layer increases to

0.002 inches thick, the required heatsink thermal

resistance increases to 5.2°C/W for the PSOP3 package.

Dividing the example thermal grease area resistance by

the area of the pad gives the actual resistance through the

thermal grease for the device:

36-pin PSOP3

0.47 °C/W

REFERENCES

The thermal resistance of thermally conductive pads is

generally higher than a thin thermal grease layer. Thermal

tape has an even higher thermal resistance and should not

be used with this package.

1. Digital Audio Measurements application report—TI

(SLAA114)

2. PowerPAD Thermally Enhanced Package

technical brief—TI (SLMA002)

Heatsink thermal resistance is generally predicted by the

heatsink vendor, modeled using a continuous flow

dynamics (CFD) model, or measured.

3. System Design Considerations for True Digital

Audio Power Amplifiers application report—TI

(SLAA117)

Thus, for a single monaural IC, the system R

thermal grease resistance + heatsink resistance.

= R

+

4. Voltage Spike Measurement Technique and

Specification application note—TI (SLEA025)

θ

JC

JA

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SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

MECHANICAL DATA

15

PACKAGE OPTION ADDENDUM

www.ti.com

9-Mar-2007

PACKAGING INFORMATION

Orderable Device

TAS5121DKD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DKD

36

29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

TAS5121DKDE4

TAS5121DKDR

TAS5121DKDRE4

SSOP

DKD

29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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型号：	TAS5121DKDE4
厂家：	TEXAS INSTRUMENTS
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