TAS5261DKDG4 [TI]
315-W Mono BTL Digital Amplifier Power Stage; 315 -W单声道BTL数字放大器功率级
| 型号： | TAS5261DKDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 315-W Mono BTL Digital Amplifier Power Stage |
| 文件： | 总21页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
TAS5261
www.ti.com
SLES188–AUGUST 2006
315-W Mono BTL Digital Amplifier Power Stage
FEATURES
The TAS5261 has complete protection circuitry
integrated on chip, safeguarding the device and
speakers against fault conditions that could damage
the system. These protection features are
short-circuit protection, overcurrent protection,
undervoltage protection, and a loss of pulse-width
modulation (PWM) input signal (PWM Activity
Detector).
•
Total Output Power
– 125 W Into 8 Ω at <0.09% THD+N
– 220 W Into 6 Ω at 10% THD+N
– 315 W Into 4 Ω at 10% THD+N
•
•
110-dB SNR (A-Weighted with TAS5518
modulator)
Supports Pulse-Width Modulation (PWM)
Frame Rates of 192 kHz to 384 kHz
A power-on reset (POR) circuit is used to eliminate
power-supply sequencing that is normally required
for most H-bridge designs.
•
•
Resistor-Programmable Current Limit
Integrated Self-Protection Circuit Including:
– Under Voltage Protection
OUTPUT POWER
vs
PVDD_x SUPPLY VOLTAGE
– Over Temperature Warning and Error
– Over Load Protection
330
– Short Circuit (OC) Protection
– PWM Activity Dectector
T
= 75°C
C
300
270
240
210
180
150
120
90
THD+N at 10%
•
•
•
•
Power-On Reset (POR) to Eliminate System
Power-Supply Sequencing
Thermally-Enhanced Package DKD (36-pin
PSOP3)
6 Ω
EMI Compliant When Used With
Recommended System Design
4 Ω
Error Reporting 3.3-V and 5-V Compliant
APPLICATIONS
60
•
•
•
•
AV Receivers
DVD Receivers
Mini/Micro Component Systems
Home Theater Systems
8 Ω
30
0
0
5
10 15 20 25 30 35 40 45 50
PVDD Supply Voltage − V
G001
DESCRIPTION
The TAS5261 is a high-performance, integrated
mono digital amplifier power stage designed to drive
4-Ω to 8-Ω speakers with low harmonic distortion.
This system requires only
demodulation filter to
high-efficiency audio amplification.
a
simple, passive
deliver high-quality,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5261
www.ti.com
SLES188–AUGUST 2006
DEVICE INFORMATION
The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heat sink.
DKD PACKAGE
(TOP VIEW)
BST_A
PVDD_A
PVDD_A
PVDD_A
PGND
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
GVDD_A
OTW
SD
3
4
RESET
PWM_A
OC_ADJ
PGND
5
PGND
6
OUT_A
OUT_A
OUT_A
OUT_B
OUT_B
OUT_B
PGND
7
8
GND
AGND
VREG
M3
9
10
11
12
13
14
15
16
17
18
M2
M1
PWM_B
VDD
PGND
PGND
GND
PVDD_B
PVDD_B
PVDD_B
GVDD_B
BST_B
P0018-02
2
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SLES188–AUGUST 2006
DISSIPATION RATINGS
PARAMETER
RθJC
CONDITION
BTL channel (four transistors)
One transistor
TYPICAL (DKD)
0.6°C/W
2.38°C/W
80 mm2
RθJC
Pad area
Protection Mode
Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
Table 1. Protection Modes
MODE PINS
PROTECTION MODE
M3(1)
M2
0
M1
0
0
0
0
0
Full protection (default)
Reserved
0
1
1
0
OC latching mode
Reserved
1
1
(1) M3 is reserved and always should be connected to board GND.
3
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SLES188–AUGUST 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
AGND
BST_A
BST_B
GND
PIN NO.
9
I
P
I
Analog ground
Bootstrap, A side
Bootstrap, B side
Power ground
1
18
8, 16
I
GVDD_A
GVDD_B
M1
2
P
I
Gate-drive voltage supply, A side
Gate-drive voltage supply, B side
Mode-selection 1 (LSB)
17
13
I
M2
12
I
Mode-selection 2 (MSB)
M3
11
I
Reserved
OC_ADJ
OTW
7
I
Overcurrent threshold programming
Overtemperature warning. Open drain, active low.
Output, half-bridge A
3
O
O
O
OUT_A
OUT_B
28, 29, 30
25, 26, 27
Output, half-bridge B
22, 23, 24, 31,
32, 33
PGND
P
Power ground
PWM_A
PWM_B
PVDD_A
PVDD_B
RESET
SD
6
I
I
PWM for half-bridge A
14
PWM Input for half-bridge B
PVDD supply for half-bridge A
PVDD supply for half-bridge B
Reset. Active low.
34, 35, 36
P
P
I
19, 20, 21
5
4
O
I
Shutdown. Open drain, active low.
Input power supply
VDD
15
10
VREG
O
Internal voltage regulator
4
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SLES188–AUGUST 2006
GVDD (12 V) and VDD (12 V)
GND
Hardwire
Over-
current
Limit
GVDD, VDD,
and VREG
Power-Supply
Decoupling
PVDD
Power-Supply
Decoupling
PVDD (0–50 V)
6
6
2
2nd-Order
OUT_A
OUT_B
L-C Output
Filter for
Each
R1
R2
M1
4–8 W
(3 W Min)
PWM_A
PWM_B
Mono
BTL
H-Bridge
H-Bridge
BST_A
BST_B
Bootstrap
Capacitors
Hardwire
Mode
Control
M2
M3
RESET_H-Bridge
RESET
SD
SD
OTW
OTW
System
Microcontroller
L1
L2
PWM_A
PWM_B
2nd-Order
L-C Output
Filter for
Each
OUT_A
OUT_B
4–8 W
(3 W Min)
Mono
BTL
H-Bridge
H-Bridge
BST_A
BST_B
M1
Bootstrap
Capacitors
Hardwire
Mode
Control
M2
M3
6
6
2
PVDD
Power-Supply
Decoupling
GVDD, VDD,
and VREG
Power-Supply
Decoupling
Hardwire
Over-
current
Limit
PVDD (0–50 V)
50 V
System
Power
Supplies
GND
GVDD (12 V) and VDD (12 V)
GND
12 V
AC
B0101-01
Figure 1. Typical System Block Diagram
5
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SLES188–AUGUST 2006
OTW
SD
VDD
P
-
OWER UP
U
VP
VREG
VREG
AGND
GND
R
ESET
M1
_A
GVDD
_B
GVDD
TEMP
SENSE
M2
M3
-
OVER LOAD
.
CURRENT
SENSE
3C
OC_
CB
ADJ
PROT
RESET
_B
GVDD
PWM
ACTIVITY
DETECTOR
BST_B
_
B
(x3)
PVDD
PWM
RECEIVER
TIMING
CONTROL
_B
PWM
-
GATE DRIVE
_
(x3)
B
CONTROL
OUT
(x3)
PGND
GVDD
_A
BST_A
_A x3)
(
PVDD
PWM
TIMING
_A
PWM
-
GATE DRIVE
_A x3)
OUT (
CONTROL
RECEIVER
CONTROL
(x3)
PGND
Figure 2. Functional Block Diagram
6
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SLES188–AUGUST 2006
ORDERING INFORMATION
TA
PACKAGE
DESCRIPTION
0°C to 70°C
TAS5261DKD
36-pin PSOP3
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
13.2
13.2
71
UNIT
V
VDD to AGND
GVDD_x to AGND
PVDD_x to PGND_x(2)
OUT_x to PGND_x(2)
BST_x to PGND_x(2)
V
V
71
V
79.7
66.5
4.2
0.3
0.3
0.3
4.2
7
V
BST_x to GVDD_x(2)
V
VREG to AGND
V
PGND_x to GND
V
PGND_x to AGND
V
GND to AGND
V
PWM_x, OC_ADJ, M1, M2, M3 to AGND
RESET, SD, OTW to AGND
V
V
Maximum continuous sink current (SD, OTW)
Maximum operating junction temperature range, TJ
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 in) from case for 10 s
Minimum pulse duration, low – minimum pulse width must be ensured by the PWM processor
9
mA
°C
°C
°C
ns
0
150
150
260
–65
50
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are only stress
ratings, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
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SLES188–AUGUST 2006
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
0
10.8(1)
10.8(1)
NOM
50
MAX UNIT
PVDD_x Half-bridge supply voltage
GVDD_x Gate-drive power supply
52.5
13.2
13.2
V
V
V
Ω
Ω
12
VDD
RL
Digital regulator supply voltage
12
Resistive load impedance, bridge-tied load (BTL)
Resistive load impedance, BTL, ROC = 22kΩ, PVDD = 50V, (no current limiting)
4-16
RL
3
5
Minimum output filter inductance under both operating and short-circuit conditions,
with appropriate OC_ADJ resistor value
LDEM
10
µH
fS
PWM frame rate
192
50
384
kHz
ns
nF
Ω
t(low)
CBS
RBS
Minimum low-state pulse duration per PWM frame, noise shaper enabled
Bootstrap capacitor, selected value supports fs = 192 kHz to 384 kHz
Bootstrap series resistor - 1/4 W
33
1.5
4.7
Ω
RCBS
Bootstrap snubber - 1/4 W
470
pF
Ultra-Fast Recovery Clamping Diode, Average forward current = 1A, Maximum
repetitive reverse voltage = 200V (ES1D, mfg:Fairchild)
DCLMP
15
nS
DTVS
CPVDD
RAGND
R
Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor)
PVDD Close Decoupling Capacitor, two capacitors
AGND resistor - 1/4 W
62
100
3.3
V
nF
Ω
Optional external pullup resistor to +3.3V or +5 V for SD and OTW
Junction temperature
3.3
0
4.7
kΩ
°C
TJ
125
(1) GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For the
purpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dc
voltage of 12 V for GVDD.
AUDIO CHARACTERISTICS
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ,
TC= 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). Audio performance is recorded as a chipset,
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.
PARAMETER
TEST CONDITIONS
RL = 8 Ω, f = 1 kHz
MIN
TYP
125
165
235
165
220
315
400
MAX UNIT
PO
Unclipped power output
RL = 6 Ω, f = 1 kHz
W
RL = 4 Ω, f = 1 kHz
RL = 8 Ω, f = 1 kHz, THD = 10%
RL = 6 Ω, f = 1 kHz, THD = 10%
RL = 4 Ω, f = 1 kHz, THD = 10%
RL = 3 Ω, f = 1 kHz, CBC allowed
PO
Maximum power output
W
%
Total harmonic distortion + noise,
AES 17 filter
1 W to 125 W, RL=8 Ω, AES17 filter,
Unclipped
THD+N
0.09
Ratio of 1-FFS to 0-FFS input,
A-weighted filter
SNR
DNR
VOO
Signal-to-noise ratio(1)
Dynamic range
110
110
dB
dB
–60-dBFS input, A-weighted filter
PWM switching frequency 384 kHz,
Measured on speaker terminals
Output offset voltage
–15
15
mV
W
Power dissipation due to idle losses
Pidle
PO = 0 W, Output switching(2)
2
(IPVDD_X
)
(1) SNR is calculated relative to the 0 dBFS input level.
(2) Actual system idle losses are also affected by core losses of output inductors.
8
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SLES188–AUGUST 2006
ELECTRICAL CHARACTERISTICS
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ,
TC = 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). AC performance is recorded as a chipset,
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator,
VREG
3.3
V
only used as reference node
Operating, 50% duty cycle
Idle, reset mode
7.7
6.7
15
IVDD
VDD supply current
mA
50% duty cycle
GVDD_x gate-supply current
per half bridge
IGVDD_x
mA
Idle, reset mode
1.5
23
50% duty cycle
mA
IPVDD_x
Half-bridge idle current
Reset mode (RESET = 1),
No switching
100
µA
Output-Stage MOSFETs
RDSON,LS Drain-to-source resistance, low side
RDSON,HS Drain-to-source resistance, high side
I/O Protection
TJ = 25°C, LDMOS only
TJ = 25°C, LDMOS only
40
40
mΩ
mΩ
VUVP,POS
OTW
Undervoltage protection limit, GVDD_x
8.5
125
25
V
Overtemperature warning
OTW hysteresis
°C
°C
°C
°C
OTWhys
OTE
Overtemperature error threshold
OTE hysteresis
155
30
OTEhys
OTE-OTW
differential
Temperature delta between OTW and OTE
Overload protection time constant
Overcurrent limit response (1)
Programming resistor
30
°C
OLPC
fPWM = 384 kHz
20
15
22
ms
Resistor programmable high end
IOC
16
17
A
with OC_ADJ = 22 kΩ(1)
ROC
100
kΩ
Connected when RESET is high to
provide a charge path for the
bootstrap capacitor
Pulldown resistor at the output of each
half-bridge
RPD
2.5
13
kΩ
µs
PWM
PWM Activity Detector
Lack of transition of any PWM input
(1) DC measurement with 1-ms pulse
9
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SLES188–AUGUST 2006
ELECTRICAL CHARACTERISTICS
GVDD_x = 12 V ± 10%, VDD = 12 V ± 10%, TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
Logic-Level and Open-Drain Outputs
VIH
VIL
High-level input voltage
Low-level input voltage
Static
Static
2
V
0.8
65
V
Static, High PWM_A, High PWM_B,
High M1, High M2, High M3
45
Static, Low PWM_A, Low PWM_B,
Low M1, Low M2, Low M3
(1)
–10
10
Ilkg
Input leakage current
µA
Static, High RESET
Static, Low RESET
20
40
–70
–50
Internal pulldown to AGND
for PWM_A and PWM_B inputs
RINT-PD
RINT-PU
50
28
kΩ
kΩ
Internal pullup resistance on OTW and SD
Resistor to VREG
20
2.4
2.5
33
VREG
4.9
Internal pullup resistor
External pullup of 3.3 kΩ to 5 V
IO = 4 mA
VOH
High-level output voltage
V
VOL
Low-level output voltage
Device fanout (OTW, SD)
0.4
V
FANOUT
External pullup to 5 V
10
Devices
(1) Pullup and pulldown resistors affect the leakage current.
10
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SLES188–AUGUST 2006
TYPICAL CHARACTERISTICS
blk
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
5
2
1
0.5
T
H
D
+
N
%
0.2
0.1
0.05
0.02
0.01
80m
200m
500m
1
2
5
10
20
50
100
200
300
Output Power W
Red - 4 Ohm
Blue - 6 Ohm
Magenta - 8 Ohm
Figure 3.
OUTPUT POWER
vs
PVDD_x SUPPLY VOLTAGE
UNCLIPPED OUTPUT POWER
vs
PVDD_x SUPPLY VOLTAGE
330
300
270
240
210
180
150
120
90
250
T
= 75°C
T = 75°C
C
C
225
200
175
150
125
100
75
THD+N at 10%
6 Ω
6 Ω
4 Ω
4 Ω
50
60
8 Ω
8 Ω
25
30
0
0
0
5
10 15 20 25 30 35 40 45 50
PVDD Supply Voltage − V
0
5
10 15 20 25 30 35 40 45 50
PVDD Supply Voltage − V
G001
G003
Figure 4.
Figure 5.
11
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TYPICAL CHARACTERISTICS
blk (continued)
SYSTEM EFFICIENCY
vs
OUTPUT POWER
SYSTEM POWER LOSS
vs
OUTPUT POWER
100
80
60
40
20
0
12
T
C
= 25°C
11
10
9
8
7
6
5
4
3
2
T
= 25°C
C
1
Two Channels
0
0
20
40
60
80
100 120
0
25
50
75
100
125
P
O
− Output Power − W
P
O
− Output Power − W
G004
G005
Figure 6.
Figure 7.
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
350
300
250
200
150
100
50
4 Ω
6 Ω
8 Ω
THD+N at 10%
25
0
0
50
75
100
125
T
C
− Case Temperature − °C
G006
Figure 8.
12
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TYPICAL CHARACTERISTICS
blk (continued)
NOISE AMPLITUDE
vs
FREQUENCY
+0
-5
-10
-15
-20
-25
-30
-35
-40
N
o
i
-45
-50
s
e
-55
-60
A
m
p
l
-65
-70
-75
i
t
-80
u
d
e
-85
-90
-
-95
d
B
r
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
0
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
11k
12k
13k
14k
15k
16k
17k
18k
19k
20k
21k
22k
f - Frequency - kHz
Figure 9.
13
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SLES188–AUGUST 2006
APPLICATION INFORMATION
Typical Application Schematic
14
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APPLICATION INFORMATION (continued)
Recommended Printed Circuit Board (PCB) Layout
PCB Requirements
•
•
2-oz copper (FR-4) recommended
PVDD voltage and capacitor selection in accordance with the data sheet
Figure 10. PCB (Top Layer)
Figure 11. PCB (Bottom Layer)
15
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THEORY OF OPERATION
PCB placement, and routing. As indicated, each half
bridge has independent power-stage supply pins
(PVDD_x). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_x pin is decoupled with two 100-nF
ceramic capacitors placed as close as possible to
each supply pin on the same side of the PCB as the
TAS5261 location. It is recommended to follow the
PCB layout of the TAS5261 reference design. For
additional information on the recommended power
supply and required components, see the application
diagrams given in this data sheet.
Power Supplies
To facilitate system design, the TAS5261 needs only
a
12-V supply in addition to a typical 50-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
To provide outstanding electrical and acoustic
characteristics, the PWM signal path, including gate
drive and output stage, is designed as identical,
independent half bridges. For this reason, each half
bridge has separated gate-drive supply (GVDD_x),
bootstrap pins (BST_x) and power-stage supply pins
(PVDD_x). Furthermore, an additional pin (VDD) is
provided as power supply for all common circuits.
Although supplied from the same 12-V source, it is
highly recommended to separate GVDD_x and VDD
on the printed circuit board (PCB) by RC filters (see
application diagram for details). These RC filters
provide the recommended high-frequency isolation.
Special attention should be paid to placing all
decoupling capacitors as close to their associated
pins as possible. In general, inductance between the
power-supply pins and decoupling capacitors must
be avoided. (See reference board documentation for
additional information.)
The 12-V supply should be powered from
a
low-noise, low-output-impedance voltage regulator.
Likewise, the 50-V power-stage supply is assumed to
have low output impedance and low noise. The
internal POR circuit eliminates the need for
power-supply sequencing. Moreover, the TAS5261 is
fully protected against erroneous power-stage turn
on due to parasitic gate charging. Thus,
voltage-supply ramp rates (dv/dt) are noncritical
within the specified range (see the Recommended
Operating Conditions section of this data sheet).
System Power-Up/Power-Down Sequence
Powering Up
There is no power-up sequence is required for the
TAS5261. The outputs of the H-bridge remain in a
high-impedance state until the gate-drive supply
voltage (GVDD_x) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is
recommended to hold RESET in a low state while
powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by
enabling a weak pulldown of the half-bridge output.
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_x) to the power-stage output pin
(OUT_x). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode
connected
between
the
gate-drive
power-supply pin (GVDD_x) and the bootstrap pin.
When the power-stage output voltage is high, the
bootstrap capacitor voltage is shifted above the
output voltage potential and, thus, provides
a
While powering up the TAS5261, RESET should be
held low.
suitable voltage supply for the high-side gate driver.
In an application with PWM switching frequencies in
the range of 352 kHz to 384 kHz, it is recommended
to use 33-nF ceramic capacitors, size 0603 or 0805,
for the bootstrap capacitor. These 33-nF capacitors
ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side
power-stage FET (LDMOS) fully started during all of
the remaining part of the PWM cycle. In an
application running at a reduced switching frequency,
generally 250 kHz to 192 kHz, the bootstrap
capacitor might need to be increased in value.
Special attention should be paid to the power-stage
power supply – this includes component selection,
Powering Down
There is no power-down sequence is required for the
TAS5261. The device remains fully operational as
long as the gate-drive supply (GVDD_x) voltage and
VDD voltage are above the undervoltage protection
(UVP) threshold level (see the Electrical
Characteristics section of this data sheet). Although
not specifically required, it is a good practice to hold
RESET low during power down, thus, preventing
audible artifacts including pops and clicks.
16
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TAS5261
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SLES188–AUGUST 2006
Error Reporting
Over Current (OC) Protection With Current
Limiting and Overload Detection
The SD and OTW pins are both active-low,
open-drain
outputs.
Their
function
is
for
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See Table 3 for OC-adjust resistor values. The
detector outputs are closely monitored by two
protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing. For instance, it
protection-mode signaling to a PWM controller or
other system-control device. Any fault resulting in
device shutdown is signaled by the SD pin going low.
Likewise, OTW goes low when the device junction
temperature exceeds 115°C. (see Table 2).
Table 2. Error Reporting
performs
a current-limiting function rather than
SD
OTW
DESCRIPTION
prematurely shutting down during combinations of
high-level music transients and extreme speaker
load impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a
second protection system triggers
shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state.
Over Temperature (OTE) or Over
Load (OLP) or Under Voltage (UVP)
0
0
Over Load (OLP), PWM Activity
Dectector, or Under Voltage (UVP)
0
1
1
1
0
1
a
latching
Over Temperature Warning. Junction
temperature higher than 125°C.
Normal operation. Junction
temperature lower than 125°C.
Table 3. OC-Adjust Resistor Values
It should be noted that asserting RESET low forces
the SD and OTW signals high, independent of faults
being present. It is recommended to monitor the
OTW signal using the system microcontroller and
respond to an overtemperature warning signal by, for
example, turning down the volume to prevent further
heating of the device resulting in device shutdown
(OTW). To reduce external component count, an
internal pullup resistor to 3.3 V is provided on both
the SD and OTW outputs. Level compliance for 5-V
logic can be obtained by adding external pullup
resistors to 5 V (see the Electrical Characteristics
section of this data sheet for further specifications).
CURRENT BEFORE OC OCCURS
(A)
OC-ADJUST
RESISTOR VALUES
(kΩ) (1)
MIN
15
12
7
TYP
16
13
8
MAX
17
14
8
22
27
47
68
5
5
6
100
3
4
4
(1) Resistor tolerance is ±5%.
For lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output
requirement and minimum load impedance.
Device Protection System
Higher-impedance loads require
threshold.
a
lower OC
The TAS5261 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as safeguarding the device from
permanent failure due to a wide range of fault
conditions, such as short circuit, overload, and
undervoltage. The TAS5261 responds to a fault by
The demodulation filter inductor must retain
minimum of 5-H inductance at twice the selected OC
threshold current.
a
Most inductors have decreasing inductance with
increasing temperature and increasing current
(saturation). To some degree, an increase in
temperature naturally occurs when operating at high
output currents, due to inductor core losses and the
dc resistance of the inductor copper winding. A
thorough analysis of inductor saturation and thermal
properties is strongly recommended.
immediately setting the power stage in
a
high-impedance state (Hi-Z) and asserting the SD
pin low. In situations other than overload, the device
automatically recovers when the fault condition has
been removed (e.g., the voltage supply has
increased). For highest possible reliability, recovering
from an overload fault requires external reset of the
device no sooner than 1 s after the shutdown (see
the Device Reset section of this data sheet).
Setting the OC threshold too low might cause issues,
such as lack of enough output power and/or
unexpected shutdowns due to sensitive overload
detection.
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the Application Information section of this
data sheet.
17
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TAS5261
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SLES188–AUGUST 2006
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND. It should be noted that a properly
functioning overcurrent detector assumes the
presence of a properly designed demodulation filter
at the power-stage output. Short-circuit protection is
not provided directly at the output pins of the power
stage but only on the speaker terminals (after the
demodulation filter). It is required to follow certain
guidelines when selecting the OC threshold and an
appropriate demodulation inductor.
VDD or GVDD_x pin results in all half-bridge outputs
immediately being set in the high-impedance state
(Hi-Z) and SD being asserted low. The device
automatically resumes operation when all supply
voltages have increased above the UVP threshold.
Device Reset
When RESET is asserted low, the output FETs in all
half bridges are forced into a high-impedance state
(Hi-Z). During this reset time, a resistor is connected
between OUT_x and PGND pins, in order to charge
the bootstrap capacitor.
Over Temperature (OTE) Protection
Asserting RESET input low removes fault
information. A rising-edge transition on the reset
input allows the device to resume operation after an
overload fault.
The
TAS5261
has
a
two-level,
temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds the OTW level stated
in the parametric table. If the device junction
temperature exceeds the OTE level stated in the
parametric table, the device is put into thermal
shutdown, resulting in all half-bridge outputs being
set in the high-impedance state (Hi-Z) and SD being
asserted low. OTE is latched in this case. To clear
the OTE latch, reset must be asserted. Thereafter,
the device resumes normal operation.
PWM Activity Detector
The PWM Activity Detector logic monitors individual
PWM inputs. If one or more inputs are stuck in either
a high state or a low state for more than a defined
length of time, the entire device is shut down.
The PWM Activity Detector is not latched and normal
operation resumes when PWM activity is present on
the PWM inputs. When an invalid PWM frame is
detected, the PWM Activity Detector responds
immediately (no delay). The TAS5261 resumes
operation as soon as valid PWM signals are present.
Under Voltage Protection (UVP) and
Power-On Reset (POR)
The UVP and POR circuits of the TAS5261 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_x and VDD supply voltages reach the UVP
level stated in the parametric table. Although
GVDD_x and VDD are independently monitored, a
supply-voltage drop below the UVP threshold on any
The PWM Activity Detector is reported as a low on
the SD pin.
Modulation Index Setting
96.1% is the recommended setting for the
modulation index limit of the PWM when driving the
TAS5261. The following shows modulation index
limit registers and setting value in hexadecimal for TI
modulators.
TAS5508/TAS5518: 0x16h at 04h
TAS5086: 0x10h at 04h
18
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
TAS5261DKD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DKD
36
36
36
36
29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5261DKDG4
TAS5261DKDR
TAS5261DKDRG4
SSOP
SSOP
SSOP
DKD
DKD
DKD
29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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