TAS5411-Q1 [TI]
具有 I2C 诊断和负载突降保护功能的汽车类 8W、单通道、4.5V 至 18V 模拟输入 D 类音频放大器;
| 型号： | TAS5411-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 诊断和负载突降保护功能的汽车类 8W、单通道、4.5V 至 18V 模拟输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总36页 (文件大小：1706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
TAS5411-Q1 具有负载突降和 I2C 诊断功能的 8W 单声道汽车类 D 类音频
放大器
1 特性
•
耐热增强型 16 引脚散热薄型小外形尺寸 HTSSOP
(PWP) 封装以及 PowerPAD™封装（焊盘朝下）
1
•
•
符合汽车类应用的 应用
具有符合 AEC-Q100 标准的下列特性：
•
•
旨在满足汽车电磁兼容性 (EMC) 要求
经 ISO9000:2002 TS16949 认证
–
器件温度等级 1：环境工作温度范围为 –40°C
至 125°C
2 应用
–
–
器件 HBM 分类等级 H2
器件 CDM 分类等级 C5
•
•
•
汽车类紧急呼叫 (eCall) 放大器
车载通讯系统
仪表板系统
•
•
单声道桥接负载 (BTL) D 类功率放大器
负载为 4Ω 且总谐波失真 + 噪声 (THD+N) 为 10%
时的输出功率为 8W
3 说明
•
•
•
•
运行电压范围：4.5V 至 18V
负载为 4Ω 时的效率为 83%
差分模拟输入
TAS5411-Q1 是一款单声道 D 类音频放大器，非常适
用于汽车类紧急呼叫 (eCall)、远程信息处理、仪表板
应用。该器件采用 14.4 VDC 汽车电池供电，可在负载
为 4Ω 且 THD+N 不超过 10% 的情况下提供高达 8W
的功率。该器件具有较宽的工作电压范围和优异的效
率，是需要起停支持或使用备用电池运行时的理想选
择。集成的负载突降保护能够缩减外部电压钳位电路的
成本与尺寸，板载负载诊断功能能够通过 I2C 报告扬声
器状态。
采用可调功率限制器的 Speaker Guard™ 扬声器保
护
•
•
75dB 电源抑制比 (PSRR)
负载诊断功能：
–
–
开路和短路输出负载
输出到电源和输出到接地短接
•
保护和监控功能：
器件信息(1)
–
–
–
–
–
短路保护
40V 负载突降保护符合 ISO-7637-2 标准
在音乐播放的同时进行输出直流电平检测
过热保护
器件编号
TAS5411-Q1
封装
封装尺寸（标称值）
HTSSOP (16)
5.00mm x 4.40mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
过压及欠压保护
效率
简化框图
100%
90%
80%
70%
60%
50%
40%
30%
20%
I2C
System
µP
OUTP
OUTN
IN_P
IN_N
TAS5411-Q1
LC
Device Efficiency
10%
System Efficiency
0
0
1
2
3
4
5
6
7
8
Output Power (W)
D001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOS921
TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 17
9.5 Register Maps......................................................... 18
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 20
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Examples................................................... 24
13 器件和文档支持 ..................................................... 26
13.1 器件支持................................................................ 26
13.2 文档支持................................................................ 26
13.3 接收文档更新通知 ................................................. 27
13.4 社区资源................................................................ 27
13.5 商标....................................................................... 27
13.6 静电放电警告......................................................... 27
13.7 术语表 ................................................................... 27
14 机械、封装和可订购信息....................................... 27
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements for I2C Interface Signals......... 8
7.7 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2015) to Revision B
Page
•
•
•
•
•
•
•
在 “特性” 列表中增加了汽车标题............................................................................................................................................. 1
Added voltage ratings for several pins to the Absolute Maximum Ratings table .................................................................. 4
Added test conditions for voltage gain in Electrical Characteristics table ............................................................................. 6
Added a capacitance specification to the I2C section of the Electrical Characteristics table................................................. 7
Changed the condition statement for the Typical Characteristics section.............................................................................. 9
Changed section title of Load Diagnostics Sequence ......................................................................................................... 13
添加了新的接收文档更新通知 部分....................................................................................................................................... 27
Changes from Original (November 2015) to Revision A
Page
•
已更改 器件状态，从产品预览更改为量产数据....................................................................................................................... 1
2
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
5 Device Comparison Table
PART NUMBER
TAS5411-Q1
TAS5421-Q1
OUTPUT POWER
OVERCURRENT SHUTDOWN
8 W
2.4 A
3.5 A
22 W
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP PowerPAD Package
Top View
GND
STANDBY
BYP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PVDD
FAULT
BSTP
OUTP
OUTN
BSTN
GND
SDA
Thermal
Pad
SCL
IN_P
IN_N
MUTE
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
BSTN
NO.
10
13
3
AI
AI
Bootstrap for negative-output high-side FET
Bootstrap for positive-output high-side FET
Voltage-regulator bypass-capacitor pin
BSTP
BYP
PBY
DO
FAULT
14
1
Active-low open-drain output used to report faults
GND
9
GND
Ground
16
7
IN_N
AI
AI
Inverting analog input
IN_P
6
Non-inverting analog input
MUTE
OUTN
OUTP
PVDD
SCL
8
DI
Mute input, active-high (no internal pullup or pulldown)
11
12
15
5
PO
PO
PWR
DI
Output (–)
Output (+)
Power supply
I2C clock
SDA
4
DI/DO
DI
I2C data
STANDBY
Thermal pad
2
Active-low STANDBY pin (no internal pullup or pulldown)
Must be soldered to ground
—
(1) DI = digital input, DO = digital output, AI = analog input, PWR = power supply, PBY = power bypass, PO = power output, GND = ground
Copyright © 2015–2018, Texas Instruments Incorporated
3
TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1)
MIN
–0.3
–1
MAX
UNIT
V
DC supply voltage range, V(PVDD)
Relative to GND
30
40
15
5
Pulsed supply voltage range, V(PVDD_MAX)
Supply voltage ramp rate, ΔV(PVDD_RAMP)
For SCL, SDA, STANDBY, FAULT pins
t ≤ 400 ms exposure
V/ms
Relative to GND
Relative to GND
Relative to GND
Relative to GND
Relative to BYP
Relative to GND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Input voltage
For IN_N, IN_P, and MUTE pins
6.5
7
BYP
V
BSTN, BSTP
36.3
30
30
±4
±1
7
BSTN, BSTP
OUTN, OUTP
DC current on PVDD, GND and OUTx pins, I(PVDD), IO
A
(2)
Current
Maximum current, on all input pins, I(IN_MAX)
mA
Maximum sink current for open-drain pin, I(IN_ODMAX)
Junction temperature, TJ
Storage temperature, Tstg
–40
–55
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Table 11 for information on analog input voltage and ac coupling.
7.2 ESD Ratings
VALUE
±3500
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply voltage range relative to GND.
V(PVDD_OP)
Includes ac transients, requires proper
4-Ω ±20% load (or higher)
4.5
14.4
18
V
decoupling.(1)
V(PVDD_RIPPLE)
Maximum ripple on PVDD
V(PVDD) < 8 V
1
Vpp
(2)
V(AIN)
Analog audio input-signal level
AC-coupled input voltage
0
2
0.25–1(3)
Vrms
STANDBY pin input voltage for logic-level
high
V(IH_STANDBY)
V(IL_STANDBY)
V(IH_SCL)
V
V
V
STANDBY pin input voltage for logic-level low
SCL pin input voltage for logic-level high
0.7
5.5
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
2.1
2.1
–0.5
–0.5
2
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
V(IH_SDA)
V(IL_SCL)
V(IL_SDA)
R(L)
SDA pin input voltage for logic-level high
SCL pin input voltage for logic-level low
SDA pin input voltage for logic-level low
Nominal speaker load impedance
5.5
1.1
1.1
16
V
V
V
Ω
V
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
R(PU_I2C) = 4.7-kΩ pullup, supply voltage =
3.3 V or 5 V
When using low-impedance loads, do not
exceed overcurrent limit.
4
Pullup voltage supply (for open-drain logic
outputs)
V(PU)
3
3.3
3.6
External pullup resistor on open-drain logic
outputs
Resistor connected between open-drain logic
output and V(PU) supply.
R(PU_EXT)
R(PU_I2C)
C(PVDD)
10
1
50
10
kΩ
kΩ
μF
I2C pullup resistance on SDA and SCL pins
4.7
10
External capacitor on the PVDD pin, typical
value ± 20%(1)
External capacitor on the BYP pin, typical
value ± 10%
C(BYP)
C(OUT)
C(IN)
1
μF
μF
μF
External capacitance to GND on OUT_X pins
4
External capacitance to analog input pin in
series with input signal
1
External boostrap capacitor, typical value ±
20%
C(BSTN), C(BSTP)
TA
220
nF
°C
Operating ambient temperature
–40
125
(1) See the Power Supply Recommendations section.
(2) Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
(3) Maximum recommended input voltage is determined by the gain setting.
7.4 Thermal Information
TAS5411-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
39.4
24.9
20
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
19.8
2
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Copyright © 2015–2018, Texas Instruments Incorporated
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ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
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7.5 Electrical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
PVDD idle current
PVDD standby current
OUTPUT POWER
In PLAY mode, no audio present
16
5
mA
STANDBY mode, MUTE = 0 V
20
μA
4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C
4 Ω, P(O) = 8 W (10% THD)
6
8
Output power per channel
W
Power efficiency
83%
AUDIO PERFORMANCE
Noise voltage at output
G = 20 dB, zero input, and A-weighting
f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P(O) = 1 W, f = 1 kHz
65
63
μV
dB
dB
Common-mode rejection ratio
Power-supply rejection ratio
Total harmonic distortion + noise
75
0.05%
400
500
3
Switching frequency selectable for AM interference
avoidance
Switching frequency
kHz
V
Internal common-mode input bias voltage
Internal bias applied to IN_N, IN_P pins
Source impedance = 0 Ω, register 0x03 bits 7–6 = 00
Source impedance = 0 Ω, register 0x03 bits 7–6 = 01
Source impedance = 0 Ω, register 0x03 bits 7–6 = 10
Source impedance = 0 Ω, register 0x03 bits 7–6 = 11
19
25
31
35
20
21
27
33
37
26
Voltage gain (VO / VIN
)
dB
32
36
PWM OUTPUT STAGE
FET drain-to-source resistance
Output offset voltage
TJ = 25°C
180
mΩ
Zero input signal, G = 20 dB
±25
mV
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set
PVDD overvoltage-shutdown hysteresis
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set
PVDD undervoltage-shutdown hysteresis
BYP
19.5
3.6
21
22.5
V
V
0.6
4
4.4
V
V
0.25
BYP pin voltage
6.4
6.9
0.3
7.4
4.1
V
POWER-ON RESET (POR)
PVDD voltage for POR
V
V
PVDD recovery hysteresis voltage for POR
6
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
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ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
Electrical Characteristics (continued)
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown
155
170
15
°C
°C
Junction temperature overtemperature shutdown
hysteresis
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current)
STANDBY PIN
2.4
0.1
2.9
A
STANDBY pin current
0.2
μA
DC DETECT
DC detect threshold
V
DC detect step response time
FAULT REPORT
700
ms
FAULT pin output voltage for logic-level high (open-drain
logic output)
External 47-kΩ pullup resistor to 3.3 V
External 47-kΩ pullup resistor to 3.3 V
2.4
V
V
FAULT pin output voltage for logic-level low (open-drain
logic output)
0.5
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or
ground
200
Ω
Open-circuit detection threshold
Short-circuit detection threshold
I2C
Including speaker wires
Including speaker wires
70
95
120
1.5
Ω
Ω
0.9
1.2
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
Capacitance for SCL and SDA pins
Capacitance for SDA pin
R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V
2.4
V
V
3-mA sink current
0.4
10
pF
pF
STANDBY mode
30
Copyright © 2015–2018, Texas Instruments Incorporated
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TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
7.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
MIN NOM
MAX
UNIT
kHz
ns
f(SCL)
tr
SCL clock frequency
400
300
300
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
ns
tw(H)
tw(L)
tsu(2)
th(2)
tsu(1)
th(1)
tsu(3)
C(B)
0.6
1.3
0.6
0.6
100
0(1)
0.6
μs
SCL pulse duration, low
μs
Setup time for START condition
START condition hold time before generation of first clock pulse
Data setup time
μs
μs
ns
Data hold time
ns
Setup time for STOP condition
Load capacitance for each bus line
μs
400
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu(1)
th(1)
SDA
T0027-03
Figure 1. SCL and SDA Timing
SCL
t(buf)
th(2)
tsu(2)
tsu(3)
SDA
Start
Condition
Stop
Condition
T0028-02
Figure 2. Timing for Start and Stop Conditions
8
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
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ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
7.7 Typical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W per channel, AES17 filter, 1-kHz input, default I2C settings (unless otherwise
noted)
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
10%
1%
0.1%
Device Efficiency
System Efficiency
0.01%
0
1
2
3
4
5
6
7
8
0.1
1
10
Output Power (W)
Output Power (W)
D001
D002
f(SW) = 400 kHz
TA = 25ºC
V(PVDD) = 14.4 V
Figure 3. Efficiency vs Output Power
Figure 4. THD+N vs Output Power
10%
1%
1.6
1.4
1.2
1
5-W Data
1-W Data
0.1%
0.8
0.6
0.4
0.2
0
0.01%
0.001%
0
1
2
3
4
5
6
7
8
10
100
1k
10k
Output Power (W)
Frequency (Hz)
D003
D004
Figure 5. Power Dissipation vs Output Power
Figure 6. THD+N vs Frequency
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D005
D006
Figure 7. Noise FFT With –60-dB Output
Figure 8. Noise FFT With 1-W Output
Copyright © 2015–2018, Texas Instruments Incorporated
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TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
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Typical Characteristics (continued)
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W per channel, AES17 filter, 1-kHz input, default I2C settings (unless otherwise
noted)
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D007
Figure 9. Overcurrent Threshold vs Temperature
8 Parameter Measurement Information
The parameters for the TAS5411-Q1 device were measured using the circuit in Figure 17.
10
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
9 Detailed Description
9.1 Overview
The TAS5411-Q1 device is a mono analog-input audio amplifier for use in the automotive environment. The
design uses an ultra-efficient class-D technology developed by Texas Instruments, but with features added for
the automotive industry. This technology allows for reduced power consumption, reduced heat, and reduced
peak currents in the electrical system. The device realizes an audio sound system design with smaller size and
lower weight than traditional class-AB solutions.
There are seven core design blocks:
•
•
•
•
•
•
•
PWM
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
9.2 Functional Block Diagram
Overcurrent Detection
DC Detection
PVDD
BYP
LDO
Regulator
GVDD
GVDD
Biases
and
References
Protection
Control
SDA
I2C
Thermal Protection
Voltage Protection
SCL
Short-to-Ground
Short-to-Power
Shorted Load
Open Load
BSTN
PVDD
Control
Diagnostics
Control
FAULT
MUTE
Gate
Drive
OUTN
STANDBY
GVDD
IN_N
Pulse
Width
GND
Gain
Control
Speaker
Guard
Preamplifier
BSTP
Modulator
(PWM)
PVDD
IN_P
GND
Gate
Drive
OUTP
GND
9.3 Feature Description
9.3.1 Analog Audio Input and Preamplifier
The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a
differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be
ac-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
The gain setting impacts the analog input impedance of the amplifier. See Table 1 for typical values.
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Table 1. Input Impedance and Gain
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
60 kΩ ± 20%
30 kΩ ± 20%
15 kΩ ± 20%
9 kΩ ± 20%
9.3.2 Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5411-Q1 device, the modulator is an advanced
design with high bandwidth, low noise, low distortion, and excellent stability.
The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V
to PVDD. The OUTP and OUTN pins are in phase with each other with no input, so that there is little or no
current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive
output voltages. The duty cycle of OUTN is greater than 50% and that of OUTP is less than 50% for negative
output voltages. The voltage across the load is at 0 V through most of the switching period, reducing power loss.
OUTP
OUTN
No Output
OUTP – OUTN
0 V
0 A
Speaker
Current
OUTP
OUTN
Positive Output
PVDD
0 V
OUTP – OUTN
Speaker
Current
0 A
OUTP
OUTN
Negative Output
0 V
OUTP – OUTN
–PVDD
0 A
Speaker
Current
Figure 10. BD Mode Modulation
12
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9.3.3 Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
9.3.4 Power FETs
The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the
load. By design, the FETs withstand large voltage transients during a load-dump event.
9.3.5 Load Diagnostics
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output
connections. The device supports the following diagnostics:
•
•
•
•
Short to GND
Short to PVDD
Short across load
Open load
The device reports the presence of any of the short or open conditions to the system via I2C register read.
9.3.5.1 Load Diagnostics Sequence
The load diagnostic function runs on deassertion of STANDBY or when the device is in a fault state (dc detect,
overcurrent, overvoltage, undervoltage, or overtemperature). During this test, the outputs are in a Hi-Z state. The
device determines whether the output is a short to GND, short to PVDD, open load, or shorted load. The load
diagnostic biases the output, which therefore requires limiting the capacitance value for proper functioning; see
the Recommended Operating Conditions. The load diagnostic test takes approximately 229 ms to run. Note that
the check phase repeats up to 5 times if a fault is present or a large capacitor to GND is present on the output.
On detection of an open load, the output still operates. On detection of any other fault condition, the output goes
into a Hi-Z state, and the device checks the load continuously until removal of the fault condition. After detection
of a normal output condition, the audio output starts. The load diagnostics run after every other overvoltage (OV)
event. The load diagnostic for open load only has I2C reporting. All other faults have I2C and FAULT pin
assertion.
The device performs load diagnostic tests as shown in Figure 11.
Figure 12 illustrates how the diagnostics determine the load based on output conditions.
Discharge
(75 ms)
Ramp Up
(52 ms)
Check
(50 ms)
Ramp Down
(52 ms)
Figure 11. Load Diagnostics Sequence of Events
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Output Conditions
Load Diagnostics
Open Load
Open Load Detected
OL Max
OL Min
SL Max
SL Min
Normal or Open Load
May Be Detected
Open Load (OL)
Detection Threshold
Normal
Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Detected
Shorted
Load
Figure 12. Load Diagnostic Reporting Thresholds
9.3.5.2 Faults During Load Diagnostics
If the device detects a fault (overtemperature, overvoltage, undervoltage) during the load diagnostics test, the
device exits the load diagnostics, which may result in a pop or click on the output.
9.3.6 Protection and Monitoring
•
Overcurrent Shutdown (OCSD)—The overcurrent shutdown forces the output into Hi-Z. The device asserts
the FAULT pin and updates the I2C register.
•
DC Detect—This circuit checks for a dc offset continuously during normal operation at the output of the
amplifier. If a dc offset occurs, the device asserts the FAULT pin and updates the I2C register. Note that the
dc detection threshold follows PVDD changes.
•
Overtemperature Shutdown (OTSD)—The device shuts down when the die junction temperature reaches
the overtemperature threshold. The device asserts the FAULT pin and updates I2C register. Recovery is
automatic when the temperature returns to a safe level.
•
•
Undervoltage (UV)—The undervoltage (UV) protection detects low voltages on PVDD. In the event of an
undervoltage condition, the device asserts the FAULT pin and resets the I2C register.
Power-On Reset (POR)—Power-on reset (POR) occurs when PVDD drops below the POR threshold. A POR
event causes the I2C bus to go into a high-impedance state. After recovery from the POR event, the device
restarts automatically with default I2C register settings. The I2C is active as long as the device is not in POR.
•
•
•
Overvoltage (OV) and Load Dump—OV protection detects high voltages on PVDD. If PVDD reaches the
overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. The device can
withstand 40-V load-dump voltage spikes.
SpeakerGuard™ Protection Circuitry—This protection circuitry limits the output voltage to the value
selected in I2C register 0x03. This value determines both the positive and negative limits. One can use this
feature to improve battery life or protect the speaker from exceeding its excursion limits.
Adjacent-Pin Shorts—The device design is such that shorts between adjacent pins do not cause damage.
9.3.7 I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions
and detections are via I2C. The system can also set numerous features and operating conditions via the I2C
interface. The I2C interface is active approximately 1 ms after the STANDBY pin is high.
14
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The I2C interface controls the following device features:
•
•
•
•
Changing the gain setting to 20 dB, 26 dB, 32 dB, or 36 dB
Controlling the peak voltage value of the SpeakerGuard protection circuitry
Reporting load diagnostic results
Changing of the switching frequency for AM radio avoidance
9.3.7.1 I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only
device that does not support a multimaster bus environment or wait-state insertion. The master device uses the
I2C control interface to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-to-
LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. Figure 13 shows these conditions. The master
generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and
then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to
indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address
for each device is a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an
external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the
communicating devices can transmit between start and stop conditions. After transfer of the last word, the master
generates a stop condition to release the bus.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-02
Figure 13. Typical I2C Sequence
To communicate with the device, the I2C master uses addresses shown in Figure 13. Transmission of read and
write data can be by single-byte or multiple-byte data transfers.
9.3.7.2 Random Write
As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
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Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-05
Figure 14. Random Write Transfer
9.3.7.3 Random Read
As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, the master device
performs both a write and a following read. Initially, the master device performs a write to transfer the address
byte of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address
and the read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal
memory address byte, the master device transmits another start condition followed by the device address and
the read/write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address
and the read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a not-
acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
Figure 15. Random Read Transfer
9.3.7.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5411-Q1
device transmits multiple data bytes to the master device as shown in Figure 16. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte and automatically increments
the I2C subaddress by 1. After receiving the last data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-07
Figure 16. Sequential Read Transfer
16
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9.4 Device Functional Modes
9.4.1 Hardware Control Pins
There are three discrete hardware pins for real-time control and indication of device status.
FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition which requires
the device to go into the Hi-Z mode. On assertion of this pin, the device has protected itself and the system
from potential damage. The system can read the exact nature of the fault via I2C with the exception of PVDD
undervoltage faults below POR, in which case the I2C bus is no longer operational.
STANDBY pin: Assertion of this active-low pin sends the device into a complete shutdown, limiting the
current draw.
MUTE pin: On assertion of this active-high pin, the device is in mute mode. The output pins stop switching
and audio does not pass from the input to the output. To place the device back into play mode, it is
necessary to deassert this pin.
9.4.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces
the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that
optimizes output transitions that cause EMI.
9.4.3 Operating Modes and Faults
The following tables list operating modes and faults.
Table 2. Operating Modes
STATE NAME
Standby
OUTPUT
Hi-Z, floating
OSCILLATOR
Stopped
Active
I2C
Stopped
Active
Active
Active
Load diagnostic
Fault and mute
Play
DC biased
Hi-Z, floating
Active
Switching with audio
Active
Table 3. Faults and Actions
FAULT
EVENT
FAULT EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
CLEARING
POR
Not applicable
I2C + FAULT pin
FAULT pin
Standby
UV or OV
Load dump(1)
OTSD
Voltage fault
All
Hard mute (no ramp)
Thermal fault
Hi-Z, mute, play
Play
Hi-Z
Self-clearing
OC fault
DC detect
Output channel
fault
I2C + FAULT pin
Load diagnostic –
short
Hi-Z, rerun
diagnostics
Diagnostic
Hi-Z
None
Load diagnostic –
open
Clears on next
diagnostic
cycle
I2C
None
(1) Tested in accordance with ISO7637-1
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9.5 Register Maps
Table 4. I2C Address
FIXED ADDRESS
READ/WRITE BIT
DESCRIPTION
I2C write
I2C read
I2C ADDRESS
MSB
6
1
1
5
0
0
4
1
1
3
1
1
2
0
0
1
0
0
LSB
1
1
0
1
0xD8
0xD9
Table 5. I2C Address Register Definitions
ADDRESS
R/W
REGISTER DESCRIPTION
0x01
0x02
0x03
R
R
Latched fault register
Status and load diagnostics register
Control register
R/W
Table 6. Fault Register (0x01)
D7
0
D6
D5
0
D4
0
D3
0
D2
0
D1
D0
FUNCTION
0
–
–
–
–
–
–
1
–
0
0
No protection-created faults, default value
Reserved
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
–
–
–
–
1
A load-diagnostics fault has occurred.
Overcurrent shutdown has occurred.
PVDD undervoltage has occurred.
PVDD overvoltage has occurred.
DC offset protection has occurred.
Overtemperature shutdown has occurred.
–
–
–
1
–
–
–
1
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
Table 7. Status and Load Diagnostic Register (0x02)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No speaker-diagnostic-created faults, default value
Output short to PVDD is present.
Output short to ground is present.
Open load is present.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Shorted load is present.
–
–
–
1
–
–
–
–
In a fault condition
–
–
1
–
–
–
–
–
Performing load diagnostics
In mute mode
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
In play mode
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Table 8. Control Register (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
1
1
1
0
0
0
26-dB gain, switching frequency set to 400 kHz, SpeakerGuard protection
circuitry disabled
–
–
–
–
–
–
–
–
–
0
1
1
–
–
–
–
–
–
–
–
–
0
0
1
–
–
1
1
1
0
0
0
0
–
–
–
–
–
1
0
0
1
1
0
0
–
–
–
–
–
0
1
0
1
0
1
0
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
1
-
Switching frequency set to 500 kHz
Reserved
–
–
–
–
–
–
–
–
–
–
SpeakerGuard protection circuitry set to 14-V peak output
SpeakerGuard protection circuitry set to 11.8-V peak output
SpeakerGuard protection circuitry set to 9.8-V peak output
SpeakerGuard protection circuitry set to 8.4-V peak output
SpeakerGuard protection circuitry set to 7-V peak output
SpeakerGuard protection circuitry set to 5.9-V peak output
SpeakerGuard protection circuitry set to 5-V peak output
Gain set to 20 dB
Gain set to 32 dB
Gain set to 36 dB
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www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The device is a mono high-efficiency class-D audio amplifier. Typical use of the device is to amplify an audio
input to drive a speaker. The intent of its use is for a bridge-tied load (BTL) application, not for support of a
single-ended configuration. This section presents how to use the device in the application, including what
external components are necessary and how to connect unused pins.
10.2 Typical Application
L1
PVDD
10uH
C8
330µF
C5
4.7µF
C4
4.7µF
C3
0.082µF
C2
2200pF
C7
10µF
C6
0.1µF
C9
IN_P
1µF
R5
49.9k
U1
L2
R6
49.9k
6
7
15
13
12
IN_P
PVDD
C10
OUTP
15µH 2.7A
C16
1µF
BSTP
OUTP
R4
5.6
IN_N
IN_N
0.22µF
C11
2.2uF
C12
0.01µF
C13
5
4
SCL
SDA
SCL
SDA
11
10
OUTN
BSTN
470pF
C14
2
8
STANDBY
MUTE
STANDBY
MUTE
0.22µF
16
9
C15
GND
GND
GND
PAD
14
FAULT
FAULT
1
470pF
L3
3
BYP
R7
5.6
TAS5411QPWPRQ1
C20
1µF
OUTM
15µH 2.7A
C17
2.2uF
C18
0.01µF
Figure 17. TAS5411-Q1 Typical Application Schematic
20
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Typical Application (continued)
10.2.1 Design Requirements
Use the following for the design requirements:
•
Power Supplies
The device needs only a single power supply compliant with the recommended operation range. The device
is designed to work with either a vehicle battery or regulated power supply such as from a backup battery.
•
Communication
The device communicates with the system controller with both discrete hardware control pins and with I2C.
The device is an I2C slave and thus requires a master. If a master I2C-compliant device is not present in the
system, it is still possible to use the device, but only with the default settings. Diagnostic information is limited
to the discrete reporting FAULT pin.
•
External Components
Table 9 lists the components required for the device.
Table 9. Supporting Components
EVM DESIGNATOR QUANTITY
C7
VALUE
10 μF ± 10%
330 μF ± 20%
1 μF ± 10%
SIZE
DESCRIPTION
X7R ceramic capacitor, 25-V
Low-ESR aluminum capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 250-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 50-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
Shielded ferrite inductor
USE IN APPLICATION
Power supply
1
1
3
2
2
2
1
1
1
2
2
1
1
2
2
1206
10 mm
0805
0603
0805
0603
0603
0603
0603
1206
0603
C8
Power supply
C9, C16, C20
C10, C14
C11, C17
C13, C15
C6
Analog audio input filter, bypass
Bootstrap capacitors
Amplifier output filtering
Amplifier output snubbers
Power supply
0.22 μF ± 10%
2.2 μF ± 10%
470 pF ± 10%
0.1 μF ± 10%
2200 pF ± 10%
0.082 μF ± 10%
4.7 μF ± 10%
0.01 μF ± 10%
10 μH ± 20%
15 μH ± 20%
49.9 kΩ ± 1%
5.6 Ω ± 5%
C2
Power supply
C3
Power supply
C4, C5
C12, C18
L1
Power supply
Output EMI filtering
Power supply
13.5 mm ×13.5 mm
7 mm × 7 mm
0805
L2, L3
R5, R6
R4, R7
Metal alloy inductor
Amplifier output filtering
Analog audio input filter
Output snubbers
Resistors, 0.125-W
0805
Resistors, 0.125-W
10.2.1.1 Amplifier Output Filtering
Output FETs drive the amplifier outputs in an H-bridge configuration. These transistors are either fully off or on.
The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. The amplifier outputs require a low-pass filter to filter out the PWM modulation carrier frequency. People
frequently call this filter the L-C filter, due to the presence of an inductive element L and a capacitive element C
to make up the 2-pole low-pass filter. The L-C filter attenuates the carrier frequency, reducing electromagnetic
emissions and smoothing the current waveform which the load draws from the power supply. See the Class-D
LC Filter Design application report, SLOA119, for a detailed description on proper component selection and
design of an L-C filter based on the desired load and response.
10.2.1.2 Amplifier Output Snubbers
A snubber is an RC network placed at the output of the amplifier to dampen ringing or overshoot on the PWM
output waveform. Overshoot and ringing have several negative impacts including: potential EMI sources,
degraded audio performance, and overvoltage stress of the output FETs or board components. For more
information on the use and design of output snubbers, see the Class-D Output Snubber Design Guide,
SLOA201.
10.2.1.3 Bootstrap Capacitors
The output stage uses dual NMOS transistors; therefore, the circuit requires bootstrap capacitors for the high
side of each output to turn on correctly. The required capacitor connection is from BSTN to OUTN and from
BSTP to OUTP as shown in Figure 17.
Copyright © 2015–2018, Texas Instruments Incorporated
21
TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
10.2.1.4 Analog Audio Input Filter
The circuit requires an input capacitor to allow biasing of the amplifier put to the proper dc level. The input
capacitor and the input impedance of the amplifier form a high-pass filter with a –3-dB corner frequency
determined by the equation: f = 1 / (2πR(i)C(i)), where R(i) is the input impedance of the device based on the gain
setting and C(i) is the input capacitor value. Table 10 lists largest recommended input capacitor values. Use a
capacitor which matches the application need for the lowest frequency but does not exceed the values listed.
Table 10. Recommended Input AC-Coupling Capacitors
TYPICAL INPUT IMPEDANCE
GAIN (dB)
INPUT CAPACITANCE (µF)
HIGH-PASS FILTER (Hz)
(kΩ)
20
60
1
2.7
1.8
5.3
1.6
2.3
1.8
1.5
1
26
30
3.3
5.6
10
32
36
15
9
10.2.2 Detailed Design Procedure
Use the following steps for the design procedure:
1. Hardware Schematic Design: Using the Typical Application Schematic as a guide, integrate the hardware
into the system schematic.
2. Following the recommended layout guidelines, integrate the device and its supporting components into the
system PCB file.
3. Thermal Design: The device has an exposed thermal pad which requires proper soldering. For more
information, see the Semiconductor and IC Package Thermal Metrics, SPRA953, and the PowerPAD
Thermally Enhanced Package, SLMA002G, application reports.
4. Develop software: The EVM User's Guide, SLOU431, has detailed instructions for how to set up the device,
interpret diagnostic information, and so forth. For information about control registers, see the Register Maps
section.
10.2.2.1 Unused Pin Connections
Even if unused, always connect pins to a fixed rail; do not leave them floating. Floating input pins represent an
ESD risk, so adhere to the following guidance for each pin.
10.2.2.1.1 MUTE Pin
If the MUTE pin is unused in the application, connect it to GND through a high-impedance resistor.
10.2.2.1.2 STANDBY Pin
If the STANDBY pin is unused in the application, connect it to a low-voltage rail such as 3.3 V or 5 V through a
high-impedance resistor.
10.2.2.1.3 I2C Pins (SDA and SCL)
If there is no microcontroller in the system, use of the device without I2C communication is possible. In this
situation, connect the SDA and SCL pins to 3.3 V.
10.2.2.1.4 Terminating Unused Outputs
If the FAULT pin does not report to a system microcontroller in the application, connect it to GND.
10.2.2.1.5 Using a Single-Ended Audio Input
When using a single-ended audio source, ac-ground the negative input through a capacitor equal in value to the
input capacitor on the positive input, and apply the audio source to the positive input. For best performance, the
ac ground should be at the audio source instead of at the device input if possible.
22
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
10.2.3 Application Curves
See the graphs listed in Table 11 for the application performance plots.
Table 11. Table of Graphs
GRAPH
FIGURE NO.
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Efficiency vs Output Power
THD+N vs Output Power
Output Power vs PVDD
THD+N vs Frequency
Noise FFT With –60-dB Output
Noise FFT With 1-W Output
Overcurrent Threshold vs Temperature
11 Power Supply Recommendations
A car battery that can have a large voltage range most commonly provides power for the device. PVDD, a filtered
battery voltage, is the supply for the output FETs and the low-side FET gate driver. Good power-supply
decoupling is necessary, especially at low voltage and temperature levels. To meet the PVDD specifications in
the Electrical Characteristics section, TI uses 10-µF and 0.1-µF ceramic capacitors near the PVDD pin along with
a larger bulk 330-µF electrolytic decoupling capacitor.
An internal linear regulator, which powers the analog circuitry, provides the voltage on the BYP pin. This supply
requires an external bypass ceramic capacitor at the BYP pin.
Copyright © 2015–2018, Texas Instruments Incorporated
23
TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The TAS5411-Q1 device has a thermal
pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC
performance. TAS5411Q1EVM illustrations form the basis for the layout discussions.
12.2 Layout Examples
12.2.1 Top Layer
The red boxes around number 1 are the copper ground on the top layer. Soldered directly to the thermal pad,
this ground is the first significant thermal dissipation needed. There are vias that go to the other layers for further
thermal relief, but vias have high thermal resistance. TI recommends that use of this top layer be mostly for
thermal dissipation. A further recommendation is short routes from output pins to the second-order LC filter for
EMC suppression. The number 2 arrow indicates these short routes. The shorter the distance, the less EMC
radiates. A short route from the PVDD pin to the LC filter from the battery or power source, as indicated by the
number 3 arrow, also improves EMC suppression. The red box around number 4 indicates the ground plane that
is common to both OUTP and OUTN. Place the capacitors of the LC filter in this common ground plane to help
with common-mode noise and short ground loops.
Figure 18. Top Layer
24
Copyright © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
Layout Examples (continued)
12.2.2 Second Layer – Signal Layer
If possible, route the I2C and the positive and negative input traces close together and cover with ground plane,
keeping the signals from noise.
Figure 19. Signal Layer
12.2.3 Third Layer – Power Layer
There is no need for a power plane, but TI recommends a wide single PVDD trace to keep the switching noise to
a minimum and provide enough current to the device. The wide trace provides a low-impedance path from the
power source to the PVDD pin and from the GND pin to the source return. Suppression of switching noise (ripple
voltage) on both the positive and return (ground) paths requires a low impedance.
Figure 20. Power Layer
Copyright © 2015–2018, Texas Instruments Incorporated
25
TAS5411-Q1
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
www.ti.com.cn
Layout Examples (continued)
12.2.4 Bottom Layer – Ground Layer
The device has an exposed thermal pad on the bottom side for improved thermal performance. Conducting heat
from the thermal pad to other layers requires thermal vias. Because the bottom layer is the secondary heat
exchange surface to ambient, the thermal vias area must have low thermal resistance, that is, no signal vias or
traces that can increase thermal resistance from the thermal vias to the bottom copper.
Figure 21. Bottom Layer
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
《AN-1737 管理 D 类音频 应用中的 EMI》
《D 类 LC 滤波器设计》
《D 类输出缓冲器设计指南》
《音频功率放大器性能测量指南》
《PowerPAD 热增强型封装》
《TAS5411Q1EVM 用户指南》
《具有负载突降和 I2C 诊断功能的 TAS5421-Q1 22W 单声道汽车类数字音频放大器》
26
版权 © 2015–2018, Texas Instruments Incorporated
TAS5411-Q1
www.ti.com.cn
ZHCSEH3B –DECEMBER 2015–REVISED SEPTEMBER 2018
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
PowerPAD, SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是适用于指定器件的最新数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航面板。
版权 © 2015–2018, Texas Instruments Incorporated
27
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5411QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TAS5411
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5411QPWPRQ1
HTSSOP PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TAS5411QPWPRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X 0.15 MAX
NOTE 5
2X 0.95 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.0
2.4
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.0
2.4
4218971/A 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
SYMM
(3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218971/A 01/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3)
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.35 X 3.35
3 X 3 (SHOWN)
2.74 X 2.74
0.125
0.15
0.175
2.54 X 2.54
4218971/A 01/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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