TAS5412TPHDRQ1_技术文档

TAS5412-Q1

www.ti.com.cn

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

双通道汽车用数字放大器

查询样品: TAS5412-Q1

1

特性

–

过热保护

过压及欠压保护

片段检测

234

•

TAS5412-Q1 - 单端输入

•

2 通道数字功率放大器

•

TAS5412-Q1 - 64 引脚四方扁平封装 (QFP) (PHD)

PowerPAD™ 表面贴装封装

•

2 个模拟输入，2 个桥接负载 (BTL) 功率输出

10% 时，每通道典型输出功率

•

与 4 通道器件引脚兼容

–

14.4 VDC 供电时，为 4Ω 负载提供每通道 28W

功率

设计用于汽车电磁兼容性 (EMC) 要求

将符合 AEC-Q100 标准要求

经 ISO9000:2002 TS16949 认证

-40°至 105°C 环境温度范围

14.4 VDC 供电时，为 2Ω 负载提供每通道 46W

功率

24 VDC 供电时，为 2Ω 负载提供每通道 79W

功率

应用范围

24 VDC 并行桥接负载 (PBTL) 时，为 2Ω 负载

提供 150W 功率

•

无线电广播音响本体

外部放大器

14.4 VDC PBTL 时，为 1Ω 负载提供 90W 功

率

•

总谐波失真 (THD) + N < 0.02%，1kHz，为 4Ω 负

载提供 1W 功率

说明

此器件是一款 2 通道数字音频放大器，此放大器设计

用于汽车音响本体和外部放大器。它在电源电压为

14.4V，THD + N 为 10% 时，用两个通道为 4Ω 负载

提供 28W 功率，或者在 THD + N 为 10% 时为 2Ω 负

载提供 46W 功率。此数字脉宽调制 (PWM) 拓扑结构

极大提升了传统线性放大器解决方案的效率。这将典

型音乐回放条件下放大器的功率耗散减少了因数 10。

此器件包含一个已获专利的 PWM 设计，此设计在汽

车应用中常见的恶劣电气环境中提供出色的电源抑制。

应用可在无需复杂电源系统配置的情况下获得高效率。

此设计可实现多个器件的同步。

•

已获专利的弹出和点击衰减技术

已获专利的 AM 干扰避免

已获专利的逐周期电流限制

75dB 电源抑制比 (PSRR)

针对器件配置和控制的 4 地址 I²C 串行接口

通道增益：12dB，20dB，26dB，32dB

负载诊断功能：

–

输出打开和短接负载

输出到电源和输出到接地短接

已获专利的高频扬声器侦测

•

保护和监控功能：

此器件包含在要求严格的 OEM 应用领域内执行所需的

全部功能，其中包括用于检测和诊断错误连接输出的负

载诊断功能。

–

短路保护

50V 负载突降保护

偶然开放式接地和电源容错

这份与其它数据表内容无关的文本只用于调整首页内的

列长度。

已获专利的在音乐播放同时进行输出 DC 电平

检测

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

PowerPAD is a trademark of Texas Instruments.

Ceramique is a trademark of Arctic Silver Inc.

Arctic Silver is a registered trademark of Arctic Silver Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLOS685

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

TAS5412-Q1 FUNCTIONAL BLOCK DIAGRAM

PIN ASSIGNMENTS AND FUNCTIONS

The pin assignments are as follows:

2

TAS5412-Q1

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ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

TAS5412-Q1

PHD Package

(Top View)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

NU

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

FAULT

MUTE

GND

2

3

GND

OUT1_M

OUT1_P

4

STANDBY

D_BYP

5

CLIP_OTW

GND

6

GND

CPC_TOP

7

GND

8

CP

CP_BOT

GND

9

REXT

10

11

12

13

14

15

16

GND

A_BYP

GND

OUT2_M

OUT2_P

GND

CM_CAP1

GND

NU

IN1_P

NU

GND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P0070-03

Table 1. TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NAME

A_BYP

NO.

11

PBY

DO

Bypass pin for the AVDD analog regulator

Reports clip detect, tweeter detection, and overtemperature warning with open-drain

output

CLIP_OTW

6

CM_CAP1

CM_CAP2

CP

13

20

41

40

42

5

AI

Common mode capacitor

CP

PBY

DO

Top of main storage capacitor for charge pump

Bottom of flying capacitor for charge pump

Top of flying capacitor for charge pump

Bypass pin for DVDD regulator output

Global fault output (open-drain): UV, OV, OTSD, OCSD, dc

CPC_BOT

CPC_TOP

D_BYP

FAULT

1

3

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

3, 7-9, 12,14,

16, 17, 21–26,

30–32, 35, 38,

39, 43, 49–51,

55–60

GND

Ground

I2C_ADDR

IN1_P

62

AI

I²C address bit

15

Non-inverting analog input for channel 1

Non-inverting analog input for channel 2

Signal return for both analog channel inputs

Gain-ramp control

IN2_P

19

AI

IN_M

18

ARTN

DI

MUTE

2

NU

33, 34, 47, 48

NC

No connect, do not connect to ground

Oscillator input from master or output to slave amplifiers

– polarity output for bridge 1

OSC_SYNC

OUT1_M

OUT1_P

OUT2_M

OUT2_P

PVDD

61

DI, DO

PO

45

44

PO

+ polarity output for bridge 1

37

PO

– polarity output for bridge 2

36

PO

+ polarity output for bridge 2

27–29, 52–54

PWR

AI

PVDD supply

REXT

10

64

63

4

Precision resistor pin to set analog reference

I²C clock input from system I²C master

I²C data I/O for communication with system I²C master

Active-low STANDBY pin. Standby (low), power up (high)

SCL

DI

SDA

DI, DO

DI

STANDBY

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

V

PVDD

DC supply voltage range

Relative to GND

–0.3 to 30

–1 to 50

15

PVDD _MAX

PVDD _RAMP

I_PVDD

Pulsed supply-voltage range

t ≤ 400 ms exposure

V

Supply-voltage ramp rate

V/ms

A

Externally imposed dc supply current per PVDD or GND pin

Pulsed supply current per PVDD pin (one shot)

Maximum allowed dc current per output pin

Pulsed output current per output pin (single pulse)

±12

I_{PVDD_MAX}

I_O

t < 100 ms

17

A

±13.5

±17

A

(1)

I_{O_MAX}

t < 100 ms

A

(2)

I_{IN_MAX}

Maximum current, all digital and analog input pins

DC or pulsed

±1

mA

I_{MUTE_MAX}

I_{IN_ODMAX}

Maximum current on MUTE pin

±20

Maximum sinking current for open-drain pins

7

Input voltage range for logic pin relative to GND (SCL and

SDA pins)

V_LOGIC

–0.3 to 6

V

V_{I2C_ADDR}

V_STANDBY

V_{OSC_SYNC}

Input voltage range for I2C_ADDR pin relative to GND

Input voltage range for STANDBY pin

–0.3 to 6

–0.3 to 5.5

–0.3 to 3.6

1.9

V

Input voltage range for OSC_SYNC pin relative to GND

V

V_{AIN_AC_MAX_5412}Maximum ac-coupled input voltage⁽²⁾, analog input pins

Vrms

V

V_GND

T_J

Maximum voltage between GND pins

Maximum operating junction temperature range

Storage temperature range

±0.3

–55 to 150

°C

T_stg

(1) Pulsed-current ratings are maximum survivable currents externally applied to the TAS5412-Q1. Reverse-battery, fortuitous open-ground,

and fortuitous open-supply fault conditions may result in high currents.

(2) See Application Information section for information on analog input voltage and ac coupling.

4

TAS5412-Q1

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ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

THERMAL CHARACTERISTICS

PARAMETER

VALUE (Typical)

UNIT

°C/W

mm

R_θJC

Junction-to-case (heat slug) thermal resistance

Exposed pad dimensions

1.7

8 × 8

ELECTROSTATIC DISCHARGE (ESD)

PARAMETER

PINS

VALUE (Typical)

UNIT

Human-body model (HBM) AEC-

Q100-002

ALL

3000

Corner pins excluding SCL

750

600

400

100

Charged-device model (CDM)

AEC-Q100-011

All pins (including SCL) except CP and CP_TOP

CP and CP_TOP pins

V

Machine model (MM) AEC-Q100- All

003

5

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

(1)

RECOMMENDED OPERATING CONDITIONS

MIN

6

NOM

14.4

MAX

UNIT

V

PVDD_OP

PVDD_I2C

V_{AIN_5412}

T_A

DC supply voltage range relative to GND

DC supply voltage range for I²C reporting

Analog audio input signal level

Ambient temperature

24

5

26.5

V

(2)

(3)

AC-coupled input voltage

0

0.25–1

Vrms

°C

–40

105

115

An adequate heat sink is required

to keep T_Jwithin specified range.

T_J

Junction temperature

–40

°C

R_L

Nominal speaker load impedance

2

3

4

Ω

V_PU

Pullup voltage supply (for open-drain logic outputs)

3.3 or 5

5.5

100

10

V

Resistor connected between open-

drain logic output and V_PUsupply

R_{PU_EXT}

R_{PU_I2C}

R_{I2C_ADD}

External pullup resistor on open-drain logic outputs

I²C pullup resistance on SDA and SCL pins

10

1

47

kΩ

4.7

Total resistance of voltage divider for I²C address

slave 1 or slave 2, connected between D_BYP and

GND pins

10

100

kΩ

R_REXT

C_{D_BYP,}C _{A_BYP}

C_OUT

External resistance on REXT pin

1% tolerance required

19.8

10

20

20.2

120

680

kΩ

nF

External capacitance on D_BYP and A_BYP pins

External capacitnace to GND on OUT_X pins

150

1

External capacitance to analog input pin in series

with input signal

C_IN

µF

C_FLY

Flying capacitor on charge pump

Charge-pump capacitor

0.47

100

1

1.5

µF

nF

pF

C_P

50 V needed for load dump

C_MUTE

Capacitance on MUTE pin

330

75

C_{OSCSYNC_MAX}

Allowed loading capacitance on OSC_SYNC pin

(1) The Recommended Operating Conditionstable specifies only that the device is functional in the given range. See the Electrical

Characteristicstable for specified performance limits.

(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB

(3) Maximum recommended input voltage is determined by the gain setting.

6

TAS5412-Q1

www.ti.com.cn

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise noted): T_Case= 25°C, PVDD = 14.4 V, R_L= 4 Ω, f_S= 417 kHz, P_out= 1 W/ch, Rext = 20 kΩ,

AES17 filter, master-mode operation (see application diagram)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OPERATING CURRENT

I_{PVDD_IDLE}

Both channels in MUTE mode

125

60

2

175

mA

PVDD idle current

I_{PVDD_Hi-Z}

Both channels in Hi-Z mode

STANDBY mode, T _J= 85°C

I_{PVDD_STBY}

PVDD standby current

12

µA

OUTPUT POWER

4 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T _c= 75°C

4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T _c= 75°C

4 Ω, PVDD = 24 V, THD+N = 1%, 1 kHz, T _c= 75°C

4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, T _c= 75°C

2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T _c= 75°C

2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T _c= 75°C

23

28

62

79

38

50

25

63

40

P_OUT

Output power per channel

W

%

PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%,

1 kHz, T _c= 75°C

150

90

PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,

1 kHz, T _c= 75°C

2 channels operating, 23-W output power per ch, L = 10

µH, T _J= 85°C

EFF_P

Power efficiency

90

AUDIO PERFORMANCE

V_NOISE

Noise voltage at output

G = 26 dB, zero input, and A-weighting

1 W, G = 26 dB, 1 kHz

60

75

100

µV

dB

Crosstalk

PSRR

Channel crosstalk

60

Power-supply rejection ratio

Total harmonic distortion + noise

G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz

P = 1 W, G = 26 dB, f = 1 kHz, 0°C = T _J= 75°C

75

THD+N

0.02%

357

417

500

82

0.1%

378

442

530

106

336

392

470

63

Switching frequency selectable for AM interference

avoidance

f_S

Switching frequency

kHz

R_AIN

Analog input resistance

Internal shunt resistance on each input pin

kΩ

Vrms

V

AC-coupled common-mode input voltage (zero

differential input)

V_{IN_CM}

V_{CM_INT}

Common-mode input voltage

Internal common-mode input bias voltage

1.3

Internal bias applied to IN_M pin

3.37

12

20

26

32

0

11

19

25

31

–1

13

21

27

33

1

Source impedance = 0 Ω, gain measurement taken at 1

W of power per channel

G

Voltage gain (V_O/ V_IN

)

dB

G_CH

Channel-to-channel variation

Any gain commanded

PWM OUTPUT STAGE

r_DSon

FET drain-to-source resistance

Output offset voltage

Not including bond-wire resistance, T _J= 25°C

75

95

mΩ

Zero input signal, dc offset reduction enabled, and

G = 26 dB

V_{O_OFFSET}

±10

±50

mV

PVDD OVERVOLTAGE (OV) PROTECTION

V_OVPVDD overvoltage shutdown

PVDD UNDERVOLTAGE (UV) PROTECTION

24.6

26.4

28.2

V

V_{UV_SET}

PVDD undervoltage shutdown

Recovery voltage for PVDD UV

5

5.3

6.6

5.6

7.2

V

V_{UV_CLEAR}

AVDD

6.2

V_{A_BYP}

A_BYP pin voltage

A_BYP UV voltage

6.5

3.5

4.3

V

V_{A_BYP_UV_SET}

V_{A_BYP_UV_CLEAR}Recovery voltage A_BYP UV

DVDD

V_{D_BYP}

D_BYP pin voltage

3.3

V

POWER-ON RESET (POR)

7

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

ELECTRICAL CHARACTERISTICS (continued)

Test conditions (unless otherwise noted): T_Case= 25°C, PVDD = 14.4 V, R_L= 4 Ω, f_S= 417 kHz, P_out= 1 W/ch, Rext = 20 kΩ,

AES17 filter, master-mode operation (see application diagram)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Maximum PVDD voltage for POR; I²C active

above this voltage

V_POR

4

V

V_{POR_HY}

REXT

PVDD recovery hysteresis voltage for POR

0.1

V_REXT

Rext pin voltage

1.27

V

CHARGE PUMP (CP)

V_{CPUV_SET}

CP undervoltage

Recovery voltage for CP UV

4.8

4.9

V

V_{CPUV_CLEAR}

OVERTEMPERATURE (OT) PROTECTION

T_{OTW1_CLEAR}

96

112

122

128

138

T _{OTW1_SET}

/

106

T_{OTW2_CLEAR}

Junction temperature for overtemperature

warning

T_{OTW2_SET}

/

116

126

136

130

132

142

152

150

148

158

168

170

T_{OTW3_CLEAR}

°C

T_{OTW3_SET}

/

T_{OTSD_CLEAR}

Junction temperature for overtemperature

shutdown

T_OTSD

Junction temperature for overtemperature

foldback

T_FB

Per channel

CURRENT LIMITING PROTECTION

Level 1

5.5

7.3

9

I_LIM

Current limit (load current)

A

Level 2 (default)

10.6

12.7

15

OVERCURRENT (OC) SHUTDOWN PROTECTION

Level 1, any short to supply, ground, or other channels

Level 2 (default)

7.8

9.8

12.2

17.7

I_MAX

Maximum current (peak output current)

11.9

14.8

TWEETER DETECT

I_{TH_TW}

Load-current threshold for tweeter detect

330

2

445

2.1

560

mA

A

I_{LIM_TW}

Load-current limit for tweeter detect

STANDBY MODE

V _{IH_STBY}

STANDBY input voltage for logic-level high

STANDBY input voltage for logic-level low

STANDBY pin current

V

V_{IL_STBY}

0.7

0.2

I_{STBY_PIN}

0.1

100

µA

MUTE MODE

G_MUTE

MUTE pin ≤ 0.5 Vdc for 200 ms, or I²C mute enabled

Output attenuation

dB

DC DETECT

V_{TH_DC_TOL}

DC-detect threshold tolerance

25%

DC-detect step-response time for two

channels

t_DCD

5.3

s

v

CLIP REPORT

V_{OH_CLIP_OTW}

CLIP_OTW pin output voltage for logic level

high (open-drain logic output)

2.4

External 47-kΩ pullup resistor to 3 V–5.5 V

CLIP_OTW pin output voltage for logic-level

low (open-drain logic output)

V_{OL_CLIP_OTW}

0.5

20

V

T_{DELAY_CLIPDET}

Signal delay when output clipping detected

µs

MODE PINS (DIAG, SOFT_MUTE, I²C MODE)

Mode pin output voltage for logic-level high

(open-drain logic output)

V_OH

2

0

5.5

0.7

V

Mode pin output voltage for logic-level low

(open-drain logic output)

V_OL

FAULT REPORT

8

TAS5412-Q1

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ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

ELECTRICAL CHARACTERISTICS (continued)

Test conditions (unless otherwise noted): T_Case= 25°C, PVDD = 14.4 V, R_L= 4 Ω, f_S= 417 kHz, P_out= 1 W/ch, Rext = 20 kΩ,

AES17 filter, master-mode operation (see application diagram)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FAULT pin output voltage for logic-level high

(open-drain logic output)

V _{OH_FAULT}

V _{OL_FAULT}

2.4

External 47-kΩ pullup resistor to 3 V–5.5 V

V

FAULT pin output voltage for logic-level low

(open-drain logic output)

0.5

OPEN/SHORT DIAGNOSTICS

Maximum resistance to detect a short from

OUT pins to PVDD or ground

R_S2P, R_S2G

200

1300

1.5

Ω

Minimum load resistance to detect open

circuit

R_{OPEN_LOAD}

R_{SHORTED_LOAD}

Including speaker wires

300

0.5

800

1.0

Maximum load resistance to detect short

circuit

CHIP SELECT

Time delay to latch I²C address after POR

Voltage on CS pin for address 0

Voltage on CS pin for address 1

Voltage on CS pin for address 2

Voltage on CS pin for address 3

t_{LATCH_CS}

300

0%

µs

Connect to GND

0%

25%

55%

85%

15%

45%

35%

65%

100%

External resistors in series between D_BYP and GND as

a voltage divider

V_CS

V_{D_BYP}

75%

Connect to D_BYP

100%

I²C

Power-on hold time before I²C

communication

t_{HOLD_I2C}

STANDBY high

1

ms

f_SCL

SCL clock frequency

400

5.5

1.1

kHz

V

V_{IH_SCL}

V_{IL_SCL}

SCL pin input voltage for logic-level high

SCL pin input voltage for logic-level low

2.1

R _{PU_I2C}= 5-kΩ pullup, supply voltage = 3.3 V or 5 V

–0.5

V

I²C read, R_I2C= 5-kΩ pullup,

supply voltage = 3.3 V or 5 V

V_{OH_SDA}

V_{OL_SDA}

V_{IH_SDA}

SDA pin output voltage for logic-level high

SDA pin output voltage for logic-level low

SDA pin input voltage for logic-level high

2.4

V

I²C read, 3-mA sink current

0.4

5.5

I²C write, R_I2C= 5-kΩ pullup,

supply voltage = 3.3 V or 5 V

2.1

I²C write, R_I2C= 5-kΩ pullup,

supply voltage = 3.3 V or 5 V

V_{IL_SDA}

SDA pin input voltage for logic-level low

Capacitance for SCL and SDA pins

–0.5

1.1

10

V

C_i

pF

OSCILLATOR

OSC_SYNC pin output voltage for logic-

level high

V_{OH_OSCSYNC}

V_{OL_OSCSYNC}

V_{IH_OSCSYNC}

V_{IL_OSCSYNC}

2.4

2

3.6

0.5

3.6

0.8

V

CS pin set to MASTER mode

CS pin set to SLAVE mode

OSC_SYNC pin output voltage for logic-

level low

OSC_SYNC pin input voltage for logic-level

high

OSC_SYNC pin input voltage for logic-level

low

CS pin set to MASTER mode, f_S= 500 kHz

CS pin set to MASTER mode, f_S= 417 kHz

CS pin set to MASTER mode, f_S= 357 kHz

3.76

3.13

2.68

4

3.33

2.85

4.24

3.63

3

f_{OSC_SYNC}

OSC_SYNC pin clock frequency

MHz

9

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

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TIMING REQUIREMENTS FOR I²C INTERFACE SIGNALS

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

ns

t_r

Rise time for both SDA and SCL signals

Fall time for both SDA and SCL signals

SCL pulse duration, high

300

t_f

ns

t_w(H)

t_w(L)

t_su2

t_h2

0.6

1.3

0.6

100

µs

SCL pulse duration, low

µs

Setup time for START condition

START condition hold time after which first clock pulse is generated

Data setup time

µs

t_su1

t_h1

ns

(1)

Data hold time

0

ns

t_su3

C_B

Setup time for STOP condition

Load capacitance for each bus line

0.6

µs

400

pF

(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of

SCL.

t_w(H)

t_w(L)

t_r

t_f

SCL

t_su1

t_h1

SDA

T0027-01

Figure 1. SCL and SDA Timing

SCL

t_(buf)

t_h2

t_su2

t_su3

SDA

Start

Condition

Stop

Condition

T0028-01

Figure 2. Timing for Start and Stop Conditions

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TYPICAL CHARACTERISTICS

THD+N

versus

THD+N

versus

BTL OUTPUT POWER AT 1 kHz

PBTL OUTPUT POWER at 1 kHz

Figure 3.

Figure 4.

THD+N

versus

FREQUENCY AT 1 W

COMMON-MODE REJECTION RATIO

versus

FREQUENCY

Figure 5.

Figure 6.

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TYPICAL CHARACTERISTICS (continued)

CROSSTALK

versus

FREQUENCY

NOISE FFT

Figure 7.

Figure 8.

EFFICIENCY,

TWO CHANNELS AT 4 Ω EACH

100

90

80

70

60

50

40

30

20

10

0

4

8

12

16

20

24

28

32

P − Power Per Channel − W

G007

Figure 9.

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DESCRIPTION OF OPERATION

OVERVIEW

The device is a two-channel analog-input audio amplifier for use in the automotive environment. The design uses

an ultra-efficient class-D technology developed by Texas Instruments. This technology allows for reduced power

consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio

sound system design with smaller size and lower weight than traditional class-AB solutions.

The device has the following major blocks:

•

Preamplifier

PWM

Gate drive

Power FETs

Diagnostics

Protection

Power supply

I²C serial communication bus

Preamplifier

The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The

high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency

response. A dedicated, internally regulated supply powers the preamplifier, giving excellent noise immunity and

channel separation. Also included in the preamplifier are:

1. Mute Pop-and-Click Control—Application of a mute at the crest or trough of an audio input signal reshapes

and amplifies the signal as a step. Listeners perceive such a step as a loud click. The TAS5412-Q1 avoids

clicks by ramping the gain gradually on reception of a mute or play command. The start or stopping of

switching in a class-D amplifier can cause another form of click and pop. The TAS5412-Q1 incorporates a

patented method to reduce the pop energy during the switching start-up and shutdown sequences. Fault

conditions require rapid protection response by the TAS5412-Q1, which does not have time to ramp the gain

down in a pop-free manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or dc fault is

encountered. Also, activation of the STANDBY pin may not be pop-free.

2. Gain Control—The four gain settings are set in the preamplifier via I²C control registers. Setting of the gain

outside of the global feedback resistors of the TAS5412-Q1 thus allows for stability in the system at all gain

settings with properly loaded conditions.

Pulse-Width Modulator (PWM)

The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is

the critical stage that defines the class-D architecture. In the TAS5412-Q1, the modulator is an advanced design

with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation capability. The

patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of PWMs when the

input signal exceeds the modulator waveform.

Gate Drive

The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power

FET stage.

Power FETs

The BTL output for each channel comprises four rugged N-channel FETs, each of which is low r_DSonfor high

efficiency and maximum power transfer to the load. These FETs handle large voltage transients during load

dump.

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Load Diagnostics

The device incorporates load-diagnostic circuitry designed to help pinpoint the nature of output misconnections

during installation. The diagnostics include functions for detecting and determining the status of output

connections. The following diagnostics are supported:

•

Short to GND

Short to PVDD

Short across load

Open load

Tweeter detection

Reporting the presence of any of the short or open conditions to the system is via I²C register read. One can

read the tweeter detect status from the CLIP_OTW pin when properly configured.

1. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open

conditions on the outputs. One can only invoke the load diagnostic function when the output is in the Hi-Z

mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all

channels must be in the Hi-Z state. The diagnostic tests all four phases on each channel, and both channels

at the same time. When fewer than two channels are in Hi-Z, the reduced level of test is the only available

option. In the reduced level, the only available tests are short to PVDD and short to GND. Load diagnostics

can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play

mode, it must Mute and then Hi-Z to allow performing the load diagnostic. By performing the mute function,

the normal pop- and click-free transitions occur before the diagnostics begin. The device performs the

diagnostics as shown in Figure 10. Figure 11 shows the impedance ranges for the open-load and shorted-

load diagnostics. Reading of the diagnostic results is from the diagnostic register for each channel via I²C.

Hi-Z Channel Synchronization

Playback

/

Mute

Phase1

S2G

Phase2

S2P

Phase3

OL

Phase4

SL

OUT1_M

OUT1_P

~50 ms

V_Speaker

(OUT1_P – OUT1_M)

20 ms

150 ms

200 ms

<20 ms

T0188-01

Figure 10. Load Diagnostics Sequence of Events

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Short Detection

Range

Open Detection

Short Detected

Normal Load Detected

Open Detected

Range

R_Load

(Including Wires)

1300

1.5

300

0.5

1 (Typ)

800 (Typ)

M0067-01

Figure 11. Open- and Shorted-Load Detection

2. Tweeter Detection—Tweeter detection is an alternate operating mode used to determine the proper

connection of a frequency-dependent load (such as a speaker with a crossover). Invocation of tweeter

detection is via I²C, and both channels should be tested individually. Tweeter detection uses the average

cycle-by-cycle current-limit circuit (see the CBC section) to measure the current delivered to the load. The

proper implementation of this diagnostic function depends on the amplitude of a user-supplied test signal and

on the impedance-versus-frequency curve of the acoustic load. The system (external to the device) must

generate a signal to which the load responds. The user must calibrate the frequency and amplitude of this

signal to result in a current draw that is greater than the tweeter detection threshold when the load under test

is present, and less than the detection threshold if the load is not properly connected. The current level for

the tweeter detection threshold, as well as the maximum current that can safely be delivered to a load when

in tweeter-detection mode, is in the Electrical Characteristics section of the datasheet. The tweeter-detection

results are available on the CLIP_OTW pin during the application of the test signal. During tweeter-detection

activation (when the tested load is present), pulses on the CLIP_OTW pin begin to toggle. The pulses on the

CLIP_OTW pin report low whenever the current exceeds the detection threshold, and the pin remains low

until the current no longer exceeds the threshold. The minimum low-pulse period that one can expect is

equal to one period of the switching frequency. Having an input signal that increases the duration of detector

activation (for example, increasing the amplitude of the input signal) increases the amount of time for which

the

reports

low.

NOTE: Because tweeter detection is an alternate operating mode, it is necessary to place the channels to be

tested in Play mode (via register 0x0C) after activation of tweeter detection in order to commence the

detection process. Additionally, the appropriate settings must be in register 0x0A, enabling the CLIP_OTW to

report the results of tweeter detection.

Protection and Monitoring

1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to limit

the output-current flow when current exceeds the average current-limit (I_LIM) threshold. The overall effect on

the audio in the case of a current overload is quite similar to a voltage-clipping event, where the device

temporarily limits power at the peaks of the musical signal and normal operation continues without disruption

on removal of the overload. The TAS5412-Q1 does not prematurely shut down in this condition. Both

channels continue in play mode and pass signal.

2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground,

the device uses a peak-current detector, and the affected channel shuts down in 200 µs to 390 µs if the

conditions are severe enough. The shutdown speed depends on a number of factors, such as the impedance

of the short circuit, supply voltage, and switching frequency. Only the shorted channels shut down in such a

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scenario. The user may restart the affected channel via I²C. An OCSD event activates the fault pin, with the

I²C fault register recording the affected channels. If the supply or ground short is strong enough to exceed

the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents

excess current from damaging the output FETs, and operation returns to normal after the short is removed.

3. DC Detect—This circuit detects a dc offset continuously during normal operation at the output of the

amplifier. If the dc offset reaches the level defined in the I²C registers for the specified time period, the circuit

triggers. By default, a dc detection event does not shut the output down. One can enable or disable the

shutdown function via I²C. If enabled, the triggered channel shuts down, but the others remain playing, and

the device asserts the FAULT pin. The I²C registers define the dc level.

4. Clip Detect—The clip-detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a

clipped waveform. When this occurs, the device passes to the CLIP_OTW pin a signal that remains asserted

until the 100% duty-cycle PWM signal is no longer present. Through I²C, one can change the CLIP_OTW

signal to clip-only, OTW-only, or both. A fourth mode, used only during diagnostics, is the option to report

detected tweeter-detection events on these pins (see the Tweeter Detection section). The microcontroller in

the system can monitor the signal at the CLIP_OTW pin. The microcontroller configuration may be such as to

reduce the volume on the channel in an active clipping-prevention circuit.

5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD), and Thermal Foldback—The

device asserts the CLIP_OTW pin when the die temperature reaches 125°C. The OTW has three

temperature thresholds with a 10°C hysteresis. Indication of the thresholds is in I²C register 0x04 bits 5, 6,

and 7. The device still functions until the temperature reaches the OTSD threshold, 155°C, at which time it

places the outputs into Hi-Z mode and asserts the FAULT pin. I²C is still active in the event of an OTSD,

which allows reading the registers for faults, but all audio ceases abruptly. The OTSD resets at 145°C, to

allow the turning the TAS5412-Q1 back on through I²C. The OTW indication persists until the temperature

drops below 115°C. All temperatures are nominal values. The thermal foldback decreases the channel gain.

6. Undervoltage (UV) and Power-On Reset (POR)—The undervoltage (UV) protection detects low voltages

on PVDD, AVDD, and CP. In the event of an undervoltage, the device asserts the FAULT pin and updates

the I²C register for the voltage which caused the event. Power-on-reset (POR) occurs when PVDD drops low

enough. A POR event causes the I²C to go into a high-impedance state. After the device recovers from the

POR event, re-initialization of the device via I²C is necessary.

7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches

the overvoltage threshold, the device asserts the FAULT pin and updates the I²C register. If the voltage

increases beyond the load dump threshold of 29 Vdc, the device shuts down and must undergo a restart

once the voltage returns to a safe value. After the device recovers from a load-dump event, the device

requires re-initialization via I²C. The TAS5412-Q1 can withstand 50-V load-dump voltage spikes. Load

Diagnostics shows the regions of operating voltage and the profile of the load-dump event.

Power Supply

A car battery that can have a large voltage swing most commonly provides the power for the device. PVDD is a

filtered battery voltage, and is the supply for the output FETS and the low-side FET gate driver. A charge pump

(CP) supply provides power to the high-side FET gate driver. The charge pump supplies the gate-drive voltages.

AVDD, which comes from an internal linear regulator, powers the analog circuitry. This supply requires a 0.1-µF,

10-V external bypass capacitor at the A_BYP pin. TI recommends attaching no external components except the

bypass capacitor to this pin. DVDD, which comes from an internal linear regulator, powers the digital circuitry.

The D_BYP pin requires a 0.1-µF, 10-V external bypass capacitor. TI recommends that no external components

except the bypass capacitor be attached to this pin.

The device can withstand fortuitous open-ground and -power conditions. Fortuitous open-ground usually occurs

when a speaker wire is shorted to ground, allowing for a second ground path through the body diode in the

output FETs. The uniqueness of the diagnostic capabilities allows debugging of the speakers and speaker wires,

eliminating the need to remove the amplifier to diagnose the problem.

I²C Serial Communication Bus

The device communicates with the system processor via the I²C serial communication bus. It is an I²C slave-only

device. The processor can poll the device via I²C to determine the operating status. Reporting of all fault

conditions and detections is via I²C. The setting of numerous features and operating conditions is also via I²C.

The I²C bus allows control of the following configurations:

•

Control the gain each channel independently. The gain settings are 12 dB, 20 dB, 26 dB, and 32 dB.

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•

Select AM non-interference switching frequency

Configure the CLIP_OTW pin

Enable or disable the dc-detect function with selectable threshold

Place channel in Hi-Z (switching stopped) mode (mute)

Select tweeter detect, set detect threshold, and initiate function

Initiate open- and shorted-load diagnostic

Reset faults and return to normal switching operation from Hi-Z mode (unmute)

In addition to the standard SDA and SCL pins for the I²C bus, the device includes a single pin that allows up to

four devices to work together in a system with no additional hardware required for communication or

synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the I²C address for that

device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2, and to D_BYP for

slave 3. The OSC_SYNC pin synchronizes the internal clock oscillators and thereby avoids beat frequencies.

Optional application of an external oscillator to this pin allows external control of the switching frequency.

Table 2. I2C_ADDR Pin Connection

DESCRIPTION

I2C_ADDR PIN CONNECTION

I²C ADDRESS

0xD8/D9

Device 0 - OSC_SYNC clock master To SGND pin

(1)

Device 1 - OSC_SYNC clock slave 1 35% DVDD (resistive voltage divider between D_BYP pin and SGND pin)

Device 2 - OSC_SYNC clock slave 2 65% DVDD (resistive voltage divider between D_BYP pin and SGND pin)

Device 3 - OSC_SYNC clock slave 3 To D_BYP pin

0xDA/DB

0xDC/DD

0xDE/DF

(1) R_CSwith 5% or better tolerance is recommended.

I²C Bus Protocol

The device has a bidirectional serial control interface that is compatible with the Inter IC (I²C) bus protocol and

supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only

device that does not support a multimaster bus environment or wait-state insertion. Use the control interface to

program the registers of the device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data transfer on the bus is serial, one bit at a time. The address and data transfers are in byte (8-bit)

format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each

byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device

driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus

uses transitions on the data terminal (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-

to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit

transitions must occur within the low time of the clock period. Figure 12 shows these conditions. The master

generates the 7-bit slave address and the read/write bit to open communication with another device and then

wait for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate

an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Addressing of each

device is by a unique 7-bit slave address plus read/write bit (1 byte). All compatible devices share the same

signals via a bidirectional bus using a wired-AND connection. There must be an external pullup resistor for the

SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes comprising a

transmission between start and stop conditions. When the last word transfers, the master generates a stop

condition to release the bus.

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8-Bit Register Data For

Address (N)

8-Bit Register Data For

Address (N)

R/

W

8-Bit Register Address (N)

7-Bit Slave Address

A

SDA

SCL

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Start

Stop

T0035-01

Figure 12. Typical I²C Sequence

Use the CS pin (pin 62) to program the device for one of four addresses. These four addresses are licensed I²C

addresses and do not conflict with other licensed I²C audio devices. To communicate with the device, the I²C

master uses addresses shown in Table 2. Read and write data transmissions can use single-byte or multiple-

byte data transfers.

Random Write

As shown in Figure 13, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I²C device address

and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte

or bytes corresponding to the internal memory address being accessed. After receiving the address byte, the

device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to

the memory address being accessed. After receiving the data byte, the device again responds with an

acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write

transfer.

Start

Condition

Acknowledge

R/W

A6 A5 A4 A3 A2 A1 A0

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

Data Byte

Stop

Condition

T0036-01

Figure 13. Random Write Transfer

Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data

bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and

the I²C subaddress automatically increments by one.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

Figure 14. Sequential Write Transfer

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A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data

bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and

the I²C subaddress automatically increments by one.

Random Read

As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start

condition followed by the I²C device address and the read/write bit. The data-read transfer actually performs a

write followed by a read. Initially, a write transfers the address byte or bytes of the internal memory address to be

read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds

with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device

transmits another start condition followed by the device address and the read/write bit again. This time the

read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again

responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being

read. After receiving the data byte, the master transmits a not-acknowledge followed by a stop condition to

complete the single-byte data-read transfer.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A0 ACK

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and

Read/Write Bit

Data Byte

Stop

Condition

T0036-03

Figure 15. Random Read Transfer

Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that the device transmits

multiple data bytes to the master as shown in Figure 16. Except for the last data byte, the master responds with

an acknowledge bit after receiving each data byte and automatically increments the I²C subaddress by one.

Note: The fault registers do not have sequential read capabilities.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

D0 ACK D7

A6

A0 R/W ACK A7 A6 A5

A0 ACK

A6

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

Figure 16. Sequential Read Transfer

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A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data

bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and

the I²C subaddress automatically increments by one.

Table 3. TAS5412-Q1 I²C Addresses

SELECTABLE WITH

ADDRESS PIN

READ/WRITE

BIT

I²C

ADDRESS

FIXED ADDRESS

DESCRIPTION

I²C WRITE

MSB

6

1

5

0

4

1

3

1

2

0

1

0

1

0

1

LSB

0

0 – OSC MASTER

1 – OSC SLAVE1

2 – OSC SLAVE2

3 – OSC SLAVE3

1

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

I²C READ

I²C WRITE

I²C READ

I²C WRITE

I²C READ

I²C WRITE

I²C READ

1

0

1

0

1

0

1

Table 4. I²C Address Register Definitions

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x13

TYPE

Read

REGISTER DESCRIPTION

Latched fault register 1, global and channel fault

Latched fault register 2, dc offset and overcurrent detect

Latched diagnostic register 1, load diagnostics, channel 1

Latched diagnostic register 2, load diagnostics, channel 2

External status register 1, temperature and voltage detect

External status register 2, Hi-Z and low-low state

External status register 3, mute and play modes

External status register 4, load diagnostics

External control register 1, channel gain select

Not used

Read

Read, Write

Read

External control register 2, switching frequency and clip pin select

External control register 3, load diagnostic, master mode select

External control register 4, output state control

External control register 5, output state control

Not used

External control register 6, dc detect threshold selection

External status register 5, overtemperature shutdown and thermal foldback

Table 5. Fault Register 1 (0x00) Protection

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No protection-created faults, default value

Overtemperature warning has occurred

DC offset has occurred in any channel

Overcurrent shutdown has occurred in any channel

Overtemperature shutdown has occurred

Charge-pump undervoltage has occurred

AVDD, analog voltage, undervoltage has occurred

PVDD undervoltage has occurred

–

1

–

1

–

1

–

1

–

1

–

1

–

1

–

1

–

PVDD overvoltage has occurred

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Table 6. Fault Register 2 (0x01) Protection

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No protection-created faults, default value

Ovecurrent shutdown channel 1 has occurred

Overcurrent shutdown channel 2 has occurred

DC offset channel 1 has occurred

DC offset channel 2 has occurred

Reserved

–

1

–

1

–

1

–

1

–

X

–

X

–

X

Table 7. Diagnostic Register 1 (0x02) Load Diagnostics

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No load-diagnostic-created faults, default value

Output short to ground channel 1 has occurred

Output short to PVDD channel 1 has occurred

Shorted load channel 1 has occurred

Open load channel 1 has occurred

Reserved

–

1

–

1

–

1

–

1

–

X

Table 8. Diagnostic Register 2(0x03) Load Diagnostics

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No load-diagnostic-created faults, default value

Output short to ground channel 2 has occurred

Output short to PVDD channel 2 has occurred

Shorted load channel 2 has occurred

Open load channel 2 has occurred

Reserved

–

1

–

1

–

1

–

1

–

X

–

Table 9. External Status Register 1 (0x04) Fault Detection

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No protection-created faults are present, default value

PVDD overvoltage fault is present

PVDD undervoltage fault is present

AVDD, analog voltage fault is present

Charge-pump voltage fault is present

Overtemperature shutdown is present

Overtemperature warning

–

1

–

1

–

1

–

1

–

1

–

1

–

1

–

Overtemperature warning level 1

1

0

1

–

Overtemperature warning level 2

1

–

Overtemperature warning level 3

Table 10. External Status Register 2 (0x05) Output State of Individual Channels

D7

0

D6

0

D5

0

D4

0

D3

0

D2

1

D1

1

D0

0

FUNCTION

Output is in Hi-Z mode, not in low-low mode ⁽¹⁾, default value

Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)

Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)

–

0

–

0

–

(1)

–

1

–

Channel 1 low-low mode (0 = not low-low, 1 = low-low)

–

1

–

Channel 2 low-low mode (0 = not low-low, 1 = low-low) ⁽¹⁾

X

–

X

–

X

Reserved

(1) Low-low is defined as both outputs actively pulled to ground.

21

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

Table 11. External Status Register 3 (0x06) Play and Mute Modes

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

Mute mode is disabled, play mode disabled, default value, (Hi-Z mode)

Channel 1 is in play mode.

–

1

–

1

–

Channel 2 is in play mode.

–

1

–

Channel 1 is in mute mode.

–

1

–

Channel 2 is in mute mode.

X

–

X

–

X

Reserved

Table 12. External Status Register 4 (0x07) Load Diagnostics

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

No channels are set in load diagnostics mode, default value

Channel 1 is in load diagnostics mode.

Channel 2 is in load diagnostics mode.

Channel 1 is in overtemperature foldback.

Channel 2 is in overtemperature foldback.

Reserved

–

1

–

1

–

1

–

1

–

X

–

X

–

X

Table 13. External Control Register 1 (0x08) Gain Select

D7

1

D6

0

D5

1

D4

0

D3

1

D2

0

D1

1

D0

0

FUNCTION

Set gain for both channels to 26 dB, default value

Set channel 1 gain to 12 dB

Set channel 1 gain to 20 dB

Set channel 1 gain to 32 dB

Set channel 2 gain to 12 dB

Set channel 2 gain to 20 dB

Set channel 2 gain to 32 dB

Reserved

–

0

–

0

1

–

1

–

0

–

0

1

–

1

–

X

–

X

Table 14. External Control Register 2 (0x0A) Switching Frequency Select and Clip_OTW Configuration

D7

D6

D5

D4

D3

D2

D1

D0

FUNCTION

0

1

0

1

Set f _S= 417 kHz, configure clip and OTW detection, 45° phase, disable

hard stop

–

1

–

1

–

1

–

1

–

0

1

–

0

1

0

–

0

1

–

0

1

–

Set f _S= 500 kHz

Set f _S= 357 kHz

Invalid frequency selection (do not set)

Configure CLIP_OTW pin for tweeter detect only

Configure CLIP_OTW pin for clip detect only

Configure CLIP_OTW pin for overtemperature warning only

Enable hard-stop mode

Set f_Sto a 180° phase difference between adjacent channels

Send sync pulse from OSC_SYNC pin (device must be in master mode).

Report thermal foldback to the CLIP_OTW pin.

Table 15. External Control Register 3 (0x0B) Load Diagnostics and Master-or-Slave Control

D7

0

D6

1

D5

0

D4

1

D3

0

D2

0

D1

0

D0

0

FUNCTION

Disable load diagnostics, enable dc-detect SD, master mode

Enable channel 1, load diagnostics

–

1

–

1

–

Enable channel 2, load diagnostics

22

TAS5412-Q1

www.ti.com.cn

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

Table 15. External Control Register 3 (0x0B) Load Diagnostics and Master-or-Slave Control (continued)

D7

–

D6

–

D5

–

D4

–

D3

X

–

D2

–

D1

–

D0

X

–

FUNCTION

Reserved

–

0

–

Disable dc detect shutdown on all channels

–

1

–

Enable tweeter-detect mode

–

0

–

Enable slave mode (provide external oscillator)

Send clock, OSC_SYNC pin has clock output (valid only in master mode)

1

–

Table 16. External Control Register 4 (0x0C) Output Control

D7

0

D6

0

D5

0

D4

1

D3

1

D2

1

D1

1

D0

1

FUNCTION

All channels, Hi-Z, mute, reset disabled

–

0

–

Set channel 1 to mute mode, non-Hi-Z

Set channel 2 to mute mode, non-Hi-Z

Reserved

–

0

–

X

–

X

–

X

–

X

–

0

–

Set non-Hi-Z channels to play mode, (unmute)

Reset device

1

–

Table 17. External Control Register 5 (0x0D) Output Control

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

Low-low state disabled, both channels

–

1

–

Set channel 1 to low-low state

Set channel 2 to low-low state

Reserved

–

1

–

X

–

X

Table 18. External Control Register 6 (0x10) DC Detect Threshold Selection

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

FUNCTION

Default dc detect value (1.6 V)

–

0

Minimum dc detect value (0.8 V)

–

1

0

Maximum dc detect value (2.4 V) Note: a value of 11 is invalid

Enable enhanced-crosstalk mode

–

1

–

1

–

Add a 20-ms delay between load diagnostic phases

4× longer short-to-power (S2P) and short-to-ground (S2G) phases

Slower common mode (CM) ramp-down from mute mode

Reserved

–

1

–

1

–

X

–

Table 19. External Status Register 5 (0x13) Overtemperature and Thermal Foldback Status

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

Default overtemperature foldback status, no channel is in foldback

Channel 1 in thermal foldback

–

1

–

1

–

Channel 2 in thermal foldback

–

1

–

Channel 1 in overtemperature shutdown

Channel 2 in overtemperature shutdown

Reserved

–

1

–

X

–

X

–

X

23

TAS5412-Q1

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

www.ti.com.cn

Hardware Control Pins

The device has several hardware pins for real-time control and indication of device status.

FAULT pin: This active-low, open-drain output pin indicates the presence of a fault condition that requires

the device to go automatically into the Hi-Z mode or standby mode. When asserting this pin high, the device

is protecting itself and the system from potential damage. One can read the exact nature of the fault via I²C,

with the exception of faults that are the result of PVDD voltage excursions below POR. In this case, the

device goes into standby mode and the I²C bus is no longer operational. However, the fault indication

remains, due to the fact that the FAULT pin is open-drain and active-high.

CLIP_OTW pin: The function of this active-low pin, configured by the user, indicates one of the following

conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.

Selection of the configuration is via I²C. During tweeter-detect diagnostics, detection of a tweeter also results

in assertion of this pin.

MUTE pin: This active-low pin is for hardware control of the mute-and-unmute function for all four channels.

Capacitor CMUTE controls the time constant for the gain ramp needed to produce a pop- and click-free mute

function. For pop- and click-free operation, implement the mute function through I²C commands. The use of a

hard mute with an external transistor does not ensure pop- and click-free operation; TI does not recommend

such use unless there is a requirement for an emergency hard mute function in case of a loss of I²C control.

Do not share the CMUTE capacitor between more than one device.

STANDBY pin: Asserting this active-low pin puts the device into a complete shutdown, limiting the current

draw to 2 µA, typical. Assertion typically occurs when the car ignition is in the off position. Another use of the

pin is to shut down the device rapidly on violation of certain operating conditions. Pin assertion causes the

loss of all I²C register content and causes the I²C bus to go into the high-impedance state.

EMI Considerations

Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level

design. Controlling sources of electromagnetic interference (EMI) is a major consideration in all aspects of the

TAS5412-Q1 design.

The TAS5412-Q1 has minimal parasitic inductances due to the short leads on the PHD package. This

dramatically reduces the EMI that results from current passing from the die to the system PCB. Each channel of

the TAS5412-Q1 also operates at a different phase. The phase between channels is I²C selectable to either 45°

or 180°, to reduce EMI caused by high-current switching. The TAS5412-Q1 incorporates patent-pending circuitry

that optimizes output transitions that cause EMI.

AM Radio EMI Reduction

To reduce interference in the AM radio band, the TAS5412-Q1 has the ability to change the switching frequency

via I²C commands. Table 20 lists the recommended frequencies. The fundamental frequency and its second

harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching

frequency being demodulated by the AM radio. To function properly, AM avoidance requires the use of a 20-kΩ,

1% tolerance Rext resistor.

Table 20. Recommended Switching Frequencies for AM Mode Operation

US

EUROPEAN

SWITCHING

FREQUENCY

(kHz)

SWITCHING

FREQUENCY

(kHz)

AM FREQUENCY

(kHz)

AM FREQUENCY

(kHz)

522-540

540–914

417

500

417

500

417

357

540–917

917–1125

1125–1375

1375–1547

1547–1700

500

417

500

417

357

914–1122

1122–1373

1373–1548

1548–1701

24

TAS5412-Q1

www.ti.com.cn

ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013

Operating States

the following tables depict the operating regions, or states, of the TAS5412-Q1.

Table 21. Operating States and Supplies

STATE NAME

STANDBY

Hi-Z

OUTPUT FETS

Hi-Z, floating

CHARGE PUMP

Stopped

Active

OSCILLATOR

Stopped

Active

I²C

AVDD and DVDD

Stopped

Active

OFF

ON

Hi-Z, weak pulldown

Switching at 50%

Switching with audio

Mute

Active

Normal operation

Active

Table 22. Global Faults and Actions

FAULT OR

EVENT


型号：	TAS5412TPHDRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 I2C 诊断和负载突降保护功能的汽车类 28W、2 通道、6V 至 24V 模拟单端输入 D 类音频放大器 \| PHD \| 64 \| -40 to 105 放大器商用集成电路音频放大器
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