TAS5615DKDR [TI]
160 W STEREO/300W MONO PurePath™ HD Analog-Input Power Stage; 为160W立体声/单声道300W的PurePath ™HD模拟输入功率级型号: | TAS5615DKDR |
厂家: | TEXAS INSTRUMENTS |
描述: | 160 W STEREO/300W MONO PurePath™ HD Analog-Input Power Stage |
文件: | 总30页 (文件大小:1066K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PurePath Digital
TAS5615
www.ti.com ...................................................................................................................................................................................................... SLAS595–JUNE 2009
160 W STEREO/300W MONO PurePath™ HD Analog-Input Power Stage
1
FEATURES
DESCRIPTION
2
•
Active Enabled Integrated Feedback Provides:
(PurePath™ HD)
The TAS5615 is a high-performance analog input
CLass amplifier with integrated closed loop
D
–
Signal Bandwidth up to 80kHz for High
Frequency Content From High Definition
Sources
feedback technology (known as PurePath™ HD). It
has the ability to drive up to 160 W(1) Stereo into 8Ω
speakers from a single 50V supply.
–
–
Ultra Low 0.03% THD at 1W into 8Ω
PurePath™ HD technology enables traditional
AB-Amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class D
amplifiers.
0.03% THD Across all Frequencies for
Natural Sound at 1W
–
–
–
–
80dB PSRR (BTL, No Input Signal)
>100dB (A weighted) SNR
Ultra Low 0.03% THD+N is flat across all frequencies,
ensuring that the amplifier doesn’t add uneven
distortion characteristics, and helps maintain a natural
sound.
Click and Pop Free Startup
Minimal External Components Compared to
Discrete Solutions
•
•
Multiple Configurations Possible on the Same
PCB:
The efficiency of this Class-D amplifier is greater than
90%. Undervoltage Protection, Overtemperature,
clipping, Short Circuit and Overcurrent Protection are
all integrated, safeguarding the device and speakers
against fault conditions that could damage the
system.
–
–
Mono Parallel Bridge Tied Load (PBTL)
2.1 Single Ended (SE) Stereo Pair and
Bridge Tied Load (BTL) Subwoofer
–
Quad Single Ended (SE) Outputs
Total Output Power at 10%THD+N
3 x OPA1632
–
–
–
300W in Mono PBTL Configuration
160W per Channel in Stereo BTL
80W per Channel in Quad Single Ended
??
PurePath HDTM
TAS5615
??
ANALOG
AUDIO
INPUT
(2.1 Configuration)
•
•
High Efficiency Power Stage (> 90%) With 120
mΩ Output MOSFETs
??
Two Thermally Enhanced Package Options:
15V
+12V
+25V to +50V
–
–
PHD (64-pin QFP)
PurePath HDTM
Class G Power Supply
Ref design
DKD (44-pin PSOP3)
•
•
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short Circuit Protection) With Error Reporting
110VAC->240VAC
EMI Compliant When Used With
Recommended System Design
APPLICATIONS
•
•
•
•
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
(1) Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve high
output power levels
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TAS5615
SLAS595–JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5615 is available in two thermally enhanced packages:
•
•
64-Pin QFP (PHD) Power Package
44-Pin PSOP3 package (DKD)
The package type contains a heat slugs that is located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE
(TOP VIEW)
DKD PACKAGE
(TOP VIEW)
PSU_REF
VDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
2
OC_ADJ
RESET
3
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
4
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
C_STARTUP
INPUT_A
INPUT_B
VI_CM
5
6
7
8
GND
9
GND
AGND
VREG
10
11
12
13
14
15
16
17
18
19
20
21
22
AGND
VREG
9
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
SD
10
11
12
13
14
15
16
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
SD
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
64-pins QFP package
OTW1
OTW
READY
M1
M2
M3
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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MODE SELECTION PINS
MODE PINS
OUTPUT
CONFIGURATION
ANALOG
INPUT
DESCRIPTION
M3
0
M2
0
M1
0
Differential
—
2 × BTL
—
AD mode
Reserved
BD mode
0
0
1
0
1
0
Differential
2 × BTL
Differential
Single Ended
0
1
1
0
1
0
1 × BTL +2 × SE
4 × SE
AD mode, BTL Differential
AD mode
Single Ended
Differential
INPUT_C(1)
INPUT_D(1)
1
0
1
1 × PBTL
0
1
0
AD mode
BD mode
0
1
1
1
1
0
1
Reserved
(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER
TAS5615PHD
3.63
TAS5615DKD
2.52
R
θJC (°C/W) – 2 BTL or 4 SE channels
RθJC (°C/W) – 1 BTL or 2 SE channel(s)
5.95
3.22
RθJC (°C/W) – 1 SE channel
9.9
6.9
(2)
Pad Area
49 mm2
80 mm2
(1) JC is junction-to-case, CH is case-to-heat sink
(2) θH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and both
R
channels active. The RθCH with this condition is 1.22°C/W for the PHD package and and 1.02°C/W for the DKD package.
ORDERING INFORMATION(1)
TA
PACKAGE
TAS5615PHD(2)
TAS5615DKD
DESCRIPTION
64 pin HTQFP
44 pin PSOP3
0°C–70°C
0°C–70°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Product Preview
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5615
UNIT
V
VDD to AGND
–0.3 to 13.2
–0.3 to 13.2
–0.3 to 69.0
–0.3 to 69.0
–0.3 to 82.2
–0.3 to 69.0
–0.3 to 4.2
–0.3 to 0.3
–0.3 to 0.3
–0.3 to 4.2
GVDD to AGND
V
PVDD_X to GND_X(2)
OUT_X to GND_X(2)
BST_X to GND_X(2)
BST_X to GVDD_X(2)
VREG to AGND
V
V
V
V
V
GND_X to GND
V
GND_X to AGND
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP,
PSU_REF to AGND
V
INPUT_X
–0.3 to 5
–0.3 to 7.0
9
V
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Operating junction temperature range, TJ
Storage temperature, Tstg
mA
°C
°C
kV
V
0 to 150
–40 to 150
±2
Human-Body Model(3) (all pins)
Charged-Device Model(3) (all pins)
Electrostatic discharge
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
PVDD_x
GVDD_x
Half-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
25
50
52.5
13.2
13.2
V
V
V
Supply for logic regulators and gate-drive
circuitry
10.8
12
VDD
Digital regulator supply voltage
10.8
7
12
8.0
4.0
4.0
15
RL(BTL)
Output filter according to schematics in
the application information section.
RL(SE)
Load impedance
3.5
3.5
14
Ω
RL(PBTL)
LOUTPUT(BTL)
LOUTPUT(SE)
LOUTPUT(PBTL)
Output filter inductance
Minimum output inductance at IOC
14
15
µH
kHz
kΩ
14
15
Nominal
350 400
310 340
260 300
450
350
PWM frame rate selectable for AM interference
avoidance; 1% Resistor tolerance
FPWM
AM1
AM2
320
Nominal; Master mode
AM1; Master mode
AM2; Master mode
9.5
19.8
29.7
10
20
30
10.5
20.2
30.3
RFREQ_ADJ
PWM frame rate programming resistor
Voltage on FREQ_ADJ pin for slave mode
operation
VFREQ_ADJ
TJ
Slave mode
3.3
Junction temperature
0
150
°C
4
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PIN FUNCTIONS
PIN
FUNCTION(1)
DESCRIPTION
NAME
AGND
PHD NO.
DKD NO.
8
10
43
34
33
24
–
P
P
P
P
P
O
O
I
Analog ground
BST_A
54
41
40
27
18
3
HS bootstrap supply (BST), external 0.033 µF capacitor to OUT_A required.
HS bootstrap supply (BST), external 0.033 µF capacitor to OUT_B required.
HS bootstrap supply (BST), external 0.033 µF capacitor to OUT_C required.
HS bootstrap supply (BST), external 0.033 µF capacitor to OUT_D required.
Clipping warning; open drain; active low
BST_B
BST_C
BST_D
/CLIP
C_STARTUP
FREQ_ADJ
5
Startup ramp requires a charging capacitor of 4.7 nF to AGND
PWM frame rate programming pin requires resistor to AGND
12
14
7, 23, 24, 57,
58
GND
9
P
Ground
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_B
GVDD_C
GVDD_D
GVDD_AB
GVDD_CD
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
48, 49
46, 47
34, 35
32, 33
55
38
37
30
29
–
P
P
P
P
P
P
P
P
P
P
I
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
Gate drive voltage supply requires 0.1 µF capacitor to GND_A
Gate drive voltage supply requires 0.1 µF capacitor to GND_B
Gate drive voltage supply requires 0.1 µF capacitor to GND_C
Gate drive voltage supply requires 0.1 uF capacitor to GND_D
Gate drive voltage supply requires 0.22 µF capacitor to GND_A/GND_B
Gate drive voltage supply requires 0.22 µF capacitor to GND_C/GND_D
Input signal for half bridge A
56
–
25
–
26
-
–
44
23
6
–
4
5
7
I
Input signal for half bridge B
10
12
13
20
21
22
–
I
Input signal for half bridge C
11
I
Input signal for half bridge D
20
I
Mode selection
M2
21
I
Mode selection
M3
22
I
Mode selection
NC
59-62
1
–
O
No connect, pins may be grounded.
OC_ADJ
3
Analog over current programming pin requires resistor to ground:
64 pin QFP package (PHD) = 22 kΩ
44 pin PSOP3 Package (DKD) = 24 kΩ
OSC_IO+
OSC_IO–
/OTW
13
14
15
16
I/O
I/O
O
Oscillaotor master/slave output/input.
Oscillaotor master/slave output/input.
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Output, half bridge A
-
18
/OTW1
16
–
O
/OTW2
17
–
O
OUT_A
OUT_B
OUT_C
OUT_D
PSU_REF
52, 53
44, 45
36, 37
28, 29
63
39, 40
36
O
O
Output, half bridge B
31
O
Output, half bridge C
27, 28
1
O
Output, half bridge D
P
PSU Reference requires close decoupling of 330 pF to AGND
Power supply input for half bridges A requires close decoupling of 2.2-µF
capacitor to GND_A.
PVDD_A
PVDD_B
PVDD_C
50, 51
42, 43
38, 39
41, 42
35
P
P
P
Power supply input for half bridges B requires close decoupling of 2.2-µF
capacitor to GND_B.
Power supply input for half bridges C requires close decoupling of 2.2-µF
capacitor to GND_C.
32
(1) I = Input, O = Output, P = Power
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PIN FUNCTIONS (continued)
PIN
FUNCTION(1)
DESCRIPTION
NAME
PVDD_D
PHD NO.
DKD NO.
Power supply input for half bridges D requires close decoupling of 2.2-µF
capacitor to GND_D.
30, 31
25, 26
P
READY
RESET
SD
19
2
19
4
O
I
Normal operation; open drain; active high
Device reset Input; active low, requires 47kΩ pull up resistor to VREG
Shutdown signal, open drain, active low
15
17
O
Power supply for internal voltage regulator requires a 10-µF capacitor with a
0.1-µF capacitor to GND for decoupling.
VDD
64
2
P
VI_CM
VREG
6
9
8
O
P
Analog comparator reference node requires close decoupling of 1 nF to GND
11
Internal regulator supply filter pin requires 0.1-µF capacitor to GND
6
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TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
System
Filtering
&
Startup/Stop
microcontroller
or
Analog circuitry
(2)
BST_A
BST_B
OSC_IO+
OSC_IO-
Oscillator
Synchronization
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
INPUT_A
INPUT_B
OUT_A
ANALOG_IN_A
ANALOG_IN_B
Input DC
Blocking
Caps
Input
H-Bridge 1
Output
H-Bridge 1
2
OUT_B
2
H-Bridge
Hardwire
2-CHANNEL
H-BRIDGE
BTL MODE
PWM Frame
Rate Adjust
&
FREQ_ADJ
Master/Slave
Mode
2nd Order
L-C Output
Filter for
each
INPUT_C
OUT_C
ANALOG_IN_C
ANALOG_IN_D
Input DC
Blocking
Caps
Input
H-Bridge 2
Output
H-Bridge 2
2
INPUT_D
OUT_D
2
H-Bridge
M1
BST_C
BST_D
Hardwire
Mode
Control
M2
M3
Bootstrap
Caps
8
8
4
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
GVDD, VDD,
50V
Over-
Current
Limit
& VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
12V
GVDD (12V)/VDD (12V)
VAC
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FUNCTIONAL BLOCK DIAGRAM
CLIP
READY
OTW1
OTW2
SD
M1
M2
M3
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
GND
RESET
TEMP
SENSE
GVDD_A
GVDD_B
GVDD_C
GVDD_D
STARTUP
CONTROL
C_STARTUP
OVER-LOAD
PROTECTION
CURRENT
SENSE
CB3C
OC_ADJ
OSC_SYNC_IO+
OSC_SYNC_IO-
4
4
OSCILLATOR
PVDD_X
OUT_X
GND_X
PPSC
4
FREQ_ADJ
GVDD_A
BST_A
PWM
ACTIVITY
DETECTOR
PVDD_X
GND
PSU_REF
VI_CM
PSU_FF
PVDD_A
OUT_A
GND_A
GVDD_B
BST_B
PWM
RECEIVER
TIMING
CONTROL
CONTROL
GATE-DRIVE
-
ANALOG
LOOP FILTER
INPUT_A
INPUT_B
+
PVDD_B
OUT_B
GND_B
GVDD_C
BST_C
PWM
RECEIVER
TIMING
CONTROL
CONTROL
CONTROL
CONTROL
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
+
-
ANALOG
LOOP FILTER
INPUT_C
INPUT_D
PVDD_C
OUT_C
GND_C
GVDD_D
BST_D
-
ANALOG
LOOP FILTER
+
PWM
RECEIVER
TIMING
CONTROL
+
-
ANALOG
LOOP FILTER
PVDD_D
OUT_D
GND_D
PWM
RECEIVER
TIMING
CONTROL
8
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AUDIO CHARACTERISTICS (BTL)
PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 8Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15µH, CDEM = 680nF, mode = 010,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 8 Ω, 10% THD+N, clipped output signal
RL = 8 Ω, 1% THD+N, unclipped output signal
1 W
MIN
TYP MAX UNIT
160
PO
Power output per channel
W
125
THD+N Total harmonic distortion + noise
0.05
%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
260
µV
|VOS
|
Output offset voltage
Signal-to-noise ratio(1)
Inputs AC coupled to AGND
40 150
mV
dB
dB
W
SNR
DNR
Pidle
100
100
2.3
Dynamic range
Power dissipation due to Idle losses (IPVDD_X
)
PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15µH, CDEM = 330nF, MODE = 100,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10% THD+N, clipped output signal
RL = 4 Ω, 1% THD+N, unclipped output signal
1 W
MIN
TYP MAX UNIT
75
PO
Power output per channel
W
60
THD+N Total harmonic distortion + noise
0.05
350
93
%
µV
dB
dB
W
Vn
Output integrated noise
Signale to noise ratio(1)
A-weighted
SNR
DNR
Pidle
A-weighted
Dynamic range
A-weighted
PO = 0, 4 channels switching(2)
93
Power dissipation due to idle losses (IPVDD_X
)
1.15
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
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AUDIO SPECIFICATION (PBTL)
PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V,
GVDD_X = 12 V, RL = 4Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15µH, CDEM = 680nF, MODE =
101-BD, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10% THD+N, clipped output signal
RL = 6 Ω, 10% THD+N, clipped output signal
RL = 8 Ω, 10% THD+N, clipped output signal
RL = 4 Ω, 1% THD+N, unclipped output signal
RL = 6 Ω, 1% THD+N, unclipped output signal
RL = 8 Ω, 1% THD+N, unclipped output signal
1 W
MIN
TYP MAX UNIT
300
210
160
PO
Power output per channel
W
240
160
125
THD+N Total harmonic distortion + noise
0.05
260
100
100
2.3
%
µV
dB
dB
W
Vn
Output integrated noise
Signale to noise ratio(1)
Dynamic range
A-weighted
SNR
DNR
Pidle
A-weighted
A-weighted
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50.0 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG
VI_CM
VDD = 12 V
3
3.3
3.6
1.9
V
V
node
Analog comparator reference node
1.5
1.75
22.5
22.5
8
Operating, 50% duty cycle
Idle, reset mode
IVDD
VDD supply current
mA
mA
50% duty cycle
IGVDD_x
Gate-supply current per half-bridge
Half-bridge idle current
Reset mode
1.5
7
50% duty cycle without output filter or load
Reset mode, No switching
mA
IPVDD_x
610
µA
ANALOG INPUTS
RIN
Input resistance
READY = HIGH
33
5
kΩ
V
VIN
Maximum input voltage swing
Maximum input current
IIN
342
23
mA
dB
G
Voltage Gain (VOUT/VIN)
OSCILLATOR
Nominal, Master Mode
AM1, Master Mode
AM2, Master Mode
3.5
3.1
4
3.4
3
4.5
3.5
3.2
fOSC_IO+
FPWM × 10
MHz
2.6
VIH
VIL
High level input voltage
Low level input voltage
1.86
V
V
1.45
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
120 200
120 200
mΩ
mΩ
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
RDS(on)
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50.0 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
I/O PROTECTION
Undervoltage protection limit, GVDD_x
and VDD
Vuvp,G
9.5
V
(1)
Vuvp,hyst
0.6
V
OTW1(1)
OTW2(1)
Overtemperature warning 1
Overtemperature warning 2
95
100 105
125 135
°C
°C
115
Temperature drop needed below OTW
temperture for OTW to be inactive after
OTW event.
(1)
OTWHYST
25
°C
OTE(1)
OTE-
Overtemperature error
145
155 165
30
°C
°C
OTE-OTW differential
(1)
OTWdifferential
A reset needs to occur for SD to be
released following an OTE event
(1)
OTEHYST
25
°C
OLPC
IOC
Overload protection counter
fPWM = 400 kHz
1.3
ms
Resistor – programmable, nominal
continious current in 1Ω load, 64 Pin QFP
package (PHD), ROCP = 22 kΩ
10
10
10
A
A
A
Overcurrent limit protection
Resistor – programmable, nominal
continious current in 1Ω load, 44 Pin PSOP3
package (DKD), ROCP = 24 kΩ
Resistor – programmable, continious current
in 1Ω load,
IOC_LATCHED
Overcurrent limit protection
ROCP = 47 kΩ
Time from switching transition to flip-state
induced by overcurrent.
IOCT
IPD
Overcurrent response time
150
3
ns
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
Output pulldown current of each half
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
Low level input voltage
Input leakage current
1.9
20
V
V
INPUT_X, M1, M2, M3, RESET
VIL
1.45
100
Leakage
µA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to
RINT_PU
26
32
kΩ
VREG, OTW2 to VREG, SD to VREG
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
IO = 4 mA
3
3.3
3.6
5
VOH
High level output voltage
V
4.5
VOL
Low level output voltage
200 500
mV
Device fanout OTW1, OTW2, SD, CLIP,
READY
FANOUT
No external pullup
30
devices
(1) Specified by design.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC+NOISE
OUTPUT POWER
vs
SUPPLY VOLTAGE
vs
OUTPUT POWER
10
5
180
170
160
150
140
130
120
110
100
90
T
= 75°C
T
= 75°C
C
THD+N at 10%
C
2
1
0.5
8W
0.2
0.1
80
70
60
8W
0.05
50
40
0.02
30
20
0.01
10
0
0.005
25 27 29 31 33 35 37 39 41 43 45 47 49
PVDD - Supply Voltage - V
20m
100m 200m
P
1
2
- Output Power - W
10 20
100 200
O
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
SYSTEM EFFICIENCY
vs
OUTPUT POWER
vs
SUPPLY VOLTAGE
150
140
130
120
110
100
90
100
90
80
70
60
50
40
30
20
T
= 75°C
C
8W
8W
80
70
60
50
40
30
T
= 75°C
20
C
THD+N at 10%
10
0
10
0
25 27 29 31 33 35 37 39 41 43 45 47 49
PVDD - Supply Voltage - V
0
40
80 120 160 200 240 280 320
2 Channels Output Power - W
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
vs
CASE TEMPERATURE
OUTPUT POWER
34
32
30
28
26
24
22
20
18
16
14
12
10
8
200
180
THD+N at 10%
T
= 75°C
C
THD+N at 10%
160
140
8W
120
100
80
8W
60
40
6
4
20
0
2
0
10 20 30 40 50 60 70 80 90 100 110 120
- Case Temperature - °C
0
40
80 120 160 200 240 280 320
2 Channels Output Power - W
T
C
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
0
T
= 75°C,
C
V
= 32.7 V,
REF
Sample Rate = 48 kHz,
FFT Size = 16384
-20
-40
-60
-80
-100
-120
-140
-160
0
2
4
6
8 10 12 14 16 18 20 22
f - Frequency - kHz
Figure 7.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
SUPPLY VOLTAGE
vs
OUTPUT POWER
10
5
90
85
T
= 75°C
C
THD+N at 10%
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
2
1
4W
0.5
6W
0.2
0.1
4W
6W
8W
8W
0.05
0.02
0.01
0.005
0
25 27 29 31 33 35 37 39 41 43 45 47 49
PVDD - Supply Voltage - V
20m
100m 200m
P
O
1
2
- Output Power - W
10 20
100
Figure 8.
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
100
THD+N at 10%
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
4W
6W
8W
5
0
10 20 30 40 50 60 70 80 90 100 110 120
- Case Temperature - °C
T
C
Figure 10.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
SUPPLY VOLTAGE
vs
OUTPUT POWER
10
5
340
320
300
280
260
240
220
200
180
160
140
120
100
80
T
= 75°C
T
= 75°C
C
C
THD+N at 10%
4W
6W
2
1
4W
8W
0.5
6W
8W
0.2
0.1
0.05
0.02
60
40
0.01
20
0
0.005
25 27 29 31 33 35 37 39 41 43 45 47 49
PVDD - Supply Voltage - V
20m 100m 200m
1
2
10 20
- Output Power - W
100 200 500
P
O
Figure 11.
Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
400
THD+N at 10%
360
320
280
240
4W
6W
200
160
120
80
8W
40
0
10 20 30 40 50 60 70 80 90 100 110 120
- Case Temperature - °C
T
C
Figure 13.
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APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2 oz. (70 µm) is recommended for use with the TAS5615. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 µF, 63 V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
DECOUPLING CAPACITOR RECOMMENDATIONS
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2µF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 63 V is required for use with a 50.0 V power
supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate "best practices" in the use of the TAS5615.
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
/ O T W 2
1 7
Figure 14. Typical Differential Input BTL Application With BD Modulation Filters
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
/ O T W 2
1 7
Figure 15. Typical Differential (2N) PBTL Application With BD Modulation Filters
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3.3R
VDD (+12V)
3.3R
GVDD (+12V)
100nF
100nF
10uF
100nF
33nF
15uH
A
GND GND
GND GND
GND
PVDD
VREG
2.2uF
GND
47k
100R
/RESET
4.7uF
GND
100pF
GND
22.0k
10nF
100R
100R
100R
100R
1
2
3
4
5
6
48
47
46
45
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
IN_A
IN_B
IN_C
IN_D
GND
GND
10uF
10uF
10uF
10uF
100pF
GND
15uH
B
GND
GND
GND
44
2.2uF
33nF
43
42
41
40
100pF
4.7uF
7
PVDD
GND
GND
GND
100nF
VREG
8
9
3.3R
AGND
GND
TAS5615PHD
47uF
63V
2.2uF
VREG
BST_C
39
38
37
36
10
11
12
13
14
15
10nF
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
/SD
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
100pF
10k
33nF
2.2uF
15uH
GND
GND
GND
C
GND
35
34
33
100pF
GND
16
/OTW1
GND
OSC_IO+
OSC_IO-
2.2uF
PVDD
/SD
/OTW1
/OTW2
/CLIP
GND
VREG
15uH
D
33nF
GND
3.3R
GVDD (+12V)
READY
3.3R
100nF
100nF
10nF
100V
10nF
100V
GND GND
GND
GND
3.3R
3.3R
OUT_A_M
OUT_B_M
A
B
PVDD
R_COMP
100nF
100nF
R_COMP
R_COMP
-
+
-
+
100V
100V
50
49
48
V
V
V
140 kOhm
160 kOhm
180 kOhm
187 kOhm
330nF
250V
330nF
250V
10k
10k
PVDD
PVDD
10k
10k
1%
470uF
100nF
100V
GND
470uF
100nF
100V
GND
50V
1%
50V
<48
V
OUT_A_P
OUT_B_P
10k
1%
10k
1%
470uF
50V
470uF
50V
3.3R
3.3R
GND
GND
100V
100V
10nF
10nF
GND
GND
10nF
100V
10nF
100V
GND
GND
3.3R
3.3R
OUT_C_M
OUT_D_M
C
D
100nF
100V
100nF
100V
R_COMP
R_COMP
-
+
-
+
330nF
250V
330nF
250V
10k
10k
PVDD
PVDD
10k
1%
10k
1%
470uF
50V
100nF
100V
GND
470uF
50V
100nF
100V
GND
OUT_C_P
OUT_D_P
10k
1%
10k
1%
470uF
50V
470uF
50V
3.3R
3.3R
GND
GND
100V
10nF
100V
10nF
GND
GND
Figure 16. Typical SE Application
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
/ O T W 2
1 7
Figure 17. Typical 2.1 System Differential Input BTL and Unbalanced Input SE Application
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5615 needs only a 12V supply in addition to the (typical) 50V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2µF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5615 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5615 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5615 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5615 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1 OTW2, OTW DESCRIPTION
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction temperature higher than 125°C
(overtemperature warning)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
1
1
0
0
1
1
0
1
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 100°C
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature higher than 100°C (overtemperature warning)
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW
outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5615 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5615 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table
BTL
MODE
PBTL
MODE
SE
MODE
LOCAL
TURNS OFF
LOCAL
TURNS OFF
LOCAL
TURNS OFF
ERROR IN
ERROR IN
ERROR IN
A
B
C
D
A+B
C+D
A
B
C
D
A+B+C+D
A
B
C
D
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,
all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
22
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typical duration is < 15ms/µF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options has individual over temperature protection schemes.
PHD Package
The TAS5615 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5615 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5615 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low.
Asserting reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high.
A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal
goes low hence filtering is needed if the signal is intended for audio muting in non microcontroller systems.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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SLAS595–JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs and needs to be slaved from an external clock.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 14.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 18. Printed Circuit Board - Top Layer
24
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Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 19. Printed Circuit Board - Bottom Layer
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2009
PACKAGING INFORMATION
Orderable Device
TAS5615DKD
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HSSOP
DKD
44
29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5615DKDR
HSSOP
DKD
44
500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5615PHD
PREVIEW
PREVIEW
HTQFP
HTQFP
PHD
PHD
64
64
90
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TAS5615PHDR
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TAS5615DKDR
HSSOP
DKD
44
500
330.0
24.4
14.7
16.4
4.0
20.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HSSOP DKD 44
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
TAS5615DKDR
500
Pack Materials-Page 2
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Applications
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