TAS5720LRSMT [TI]
20W 单声道、4.5V 至 16.5V 电源电压、数字输入 D 类音频放大器 | RSM | 32 | -25 to 85;
| 型号： | TAS5720LRSMT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20W 单声道、4.5V 至 16.5V 电源电压、数字输入 D 类音频放大器 | RSM | 32 | -25 to 85 放大器 商用集成电路 音频放大器 |
| 文件： | 总51页 (文件大小：1669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
TAS5720x 具有支持多达 8 通道的 TDM 接口的数字输入单声道 D 类音频
放大器
1 特性
3 说明
1
•
单声道 D 类放大器
TAS5720x 器件是一款高效单声道 D 类音频功率放大
器，针对高瞬态功率能力进行了优化，从而能够利用小
型扬声器的动态功率余量。该器件可持续为 4Ω 的扬声
器提供超过 15W 的功率。
–
0.15% 总谐波失真 (THD) 时的持续输出功率为
20W
(19V/4Ω)
•
时分复用 (TDM) 音频输入
数字时分复用 (TDM) 接口支持多达 8 个器件共用同一
条总线。
–
多达 8 条通道（32 位，48kHz）
•
•
I2C 控制，有 8 个 I2C 地址可供选择
电源
TAS5720x 器件采用 32 引脚、
–
–
–
功率放大器：4.5V 至 16.5V，TAS5720L
功率放大器：4.5V 至 26.4V，TAS5720M
数字 I/O 电压：3.3V
4mm × 4mm、VQFN 封装，使得 PCB 外形更加紧
凑。
器件信息(1)
•
•
保护：热保护和短路保护
器件型号
TAS5720L
TAS5720M
封装
封装尺寸（标称值）
封装：4mm × 4mm、32 引脚超薄四方扁平无引线
封装 (VQFN)
VQFN (32)
4.00mm x 4.00mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
低音炮
音箱
条形扬声器
环绕立体声系统
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS903
TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
www.ti.com.cn
中的引脚名称 SCLK 更改为 BCLK
简化电路原理图
4.5 V - 16.5 V, TAS5720L
4.5 V - 26.4 V, TAS5720M
3.3 V
BST_P
OUT_P
SDZ
Protections:
Pop/Click
Overcurrent
Over Temperature
ñ
ñ
ñ
ADR0
ADR1
SCL
Closed-
Loop
Class-D
Amplifier
OUT_N
BST_N
SDA
System
Interface
DAC
FAULTZ
SDIN
LRCLK
BCLK
Voltage
Regulators
MCLK
TAS5720L/M
2
版权 © 2015–2016, Texas Instruments Incorporated
TAS5720L, TAS5720M
www.ti.com.cn
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
目录
7.4 Device Functional Modes ....................................... 31
7.5 Register Maps......................................................... 33
Applications and Implementation ...................... 41
8.1 Application Information............................................ 41
8.2 Typical Application .................................................. 41
Power Supply Recommendations...................... 43
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements.............................................. 10
6.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 20
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 20
7.3 Feature Description................................................. 20
8
9
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 44
11 器件和文档支持 ..................................................... 45
11.1 文档支持................................................................ 45
11.2 社区资源................................................................ 45
11.3 商标....................................................................... 45
11.4 静电放电警告......................................................... 45
11.5 Glossary................................................................ 45
12 机械、封装和可订购信息....................................... 45
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2015) to Revision B
Page
•
•
Updated Typical Characteristics graphs with new data, new standards.............................................................................. 13
已添加 new Layout Example ............................................................................................................................................... 44
Changes from Original (September 2015) to Revision A
Page
•
量产发布 ................................................................................................................................................................................ 1
Copyright © 2015–2016, Texas Instruments Incorporated
3
TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
www.ti.com.cn
5 Pin Configuration and Functions
RSM Package
VQFN 32 PINS
Top View
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VREF_N
FAULTZ
SDZ
OUT_P
BST_P
PGND
PGND
PGND
PGND
BST_N
OUT_N
LRCLK
MCLK
BCLK
SDIN
Exposed Thermal Pad
SCL
Pin Functions
PIN
I/O/P(1) DESCRIPTION
NAME
ADR1
NO.
12
13
28
18
23
11
2
I2C address inputs. Each pin can detect a short to DVDD, a short to GND, a 22-kΩ connection to GND,
and a 22-kΩ connection to DVDD.
I
ADR0
I
AVDD
BST_N
BST_P
DVDD
FAULTZ
LRCLK
P
P
P
P
O
I
Analog power supply input. Connect directly to PVDD.
Class-D Amplifier negative bootstrap. Connect to a capacitor between BST_N and OUT_N.
Class-D Amplifier positive bootstrap. Connect to a capacitor between BST_P and OUT_P.
Digital power supply. Connect to a 3.3-V supply with external decoupling capacitor.
Open drain active low fault flag. Pull up on PCB with resistor to DVDD.
TDM interface frame synchronization.
4
10
29
30
5
GND
P
Ground. Connect to PCB ground plane.
GVDD
MCLK
O
I
Class-D amplifier gate drive regulator output. Connect decoupling cap to PCB ground plane.
Device master clock.
19
20
21
22
14
15
26
27
16
17
24
25
6
PGND
P
Power ground. Connect to PCB ground plane.
PVDD
P
Class-D amplifier power supply input. Connect to PVDD supply and decouple externally.
Class-D amplifier negative output.
OUT_N
O
OUT_P
BCLK
O
I
Class-D amplifier positive output.
TDM Interface serial bit clock.
(1) I = input, O = output, P = power, I/O = bi-directional
4
Copyright © 2015–2016, Texas Instruments Incorporated
TAS5720L, TAS5720M
www.ti.com.cn
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
Pin Functions (continued)
PIN
NAME
SCL
I/O/P(1) DESCRIPTION
NO.
8
I
I/O
I
I2C clock Input. Pull up on PCB with a 2.4-kΩ resistor.
I2C bi-directional data. Pull up on PCB with a 2.4-kΩ resistor.
TDM interface data input.
SDA
9
SDIN
7
SDZ
3
I
Active low shutdown signal. Assert low to hold device inactive.
Thermal
Pad
33
G
Connect to GND for best system performance. If not connected to GND, leave floating.
VCOM
VREF_N
VREG
32
1
O
P
Common mode reference output. Connect decoupling capacitor to the VREF_N pin.
Negative reference for analog. Connect to VCOM and VREG capacitor negative pins.
Analog regulator output. Connect decoupling capacitor to the VREF_N pin.
31
O
Copyright © 2015–2016, Texas Instruments Incorporated
5
TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.5
–25
MAX
UNIT
PVDD, AVDD (TAS5720L)
20
Supply voltage(2)
PVDD, AVDD (TAS5720M)
DVDD
30
V
4
VDVDD + 0.5
85
Digital input voltage
Digital inputs referenced to DVDD supply
V
Ambient operating temperature, TA
Storage temperature, Tstg
°C
°C
–40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) All voltages are with respect to network ground pin.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
3
TYP
MAX
16.5
26.4
3.6
UNIT
V
TAS5720L
TAS5720M
PVDD/
AVDD
Power supply voltage
V
DVDD
VIH(DR)
VIL(DR)
RSPK
TA
Power supply voltage
3.3
VDVDD
0
V
High-level digital input voltage
Low-level digital input voltage
Minimum speaker load
V
V
3.2
–25
–25
Ω
Operating free-air temperature
Operating junction temperature
85
°C
°C
TJ
150
6.4 Thermal Information
TAS5720x
RSM (VQFN)
32 PINS
37.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30.4
7.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
7.7
RθJCbot
2.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6
版权 © 2015–2016, Texas Instruments Incorporated
TAS5720L, TAS5720M
www.ti.com.cn
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
6.5 Electrical Characteristics
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT AND OUTPUT
High-level digital input logic
voltage threshold
VIH
All digital pins
All digital pins
70% VDVDD
Low-level digital input logic
voltage threshold
VIL
30% VDVDD
Input logic "high" leakage for
digital inputs
IIH
All digital pins, excluding SDZ
15
µA
µA
µA
µA
Input logic "low" leakage for
digital inputs
IIL
All digital pins, excluding SDZ
–15
Input logic "high" leakage for
SDZ inputs
IIH(SDZ)
IIL(SDZ)
VOL
CIN
SDZ
1
–1
Input logic "low" leakage for
SDZ inputs
SDZ
Output logic "low" for FAULTZ
open drain Output
IOL = –2 mA
All digital pins
10% VDVDD
Input capacitance for digital
inputs
5
pF
MASTER CLOCK
D(MCLK)
Allowable MCLK duty cycle
MCLK input frequency
45%
50%
55%
25
MHz
Supported single-speed MCLK
frequencies
Values: 64, 128, 256, and 512
Values: 64, 128, and 256
64 × fS
64 × fS
512 × fS
256 × fS
f(MCLK)
Supported double-speed MCLK
frequencies
SERIAL AUDIO PORT
D(BCLK)
Allowable BCLK duty cycle
BCLK input frequency
45%
50%
55%
25
MHz
Supported single-speed BCLK
frequencies
Values: 64, 128, 256, and 512
Values: 64, 128, and 256
Values: 44.1 and 48
64 × fS
64 × fS
44.1
512 × fS
256 × fS
48
f(BCLK)
Supported double-speed BCLK
frequencies
Supported single-speed input
sample rates
kHz
kHz
fS
Supported double-speed input
sample rates
Values: 88.2 and 96
88.2
96
I2C CONTROL PORT
Allowable load capacitance for
each I2C Line
CL(I2C)
400
400
pF
fSCL
SCL frequency
No wait states
kHz
PROTECTION
Overtemperature error (OTE)
threshold
OTE(THRESH)
OTE(HYST)
150
15
°C
°C
Overtemperature error (OTE)
hysteresis
Overcurrent error (OCE)
threshold
OCE(THRESH)
DCE(THRESH)
V(PVDD) = 16.5 V, TA = 25°C
V(PVDD) = 16.5 V, TA = 25°C
6
A
V
DC error (DCE) threshold
2.6
版权 © 2015–2016, Texas Instruments Incorporated
7
TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Electrical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AMPLIFIER PERFORMANCE
RL= 4 Ω, 10% THD+N, V(PVDD) = 7.2 V,
fIN = 1 kHz
6.6
3.7
RL= 8 Ω, 10% THD+N, V(PVDD) = 7.2 V,
fIN = 1 kHz
RL= 4 Ω, 10% THD+N, V(PVDD) = 12 V,
fIN = 1 kHz
17.8
10.1
27.4
15.8
27
RL= 8 Ω, 10% THD+N, V(PVDD) = 12 V,
fIN = 1 kHz
RL= 4 Ω, 10% THD+N, V(PVDD) = 15 V,
fIN = 1 kHz, TA= 60°C
POUT
Continuous average power
W
RL= 8 Ω, 10% THD+N, V(PVDD) = 15 V,
fIN = 1 kHz
RL= 4 Ω, 10% THD+N, V(PVDD) = 19 V,
fIN = 1 kHz
RL= 8 Ω, 10% THD+N, V(PVDD) = 19 V,
fIN = 1 kHz
25.3
RL= 4 Ω, 10% THD+N, V(PVDD) = 24 V,
fIN = 1 kHz
22.1
39.8
RL= 8 Ω, 10% THD+N, V(PVDD) = 24 V,
fIN = 1 kHz
RL= 4 Ω,V(PVDD) = 7.2 V, POUT = 1 W,
fIN = 1 kHz
0.033%
0.015%
0.03%
RL= 8 Ω,V(PVDD) = 7.2 V, POUT = 1 W,
fIN = 1 kHz
RL= 4 Ω, V(PVDD)= 12 V, POUT = 1 W,
fIN = 1 kHz
RL= 8 Ω, V(PVDD)= 12 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz
0.013v
0.028%
0.012%
0.026%
0.013%
0.026%
RL= 4 Ω, V(PVDD) = 15 V, POUT = 1 W,
20 Hz ≤ fIN≤ 20 kHz
Total harmonic distortion plus
noise
THD+N
RL= 8 Ω, V(PVDD) = 15 V, POUT = 1 W,
20 Hz ≤ fIN≤ 20 kHz
RL= 4 Ω, V(PVDD) = 19 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz
RL= 8 Ω, V(PVDD) = 19 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz
RL= 4 Ω, V(PVDD) = 24 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz
RL= 8 Ω, V(PVDD) = 24 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz
0.016%
91%
RL= 8 Ω, V(PVDD) = 12 V, POUT = 9 W
RL= 8 Ω, V(PVDD) = 12 V, POUT = 9 W;
fPWM = 384 kHz
PEFF
Power efficiency
90%
RL= 8 Ω, V(PVDD) = 24 V, POUT = 40 W
A-Weighted,RL= 8 Ω, Gain = 20.7 dBV
90%
50
VN
Integrated noise floor voltage
Channel-to-channel phase shift
µVrms
deg
Output phase shift between multiple
devices from 20 Hz to 20 kHz. Across all
sample frequencies and SAIF operating
modes.
φCC
0.2
Maximum deviation above or below
passband gain.
A(RIPPLE)
Frequency response
±0.15
dB
Hz
-3 dB Output Cutoff Frequency
0.47 × fS
8
版权 © 2015–2016, Texas Instruments Incorporated
TAS5720L, TAS5720M
www.ti.com.cn
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
Electrical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AV(00)
AV(01)
AV(10)
AV(11)
ANALOG_GAIN[1:0] register bits set to
"00"
19.2
dBV
ANALOG_GAIN[1:0] register bits set to
"01"
20.7
23.5
26.3
Amplifier analog gain(1)
ANALOG_GAIN[1:0] register bits set to
"10"
ANALOG_GAIN[1:0] register bits set to
"11"
AV(ERROR)
VOS
Amplifier analog gain error
DC output offset voltage
Click-pop performance
±0.15
dB
mV
Measured between OUTP and OUTN
1.5
–60
87
KCP
dBV
DC, 5.5 V ≤ V(PVDD) ≤ 26.4 V
AC, V(PVDD)= 16.5 V + 100 mVP-P, f(RIPPLE)
from 20 Hz to 10 kHz
53
PSRR
Power supply rejection ratio
dB
AC, V(PVDD)= 16.5 V + 100 mVP-P, f(RIPPLE)
from 10 Hz to 20 kHz
50
120
150
RDS(on)FET
RDS(on)TOT
IPK
Power stage FET on-resistance TA = 25°C
mΩ
mΩ
A
Power stage total on-resistance
TA = 25°C
(FET+bond+package)
Peak output current
TA = 25°C
5
3.675
4
f = 44.1 kHz
f = 48 kHz
–3 dB high-pass filter corner
frequency
f(HP)
Hz
f = 88.2 kHz
7.35
8
f = 96 kHz
f(PWM)
PWM switching frequency
Values: 6, 8, 10, 12, 14, 16, 20, and 24
6
24
fS
(1) When PVDD is less than 5.5 V, the voltage regulator that operates the analog circuitry does not have enough headroom to maintain the
nominal 5.4-V internal voltage. The lack of headroom causes a direct reduction in gain (approximately –0.8 dB at 5 V and –1.74 dB at
4.5 V), but the device functions properly down to VPVDD = 4.5 V.
版权 © 2015–2016, Texas Instruments Incorporated
9
TAS5720L, TAS5720M
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
www.ti.com.cn
MAX UNIT
6.6 Timing Requirements
MIN
NOM
From deassertion of SDZ (both pin and I2C
register bit) until the Class-D amplifier
begins switching.
tACTIVE
Shutdown to Active Time
25
From the deassertion of SLEEP until the
Class-D amplifier starts switching.
tWAKE
tSLEEP
tMUTE
tPLAY
Wake Time
1
tvrmp + 1
tvrmp
From the assertion of SLEEP until the
Class-D amplifier stops switching.
Sleep Time
ms
From the assertion of MUTE mode until the
volume has ramped to the minimum.
Play to Mute Time
Un-Mute to Play Time
From the deassertion of MUTE until the
volume has returned to its current setting.
tvrmp
From the assertion of SDZ (pin or I2C
register bit) until the Class-D amplifier stops
switching.
tSD
Active to Shutdown Time
tvrmp + 1
SERIAL AUDIO PORT
Time high and low, BCLK, LRCLK,
SDIN inputs
tH_L
10
ns
Input tRISE ≤ 1 ns, input tFALL ≤ 1 ns
Input tRISE ≤ 4 ns, input tFALL ≤ 4 ns
Input tRISE ≤ 8 ns, input tFALL ≤ 8 ns
5
tSU
tHLD
Setup and hold time. LRCLK,
SDIN input to BCLK edge.
8
ns
12
Rise-time BCLK, LRCLK, SDIN
inputs
tRISE
tFALL
8
8
ns
Fall-time BCLK, LRCLK, SDIN
inputs
I2C CONTROL PORT
Bus free time between start and
stop conditions
tBUS
1.3
µs
tHOLD1(I2C)
tHOLD2(I2C)
Hold Time, SCL to SDA
Hold Time, start condition to SCL
80
ns
µs
0.6
I2C Startup Time after DVDD
Power On Reset
tSTART(I2C)
12
ms
tRISE(I2C)
tFALL(I2C)
tSU1(I2C)
tSU2(I2C)
tSU3(I2C)
Rise Time, SCL and SDA
Fall Time, SCL and SDA
Setup, SDA to SCL
300
300
ns
ns
ns
µs
µs
100
0.6
0.6
Setup, SCL to start condition
Setup, SCL to stop condition
Required pulse duration, SCL
"HIGH"
tW(H)
0.6
1.3
µs
µs
Required pulse duration, SCL
"LOW"
tW(L)
PROTECTION
DC detect error
650
1.3
ms
s
tFAULTZ
Amplifier fault time-out period
OTE or OCE fault
10
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TAS5720L, TAS5720M
www.ti.com.cn
ZHCSET5B –MAY 2015–REVISED FEBRUARY 2016
t
SU
BCLK
t
t
HD
HD
t
SU
LRCLK
SDIN
图 1. SAIF Timing
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
图 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
图 3. Start and Stop Conditions Timing
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When SDZ is deasserted (and the device is not in sleep mode), the amplifier begins to switch after a period of
tACTIVE. At this point, the volume ramps from –100 dB to the programmed digital volume control (DVC) setting at
a rate of 0.5 dB every eight sample periods. Ramping the volume prevents audible artifacts that can occur if
discontinuous volume changes are applied while audio is being played back. This period, tVRMP, depends on the
DVC setting and sample rate. Typical values for tVRMP for a DVC of 0 dB are shown in Timing Requirements. 图 4
illustrates mode timing.
The time to enter or exit sleep or mute and the time to enter shudown are dominated by tVRMP. 表 1 lists the
timing parameters based on tVRMP
.
tMUTE
tPLAY
tSD
t
t
t
SLEEP
ACTIVE
VRMP
t
WAKE
SDZ
SLEEP
MUTE
VOLUME
OUTx
图 4. Mode Timing
表 1. Typical DVC Ramp Times
SAMPLE
RAMP TIMES (tVRAMP)
RATE (kHZ)
FROM –100 dB to 0 dB (ms)
44.1
48
36.3
33.3
18.1
16.7
88.2
96
12
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6.7 Typical Characteristics
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D0021
D0021
V(PVDD) = 7.2 V
POUT = 1 W
f(PWM) = 384 kHz
V(PVDD) = 7.2 V
POUT = 1 W
图 5. THD+N vs Frequency
图 6. THD+N vs Frequency
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
0.1
1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D0021
D0021
V(PVDD) = 12 V
POUT = 1 W
f(PWM) = 384 kHz
V(PVDD) = 12 V
POUT = 1 W
图 7. THD+N vs Frequency
图 8. THD+N vs Frequency
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
0.1
1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D006
D007
V(PVDD) = 15 V
POUT = 1 W
f(PWM) = 384 kHz
V(PVDD) = 15 V
POUT = 1 W
图 9. THD+N vs Frequency
图 10. THD+N vs Frequency
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D008
D009
V(PVDD) = 19 V
POUT = 1 W
f(PWM) = 384 kHz
V(PVDD) = 19 V
POUT = 1 W
图 11. THD+N vs Frequency
图 12. THD+N vs Frequency
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
0.1
1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D010
D011
V(PVDD) = 24 V
POUT = 1 W
f(PWM) = 384 kHz
V(PVDD) = 24 V
POUT = 1 W
图 13. THD+N vs Frequency
图 14. THD+N vs Frequency
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.005
0.005
0.01
0.1
Output Power (W)
1
10
0.01
0.1
Output Power (W)
1
10
D012
D013
V(PVDD) = 7.2 V
f(PWM) = 384 kHz
V(PVDD) = 7.2 V
图 16. THD+N vs Output Power
图 15. THD+N vs Output Power
14
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.005
0.01
0.1
1
10 20
0.01
0.1
1
10 20
Output Power (W)
Output Power (W)
D014
D015
V(PVDD) = 12 V
f(PWM) = 384 kHz
V(PVDD) = 12 V
图 17. THD+N vs Output Power
图 18. THD+N vs Output Power
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.005
0.01
0.1
1
10
30
0.01
0.1
1
10
30
Output Power (W)
Output Power (W)
D016
D017
V(PVDD) = 15 V
f(PWM) = 384 kHz
V(PVDD) = 15 V
图 19. THD+N vs Output Power
图 20. THD+N vs Output Power
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.1
0.01
0.01
0.005
0.01
0.1
1
10
50
0.01
0.1
1
10
50
Output Power (W)
Output Power (W)
D018
D019
V(PVDD) = 19 V
f(PWM) = 384 kHz
V(PVDD) = 19 V
图 22. THD+N vs Output Power
图 21. THD+N vs Output Power
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
10
10
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
1
0.1
0.01
0.1
0.01
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
D020
D021
V(PVDD) = 24 V
f(PWM) = 384 kHz
V(PVDD) = 24 V
Gain = 20.7 dBV
图 23. THD+N vs Output Power
图 24. THD+N vs Output Power
80
70
RL = 8 W
RL = 8 W
RL = 6 W
RL = 6 W
70
60
50
40
30
20
10
0
60
RL = 4 W
RL = 4 W
RL = 6 W, Thermal Limit
RL = 4 W, Thermal Limit
RL = 6 W, Thermal Limit
RL = 4 W, Thermal Limit
50
40
30
20
10
0
10
15
Supply Voltage (V)
20
25
10
15
Supply Voltage (V)
20
25
D022
D023
Analog Gain = Setting 11
f(PWM) = 384 kHz
Analog Gain = Setting 11
图 26. Output Power vs Supply Voltage
图 25. Output Power vs Supply Voltage
16
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
Analog Gain = 00
Analog Gain = 01
Analog Gain = 10
Analog Gain = 11
Analog Gain = 00
Analog Gain = 01
Analog Gain = 10
Analog Gain = 11
5
10
15
20
25
5
10
15
20
25
Supply Voltage (V)
Supply Voltage (V)
D025
D024
f(PWM) = 384 kHz
图 27. A-Weighted Idle Channel Noise vs Supply Voltage
图 28. Efficiency vs Output Power
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
PVDD = 7.2 V
PVDD = 12 V
PVDD = 15 V
PVDD = 19 V
PVDD = 24 V
PVDD = 7.2 V
PVDD = 12 V
PVDD = 15 V
PVDD = 19 V
PVDD = 24 V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Power (W)
Output Power (W)
D026
D027
RL = 4 Ω
f(PWM) = 384 kHz
RL = 4 Ω
图 29. Efficiency vs Output Power
图 30. Efficiency vs Output Power
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVDD = 7.2 V
PVDD = 12 V
PVDD = 15 V
PVDD = 19 V
PVDD = 24 V
PVDD = 7.2 V
PVDD = 12 V
PVDD = 15 V
PVDD = 19 V
PVDD = 24 V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Power (W)
Output Power (W)
D028
D029
RL = 8 Ω
f(PWM) = 384 kHz
RL = 8 Ω
图 31. Efficiency vs Output Power
图 32. Efficiency vs Output Power
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
PVDD = 12V
PVDD = 24V
PVDD = 12V
PVDD = 24V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D030
D031
f(PWM) = 384 kHz
图 33. PVDD PSRR vs Frequency
图 34. PVDD PSRR vs Frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
PVDD = 12V
PVDD = 24V
PVDD = 12V
PVDD = 24V
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D032
D033
f(PWM) = 384 kHz
图 35. DVDD PSRR vs Frequency
图 36. DVDD PSRR vs Frequency
18
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Typical Characteristics (接下页)
TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1,
Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction
filter at the device output.
30
26
22
18
14
10
70
60
50
40
30
20
10
FPWM = 384kHz
FPWM = 768kHz
5
10
15
Supply Voltage (V)
20
25
5
10
15
20
25
Supply Voltage (V)
D034
D035
图 37. Supply Idle Current vs PVDD
图 38. Shutdown Current vs PVDD
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7 Detailed Description
7.1 Overview
The TAS5720L/M device is a high-efficiency mono Class-D audio power amplifier optimized for high-transient
power capability to utilize the dynamic power headroom of small loudspeakers. It’s capable of delivering more
than 15-W continuously into a 4-Ω speaker.
7.2 Functional Block Diagram
DVDD
PVDD AVDD
SDZ
ADR0
ADR1
SDA
Protections:
Pop/Click
Overcurrent
OUT_P
BST_P
ñ
ñ
ñ
Over Temperature
Closed-Loop
Class-D
Amplifier
OUT_N
BST_N
DAC
System
Interface
FAULTZ
SDIN
LRCLK
BCLK
Voltage
Regulators
MCLK
TAS5720L/M
VREF_N
PGND
GND
VCOM
VREG GVDD
7.3 Feature Description
7.3.1 Adjustable I2C Address
The TAS5720L/M device has two address pins, which allow up to 8 I2C addressable devices to share a common
TDM bus. 表 2 lists each I2C Device ID setting.
注
The I2C Device ID is the 7 most significant bits of the 8-bit address transaction on the bus
(with the read/write bit being the least significant bit). For example, a Device ID of 0x6C
would be read as 0xD8 when the read/write bit is 0.
表 2. I2C Device Identifier (ID) Generation
DEFAULT TDM
ADR1
ADR0
I2C_DEV_ID
SLOT
Short to GND
22-kΩ to GND
22-kΩ to DVDD
Short to DVDD
Short to GND
22-kΩ to GND
22-kΩ to DVDD
Short to DVDD
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0
1
2
3
4
5
6
7
Short to GND
22-kΩ to GND
20
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Use a 22-kΩ resistor with a 5% (or better) tolerance to operate as a pull-up or pull-down resistor. By default, the
device uses the TDM time slot equal to the offset from the base I2C Device ID (see 表 2). The TDM slot can also
be manually configured by setting the TDM_CFG_SRC bit high (bit 6, reg 0x02) and programming the
TDM_SLOT_SELECT[2:0] bits to the desired slot (bits 0-2, reg 0x03).
For 2-channel, I2S operation, TDM slots 0 and 1 correspond to right and left channels respectively. For left and
right justified formats, TDM slots 0 and 1 correspond to left and right channels respectively.
7.3.2 I2C Interface
The TAS5720L/M device has a bidirectional I2C interface that is compatible with the Inter-Integrated Circuit (I2C)
bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This slave-only device does not
support a multimaster bus environment or wait-state insertion. The control interface is used to program the
registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock (SCL) is "HIGH" to indicate start and stop
conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal
data-bit transitions must occur within the low time of the clock period. The conditions are shown in 图 39. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5720L/M device holds SDA "LOW" during the
acknowledge clock period to indicate an acknowledgment. When this hold occurs, the master transmits the next
byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND
connection. An external pull-up resistor must be used for the SDA and SCL signals to set the "HIGH" level for the
bus.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
图 39. Typical I2C Timing Sequence
Any number of bytes can be transmitted between start and stop conditions. When the last word transfers, the
master generates a stop condition to release the bus. A generic data transfer sequence is shown in 图 39.
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7.3.2.1 Writing to the I2C Interface
As shown 图 40, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C bit and the read/write bit. The read/write bit determines the direction of the data transfer. For
a data-write transfer, the read/write bit is a 0. After receiving the correct I2C bit and the read/write bit, the
TAS5720L/M device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the TAS5720L/M device register being accessed. After receiving the address byte, the
TAS5720L/M device again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5720L/M device again
responds with an acknowledge bit. Lastly, the master device transmits a stop condition to complete the single-
byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-01
图 40. Single Byte Write Transfer Timing
A multi-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are
transmitted as shown in 图 41. After receiving each data byte, the TAS5720L/M device responds with an
acknowledge bit. Sequential data bytes are written to sequential addresses.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
图 41. Multi-Byte Write Transfer Timing
22
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7.3.2.2 Reading from the I2C Interface
As shown in 图 41, a data-read transfer begins with the master device transmitting a start condition, followed by
the I2 device address and the read/write bit. For the data read transfer, both a write followed by a read are
actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result,
the read/write bit becomes a 0. After receiving the TAS5720L/M device address and the read/write bit,
TAS5720L/M device responds with an acknowledge bit. In addition, after sending the internal memory address
byte or bytes, the master device transmits another start condition followed by the TAS5720L/M device address
and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving
the address and the read/write bit, the TAS5720L/M device again responds with an acknowledge bit. Next, the
TAS5720L/M device transmits the data byte from the register being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the data-read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
图 42. Single Byte Read Transfer Timing
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5720L/M to the master device as shown 图 43. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
图 43. Multi-Byte Read Transfer Timing
7.3.3 Serial Audio Interface (SAIF)
The TAS5720L/M device SAIF supports a variety of standard stereo serial audio formats including I2S, left-
justifiedand Right Justified. The device also supports a time division multiplexed (TDM) format that is capable of
transporting up to 8 channels of audio data on a single bus. LRCLK and SDIN are sampled on the rising edge of
BCLK.
For the stereo formats (I2S, left-justified and right-justified), the TAS5720L/M device supports BCLK to LRCLK
ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be tied directly to BCLK. Otherwise MCLK
must be driven externally. The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of
MCLK is 25MHz or less.
For TDM operation, the TAS5720L/M device supports 4 or 8 channels for single speed (44.1/48 kHz) and double
speed (88.2/96 kHz) sample rates. Each channel occupies a 32-bit time slot, therefore valid BCLK to LRCLK
ratios are 128 and 256. MCLK can be tied to BCLK for all TDM modes or driven externally. If MCLK is driven
externally, the MCLK to LRCLK ratio should be 64, 128, 256 or 512 and MCLK should be no faster than 25MHz.
The TAS5720L/M device selects the channel for playback based on either the I2C base address offset or based
on a dedicated time slot selection register. See the Adjustable I2C Address section for more information.
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7.3.3.1 Stereo I2S Format Timing
图 44 illustrates the timing of the stereo I2S format with 64 BCLKs per LRCLK. Two’s complement data is
transmitted MSB to LSB with the left channel word beginning one BCLK after the falling edge of LRCLK and the
right channel beginning one BCLK after the rising edge of LRCLK. Because data is MSB aligned to the beginning
of word transmission, data precision does not be configured. Set the SAIF_FORMAT[2:0] register bits to I2S
(register 0x02, bits 2:0=3’b100).
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Right Channel
Left Channel
BCLK
BCLK
MSB
24-Bit Mode
SDIN
LSB
MSB
LSB
23 22
9
5
1
8
4
0
5
1
4
1
0
23 22
19 18
15 14
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
0
16-Bit Mode
15 14
A. Data presented in two's-complement form with most significant bit (MSB) first.
图 44. I2S 64-fSW Format
24
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7.3.3.2 Stereo Left-Justified Format Timing
The stereo left justified format is very similar to the I2S format timing, except the data word begins transmission
at the same cycle that LRCLK toggles (when it is shifted by one bit from I2S). The phase of LRCLK is also
opposite of I2S. The left channel begins transmission when LRCLK transitions from low to high and the right
channel begins transmission when LRCLK transitions from high-to-low. Set the SAIF_FORMAT[2:0] register bits
to left-justified (register 0x02, bits 2:0=3’b101).The timing is illustrated in 图 45.
32 Clks
32 Clks
LRCLK
Right Channel
Left Channel
BCLK
BCLK
MSB
24-Bit Mode
SDIN
LSB MSB
23 22
LSB
23 22
9
5
1
8
4
0
5
1
4
0
1
9
5
1
8
4
0
5
1
4
0
1
0
0
20-Bit Mode
19 18
19 18
15 14
16-Bit Mode
15 14
A. Data presented in two's-complement form with most significant bit (MSB) first.
图 45. Left-Justified 64-fSW Format
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7.3.3.3 Stereo Right-Justified Format Timing
The stereo right justified format aligns the LSB of left channel data to the high to low transition of LRCLK and the
LSB of the right channel data to the low to high transition of LRCLK. To insure data is received correctly, the
SAIF must be configured for the proper data precision. The TAS5720L/M supports 16, 18, 20 and 24-bit data
precision in right justified format. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the
appropriate right-justifiedsetting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-
bit and 3’b011 for 16-bit). The timing is illustrated in 图 46.
32 Clks
32 Clks
LRCLK
Right Channel
Left Channel
BCLK
MSB
BCLK
LSB MSB
LSB
0
24-Bit Mode
SDIN
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
0
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
20-Bit Mode
16-Bit Mode
0
0
0
0
图 46. Right-Justified 64-fSW Format
26
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7.3.3.4 TDM Format Timing
A TDM frame begins with the low to high transition of LRCLK. As long as LRCLK is high for at least one BCLK
period and low for one BCLK period, duty cycle is irrelevent. The SAIF automatically detects the number of time
slots as long as valid BCLK to LRCLK ratios are utilized (see Serial Audio Interface (SAIF)).
For I2S aligned TDM operation (when time slot 0 begins one clock cycle after the low to high transition of LRCLK,
set SAIF_FORMAT[2:0] register bits to I2S (register 0x02, bits 2:0=3’b100). Data is MSB aligned within the 32-bit
time slots, therefore data precision is not required to be configured. The TDM format timing is illustrated in 图 47.
BCLK
LRCLK
Slot N
LSB
Slot 0
MSB
Slot 0
MSB-1
Slot 0
LSB
Slot 1
MSB
Slot 1
MSB-1
Slot 1
MSB-2
Slot N-1
LSB
Slot N
MSB
Slot N
MSB-1
Slot N
MSB-2
Slot N
LSB+1
SDIN
图 47. TDM I2S Format
For left-justifiedTDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high),
SAIF_FORMAT[2:0] register bits to left-justified(register 0x02, bits 2:0=3’b101). As with I2S, data is MSB aligned.
The timing is illustrated in 图 48.
BCLK
LRCLK
Slot 0
MSB
Slot 0
MSB-1
Slot 0
MSB-2
Slot 0
LSB
Slot 1
MSB
Slot 1
MSB-1
Slot 1
MSB-2
Slot N-1
LSB
Slot N
MSB
Slot N
MSB-1
Slot N
MSB-2
Slot N
LSB
SDIN
图 48. TDM Left- and Right-Justified Format
For right-justified TDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), data is
LSB aligned to the 32-bit time slot. As with stereo right-justified formats, the TAS5720L/M must have the data
precision configured. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-
justified setting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011 for
16-bit). The timing shown in 图 48 is the same as left-justified TDM, with the data LSB aligned.
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7.3.4 Audio Signal Path
图 49 illustrates the audio signal flow from the TDM SAIF to the speaker.
Digital
Volume
Control
œ100 dB
to 24 dB
0.5 dB Steps
SDIN
LRCLK
BCLK
¯D
DAC
Class-D
Amplifier
TDM
SAIF
HPF
œ3 dB
at
Interpolation
Filter
Digital
Clipper
4 Hz
MCLK
19.2 dBV | 20.7 dBV | 23.5 dBV | 26.3 dBV
图 49. Audio Signal Path
7.3.4.1 High-Pass Filter (HPF)
Excessive DC in audio content can damage loudspeakers, therefore the amplifier employs a DC detect circuit
that shutdowns the power stage and issue a latching fault if this condition occurs. A high-pass filter is provided in
the TAS5720L/M device to remove DC from incoming audio data to prevent this from occurring. 表 3 shows the
high-pass, –3 dB corner frequencies for each sample rate. The filter can be bypassed by writing a 1 into bit 7 of
register 0x02.
表 3. High-Pass Filter –3 dB Corner Frequencies by
Sample Rate
SAMPLE
-3dB CORNER
RATE (kHZ)
FREQUENCY (Hz)
44.1
48.0
88.2
96.0
3.675
4.000
7.350
8.000
7.3.4.2 Amplifier Analog Gain and Digital Volume Control
The gain from TDM SAIF to speaker is controlled by setting the amplifier’s analog gain and digital volume
control. Amplifier analog gain settings are presented as the output level in dBV (dB relative to 1 Vrms) with a full
scale serial audio input (0 dBFS) and the digital volume control set to 0 dB. These levels might not be achievable
because of analog clipping in the amplifier, therefore they should be used to convey gain only.
表 4 outlines each gain setting expressed in dBV and VPK
.
表 4. Amplifier Gain Settings
FULL SCALE OUTPUT
ANALOG_GAIN {1:0}
SETTING
dBV
VPEAK
12.9
15.3
21.2
29.2
00
01
10
11
19.2
20.7
23.5
26.3
公式 1 calculates the amplifiers output voltage.
6°≠∞ = )Æ∞µ¥ + !§∂£ + !°≠∞ §"6
where
•
•
•
•
VAMP is the amplifier output voltage in dBV
Input is the digital input amplitude in dB with respect to 0 dBFS
ADVC is the digital volume control setting, –100 dB to 24dB in 0.5-dB steps
AAMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV
(1)
Clipping in the digital domain occurs if the input level (in dB relative to 0 dBFS) plus the digital volume control
setting (in dB) are greater than 0 dB. The signal path has approximately 0.5 dB of headroom, but TI does not
recommend utilizing it.
28
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The digital volume control can be adjusted from –100 dB to 24 dB in 0.5-dB steps. 公式 2 calculates the 8-bit
volume control register setting at address 0x04.
!
§∂£
$6#∂°¨µ• = 0∏#& +
(2)
For example, digital volume settings of 0 dB, 24 dB and –100 dB map to 0xCF, 0xFF and 0x07 respectively.
Values below 0x07 are equivalent to mute (the amplifier continues to switch with no audio).When a change in
digital volume control occurs, the device ramps the volume to the new setting in 0.5 dB steps after every 8 audio
samples to ensure smooth transitions in volume.
The Class-D amplifier uses a closed-loop architecture, therefore the gain does not depend on the supply input
(VPVDD). The approximate threshold for the onset of analog clipping is calculated in 公式 3.
2ꢀ
60+(≠°∏ ,∞≤•£¨©∞ ) = 606$$
F
G 6
ꢁ × 2$3(ØÆ) ꢂ 2©Æ¥•≤£ØÆÆ•£¥ ꢂ 2ꢀ
where
•
•
•
•
•
VPK(max,preclip) is the maximum peak unclipped output voltage in V
VPVDD is the power supply voltage
RL is the speaker load in Ω
Rinterconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
RDS(on) is the power stage total on resistance (FET+bonding+packaging) in Ω
(3)
The effective on-resistance for this device (including FETs, bonding and packaging leads) is approximately 150
mΩ at room temperature and increasex by approximately 1.6 times over 100°C rise in temperature.表 5 shows
approximate maximum unclipped peak output voltages at room temperature (excluding interconnect resistances).
表 5. Approximate Maximum Unclipped Peak Output
Voltage at Room Temperature
MAXIMUM UNCLIPPED
PEAK VOLTAGE
VPK (V)
SUPPLY VOLTAGE
VPVDD (V)
RL = 4 Ω
RL = 8 Ω
11.57
12
17
11.16
15.81
16.39
7.3.4.3 Digital Clipper
The digital clipper hard limits the maximum DAC sample value, which provides a simple hardware mechanism to
control the largest signal applied to the speaker. Because this block resides in the digital domain, the actual
maximum output voltage also depends on the amplifier gain setting and the supply voltage (VPVDD) limited
amplifier voltage swing (For example, analog clipping can occur before digital clipping).
The maximum amplifier output voltage (excluding limitation due to swing) is calculated in 公式 4.
$#¨•∂•¨
6!-0 ≠°∏ ,§£ = 2ꢀ × ¨Øß l
p + ꢀ.5 + !!-0
:
;
1ꢀ
where
•
•
•
VAMP(max,dc) is the amplifier maximum output voltage in dBV
DClevel is the digital clipper level
AAMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV
(4)
Configure the digital clipper by writing the 20-bit DClevel to registers 0x01, 0x10 and 0x11. Set the DClevel to
0xFFFFF effectively bypasses the digital clipper.
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7.3.4.4 Class-D Amplifier Settings
The PWM switching rate of the Class-D amplifier is a phase locked multiple of the input audio sample rate. 表 6
lists the PWM switching rate settings as programmed in bit 4 through bit 6 in register 0x06. The double-speed
sample rates (for example 88.2kHz, 96kHz) have the same PWM switching frequencies as their equivalent
single-speed sample rates.
表 6. PWM Switching Rates
SINGLE-SPEED
PWM RATE (× fLRCLK
DOUBLE-SPEED
PWM RATE × fLRCLK)
44.1 kHz, 88.2 kHz
fPWM(kHz)
48 kHz, 96 kHz
fPWM(kHz)
PWM_RATE[2:0]
)
000
001
010
011
100
101
110
111
6
3
4
264.6
352.8
441
288
384
480
576
672
768
960
1152
8
10
12
14
16
20
24
5
6
529.2
617.4
705.6
882
7
8
10
12
1058.4
The Class-D power stage Over Current detector issues a latching fault if the load current exceeds the safe limit
for the device. The threshold can be proportionately adjusted if desired by programming bits 4-5 of register 0x08.
表 7 shows the relative setting for each Over Current setting.
表 7. Over Current Threshold Settings
OC_THRESH
[1:0]
OVERCURRENT
THRESHOLD (%)
00
01
10
11
100
75
50
25
30
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7.4 Device Functional Modes
This section describes the modes of operation for the TAS5720L/M device.
表 8. Typical Current Consumption(1)
INPUT
VOLTAGE
VPVDD (V)
PWM
FREQUENCY
fPWM (kHz)
INPUT
CURRENT
IDVDD (mA)
IPVDD+IAVDD
MODE
(mA)
384
768
—
14.5
18.4
9.0
Idle and Mute
4.1
7.2
12
15
19
24
Sleep
1.32
Shutdown
—
0.039
17.4
21.3
9.0
0.077
384
768
—
Idle and Mute
4.1
Sleep
1.32
Shutdown
—
0.045
19.4
22.9
9.1
0.077
384
768
—
Idle and Mute
4.1
Sleep
1.32
Shutdown
—
0.049
22.4
24.8
9.3
0.077
384
768
—
Idle and Mute
4.1
Sleep
1.32
Shutdown
—
0.054
26.2
26.9
9.4
0.077
384
768
—
Idle and Mute
4.1
Sleep
1.32
Shutdown
—
0.061
0.077
(1) TA = 25ºC, PVDD pin tied to AVDD pin, VDVDD = 3.3 V, RLOAD = 4Ω, fIN = Idle, fS = 48 kHz, Gain =
20.7 dBV
7.4.1 Shutdown Mode (SDZ)
The device enters shutdown mode if either the SDZ pin is asserted low or the I2C SDZ register bit is set low (bit
0, reg 0x01). In shutdown mode, the device consumes the minimum quiescent current with most analog and
digital blocks powered down. The Class-D amplifier power stage powers down and the output pins are in a Hi-Z
state. I2C communication remains possible in shutdown mode and register bits states are retained.
If a latching fault condition has occurred (over temperature, Over Current or DC detect), the SDZ pin or I2C bit
must toggle low before the fault register can be cleared. For more information on faults and recovery, see the
Faults and Status section.
When the device exits shutdown mode (by releasing both the SDZ pin high and setting the I2C SDZ register bit
high), the device powers up the internal analog and digital blocks required for operation. If the I2C SLEEP bit is
set low (bit 1, reg 0x01), the device powers up the Class-D amplifier and begins the switching of the power
stage. If the I2C MUTE bit is set low (bit 4, reg 0x03), the device ramps up the volume to the current setting and
begins playing audio.
If shutdown mode is asserted while audio is playing, the device ramps down the volume on the audio, stops the
Class-D switching, puts the Class-D power stage output pins in a Hi-Z state and powers down the analog and
digital blocks.
7.4.2 Sleep Mode
Sleep mode is similar to shutdown mode, except analog and digital blocks required to begin playing audio quickly
are left powered up. Sleep mode operates as a hard mute where the Class-D amplifier stops switching, but the
device does not power down completely. Entering sleep mode does not clear latching faults.
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7.4.3 Active Mode
If shutdown mode and sleep mode are not asserted, the device is in active mode. During active mode, audio
playback is enabled.
7.4.4 Mute Mode
When the I2C_MUTE bit is set high (bit 4, reg 0x03) and the device is in active mode, the volume is ramped
down and the Class-D amplifier continues to operate with an idle audio input.
7.4.5 Faults and Status
During the power-up sequence, the power-on-reset circuit (POR) monitoring the DVDD pin domain releases all
registers from reset (including the I2C registers) once DVDD is valid. The device does not exit shutdown mode
until the PVDD pin has a valid voltage between the undervoltage lockout (UVLO) and overvoltage lockout
(OVLO) thresholds. If DVDD drops below the POR threshold the device transitions into shutdown mode with all
registers held in reset. If UVLO or OVLO thresholds are violated by the PVDD pin thresholds, the device
transitions into shutdown mode, but registers are not be forced into reset. Both of the conditions are non-latching
and the device operates normally once supply voltages are valid again. The device can be reset only by reducing
DVDD below the POR threshold.
The device transitions into sleep mode if it detects any faults with the SAIF clocks such as
•
•
•
Invalid MCLK to LRCLK and BCLK to LRCLK ratios
Invalid MCLK and LRCLK switching rates
Halting of MCLK, BCLK or LRCLK switching
Upon detection of a SAIF clock error, the device transitions into sleep mode as quickly as possible to limit the
possibility of audio artifacts. Once all SAIF clock errors are resolved, the device will volume ramp back to the
previous playback state. During a SAIF clock error, the FAULTZ pin will be asserted low and the CLKE bit will be
asserted high (register 0x08, bit 3).
While operating in shutdown mode, the SAIF clock error detect circuitry powers down and the CLKE bit reads
high. This reading is not an indication of a SAIF clock error. If the device has not entered active mode after a
power-up sequence or after transitioning out of shutdown mode, the FAULTZ pin pulses low for only
approximately 10 µs every 350 µs. This action prevents a possible locking condition if the FAULTZ is connected
to the SDZ pin to accomplish automatic recovery. Once the device has entered active mode one time (after
power up or deassertion of shutdown mode), the SAIF clock errors pull the FAULTZ pin low continuously until the
fault has cleared.
The device also monitors die temperature, power stage load current and amplifier output DC content and issues
latching faults if any of the conditions occur. A die temperature of approximately 150°C causes the device to
enter sleep mode and issue an Over-temperature error (OTE) readable via I2C (bit 0, reg 0x08).
Sustained excessive DC content at the output of the Class-D amplifier can damage loudspeakers via voice coil
heating. The amplifier has an internal circuit to detect significant DC content that forces the device into sleep
mode. The device issues a DC detect error (DCE) readable via I2C (bit 1, reg 0x08).
If the Class-D amplifier load current exceeds the threshold set by the OC_THRESH register bits (bits 5-4, reg
0x08), the device enters sleep mode and issues an Over Current Error (OCE) that is readable via I2C (bit 2, reg
0x08).
During OTE, DCE and OCE, the FAULTZ pin asserts low until the latched fault is cleared. FAULTZ is an open
drain pin and requires a pull-up resistor to the DVDD pin.
Latched faults can be cleared only by toggling the SDZ pin or SDZ I2C bit (bit 0, reg 0x01). This toggle does not
clear I2C registers (except the fault status of OTE, OCE and DCE). If the device is intended to attempt automatic
recovery after latching faults, implement a circuit like the one shown in 图 50. The device waits approximately
650 ms after a DCE fault has cleared and 1.3 s after an OTE or OCE fault has cleared before releasing FAULTZ
high and allowing the device to enter active mode.
32
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DVDD
10 kΩ
TAS5720L
SDZ
Signal from Host
FAULTZ
Open-drain driver
or
N-channel FET
图 50. Auto Recovery Circuit
7.5 Register Maps
When writing to registers with reserved bits, maintain the values shown in 表 9 to ensure proper device
operation. Default register values are loaded during the power-up sequence or any time the DVDD voltage falls
below the power-on-reset (POR) threshold and then returns to valid operation.
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表 9. I2C Register Map Summary
REGISTER BITS
ADDR
(Dec)
ADDR
(Hex)
REGISTER
NAME
DEFAULT
(Hex)
B7
0
B6
0
B5
B4
B3
B2
0
B1
B0
DEVICE_ID
0
1
0x00
0x01
0x02
0x03
0x04
0x06
0x08
0x10
0x11
Device ID
0x01
0xFD
0x04
0x80
0xCF
0x55
0x00
0xFF
0xFC
0
0
0
0
1
SDZ
1
DIGITAL_CLIP_LEVEL [19:14]
SLEEP
Power Control
Digital Control 1
Digital Control 2
Volume Control
Analog Control
1
1
1
0
0
1
1
SSZ/DS
0
1
0
HPF_BYPASS TDM_CFG_SRC
RSV
SAIF_FORMAT
2
0
0
RSV
0
0
MUTE
0
1
0
0
0
1
RSV
0
TDM_SLOT_SELECT
0
3
1
0
VOLUME_CONTROL
4
1
RSV
0
1
1
0
1
1
0
PWM_RATE
0
0
1
0
1
1
1
RSV
0
ANALOG_GAIN
6
0
CLKE
0
1
OCE
0
1
OTE
0
RSV
OC_THRESH
DCE
0
Fault Config and
Error Status
8
0
1
1
0
1
DIGITAL_CLIP_LEVEL[13:6]
16
17
Digital Clipper 2
Digital Clipper 1
1
1
1
1
1
1
0
DIGITAL_CLIP_LEVEL[5:0]
RSV
0
1
1
1
34
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7.5.1 Device Identification
图 51. Device Identification, Address: 0x000
7
6
5
4
3
2
1
0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. Device Identification, Address: 0x000
Bit
7
Field
Type
Reset
Description
0
0
0
0
0
0
0
1
6
5
4
DEVICE_ID[7:0]
R
This register returns a value of 0x01 when read.
3
2
1
0
7.5.2 Power Control Register
表 11. Power Control Register, Address: 0x001
7
6
5
4
3
2
1
0
DIGITAL_CLIP_LEVEL
R/W
SLEEP
R/W
SDZ
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. Power Control Register, Address: 0x001
Bit
7
Field
Type
Reset
Description
1
1
1
1
1
1
6
This register holds the top 6-bits of the 20-bit Digital Clipper
level. The Digital Clipper limits the magnitude of the sample
applied to the DAC. See the Digital Clipper section for more
information.
5
DIGITAL_CLIP_LEVEL[19:14]
R/W
4
3
2
When the device enters SLEEP mode, volume ramps down and
the Class-D output stage powers down to a Hi-Z state. The rest
of the blocks will be kept in a state such that audio playback can
be restarted as quickly as possible. This mode has lower
dissipation than MUTE, but higher than SHUTDOWN. For more
information see the Device Functional Modes section.
0: Exit Sleep (default)
1
0
SLEEP
R/W
R/W
0
1
1: Enter Sleep
The device enters SHUTDOWN mode if either this bit is set to a
0 or the SDZ pin is pulled low externally. In SHUTDOWN, the
device holds the lowest dissipation state. I2C communication
remains functional and all registers are retained. For more
information see the Device Functional Modes section.
0: Enter SHUTDOWN
SDZ
1: Exit SHUTDOWN (default)
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7.5.3 Digital Control Register 1
表 13. Digital Control Register 1, Address: 0x002
7
6
5
4
3
2
1
0
HPF_BYPASS TDM_CFG_SR
C
RSV
R/W
SSZ/DS
SAIF_FORMAT
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. Digital Control Register 1, Address: 0x002
Bit
Field
Type
Reset
Description
The high-pass filter removes any DC component in the audio
content that could trip the DC detect protection feature in the
amplifer, which is a latching fault. Setting this bit bypasses the
high-pass filter. See the High-Pass Filter (HPF) section for more
information.
7
HPF_BYPASS
R/W
0
0:Enable high-pass filter (default)
1: Bypass high-pass filter
This bit determines how the device selects which audio channel
direct to the playback stream. See the Serial Audio Interface
(SAIF) section for more information.
6
TDM_CFG_SRC
RSV[1:0]
R/W
0
0:Set TDM Channel to I2C Device ID (default).
1:Set TDM Channel to TDM_SLOT_SELECT in register 0x03.
5
4
R/W
R/W
0
0
These bits are reserved and should be set to 00 when writing to
this register.
This bit sets the sample rate to single speed or double speed
operation. See the Serial Audio Interface (SAIF) section for more
information.
0: Single speed operation (44.1 kHz/48 kHz) - default.
1: Double speed operation (88.2 kHz/96 kHz)
3
2
SSZ/DS
R/W
R/W
0
1
These bits set the Serial Audio Interface format. See the Serial
Audio Interface (SAIF) section for more information.
000: Right justified, 24-bit
001: Right justified, 20-bit
010: Right justified, 18-bit
011: Right justified, 16-bit
100: I2S (default)
SAIF_FORMAT[2:0]
1
0
R/W
R/W
0
0
101: Left Justified, 16-24 bits
110: Reserved. Do not select this value.
111: Reserved. Do not select this value.
36
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7.5.4 Digital Control Register 2
表 15. Digital Control Register 2, Address: 0x003
7
6
5
4
3
2
1
TDM_SLOT_SELECT
R/W
0
RSV
R/W
MUTE
R/W
RSV
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. Digital Control Register 2, Address: 0x003
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
1
0
0
These bits are reserved and should be set to 100 when this
register is written to
6
RSV[2:0]
5
When set the device ramps down volume and play idle audio.
See the Amplifier Analog Gain and Digital Volume Control
section for more information.
4
MUTE
R/W
0
0: Exit mute mode (default)
1: Enter mute mode
This bit is reserved and should be set to 0 when writing to this
register.
3
RSV
R/W
0
2
1
0
R/W
R/W
R/W
0
0
0
When the TDM_CFG_SRC bit is set to 1 in register 0x02, these
bits select which TDM channel is directed to audio playback.
See the Serial Audio Interface (SAIF) section for more
information
TDM_SLOT_SELECT[2:0]
7.5.5 Volume Control Register
表 17. Volume Control Register, Address: 0x004
7
6
5
4
3
2
1
0
VOLUME_CONTROL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. Volume Control Register, Address: 0x004
Bit
Field
Type
Reset
Description
This register sets the Digital Volume Control, which ranges from
-100 dB to +24 dB in 0.5 dB steps. Register settings of less than
0x07 are equivalent to setting the Mute bit in register 0x03. See
the Amplifier Analog Gain and Digital Volume Control section for
more information.
7
R/W
1
0xFF: +24.0 dB
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
1
1
0xFE: +23.5 dB
...
VOLUME_CONTROL[7:0]
0xCF: 0 dB (default)
...
0x08: –99.5 dB
0x07: –100 dB
< 0x07: MUTE
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7.5.6 Analog Control Register
表 19. Analog Control Register, Address: 0x006
7
6
5
4
3
2
1
0
RSV
R/W
PWM_RATE
R/W
ANALOG_GAIN
R/W
RSV
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. Analog Control Register, Address: 0x006
Bit
Field
Type
Reset
Description
This bit is reserved and should be set to a 0 when this register is
written to.
7
RSV
R/W
0
These bits set the PWM switching rate, which is a locked ratio of
LRCLK. For more information see the Class-D Amplifier Settings
section.
000: 6 × LRCLK (single speed), 3 × LRCLK (double speed)
001: 8 × LRCLK (single speed), 4 × LRCLK (double speed)
6
5
R/W
1
010: 10 × LRCLK (single speed), 5 × LRCLK (double speed)
011: 12 × LRCLK (single speed), 6 × LRCLK (double speed)
100: 14 × LRCLK (single speed), 7 × LRCLK (double speed)
PWM_RATE[2:0]
R/W
R/W
0
1
101: 16 × LRCLK (single speed), 8 × LRCLK (double speed) -
default
110: 20 × LRCLK (single speed), 10 × LRCLK (double speed)
111: 24 × LRCLK (single speed), 12 × LRCLK (double speed)
4
Sets the analog gain of the Class-D amplifer. The values shown
indicate the output level with digital volume control set to 0 dB
and a full scale digital input (0 dBFS). This level might not be
acheivable because of analog clipping. See the Amplifier Analog
Gain and Digital Volume Control section for more information.
00: 19.2 dBV
3
2
R/W
R/W
0
1
ANALOG_GAIN[1:0]
01: 20.7 dBV (default)
10: 23.5 dBV
11: 26.3 dBV
1
0
R/W
R/W
0
1
These bits are reserved and should be set to 01 when writing to
this register
RSV[1:0]
38
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7.5.7 Fault Configuration and Error Status Register
表 21. Fault Configuration and Error Status Register, Address: 0x008
7
6
5
4
3
CLKE
R
2
OCE
R
1
DCE
R
0
OTE
R
RSV
R/W
OC_THRESH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. Fault Configuration and Error Status Register, Address: 0x008
Bit
7
Field
Type
R/W
R/W
Reset
Description
0
0
This bit is reserved and should be set to a 00 when this register
is written to.
RSV[1:0]
6
This register sets the Over Current detector threshold. For more
information see the Class-D Amplifier Settings section.
00: 100% of Over Current limit (default)
5
4
3
R/W
R/W
R
0
1
0
OC_THRESH[1:0]
01: 75% of Over Current limit
10: 50% of Over Current limit
11: 25% of Over Current limit
This bit indicates the status of the SAIF clock error detector.
This is a self clearning value.
0: No SAIF clock errors.
CLKE
OCE
1: SAIF clock errors are present.
This bit indicates the status of the over current error detector.
This is a latching value
0: The Class-D output stage has not experienced an over
current event.
1: The Class-D output stage has experienced an over current
event.
2
1
0
R
R
R
0
0
0
This bit indicates the status of the DC detector. This is a latching
value.
0: The Class-D output stage has not experienced a DC detect
error.
1: The Class-D output stage has experienced a DC detect error.
DCE
OTE
This bit indicates the status of the over temperature detector.
This is a latching value.
0: The Class-D output stage has not experienced an over
temperature error.
1: The Class-D output stage has experienced an over
temperature error.
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7.5.8 Digital Clipper 2
表 23. Digital Clipper 2, Address: 0x010
7
6
5
4
3
2
1
0
DIGITAL_CLIP_LEVEL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. Digital Clipper 2, Address: 0x010
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
1
1
1
1
1
1
1
1
6
5
This register holds the bits 13 through 6 of the 20-bit Digital
Clipper level. The Digital Clipper limits the magnitude of the
sample applied to the DAC. See the Digital Clipper section for
more information.
4
DIGITAL_CLIP_LEVEL[13:6]
3
2
1
0
7.5.9 Digital Clipper 1
表 25. Digital Clipper 1, Address: 0x011
7
6
5
4
3
2
1
0
DIGITAL_CLIP_LEVEL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 26. Digital Clipper 1, Address: 0x011
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
1
1
1
1
1
1
0
0
6
This register holds the bits 5 through 0 of the 20-bit Digital
Clipper level. The Digital Clipper limits the magnitude of the
sample applied to the DAC. See the Digital Clipper section for
more information.
5
DIGITAL_CLIP_LEVEL[5:0]
4
3
2
1
These bits are reserved and should be set to 00 when writing to
this register.
RSV[1:0]
0
40
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8 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a filter-free,TDM application.
8.2 Typical Application
PVDD
4.5 V to 26.4 V
1 µF
1 µF
1 µF
0.1 µF
220 nF
100 µF
3.3 V
OUT_P
VREF_N
100 kΩ
Control and
Status
BST_P
PGND
PGND
PGND
PGND
BST_N
OUT_N
FAULTZ
SDZ
TAS5720x
LRCLK
MCLK
BCLK
TDM Master
220 nF
SDIN
SCL
3.3 V
3.3 V
2.5 kΩ
2.5 kΩ
I2C Master
3.3 V
PVDD
1 µF
0.1 µF
100 µF
图 52. Filter Free 3-Wire TDM Application Circuit (I2C_DEV_ID = 0x6C)
8.2.1 Design Requirements
•
•
•
•
Input voltage range PVDD and AVDD: 4.5 V to 26.4 V
Input voltage range DVDD: 3.3 V to 3.6 V
Input sample rate: 44.1 kHz to 48 kHz or 88.2 kHz to 96 kHz
I2C clock frequency: up tp 400 kHz
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Typical Application (接下页)
8.2.2 Design Procedure
8.2.2.1 Overview
The TAS5720L/M is a flexible and easy to use Class D amplifier; therefore the design process is straightforward.
Before beginning the design, gather the following information regarding the audio system.
•
•
•
•
•
PVDD rail planned for the design
Speaker or load impedance
Audio sample rate
Maximum output power requirement
Desired PWM frequency
8.2.2.2 Select the PWM Frequency
Set the PWM frequency by writing to the PWM_RATE bits (bits 6-4, reg 0x06). The default setting for this register
is 101, which is 16 × LRCLK for single speed applications and 8 × LRCLK for double speed application. This
value equates to a default PWM frequency of 768 kHz for a 48 Hz sample rate.
8.2.2.3 Select the Amplifier Gain and Digital Volume Control
To select the amplifier gain setting, the designer must determine the maximum power target and the speaker
impedance. Once the parameters have been determined, calculate the required output voltage swing which
delivers the maximum output power.
Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the
required output swing for maximum power. The analog gain can be set by writing to the ANALOG_GAIN bits (bits
3-2, reg 0x06). The default gain setting is 20.7 dBV referenced to 0dBFS input.
8.2.2.4 Select Input Capacitance
Select the bulk capacitors at the PVDD inputs for proper voltage margin and adequate capacitance to support the
power requirements. The TAS5720L/M has very good PVDD PSRR, so the capacitor is more about limiting the
ripple and droop for the rest of system than preserving good audio performance. The amount of bulk decoupling
can be reduced as long as the droop and ripple is acceptable. One capacitor should be placed near the PVDD
inputs at each side of the device. PVDD capacitors should be a low ESR type because they are being used in a
high-speed switching application.
8.2.2.5 Select Decoupling Capacitors
Good quality decoupling capacitors should be added at each of the PVDD inputs to provide good reliability, good
audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, the decoupling capacitors should be located near the PVDD and GND connections to the device to
minimize series inductances.
8.2.2.6 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.22-µF, 25-V capacitors of X5R quality or better.
42
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Typical Application (接下页)
8.2.3 Application Curves
10
10
1
Rspk = 4 W
Rspk = 8 W
Rspk = 4 W
Rspk = 8 W
1
0.1
0.1
0.01
0.01
0.01
0.1
1
10
30
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
D016
D020
V(PVDD) = 15 V
f(PWM) = 384 kHz
V(PVDD) = 24 V
f(PWM) = 384 kHz
图 53. THD+N vs. Output Power
图 54. THD+N vs. Output Power
9 Power Supply Recommendations
The power supply requirements for the TAS5720L/M device consist of one 3.3-V supply to power the low-voltage
analog and digital circuitry and one higher-voltage supply to power the output stage of the speaker amplifier.
Several on-chip regulators are included on the TAS5720L/M device to generate the voltages necessary for the
internal circuitry of the audio path. The voltage regulators which have been integrated are sized only to provide
the current necessary to power the internal circuitry. The external pins are provided only as a connection point
for off-chip bypass capacitors to filter the supply. Connecting external circuitry to the regulator outputs can result
in reduced performance and damage to the device.
The TAS5720L/M requires two power supplies. A 3.3-V supply, called DVDD, is required to power the digital
section of the chip. A higher-voltage supply, between 4.5 V and 26.4 V, supplies the analog circuitry (AVDD) and
the power stage (PVDD). The AVDD supply feeds several LDOs including GVDD, VREG, and VCOM. The LDO
outputs are connected to external pins for filtering purposes, but should not be connected to external circuits. The
LDO outputs have been sized to provide current necessary for internal functions but not for external loading.
10 Layout
10.1 Layout Guidelines
•
Pay special attention to the power stage power supply layout. Each H-bridge has two PVDD input pins so that
decoupling capacitors can be placed nearby. Use at least a 0.1-µF capacitor of X5R quality or better for each
set of inputs.
•
•
Keep the current circulating loops containing the supply decoupling capacitors, the H-bridges in the device
and the connections to the speakers as tight as possible to reduce emissions.
Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. The area directly under the device should be treated as a central ground area for the
device, and all device grounds must be connected directly to that area.
•
•
Use a via pattern to connect the area directly under the device to the ground planes in copper layers below
the surface. This connection helps to dissipate heat from the device.
Avoid interrupting the ground plane with circular traces around the device. Interruption disconnects the copper
and interrupt flow of heat and current. Radial copper traces are better to use if necessary.
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10.2 Layout Example
Connect top ground
to lower ground plane
with vias
Connect top power
connection to lower
supply layer with vias
Speaker Connector
OUT_P
BST_P
LRCLK
Serial
Audio
MCLK
BCLK
SDIN
Source
BST_N
OUT_N
Exposed Thermal
Pad Area
I2C
SCL
Control
SDA
图 55. TAS5720L Layout Example
44
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11 器件和文档支持
11.1 文档支持
11.1.1 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访
问。
表 27. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TAS5720L
TAS5720M
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5720LRSMR
TAS5720LRSMT
TAS5720MRSMR
TAS5720MRSMT
ACTIVE
VQFN
VQFN
VQFN
VQFN
RSM
32
32
32
32
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
-25 to 85
-25 to 85
TAS
5720L
ACTIVE
ACTIVE
ACTIVE
RSM
NIPDAU
NIPDAU
NIPDAU
TAS
5720L
RSM
TAS
5720M
RSM
TAS
5720M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5720LRSMR
TAS5720LRSMT
TAS5720MRSMR
TAS5720MRSMT
VQFN
VQFN
VQFN
VQFN
RSM
RSM
RSM
RSM
32
32
32
32
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS5720LRSMR
TAS5720LRSMT
TAS5720MRSMR
TAS5720MRSMT
VQFN
VQFN
VQFN
VQFN
RSM
RSM
RSM
RSM
32
32
32
32
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
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