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TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

TAS5733L - 具有 EQ 和 3 波段 AGL 且集成耳机放大器的数字输入音频

1 特性

2 应用

1

•

音频输入/输出

•

LCD TV、LED TV

低成本音频设备

–

单立体声串行音频输入

支持 44.1kHz 和 48kHz 采样速率 (LJ/RJ/I²S)

支持三线制 I²S 模式（无需 MCLK）

自动音频端口速率检测

3 说明

TAS5733L 器件是一款高效数字输入音频放大器，用

于驱动采用桥接负载 (BTL) 配置的立体声扬声器。对

于并行桥接负载 (PBTL)，该器件可将并行输出驱动为

单个低阻抗负载，从而产生更高功率。一个串行数据输

入可处理最多两个离散音频通道并能与大多数数字音频

处理器和 MPEG 解码器无缝整合。此器件可接受宽范

围的输入数据和数据传输速率。一个完全可编程数据路

径将这些通道路由至内部扬声器驱动器。

支持桥接负载 (BTL) 和并行桥接负载 (PBTL) 配

置

–

P_OUT= 10 W（总谐波失真 + 噪声 (THD+N) 为

10% 时）

–

PVDD = 12V、8Ω、1kHz

•

音频/脉宽调制 (PWM) 处理

–

独立通道音量控制，增益为静音到 24dB 增益

（步长为 0.125dB）

TAS5733L 器件仅用作从器件，以接收外部提供的所

有时钟。TAS5733L 器件采用开关频率介于 288kHz

和 384kHz 之间的 PWM 载波，具体取决于输入采样

率。与四阶噪声整形器结合的过采样可提供一个白噪音

基准以及 20Hz 至 20kHz 的出色动态范围。

–

可编程 3 波段自动增益限制 (AGL)

20 个可编程的 Biquad，适用于扬声器均衡

(EQ) 及其他音频处理特性

总体说明特性

–

104-dB 信噪比 (SNR)，A 加权，以满量程

(0dB) 为基准

器件信息⁽¹⁾

–

具有两个地址的 I²C 串行控制接口

热保护、短路保护和欠压保护

效率高达 90%

器件型号

TAS5733L

封装

封装尺寸（标称值）

HTSSOP (48)

12.50mm x 6.10mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

AD、BD 和三重调制

脉宽调制 (PWM) 电平计量

功率与 PVDD 间的关系

30

简化框图

AVDD

RL = 4 Ω

DVDD

PVDD

RL = 8 Ω

25

Power-On Reset

(POR)

Internal Voltage Supplies

Internal Regulation and Power Distribution

MCLK Monitoring

and Watchdog

Open Loop Stereo

Stereo PWM Amplifier

Digital to PWM

Converter

(DPC)

20

15

10

5

Sensing & Protection

Serial Audio Port

(SAP)

AMP_OUT_A

AMP_OUT_B

MCLK

LRCK

SCLK

SDIN

Digital Audio

Processor

(DAP)

Sample Rate

Converter

(SRC)

2 Ch. PWM

Modulator

Temperature

Short Circuits

PVDD Voltage

Output Current

Sample Rate

Auto-Detect

Noise Shaping

PLL

AMP_OUT_C

AMP_OUT_D

Click & Pop

Suppression

Fault Notification

Internal Register/State Machine Interface

I²C Control Port

0

8

9

10

11

12

13

14

15

SCL SDA DR_SD PDN

RST

PVDD (V)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASE77

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Audio Signal Processing Overview......................... 16

7.4 Feature Description................................................. 17

7.5 Device Functional Modes........................................ 19

7.6 Programming........................................................... 20

7.7 Register Maps......................................................... 31

Application and Implementation ........................ 49

8.1 Application Information............................................ 49

8.2 Typical Applications ............................................... 50

Power Supply Recommendations...................... 55

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Characteristics ............................................ 6

6.5 Electrical Characteristics........................................... 6

6.6 Speaker Amplifier Characteristics............................. 7

6.7 Protection Characteristics ......................................... 7

6.8 Master Clock Characteristics .................................... 7

6.9 I²C Interface Timing Requirements........................... 8

6.10 Serial Audio Port Timing Requirements.................. 8

6.11 Typical Characteristics - Stereo BTL Mode .......... 11

6.12 Typical Characteristics - Mono PBTL Mode ......... 13

Detailed Description ............................................ 15

8

9

10 Layout................................................................... 56

10.1 Layout Guidelines ................................................. 56

10.2 Layout Example .................................................... 57

11 器件和文档支持 ..................................................... 59

11.1 商标....................................................................... 59

11.2 静电放电警告......................................................... 59

11.3 Glossary................................................................ 59

12 机械、封装和可订购信息....................................... 60

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (March 2016) to Revision A

Page

•

已从“产品预览”改为“量产数据”版本。 ..................................................................................................................................... 1

2

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

5 Pin Configuration and Functions

DCA Package

48-Pin HTSSOP With PowerPAD™

Top View

BSTRP_B

AMP_OUT_B

PGND

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

BSTRP_C

AMP_OUT_C

PGND

2

3

4

PGND

5

PGND

AMP_OUT_A

PVDD

6

AMP_OUT_D

PVDD

7

PVDD

8

PVDD

BSTRP_A

SSTIMER

PBTL

9

BSTRP_D

GVDD_REG

AVDD_REG

NC

10

11

12

13

14

15

16

17

18

19

NC

PLL_GND

PLL_FLTM

PLL_FLTP

AVDD _REF

AVDD

AGND

DGND

DVDD

TEST

PowerPAD^TM

RST

ADR / FAULT

MCLK

NC

SCL

20

21

22

23

24

29

28

27

26

25

OSC_RES

OSC _GND

DVDD_REG

PDN

SDA

SDIN

SCLK

LRCLK

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if

pulled to AVDD. Also, if configured to be a fault output by the methods described in the

Fault Indication section, this terminal will be pulled low when an internal fault occurs.

ADR/FAULT

19

DI/DO

P

Ground reference for analog circuitry (NOTE: This terminal should be connected to the

system ground)

AGND

35

AMP_OUT_A

6

2

AMP_OUT_B

AMP_OUT_C

3

AO

Speaker amplifier outputs

46

47

43

18

AMP_OUT_D

AVDD

P

Power supply for internal analog circuitry

Internal power supply (NOTE: This terminal is provided as a connection point for filtering

capacitors for this supply and must not be used to power any external circuitry)

AVDD_REF

17

Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

AVDD_REG

38

P

BSTRP_A

BSTRP_B

BSTRP_C

BSTRP_D

9

1

Connection points to for the bootstrap capacitors, which are used to create a power

supply for the gate drive for the high-side device

48

40

Ground reference for digital circuitry (NOTE: This terminal should be connected to the

system ground)

DGND

DVDD

34

33

P

Power supply for the internal digital circuitry

Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

DVDD_REG

23

P

Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

GVDD_REG

LRCLK

39

25

P

Word select clock for the digital signal that is active on the input data line of the serial

port

DI

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

3

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

MCLK

NO.

20

12

13

30

36

37

DI

Master clock used for internal clock tree and sub-circuit/state machine clocking

Not connected inside the device (all "no connect" terminals should be connected to

system ground)

NC⁽²⁾

P

Ground reference for oscillator circuitry (NOTE: These terminals should be connected to

the system ground)

OSC_GND

OSC_RES

22

21

11

P

Connection point for precision resistor used by internal oscillator circuit. Details for this

resistor are shown in the Typical Applications section

AO

Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled

high

PBTL

PDN

DI

24

4

Places the device in power down when pulled low

5

Ground reference for power device circuitry (NOTE: This terminal should be connected

to the system ground)

PGND

—

44

45

15

16

PLL_FLTM

PLL_FLTP

AO

Negative connection point for the PLL loop filter components

Positive connection point for the PLL loop filter components

Ground reference for PLL circuitry (NOTE: This terminal should be connected to the

system ground)

PLL_GND

14

P

7

8

PVDD

P

Power supply for internal power circuitry

41

42

31

29

26

28

27

RST

DI

Places the devices in reset when pulled low

I²C serial control port clock

SCL

SCLK

SDA

SDIN

DI

Bit clock for the digital signal that is active on the input data line of the serial data port

I²C serial control port data

DI/DO

DI

Data line to the serial data port

Connection point for the capacitor that is used by the ramp timing circuit, as described in

the SSTIMER Pin Functionality section

SSTIMER

TEST

10

32

AO

—

Used by TI for testing during device production (NOTE: This terminal should be

connected to system ground)

Exposed metal pad on the underside of the device, which serves as an electrical

connection point for ground as well as a heat conduction path from the device into the

board (NOTE: This terminal should be connected to ground through a land pattern

defined in the Mechanical Data section)

PowerPAD

—

P

(2) Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground

plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the

device and into the surrounding PCB area.

4

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.3 to 3.6

UNIT

DVDD, AVDD

Supply voltage

V

PVDD

–0.3 to 20

3.3-V digital input

5-V tolerant⁽²⁾digital input (except MCLK)

–0.5 to DVDD + 0.5

–0.5 to DVDD + 2.5⁽³⁾

–0.5 to AVDD + 2.5⁽³⁾

22⁽⁴⁾

Input voltage

V

5-V tolerant MCLK input

AMP_OUT_x to GND

V

BSTRP_x to GND

29⁽⁴⁾

Operating free-air temperature

Storage temperature range, T_stg

0 to 85

°C

–40 to 125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.

(3) Maximum pin voltage should not exceed 6 V.

(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM

MAX

UNIT

V

DVDD, AVDD Digital, analog supply voltage

3

8

3.3

3.6

PVDD

Output power devices supply voltage

16.5⁽¹⁾

V

(2)

V_IH

V_IL

T_A

High-level input voltage

5-V tolerant

2

V

Low-level input voltage

0.8

85

Operating ambient temperature range

Operating junction temperature range

Load impedance

0

4

2

°C

Ω

(2)

T_J

125

R_L

8

Load impedance in PBTL

Ω

Minimum output inductance under

short-circuit condition

L_O

Output-filter inductance

10

μH

(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.

(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the

device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is

not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and

reduction in device reliability.

5

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

6.4 Thermal Characteristics

DCA (48 PINS)

THERMAL METRIC⁽¹⁾

UNITS

JEDEC

Standard 2-

Layer PCB

JEDEC

Standard 4-

Layer PCB

TAS5733LEVM

Special Test

Case

θ_JA

θ_JCtopJunction-to-case (top) thermal resistance⁽³⁾

Junction-to-ambient thermal resistance⁽²⁾

50.7

27.6

16.7

7.9

25.0

°C/W

14.9

6.9

θ_JB

ψ_JT

ψ_JB

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

1.2

0.8

0.7

5.8

11.8

7.8

θ_JCbotJunction-to-case (bottom) thermal resistance⁽⁷⁾

1.7

2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

6.5 Electrical Characteristics

T_A= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL BD mode, f_S= 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

I_OH= –4 mA

DVDD = AVDD = 3 V

V_OH

V_OL

I_IL

High-level output voltage

2.4

V

ADR/FAULT and SDA

Digital Inputs

I_OL= 4 mA

DVDD = AVDD = 3 V

Low-level output voltage

Low-level input current

High-level input current

0.5

75

V

V_I< V_IL

DVDD = AVDD = 3.6 V

μA

V_I> V_IH

DVDD = AVDD = 3.6 V

I_IH

Normal mode

49

23

68

38

3.3-V supply voltage

(DVDD, AVDD)

I_DD

3.3-V supply current

mA

Reset (RST = low, PDN =

high)

6

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

6.6 Speaker Amplifier Characteristics

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, f_S= 48 KHz, R_L= 8 Ω, audio frequency = 1 kHz, AES17 filter, f_PWM

=

384 kHz, T_A= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions

and as tested on the TAS5733L EVM.

PARAMETER

TEST CONDITIONS

PVDD = 12 V, 10% THD, 1-kHz input signal

PVDD = 12 V, 7% THD, 1-kHz input signal

PVDD = 12 V, 1% THD, 1-kHz input signal

PVDD = 13.2 V, 10% THD, 1-kHz input signal

PVDD = 13.2 V, 7% THD, 1-kHz input signal

PVDD = 13.2 V, 1% THD, 1-kHz input signal

PVDD = 12 V, P_O= 1 W

MIN

TYP

10

MAX UNIT

9

7.5

12

P_O

Power output per channel

W

11

9

0.25

0.3

30

Total harmonic distortion +

noise

THD+N

V_n

%

PVDD = 13.2 V, P_O= 1 W

Output integrated noise (rms) A-weighted

μV

dB

P_O= 1 W, f = 1 kHz (BD Mode), PVDD = 12 V

–79

–62

288

384

16

Crosstalk

P_O=1 W, f = 1 kHz (AD Mode), PVDD = 12 V

11.025, 22.05, 44.1-kHz data rate ±2%

48, 24, 12, 8, 16, 32-kHz data rate ±2%

Output switching frequency

Supply current

kHz

Normal mode

No load (PVDD)

25

mA

8

I_PVDD

Reset (RST = low, PDN = high)

3

Drain-to-source resistance,

low side

T_J= 25°C, includes metallization resistance

120

3

(1)

r_DS(on)

mΩ

kΩ

Drain-to-source resistance,

high side

T_J= 25°C, includes metallization resistance

Internal pulldown resistor at

the output of each half-bridge state to provide bootstrap capacitor charge.

Connected when drivers are in the high-impedance

R_PD

(1) This does not include bond-wire or pin resistance.

6.7 Protection Characteristics

T_A= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL BD mode, f_S= 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

V_uvp(fall)

V_uvp(rise)

OTE

Undervoltage protection limit

Overtemperature error

PVDD falling

PVDD rising

5.4

5.8

150

4

V

°C

A

I_OC

Overcurrent limit protection

Overcurrent response time

I_OCT

150

ns

6.8 Master Clock Characteristics⁽¹⁾

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, f_S= 48 kHz, R_L= 8 Ω, audio frequency = 1 kHz, AES17 filter, f_PWM

=

384 kHz, T_A= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions

(unless otherwise specified).

PARAMETER

PLL INPUT PARAMETERS

f_MCLKIMCLK frequency

MCLK duty cycle

t_r/ t_f(MCLK)Rise/fall time for MCLK

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

ns

2.8224

40%

24.576

60%

5

50%

(1) For clocks related to the serial audio port, please see Serial Audio Port Timing Requirements.

7

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

MAX UNIT

6.9 I²C Interface Timing Requirements

MIN

NOM

t_w(RST)

t_{d(I²C_ready)}

f_SCL

t_w(H)

t_w(L)

t_r

Pulse duration, RST active

Time to enable I²C after RST goes high

Frequency, SCL

100

μs

13.5

400

ms

kHz

μs

ns

μs

pF

Pulse duration, SCL high

0.6

1.3

Pulse duration, SCL low

Rise time, SCL and SDA

300

t_f

Fall time, SCL and SDA

t_su1

Setup time, SDA to SCL

100

0

t_h1

Hold time, SCL to SDA

t_(buf)

t_su2

Bus free time between stop and start conditions

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

Load capacitance for each bus line

1.3

0.6

t_h2

t_su3

C_L

400

6.10 Serial Audio Port Timing Requirements

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_SCLKIN

Frequency, SCLK 32 × f_S, 48 × f_S, 64 × f_S

C_L≤ 30 pF

1.024

12.28

8

MHz

t_su1

t_h1

t_su2

t_h2

Setup time, LRCK to SCLK rising edge

Hold time, LRCK from SCLK rising edge

Setup time, SDIN to SCLK rising edge

Hold time, SDIN from SCLK rising edge

LRCK frequency

10

ns

10

ns

10

ns

8

48

50%

48

60%

kHz

SCLK duty cycle

40%

LRCK duty cycle

SCLK

edges

SCLK rising edges between LRCK rising edges

32

64

t_(edge)

t_r/t_f

SCLK

period

LRCK clock edge with respect to the falling edge of SCLK

–1/4

1/4

Rise/fall time for SCLK/LRCK

8

4

ns

LRCK allowable drift before LRCK reset

MCLKs

8

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

RST

t_w(RST)

I²C Active

t_{d(I2C_ready)}

System Initialization.

Enable via I²C.

T0421-01

NOTE: On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.

NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is

deasserted (HIGH).

图 1. Reset Timing

t_w(H)

t_w(L)

t_r

t_f

SCL

t_su1

t_h1

SDA

T0027-01

图 2. SCL and SDA Timing

SCL

t_(buf)

t_h2

t_su2

t_su3

SDA

Start

Condition

Stop

Condition

T0028-01

图 3. Start and Stop Conditions Timing

9

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t_r

t_f

SCLK

(Input)

t_(edge)

t_h1

t_su1

LRCLK

(Input)

t_h2

t_su2

SDIN

T0026-04

图 4. Serial Audio Port Timing

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6.11 Typical Characteristics - Stereo BTL Mode

30

50

45

40

35

30

25

20

15

10

5

THD+N = 10%; 8 Ohms

THD+N = 1%; 8 Ohms

THD+N = 10%; 6 Ohms

THD+N = 1%; 6 Ohms

THD+N = 10%; 4 Ohms

THD+N = 1%; 4 Ohms

8 Ohms

6 Ohms

4 Ohms

25

20

15

10

5

0

8

9

10

11

12

13

14

15

8

9

10

11

12

13

14

15

PVDD (V)

D007

D012

图 5. Output Power vs Supply Voltage - BTL

图 6. Idle Channel Noise vs Supply Voltage - BTL

10

1

10

1

1 W

2.5 W

5 W

1 W

2.5 W

5 W

0.1

0.01

0.002

20

100

1k

10k 20k

10

100

1k

10k 20k

Frequency (Hz)

D001

D002

PVDD = 12 V

R_L= 8 Ω

PVDD = 12 V

R_L= 6 Ω

图 7. THD+N vs Frequency - BTL

图 8. THD+N vs Frequency - BTL

10

1

5

1

20 Hz

1 kHz

7 kHz

1 W

2.5 W

5 W

0.1

0.01

0.1

0.001

0.01

20

100

1k

10k 20k

0.01

0.1

1

10

50

Frequency (Hz)

Output Power (W)

D003

D001

PVDD = 12 V

R_L= 4 Ω

PVDD = 12 V

R_L= 8 Ω

图 9. THD+N vs Frequency - BTL

图 10. THD+N vs Output Power - BTL

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Typical Characteristics - Stereo BTL Mode (接下页)

20

10

1

20 Hz

1 kHz

7 kHz

20 Hz

1 kHz

7 kHz

1

0.1

0.01

0.001

0.01

0.1

1

10

50

0.01

0.1

1

10

50

Output Power (W)

D001

D006

PVDD = 12 V

R_L= 6 Ω

PVDD = 12 V

R_L= 4 Ω

图 11. THD+N vs Output Power - BTL

图 12. THD+N vs Output Power - BTL

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = 8 V

PVDD = 12 V

PVDD = 13.2 V

PVDD = 8 V

PVDD = 12 V

PVDD = 13.2 V

0

5

10

15

20

25

0

5

10

15

20

25

30

35

40

45

50

Total Output Power (W)

Output Power (W)

D008

D009

R_L= 8 Ω

R_L= 4 Ω

Total Output Power includes power delivered from both amplifier

outputs. For instance, 40 W of total output power means 2 × 20 W,

with 20 W delivered by one channel and 20 W delivered by the

other channel.

Total Output Power includes power delivered from both amplifier

outputs. For instance, 40 W of total output power means 2 × 20 W,

with 20 W delivered by one channel and 20 W delivered by the

other channel.

图 13. Efficiency vs Total Output Power - BTL

图 14. Efficiency vs Total Output Power - BTL

0

Right to Left

Left to Right

Right to Left

Left to Right

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-20

-30

-40

-50

-60

-70

-80

-90

-100

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D010

D011

PVDD = 12 V

R_L= 8 Ω

PVDD = 12 V

R_L= 4 Ω

图 15. Crosstalk vs Frequency - BTL

图 16. Crosstalk vs Frequency - BTL

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6.12 Typical Characteristics - Mono PBTL Mode

10

5

1

1 W

2.5 W

5 W

1 W

2.5 W

5 W

1

0.1

0.01

0.001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

D013

D014

PVDD = 12 V

R_L= 4 Ω

PVDD = 12 V

R_L= 3 Ω

图 17. THD+N vs Frequency - PBTL

图 18. THD+N vs Frequency - PBTL

10

1

20

10

1 W

2.5 W

5 W

20 Hz

1 kHz

7 kHz

1

0.1

0.01

0.001

0.01

20

100

1k

10k 20k

0.001

0.01

0.1

1

10

50

Frequency (Hz)

Output Power (W)

D015

D016

PVDD = 12 V

R_L= 2 Ω

PVDD = 12 V

R_L= 4 Ω

图 19. THD+N vs Frequency - PBTL

图 20. THD+N vs Output Power - PBTL

20

10

20

10

20 Hz

1 kHz

7 kHz

20 Hz

1 kHz

7 kHz

1

0.1

1

0.1

0.01

0.02

0.001

0.01

0.1

1

10

50

0.002

0.01

0.1

1

10

60

Output Power (W)

D017

D018

PVDD = 12 V

R_L= 3 Ω

PVDD = 12 V

R_L= 2 Ω

图 21. THD+N vs Output Power - PBTL

图 22. THD+N vs Output Power - PBTL

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Typical Characteristics - Mono PBTL Mode (接下页)

100

80

60

40

20

0

60

THD+N = 10%; RL = 4R

THD+N = 1%; RL = 4R

THD+N = 10%; RL = 3R

THD+N = 1%; RL = 3R

THD+N = 10%; RL = 2R

THD+N = 1%; RL = 2R

50

40

30

20

10

0

PVDD = 8 V

PVDD = 12 V

PVDD = 13.2 V

8

9

10

11

12

13

14

15

0

5

10

15

20

25

Supply Voltage (V)

Output Power (W)

D019

D020

R_L= 4 Ω

Total Output Power includes power delivered from both amplifier

outputs. For instance, 40 W of total output power means 2 × 20 W,

with 20 W delivered by one channel and 20 W delivered by the

other channel.

图 23. Output Power vs PVDD - PBTL

图 24. Efficiency vs Output Power - PBTL

100

90

80

70

60

50

40

30

20

10

0

60

RL = 4 R

RL = 3 R

RL = 2 R

50

40

30

20

10

0

PVDD = 8 V

PVDD = 12 V

PVDD = 13.2 V

0

5

10

15

20

25

30

35

40

45

8

9

10

11

12

13

14

15

Output Power (W)

PVDD (V)

D021

D022

R_L= 2 Ω

Total Output Power includes power delivered from both amplifier

outputs. For instance, 40 W of total output power means 2 × 20 W,

with 20 W delivered by one channel and 20 W delivered by the

other channel.

图 26. Idle Channel Noise vs PVDD - PBTL

图 25. Efficiency vs Output Power - PBTL

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7 Detailed Description

7.1 Overview

The TAS5733L device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a

bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel

outputs into a single lower impedance load. One serial data input allows processing of up to two discrete audio

channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a

wide range of input data and data rates. A fully programmable data path routes these channels to the internal

speaker drivers.

The TAS5733L device is a slave-only device receiving all clocks from external sources. The TAS5733L device

operates with a PWM carrier between a 384-kHz switching rate and a 288-kHz switching rate, depending on the

input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and

excellent dynamic range from 20 Hz to 20 kHz.

7.2 Functional Block Diagram

DVDD

AVDD

PVDD

Power-On Reset

(POR)

Internal Voltage Supplies

Internal Regulation and Power Distribution

MCLK Monitoring

and Watchdog

Open Loop Stereo

Stereo PWM Amplifier

Digital to PWM

Converter

(DPC)

Sensing & Protection

Serial Audio Port

(SAP)

AMP_OUT_A

AMP_OUT_B

MCLK

LRCK

SCLK

SDIN

Digital Audio

Processor

(DAP)

Sample Rate

Converter

(SRC)

2 Ch. PWM

Modulator

Temperature

Short Circuits

PVDD Voltage

Output Current

Sample Rate

Auto-Detect

Noise Shaping

PLL

AMP_OUT_C

AMP_OUT_D

Click & Pop

Suppression

Fault Notification

Internal Register/State Machine Interface

I²C Control Port

SCL SDA DR_SD PDN

RST

图 27. TAS5733L Functional Block Diagram

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7.3 Audio Signal Processing Overview

DC Block and LR Mixer

Equalizer

Multi Band AGL

Full Band AGL

Master Volume

0x59

0x3B - 0x3C, 0x40

Biquad

AGL 1

Low Band

0x5E

0x8

0x51

0x72, 0x73

Biquad

0x26

0x27 - 0x2F, 0x58

10 Biquads

0x44 - 0x45, 0x48

0x07 - 0x57, 0x56

Input

Mixer L

Biquad

L

Mixer L

L

0x5A

0x3E - 0x3F, 0x43

Vol 1

0x9

Biquad

AGL 4

Full Band

AGL 2

High Band

Master Volume,

Pre Scale,

Post Scale

R

0x5F

0x52

0x76, 0x77

Biquad

0x30

0x31 - 0x39, 0x5D

10 Biquads

Input

Mixer R

Biquad

R

0x5B, 0x5C

0x42 - 0x41, 0x47

Vol 2

2 Biquads

AGL 3

Mid Band

0x60, 0x61

2 Biquads

图 28. TAS5733L Audio Process Flow

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7.4 Feature Description

7.4.1 Clock, Autodetection, and PLL

The TAS5733L device is an I²S slave device. The TAS5733L device accepts MCLK, SCLK, and LRCK. The

digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control

Register.

The TAS5733L device checks to verify that SCLK is a specific value of 32 f_S, 48 f_S, or 64 f_S. The DAP only

supports a 1 × f_SLRCK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The

clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to

produce the internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the Clock Control Register.

The TAS5733L device has robust clock error handling that uses the built-in trimmed oscillator clock to quickly

detect changes/errors. Once the system detects a clock change/error, the system mutes the audio (through a

single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks

are stable, the system autodetects the new rate and reverts to normal operation. During this process, the default

volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp

back slowly (also called soft unmute) as defined in the Volume Configuration Register.

7.4.2 PWM Section

The TAS5733L DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz.

The PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For PVDD > 14.5 V the

modulation index must be limited to 96.1% for safe and reliable operation.

7.4.3 PWM Level Meter

The structure in 图 29 shows the PWM level meter that can be used to study the power profile.

Post-DAP Processing

1 – a

Z^–1

32-Bit Level

rms

a

Ch1

Ch2

ABS

ADDR = 0x6B

I²C Registers

(PWM Level Meter)

1 – a

Z^–1

32-Bit Level

rms

ADDR = 0x6C

B0396-01

图 29. PWM Level Meter Structure

7.4.4 Automatic Gain Limiter (AGL)

The AGL scheme has three AGL blocks. One ganged AGL exists for the high-band left/right channels, the mid-

band left/right channels, and the low-band left/right channels.

The AGL input/output diagram is shown in 图 30.

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Feature Description (接下页)

1:1 Transfer Function

Implemented Transfer Function

T

Input Level (dB)

M0091-04

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.

• Each AGL has adjustable threshold levels.

• Programmable attack and decay time constants

• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,

and decay times can be set slow enough to avoid pumping.

图 30. Automatic Gain Limiter

Alpha Filter Structure

S

a

–1

Z

w

T = 9.23 format, all other AGL coefficients are 3.23 format

图 31. AGL Structure

表 1. AGL Structure

α, ω

0x3B

0x3E

0x47

0x48

T

αa, ωa / αd, ωd

AGL 1

AGL 2

AGL 3

AGL 4

0x40

0x43

0x41

0x44

0x3C

0x3F

0x42

0x45

7.4.5 Fault Indication

ADR/FAULT is an input pin during power up. This pin can be programmed after RST to be an output by writing 1

to bit 0 of I²C register 0x05. In that mode, the ADR/FAULT pin has the definition shown in 表 2.

Any fault resulting in device shutdown is signaled by the ADR/FAULT pin going low (see 表 2). A latched version

of this pin is available on D1 of register 0x02. This bit can be reset only by an I²C write.

表 2. ADR/FAULT Output States

ADR/FAULT

DESCRIPTION

0

Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage

error

1

No faults (normal operation)

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7.4.6 SSTIMER Pin Functionality

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when

exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current

source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the

desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is

shut down, the drivers are placed in the high-impedance state and transition slowly down through an internal 3-

kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER

pin capacitance. Larger capacitors increase the start-up time, while smaller capacitors decrease the start-up

time. The SSTIMER pin can be left floating for BD modulation.

7.4.7 Device Protection System

7.4.7.1 Overcurrent (OC) Protection With Current Limiting

The TAS5733L device has independent, fast-reacting current detectors on all high-side and low-side power-stage

FETs. The detector outputs are closely monitored to prevent the output current from increasing beyond the

overcurrent threshold defined in the Protection Characteristics table.

If the output current increases beyond the overcurrent threshold, the device shuts down and the outputs

transition to the off or high impedance (Hi-Z) state. The device returns to normal operation once the fault

condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not

independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent

fault, half-bridges A, B, C, and D shut down.

7.4.7.2 Overtemperature Protection

The TAS5733L device has an overtemperature-protection system. If the device junction temperature exceeds

150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance

(Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The TAS5733L

device recovers automatically once the junction temperature of the device drops approximately 30°C.

7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5733L device fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD

and AVDD are independently monitored. For PVDD, if the supply voltage drops below the UVP threshold, the

protection feature immediately sets all half-bridge outputs to the high-impedance (Hi-Z) state and asserts

ADR/FAULT low.

7.5 Device Functional Modes

The TAS5733L device is a digital input class-d amplifier with audio processing capabilities. The TAS5733L

device has numerous modes to configure and control the device.

7.5.1 Serial Audio Port Operating Modes

The serial audio port in the TAS5733L device supports industry-standard audio data formats, including I²S, Left-

justified(LJ) and Right-justified(RJ) formats. To select the data format that will be used with the device can

controlled by using the serial data interface registers 0x04. The default is 24bit, I²S mode. The timing diagrams

for the various serial audio port are shown in the Serial Interface Control and Timing section

7.5.2 Communication Port Operating Modes

The TAS5733L device is configured via an I²C communication port. The I²C communication protocol is detailed in

the 7.7 I²C Serial Control Port Requirements and Specifications section.

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Device Functional Modes (接下页)

7.5.3 Speaker Amplifier Modes

The TAS5733L device can be configured as:

•

Stereo Mode

Mono Mode

7.5.3.1 Stereo Mode

Stereo mode is the most common option for the TAS5733L. TAS5733L can be connected in 2.0 mode to drive

stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge Tied

Load Application section.

7.5.3.2 Mono Mode

Mono mode is described as the operation where the two BTL outputs of amplifier are placed in parallel with one

another to provide increase in the output power capability. This mode is typically used to drive subwoofers, which

require more power to drive larger loudspeakers with high-amplitude, low-frequency energy. Detailed application

section regarding the mono mode is discussed in the Mono Parallel Bridge Tied Load Application section.

7.6 Programming

7.6.1 I²C Serial Control Interface

The TAS5733L device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.

This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The

control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation

(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.

7.6.1.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in 图 32. The master

generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and

then waits for an acknowledge condition. The TAS5733L device holds SDA low during the acknowledge clock

period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.

Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for

the SDA and SCL signals to set the high level for the bus.

8-Bit Register Data For

Address (N)

8-Bit Register Data For

Address (N)

R/

W

8-Bit Register Address (N)

7-Bit Slave Address

A

SDA

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SCL

Start

Stop

T0035-01

图 32. Typical I²C Sequence

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Programming (接下页)

No limit exists for the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in 图 32.

The 7-bit address for the TAS5733L device is 0101 010 (0x54) or 0101 011 (0x56) as defined by ADR/FAULT

(external pulldown for 0x54 and pullup for 0x56).

7.6.1.2 I²C Slave Address

The ADR/FAULT is an input pin during power-up and after each toggle of RST, which is used to set the I²C sub-

address of the device. The ADR/FAULT can also operate as a fault output after power-up is complete and the

address has been latched in.

At power-up, and after each toggle of RST, the pin is read to determine its voltage level. If the pin is left floating,

an internal pull-up will set the I²C sub-address to 0x56. This will also be the case if an external resistor is used to

pull the pin up to AVDD. To set the sub-address to 0x54, an external resistor (specified in Typical Applications )

must be connected to the system ground.

As mentioned, the pin can also be reconfigured as an output driver via I²C for fault monitoring. Use System

Control Register 2 (0x05) to set ADR/FAULT pin to be used as a fault output during fault conditions.

I²C Device Address Change Procedure

1. Write to device address change enable register, 0xF8 with a value of 0xF9A5 A5A5.

2. Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.

3. Any writes after that should use the new device address XX.

7.6.1.3 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received

when a stop command (or another start command) is received, the received data is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The

TAS5733L device also supports sequential I²C addressing. For write transactions, if a subaddress is issued

followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has

taken place, and the data for all 16 subaddresses is successfully received by the TAS5733L device. For I²C

sequential-write transactions, the subaddress then serves as the start address, and the amount of data

subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written.

As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If

only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,

all other data written is accepted; only the incomplete data is discarded.

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Programming (接下页)

7.6.1.4 Single-Byte Write

As shown in 图 33, a single-byte data-write transfer begins with the master device transmitting a start condition

followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data

transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address and the

read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes

corresponding to the internal memory address being accessed. After receiving the address byte, the TAS5733L

device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to

the memory address being accessed. After receiving the data byte, the TAS5733L device again responds with an

acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write

transfer.

Start

Condition

Acknowledge

R/W

A6 A5 A4 A3 A2 A1 A0

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

Data Byte

Stop

Condition

T0036-01

图 33. Single-Byte Write Transfer

7.6.1.5 Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes

are transmitted by the master device to the DAP as shown in 图 34. After receiving each data byte, the

TAS5733L device responds with an acknowledge bit.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

图 34. Multiple-Byte Write Transfer

7.6.1.6 Single-Byte Read

As shown in 图 35, a single-byte data-read transfer begins with the master device transmitting a start condition,

followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a

read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5733L address and the

read/write bit, TAS5733L device responds with an acknowledge bit. In addition, after sending the internal

memory address byte or bytes, the master device transmits another start condition followed by the TAS5733L

address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After

receiving the address and the read/write bit, the TAS5733L device again responds with an acknowledge bit.

Next, the TAS5733L device transmits the data byte from the memory address being read. After receiving the

data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-

byte data-read transfer.

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Programming (接下页)

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A0 ACK

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and

Read/Write Bit

Data Byte

Stop

Condition

T0036-03

图 35. Single-Byte Read Transfer

7.6.1.7 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes

are transmitted by the TAS5733L device to the master device as shown in 图 36. Except for the last data byte,

the master device responds with an acknowledge bit after receiving each data byte.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

D0 ACK D7

A6

A0 R/W ACK A7 A6 A5

A0 ACK

A6

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

图 36. Multiple-Byte Read Transfer

7.6.2 Serial Interface Control and Timing

7.6.2.1 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5733L DAP accepts serial data

in 16-bit, 20-bit, or 24-bit left-justified, right-justified, and I²S serial data formats.

7.6.2.2 I²S Timing

I²S timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for

the right channel. LRCK is low for the left channel and high for the right channel. A bit clock running at 32 × f_S,

48 × f_S, or 64 × f_Sis used to clock in the data. A delay of one bit clock exists from the time the LRCK signal

changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge

of bit clock. The DAP masks unused trailing data bit positions.

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

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Programming (接下页)

2-Channel I²S (Philips Format) Stereo Input

32 Clks

LRCLK (Note Reversed Phase)

Right Channel

Left Channel

SCLK

MSB

LSB

MSB

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

0

1

0

23 22

19 18

15 14

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

16-Bit Mode

15 14

T0034-01

NOTE: All data presented in two's-complement form with MSB first.

图 37. I²S 64-f_SFormat

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

Programming (接下页)

2-Channel I²S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

24-Bit Mode

23 22

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

0

23 22

19 18

15 14

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

1

20-Bit Mode

19 18

16-Bit Mode

15 14

9

8

9

8

T0092-01

NOTE: All data presented in two's-complement form with MSB first.

图 38. I²S 48-f_SFormat

2-Channel I²S (Philips Format) Stereo Input

16 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

0

15 14 13 12 11 10

9

8

5

4

3

2

1

T0266-01

NOTE: All data presented in two's-complement form with MSB first.

图 39. I²S 32-f_SFormat

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

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Programming (接下页)

7.6.2.3 Left-Justified

Left-justified (LJ) timing uses LRCK to define when the data being transmitted is for the left channel and when

the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock

running at 32 × f_S, 48 × f_S, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data lines at

the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The

DAP masks unused trailing data bit positions.

2-Channel Left-Justified Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

23 22

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

0

1

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

15 14

16-Bit Mode

15 14

T0034-02

NOTE: All data presented in two's-complement form with MSB first.

图 40. Left-Justified 64-f_SFormat

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Programming (接下页)

2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18 17

16-Bit Mode

15 14 13

9

8

15 14 13

9

8

T0092-02

NOTE: All data presented in two's-complement form with MSB first.

图 41. Left-Justified 48-f_SFormat

2-Channel Left-Justified Stereo Input

16 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

1

0

15 14 13 12 11 10

9

8

5

4

3

2

1

0

T0266-02

NOTE: All data presented in two's-complement form with MSB first.

图 42. Left-Justified 32-f_SFormat

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Programming (接下页)

7.6.2.4 Right-Justified

Right-justified (RJ) timing uses LRCK to define when the data being transmitted is for the left channel and when

the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock

running at 32 × f_S, 48 × f_S, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data 8 bit-

clock periods (for 24-bit data) after LRCK toggles. In RJ mode, the LSB of data is always clocked by the last bit

clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP

masks unused leading data bit positions.

2-Channel Right-Justified (Sony Format) Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

0

24-Bit Mode

23 22

19 18

15 14

1

0

23 22

19 18

15 14

1

20-Bit Mode

16-Bit Mode

0

T0034-03

All data presented in two's-complement form with MSB first.

图 43. Right-Justified 64-f_SFormat

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TAS5733L

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

Programming (接下页)

2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22

19 18

15 14

6

5

2

1

0

23 22

19 18

15 14

6

5

2

1

0

20-Bit Mode

16-Bit Mode

0

T0092-03

All data presented in two's-complement form with MSB first.

图 44. Right-Justified 48-f_SFormat

All data presented in two's-complement form with MSB first.

图 45. Right-Justified 32-f_SFormat

7.6.3 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23

numbers mean that the binary point has 3 bits to the left and 23 bits to the right. This is shown in 图 46.

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Programming (接下页)

2^–23Bit

2^–5Bit

2^–1Bit

2⁰Bit

2¹Bit

Sign Bit

S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

M0125-01

图 46. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in 图 46. If the most

significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If

the most significant bit is a logic 1, then the number is a negative number. In the case every bit must be inverted,

a 1 added to the result, and then the weighting shown in 图 47 applies to obtain the magnitude of the negative

number.

2¹Bit

2⁰Bit

2^–1Bit

2^–4Bit

2^–23Bit

(1 or 0) ´ 2¹+ (1 or 0) ´ 2⁰+ (1 or 0) ´ 2^–1+ ....... (1 or 0) ´ 2^–4+ ....... (1 or 0) ´ 2^–23

M0126-01

图 47. Conversion Weighting Factors—3.23 Format to Floating Point

Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit

number (4-byte or 8-digit hexadecimal number) is shown in 图 48.

Fraction

Digit 6

Sign

Bit

Fraction

Digit 1

Fraction

Digit 2

Fraction

Digit 3

Fraction

Digit 4

Fraction

Digit 5

Integer

Digit 1

u

x

x.

x

x x x x

0

S

Coefficient

Digit 8

Coefficient

Digit 7

Coefficient

Digit 6

Coefficient

Digit 5

Coefficient

Digit 4

Coefficient

Digit 3

Coefficient

Digit 2

Coefficient

Digit 1

u = unused or don’t care bits

Digit = hexadecimal digit

M0127-01

图 48. Alignment of 3.23 Coefficient in 32-Bit I²C Word

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

表 3. Sample Calculation for 3.23 Format

db

0

Linear

1

Decimal

8,388,608

14,917,288

4,717,260

Hex (3.23 Format)

80 0000

5

1.77

00E3 9EA8

0047 FACC

–5

X

0.56

L = 10^{(X / 20)}

D = 8,388,608 × L H = dec2hex (D, 8)

表 4. Sample Calculation for 9.17 Format

db

0

Linear

1

Decimal

131,072

Hex (9.17 Format)

2 0000

5

1.77

231,997

3 8A3D

–5

X

0.56

L = 10^{(X / 20)}

73,400

1 1EB8

D = 131,072 × L

H = dec2hex (D, 8)

7.7 Register Maps

7.7.1 Register Summary

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

CONTENTS

A u indicates unused bits.

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

Clock control register

1

2

1

Description shown in subsequent section

Reserved⁽¹⁾

0x6C

0x40

Device ID register

Error status register

System control register 1

Serial data interface register

System control register 2

Soft mute register

Master volume

0x00

0xA0

0x05

0x40

0x00

0x03FF (mute)

0x00C0 (0 dB)

0x03FF

0x00C0

0xC0

Channel 1 vol

Channel 2 vol

Channel 3 vol

Reserved

Reserved⁽¹⁾

Volume configuration register

Reserved

Description shown in subsequent section

Reserved⁽¹⁾

0xF0

0x97

Modulation limit register

IC delay channel 1

IC delay channel 2

IC delay channel 3

IC delay channel 4

Reserved

Description shown in subsequent section

Reserved⁽¹⁾

0x01

0xAC

0x54

0xAC

0x54

0xAC

0x54

0x00

PWM Start

0x0F

PWM Shutdown Group Register

Start/stop period register

Oscillator trim register

1

Description shown in subsequent section

0x30

0x68

0x82

(1) Do not access reserved registers.

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Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

BKND_ERR register

CONTENTS

0x1C

0x1D–0x1F

0x20

1

Description shown in subsequent section

Reserved⁽¹⁾

0x57

0x00

Input MUX register

Reserved

4

Description shown in subsequent section

Reserved⁽¹⁾

0x0001 7772

0x0000 4303

0x0000 0000

0x0102 1345

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x21

4

0x22

4

0x23

4

0x24

4

0x25

PWM MUX register

ch1_bq[0]

4

Description shown in subsequent section

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x26

20

0x27

0x28

0x29

0x2A

0x2B

0x2C

ch1_bq[1]

ch1_bq[2]

ch1_bq[3]

ch1_bq[4]

ch1_bq[5]

ch1_bq[6]

20

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

CONTENTS

0x2D

ch1_bq[7]

ch1_bq[8]

ch1_bq[9]

ch2_bq[0]

ch2_bq[1]

ch2_bq[2]

ch2_bq[3]

ch2_bq[4]

ch2_bq[5]

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

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Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

ch2_bq[6]

CONTENTS

0x36

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

Reserved⁽¹⁾

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x37

0x38

0x39

ch2_bq[7]

ch2_bq[8]

ch2_bq[9]

Reserved

0x3A

0x3B

4

8

0x0080 0000 0000

0000

AGL1 softening filter alpha

AGL1 softening filter omega

AGL1 attack rate

u[31:26], ae[25:0]

u[31:26], oe[25:0]

0x0008 0000

0x0078 0000

0x0000 0100

0xFFFF FF00

0x3C

8

Description shown in subsequent section

AGL1 release rate

34

TAS5733L

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

CONTENTS

0x3D

0x3E

8

Reserved⁽¹⁾

AGL2 softening filter alpha

AGL2 softening filter omega

AGL2 attack rate

u[31:26], ae[25:0]

0x0008 0000

0x0078 0000

0x0008 0000

0xFFF8 0000

0x0800 0000

0x0074 0000

0x0008 0000

0xFFF8 0000

0x0074 0000

0x0008 0000

0xFFF8 0000

0x0002 0000

0x0008 0000

0x0078 0000

0x0008 0000

0x0078 0000

u[31:26], oe[25:0]

0x3F

8

u[31:26], at[25:0]

AGL2 release rate

u[31:26], rt[25:0]

0x40

0x41

0x42

AGL1 attack threshold

AGL3 attack threshold

AGL3 attack rate

4

8

T1[31:0] (9.23 format)

Description shown in subsequent section

T2[31:0] (9.23 format)

T1[31:0] (9.23 format)

AGL3 release rate

0x43

0x44

0x45

AGL2 attack threshold

AGL4 attack threshold

AGL4 attack rate

4

8

AGL4 release rate

0x46

0x47

AGL control

4

8

Description shown in subsequent section

u[31:26], ae[25:0]

AGL3 softening filter alpha

AGL3 softening filter omega

AGL4 softening filter alpha

AGL4 softening filter omega

Reserved

u[31:26], oe[25:0]

0x48

8

u[31:26], ae[25:0]

u[31:26], oe[25:0]

Reserved⁽¹⁾

0x49

0x4A

4

0x1212 1010 E1FF

FFFF F95E 1212

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

4

0x0000 296E

0x0000 5395

0x0000 0000

0x0000 0008

0x0F70 8000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

4

PWM switching rate control

Bank switch control

4

u[31:4], src[3:0]

4

Description shown in subsequent section

Ch 1 output mix1[2]

Ch 1 output mix1[1]

Ch 1 output mix1[0]

Ch 2 output mix2[2]

Ch 2 output mix2[1]

Ch 2 output mix2[0]

Reserved⁽¹⁾

Ch 1 output mixer

12

0x52

Ch 2 output mixer

12

0x53

0x54

16

0x0080 0000 0000

0000 0000 0000

Reserved⁽¹⁾

0x0080 0000 0000

0000 0000 0000

0x56

0x57

0x58

Output post-scale

Output pre-scale

ch1_bq[10]

4

u[31:26], post[25:0]

u[31:26], pre[25:0] (9.17 format)

u[31:26], b0[25:0]

0x0080 0000

0x0002 0000

0x0080 0000

0x0000 0000

20

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

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Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

ch1_cross_bq[0]

CONTENTS

0x59

20

4

u[31:26], b0[25:0]

ch1_cross_bq[1]

ch1_cross_bq[2]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0000 0080

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

ch1_cross_bq[1]

ch1_cross_bq[2]

ch1_cross_bq[3]

ch2_bq[10]

ch2_cross_bq[0]

ch2_cross_bq[1]

ch2_cross_bq[2]

ch2_cross_bq[3]

IDF post scale

Description shown in subsequent section

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ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

Register Maps (continued)

NO. OF

BYTES

DEFAULT

VALUE

SUBADDRESS

REGISTER NAME

CONTENTS

0x63–0x69

0x6A

Reserved

4

8

Reserved⁽¹⁾

0x0000 0000

0x0000 8312

0x007F 7CED

0x0000 0000

0x6B

Left channel PWM level meter

Right channel PWM level meter

Reserved

Data[31:0]

Reserved⁽¹⁾

0x6C

0x6D

0x0000 0000 0000

0000

0x6E–0x6F

0x70

4

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0000 0054

ch1 inline mixer

u[31:26], in_mix1[25:0]

u[31:26], in_mixagl_1[25:0]

u[31:26], right_mix1[25:0]

u[31:26], left_mix_1[25:0]

u[31:26], in_mix2[25:0]

u[31:26], in_mixagl_2[25:0]

u[31:26], left_mix1[25:0]

u[31:26], right_mix_1[25:0]

Reserved⁽¹⁾

0x71

inline_AGL_en_mixer_ch1

ch1 right_channel mixer

ch1 left_channel_mixer

ch2 inline mixer

0x72

0x73

0x74

0x75

inline_AGL_en_mixer_ch2

ch2 left_chanel mixer

ch2 right_channel_mixer

0x76

0x77

0x78–0xF7

0xF8

Update device address key

Update device address

4

Dev Id Update Key[31:0] (Key =

0xF9A5A5A5)

0xF9

u[31:8],New Dev Id[7:0] (New Dev Id = 0x54

for TAS5733L)

Reserved⁽¹⁾

0x0000 0054

0x0000 0000

0xFA–0xFF

All DAP coefficients are 3.23 format unless specified otherwise.

Registers 0x3B through 0x46 should be altered only during the initialization phase.

7.7.2 Detailed Register Descriptions

7.7.2.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5733L. The clock control register contains the

autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

Table 5. Clock Control Register (0x00)

D7

0

1

–

0

–

D6

0

1

0

1

–

0

–

D5

0

1

0

1

0

1

0

1

–

0

–

D4

–

0

D3

–

0

1

D2

–

0

1

0

1

D1

–

1

0

–

D0

–

0

–

FUNCTION

f_S= 32-kHz sample rate

Reserved

f_S= 44.1/48-kHz sample rate⁽¹⁾

f_S= 16-kHz sample rate

f_S= 22.05/24-kHz sample rate

f_S= 8-kHz sample rate

f_S= 11.025/12-kHz sample rate

(2)

MCLK frequency = 64 × f_S

(2)

MCLK frequency = 128 × f_S

(3)

MCLK frequency = 192 × f_S

(1)(4)

MCLK frequency = 256 × f_S

(1) Default values are in bold.

(2) Only available for 44.1-kHz and 48-kHz rates

(3) Rate only available for 32/44.1/48-KHz sample rates

(4) Not available at 8 kHz

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Table 5. Clock Control Register (0x00) (continued)

D7

–

D6

–

D5

–

D4

1

D3

0

D2

0

D1

–

D0

–

FUNCTION

MCLK frequency = 384 × f_S

MCLK frequency = 512 × f_S

Reserved

–

1

0

1

–

1

0

–

1

–

Reserved

–

0

–

Reserved

–

0

Reserved

7.7.2.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision.

Table 6. General Status Register (0x01)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

(1)

Identification code

(1) Default values are in bold.

7.7.2.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the

register (write zeroes) and then read them to determine if they are persistent errors.

Error definitions:

•

MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.

SCLK error: The number of SCLKs per LRCLK is changing.

LRCLK error: LRCLK frequency is changing.

Frame slip: LRCLK phase is drifting with respect to internal frame sync.

Table 7. Error Status Register (0x02)

D7

1

D6

-

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

FUNCTION

MCLK error

–

1

–

0

–

PLL autolock error

SCLK error

–

1

–

1

–

LRCLK error

Frame slip

–

1

–

1

–

Clip indicator

–

1

–

Overcurrent, overtemperature, overvoltage, or undervoltage error

Reserved

0

(1)

0

No errors

(1) Default values are in bold.

7.7.2.4 System Control Register 1 (0x03)

System control register 1 has several functions:

Bit D7:

Bit D5:

If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled.

If 0, use soft unmute on recovery from a clock error. This is a slow recovery. Unmute takes the

same time as the volume ramp defined in register 0x0E.

If 1, use hard unmute on recovery from clock error. This is a fast recovery, a single-step volume

ramp.

Bits D1–D0: Select de-emphasis

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Table 8. System Control Register 1 (0x03)

D7

0

1

–

D6

–

0

–

D5

–

1

–

D4

–

0

–

D3

–

0

–

D2

–

0

–

D1

–

0

1

D0

–

0

1

0

1

FUNCTION

PWM high-pass (dc blocking) disabled

(1)

PWM high-pass (dc blocking) enabled

(1)

Reserved

(1)

Soft unmute on recovery from clock error

Hard unmute on recovery from clock error

(1)

Reserved

(1)

Reserved

(1)

Reserved

(1)

No de-emphasis

De-emphasis for f_S= 32 kHz

De-emphasis for f_S= 44.1 kHz

De-emphasis for f_S= 48 kHz

(1) Default values are in bold.

7.7.2.5 Serial Data Interface Register (0x04)

As shown in Table 9, the TAS5733L supports nine serial data modes. The default is 24-bit, I²S mode.

Table 9. Serial Data Interface Control Register (0x04) Format

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD

LENGTH

D7–D4

D3

D2

D1

D0

Right-justified

16

20

24

16

20

24

16

20

24

0000

000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Right-justified

I²S

0000

(1)

I²S

Left-justified

Reserved

(1) Default values are in bold.

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7.7.2.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs

are shut down (hard mute).

Table 10. System Control Register 2 (0x05)

D7 D6 D5

D4

–

D3

–

D2

–

D1

–

D0

–

FUNCTION

(1)

0

1

–

0

1

–

0

Mid-Z ramp disabled

–

Mid-Z ramp enabled

–

Exit all-channel shutdown (normal operation)

(1)

–

Enter all-channel shutdown (hard mute)

(1)

0

–

Reserved

(1)

0

–

Ternary modulation disabled

–

1

–

Ternary modulation enabled

(1)

–

0

–

Reserved

–

0

–

configured as input

–

1

–

configured configured as output to function as fault output pin.

(1)

–

0

Reserved

(1) Default values are in bold.

Ternary modulation is disabled by default. To enable ternary modulation, the following writes are required before

bringing the system out of shutdown:

1. Set bit D3 of register 0x05 to 1.

2. Write the following ICD settings:

(a) 0x11= 80

(b) 0x12= 7C

(c) 0x13= 80

(d) 0x14 =7C

3. Set the input mux register as follows:

(a) 0x20 = 00 89 77 72

7.7.2.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

Table 11. Soft Mute Register (0x06)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

(1)

0

–

0

–

0

–

0

–

0

–

Reserved

1

–

Soft mute channel 3

(1)

0

–

Soft unmute channel 3

Soft mute channel 2

–

1

–

0

–

Soft unmute channel 2

Soft mute channel 1

–

1

–

0

Soft unmute channel 1

(1) Default values are in bold.

7.7.2.8 Volume Registers (0x07, 0x08, 0x09)

The volume register 0x07, 0x08, and 0x09 correspond to master volume, channel 1 volume, and channel 2

volume, respectively. Step size is 0.125 dB and volume registers are 2 bytes.

Master volume

– 0x07 (default is mute, 0x03FF)

– 0x08 (default is 0 dB, 0x00C0)

Channel-1 volume

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Channel-2 volume

– 0x09 (default is 0 dB, 0x00C0)

Table 12. Master Volume

Table

Value

0x0000

0x0001

...

Level

24.000

23.875

(0.125 dB steps)

–103.750

0x03FE

0x03FF

Mute

7.7.2.9 Volume Configuration Register (0x0E)

Bits Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the

D2–D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of

the I²S data as follows:

Sample rate (kHz)

8/16/32

Approximate ramp rate

125 μs/step

11.025/22.05/44.1

12/24/48

90.7 μs/step

83.3 μs/step

In two-band AGL, register 0x0A should be set to 0x30 and register 0x0E bits 6 and 5 should be set to 1.

Table 13. Volume Configuration Register (0x0E)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

(1)

1

–

0

1

–

0

1

–

1

–

0

–

Reserved

–

AGL2 volume 1 (ch4) from I²C register 0x08

AGL2 volume 1 (ch4) from I²C register 0x0A⁽¹⁾

AGL2 volume 2 (ch3) from I²C register 0x09

AGL2 volume 2 (ch3) from I²C register 0x0A⁽¹⁾

–

(1)

–

Reserved

(1)

0

Volume slew 512 steps (43 ms volume ramp time at 48 kHz)

Volume slew 1024 steps (85-ms volume ramp time at 48 kHz)

Volume slew 2048 steps (171-ms volume ramp time at 48 kHz)

Volume slew 256 steps (21-ms volume ramp time at 48 kHz)

Reserved

0

1

0

1

0

1

X

(1) Default values are in bold.

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7.7.2.10 Modulation Limit Register (0x10)

Table 14. Modulation Limit Register (0x10)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

–

D1

–

D0

–

MODULATION LIMIT

Reserved

98.4%⁽¹⁾

97.7%

–

0

–

0

1

–

0

1

0

–

0

1

96.9%

–

1

0

96.1%

–

1

0

1

95.3%

–

1

0

94.5%

–

1

93.8%

(1) Default values are in bold.

7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 15. Channel Interchannel Delay Register Format

BITS DEFINITION

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

–

D0

–

FUNCTION

Minimum absolute delay, 0 DCLK cycles

Maximum positive delay, 31 × 4 DCLK cycles

Maximum negative delay, –32 × 4 DCLK cycles

Reserved

0

1

–

1

0

–

0

SUBADDRESS

0x11

D7

1

D6

0

D5

1

D4

0

D3

1

D2

1

D1

–

D0 Delay = (value) × 4 DCLKs

(1)

–

Default value for channel 1

Default value for channel 2

Default value for channel 1

Default value for channel 2

0x12

0

1

0

1

0

1

–

0x13

1

0

1

0

1

–

0x14

0

1

0

1

0

1

–

(1) Default values are in bold.

ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore,

appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD

mode, then update these registers before coming out of all-channel shutdown.

MODE

0x11

0x12

0x13

0x14

AD MODE

BD MODE

AC

54

B8

60

A0

48

AC

54

7.7.2.12 PWM Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The functionality of this register is tied to the

state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group. If a 1 is set in the shutdown group register,

that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0

in system control register 2, 0x05).

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Table 16. PWM Shutdown Group Register (0x19)

D7

0

–

D6

–

0

–

D5

–

1

–

D4

–

1

–

D3

–

0

1

–

D2

–

0

1

–

D1

–

0

1

–

D0

–

0

1

FUNCTION

(1)

Reserved

(1)

PWM channel 4 does not belong to shutdown group.

PWM channel 4 belongs to shutdown group.

PWM channel 3 does not belong to shutdown group.

PWM channel 3 belongs to shutdown group.

PWM channel 2 does not belong to shutdown group.

PWM channel 2 belongs to shutdown group.

PWM channel 1 does not belong to shutdown group.

PWM channel 1 belongs to shutdown group.

(1) Default values are in bold.

7.7.2.13 Start/Stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown

command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times

are only approximate and vary depending on device activity level and I²S clock stability.

Table 17. Start/Stop Period Register (0x1A)

D7 D6 D5 D4 D3

D2

–

0

1

0

1

0

1

D1

–

0

1

0

1

0

1

0

1

0

1

0

D0

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FUNCTION

(1)

0

1

–

1

–

1

–

0

1

–

0

1

0

1

SSTIMER enabled

SSTIMER disabled

(1)

Reserved

No 50% duty cycle start/stop period

16.5-ms 50% duty cycle start/stop period

23.9-ms 50% duty cycle start/stop period

31.4-ms 50% duty cycle start/stop period

40.4-ms 50% duty cycle start/stop period

53.9-ms 50% duty cycle start/stop period

70.3-ms 50% duty cycle start/stop period

94.2-ms 50% duty cycle start/stop period

125.7-ms 50% duty cycle start/stop period⁽¹⁾

164.6-ms 50% duty cycle start/stop period

239.4-ms 50% duty cycle start/stop period

314.2-ms 50% duty cycle start/stop period

403.9-ms 50% duty cycle start/stop period

538.6-ms 50% duty cycle start/stop period

703.1-ms 50% duty cycle start/stop period

942.5-ms 50% duty cycle start/stop period

1256.6-ms 50% duty cycle start/stop period

1728.1-ms 50% duty cycle start/stop period

2513.6-ms 50% duty cycle start/stop period

3299.1-ms 50% duty cycle start/stop period

4241.7-ms 50% duty cycle start/stop period

5655.6-ms 50% duty cycle start/stop period

7383.7-ms 50% duty cycle start/stop period

(1) Default values are in bold.

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Table 17. Start/Stop Period Register (0x1A) (continued)

D7 D6 D5 D4 D3

D2

1

D1

1

D0

0

FUNCTION

9897.3-ms 50% duty cycle start/stop period

13,196.4-ms 50% duty cycle start/stop period

–

1

7.7.2.14 Oscillator Trim Register (0x1B)

The TAS5733L PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This

reduces system cost because an external reference is not required. A reference resistor must be connected

between pin 16 and 17, as shown in Table 18.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

Note that trim must always be run following reset of the device.

Table 18. Oscillator Trim Register (0x1B)

D7

1

D6

–

D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

(1)

–

0

–

0

–

0

–

Reserved

(1)

–

0

–

Oscillator trim not done (read-only)

–

1

–

Oscillator trim done (read only)

(1)

–

0

–

Reserved

–

0

–

Select factory trim (Write a 0 to select factory trim; default is 1.)

(1)

–

1

–

Factory trim disabled

(1)

–

0

Reserved

(1) Default values are in bold.

7.7.2.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all

PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting

to re-start the power stage.

Table 19. BKND_ERR Register (0x1C)⁽¹⁾

D7 D6 D5 D4 D3

D2

x

D1

x

D0

X

0

FUNCTION

0

–

1

–

0

–

1

–

x

0

1

Reserved

0

1

Set back-end reset period to 299 ms⁽²⁾

Set back-end reset period to 449 ms

Set back-end reset period to 598 ms

Set back-end reset period to 748 ms

Set back-end reset period to 898 ms

Set back-end reset period to 1047 ms

Set back-end reset period to 1197 ms

Set back-end reset period to 1346 ms

Set back-end reset period to 1496 ms

0

1

0

1

0

1

0

1

0

1

0

1

X

1

Set back-end reset period to 1496 ms

(1) This register can be written only with a non-reserved value. The RSTz pin must be toggled between subsequent writes to this register.

(2) Default values are in bold.

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7.7.2.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal

channels.

Table 20. Input Multiplexer Register (0x20)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

(1)

Reserved

D23

0

D22

–

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

(1)

Channel-1 AD mode

Channel-1 BD mode

SDIN-L to channel 1

SDIN-R to channel 1

Reserved

1

–

(1)

–

0

–

0

1

–

0

1

0

–

0

1

–

Reserved

–

1

0

–

Reserved

–

1

0

1

–

Reserved

–

1

0

–

Ground (0) to channel 1

–

1

–

Reserved

(1)

–

0

–

Channel 2 AD mode

–

1

–

Channel 2 BD mode

SDIN-L to channel 2

–

0

(1)

–

0

1

SDIN-R to channel 2

–

0

1

0

Reserved

–

0

1

Reserved

–

1

0

Reserved

–

1

0

1

Reserved

–

1

0

Ground (0) to channel 2

Reserved

–

1

D15

0

D14

1

D13

1

D12

1

D11

0

D10

1

D9

1

D8

1

FUNCTION

(1)

Reserved

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

1

D0

0

FUNCTION

(1) Default values are in bold.

7.7.2.17 PWM Output MUX Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be

output to any external output pin.

Bits D21–D20:

Bits D17–D16:

Bits D13–D12:

Bits D09–D08:

Selects which PWM channel is output to AMP_OUT_A

Selects which PWM channel is output to AMP_OUT_B

Selects which PWM channel is output to AMP_OUT_C

Selects which PWM channel is output to AMP_OUT_D

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.

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Table 21. PWM Output MUX Register (0x25)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

1

FUNCTION

(1)

Reserved

D23

0

D22

0

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

FUNCTION

(1)

Reserved

(1)

–

0

–

Multiplex channel 1 to AMP_OUT_A

Multiplex channel 2 to AMP_OUT_A

Multiplex channel 1 to AMP_OUT_A

Multiplex channel 2 to AMP_OUT_A

–

0

1

–

1

0

–

1

–

(1)

–

0

–

Reserved

–

0

Multiplex channel 1 to AMP_OUT_B

Multiplex channel 2 to AMP_OUT_B

Multiplex channel 1 to AMP_OUT_B

Multiplex channel 2 to AMP_OUT_B

–

0

1

(1)

–

1

0

–

1

D15

0

D14

0

D13

–

D12

–

D11

–

D 10

–

D9

–

D8

–

FUNCTION

(1)

Reserved

–

0

–

Multiplex channel 1 to AMP_OUT_C

Multiplex channel 2 to AMP_OUT_C

Multiplex channel 1 to AMP_OUT_C

Multiplex channel 2 to AMP_OUT_C

(1)

–

0

1

–

1

0

–

1

–

(1)

–

0

–

Reserved

–

0

Multiplex channel 1 to AMP_OUT_D

Multiplex channel 2 to AMP_OUT_D

Multiplex channel 1 to AMP_OUT_D

Multiplex channel 2 to AMP_OUT_D

–

0

1

–

1

0

(1)

–

1

D7

0

D6

1

D5

0

D4

0

D3

0

D2

1

D1

0

D0

1

FUNCTION

(1)

Reserved

(1) Default values are in bold.

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7.7.2.18 AGL Control Register (0x46)

Table 22. AGL Control Register (0x46)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

(1)

Reserved

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

–

D6

0

–

D5

–

0

1

–

D4

–

0

–

D3

–

0

1

–

D2

–

0

1

–

D1

–

0

1

–

D0

–

0

1

Reserved

(1)

AGL4 turned OFF

AGL4 turned ON

AGL3 turned OFF

AGL3 turned ON

AGL2 turned OFF

AGL2 turned ON

AGL1 turned OFF

AGL1 turned ON

(1) Default values are in bold.

7.7.2.19 PWM Switching Rate Control Register (0x4F)

PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown.

Table 23. PWM Switching Rate Control Register (0x4F)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

(1)

Reserved

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

–

D6

–

D5

0

D4

0

D3

–

D2

–

D1

–

D0

–

Reserved⁽¹⁾

SRC = 6

–

0

1

0

–

0

1

SRC = 7

–

1

0

SRC = 8⁽¹⁾

–

1

0

1

SRC = 9

–

1

0

1

0

Reserved

–

1

–

(1) Default values are in bold.

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7.7.2.20 Bank Switch and EQ Control (0x50)

Table 24. Bank Switching Command (0x50)

D31

0

D30

0

D29

0

D28

0

D27

1

D26

1

D25

1

D24

1

FUNCTION

(1)

Reserved

D23

0

D22

1

D21

1

D20

1

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

D5

D4

D3

D2

D1

D0

(1)

EQ ON

1

–

0

–

0

1

–

EQ OFF (bypass BQ 1–11 of channels 1 and 2)

(1)

–

Reserved

(1)

–

Ignore bank-mapping in bits D31–D8. Use default mapping.

Use bank-mapping in bits D31–D8.

(1)

–

0

–

L and R can be written independently.

L and R are ganged for EQ biquads; a write to the left-channel

biquad is also written to the right-channel biquad. (0x29–0x2F is

ganged to 0x30–0x36. Also, 0x58–0x5B is ganged to 0x5C–0x5F.

–

1

(1)

–

0

–

0

1

–

0

1

X

–

0

1

X

Reserved

(1)

No bank switching. All updates to DAP

Configure bank 1 (32 kHz by default)

Reserved

(1) Default values are in bold.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

As mentioned previously, the TAS5733L device can be used in stereo and mono mode. This section describes

the information required to configure the device for several popular configurations and for integrating the

TAS5733L device into the larger system.

8.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the

supporting required components in each of the System Application Schematics. Where possible, the supporting

component requirements have been consolidated to minimize the number of unique components which are used

in the design. Component list consolidation is a method to reduce the number of unique part numbers in a

design. Consolidation is done to ease inventory management and reduce the manufacturing steps during board

assembly. For this reason, some capacitors are specified at a higher voltage than what would normally be

required. An example of this is a 50-V capacitor can be used for decoupling of a 3.3-V power supply net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of

that value into a single component type. Similarly, several unique resistors, all having the same size and value

but different power ratings can be consolidated by using the highest rated power resistor for each instance of that

resistor value.

While this consolidation can seem excessive, the benefits of having fewer components in the design can far

outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere

in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the

capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of

the capacitors should be 1.5 times to 1.75 times the power dissipated in the capacitors during normal use case.

8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components

shown in the component list were intentionally chosen to allow for proper board layout, component placement,

and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane

extends from the TAS5733L device between two pads of a surface mount component and into to the surrounding

copper for increased heat-sinking of the device. While components can be offered in smaller or larger package

sizes, the package size should remain identical to that used in the application circuit as shown. This consistency

ensures that the layout and routing can be matched very closely, optimizing thermal, electromagnetic, and audio

performance of the TAS5733L device in circuit in the final system.

8.1.1.2 Amplifier Output Filtering

The TAS5733L device is often used with a low-pass filter, which is used to filter out the carrier frequency of the

PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive

element L and a capacitive element C to make up the 2-pole filter. The L-C filter removes the carrier frequency,

reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply.

The presence and size of the L-C filter is determined by several system level constraints. In some low-power use

cases that do not have other circuits which are sensitive to EMI, a simple ferrite bead or ferrite bead and

capacitor can replace the traditional large inductor and capacitor that are commonly used. In other high-power

applications, large toroid inductors are required for maximum power and film capacitors can be preferred due to

audio characteristics. Refer to the application report Class-D Filter Design (SLOA119) for a detailed description

of proper component selection and design of an L-C filter based upon the desired load and response.

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8.2 Typical Applications

These typical connection diagrams highlight the required external components and system level connections for

proper operation of the device in several popular use cases. Each of these configurations can be realized using

the Evaluation Module (EVM) for the device. These flexible modules allow full evaluation of the device in the

most common modes of operation. Any design variation can be supported by TI through schematic and layout

reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional

information.

8.2.1 Stereo Bridge Tied Load Application

A stereo system generally refers to a system inside which are two full range speakers without a separate

amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are

presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two

separate speakers.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the

audio for the left channel and the other channel containing the audio for the right channel. While the two

channels can contain any two audio channels, such as two surround channels of a multi-channel speaker

system, the most popular occurrence in two channels systems is a stereo pair.

The Stereo BTL Configuration is shown in 图 49.

图 49. Stereo Bridge Tied Load Application

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Typical Applications (接下页)

8.2.1.1 Design Requirements

The design requirements for the Stereo Bridge Tied Load Application of the TAS5733L device is found in 表 25

表 25. Design Requirements for Stereo Bridge Tied Load Application

PARAMETER

EXAMPLE

Low Power Supply

High Power Supply

3.3 V

8 V to 15 V

I²S Compliant Master

I²C Compliant Master

GPIO Control

Digital

(1)

Output Filters

Speaker

Inductor-Capacitor Low Pass Filter

4 Ω minimum.

(1) Refer to SLOA119 for a detailed description on the filter design.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found on the TAS5733L User’s Guide.

The device was tested with this list of components, deviation from this typical application components unless

recommended by this document can produce unwanted results, which could range from degradation of audio

performance to destructive failure of the device. The application report Class-D Filter Design (SLOA119) offers a

detailed description of proper component selection and design of the output filter based upon the modulation

used, desired load and response.

8.2.1.2.2 Control and Software Integration

The TAS5733L device has a bidirectional I²C used to program the registers of the device and to read device

status. The TAS5733LEVM and the PurePath Console GUI are powerful tools that allow the TAS5733L

evaluation, control and configuration. The Register Dump feature of the PurePath Console software can be used

to generate a custom configuration file for any end-system operating mode. Prior approval is required to

download PurePath Console GUI. Please request access at http://www.ti.com/tool/purepathconsole.

8.2.1.2.3 I²C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical

Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part

of the associated passive components for the System Processor. These resistor values should be chosen per the

guidance provided in the I²C Specification.

8.2.1.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5733L are described in previous sections. As discussed, whenever a static digital

pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to

DVDD through a pull-up resistor to control the slew rate of the voltage presented to the digital I/O pins. However,

having a separate pull-up resistor for each static digital I/O line is not necessary. Instead, a single resistor can be

used to tie all static I/O lines HIGH to reduce BOM count.

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8.2.1.2.5 Recommended Startup and Shutdown Procedures

Initialization

Normal Operation

Shutdown

Power Down

3 V

AVDD/DVDD

0 µs

8 V

6 V

PVDD

100 µs

6 V

2 µs

AMP

Config

Exit

SD

Volume and Mute

Commands

Enter

SD

10 µs

Trim

I2C

2 µs

13.5 ms

I2S

1 ms + 1.3 t_START

50 ms

1 ms + 1.3 t_STOP

RST

PDN

100 µs

t_PLL

2 µs

t_PLLhas to be greater than 240 ms + 1.3 t_START, after the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets.

t_START/t_STOP= PWM start/stop time as defined in register 0x1A

图 50. Recommended Start-Up and Shutdown Sequence

8.2.1.2.5.1 Start-Up Sequence

Use the following sequence to power up and initialize the device:

1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.

2. Initialize digital inputs and PVDD supply as follows:

–

Drive RST = 0, PDN = 1, and other digital inputs to their desired state. Wait at least 100 µs, drive RST

high

–

Wait ≥ 13.5 ms.

Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after

AVDD/DVDD reaches 3 V.

–

Wait ≥ 10 µs.

3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.

4. Configure the Digital Audio Processor of the Amplifier via I²C, refer to Section 8.5 Register Maps for more

information.

5. Configure remaining registers.

6. Exit shutdown (sequence defined in Shutdown Sequence).

8.2.1.2.5.2 Normal Operation

The following are the only events supported during normal operation:

1. Writes to master/channel volume registers.

2. Writes to soft-mute register.

3. Enter and exit shutdown (sequence defined in Shutdown Sequence).

注

Event 3 is not supported for 240 ms + 1.3 × t_startafter trim following AVDD/DVDD power-

up ramp (where t_startis specified by register 0x1A).

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8.2.1.2.5.3 Shutdown Sequence

Enter:

1. Write 0x40 to register 0x05.

2. Wait at least 1 ms + 1.3 × t_stop(where t_stopis specified by register 0x1A).

3. If desired, reconfigure by returning to step 4 of initialization sequence.

Exit:

1. Write 0x00 to register 0x05 (exit shutdown command can not be serviced for as much as 240 ms after trim

following AVDD/DVDD power-up ramp).

2. Wait at least 1 ms + 1.3 × t_start(where t_startis specified by register 0x1A).

3. Proceed with normal operation.

8.2.1.2.5.4 Power-Down Sequence

Use the following sequence to power down the device and its supplies:

1. If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of sudden power

loss, assert PDN = 0 and wait at least 2 ms.

2. Assert RST = 0.

3. Drive digital inputs low and ramp down PVDD supply as follows:

–

Drive all digital inputs low after RST has been low for at least 2 µs.

Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs.

4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V.

8.2.1.3 Application Performance Plots

CURVE TITLE

Output Power Vs Supply Voltage Stereo BTL Mode

FIGURE

图 5

Total Harmonic Distortion + Noise Vs Output Power Stereo BTL Mode

Total Harmonic Distortion + Noise Vs Frequency Stereo BTL Mode

Power Efficiency Vs Output Power Stereo BTL Mode

Crosstalk Vs Frequency Stereo BTL Mode

图 10

图 7

图 13

图 15

8.2.2 Mono Parallel Bridge Tied Load Application

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge

Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the

loudspeaker simultaneously using an identical audio signal. The primary benefit of operating this device in PBTL

operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output.

In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance

is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an

audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed

together and sent through a low-pass filter to create a single audio signal which contains the low-frequency

information of the two channels.

The Mono PBTL Configuration is shown in 图 51.

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图 51. Mono Parallel Bridge Tied Load Application

8.2.2.1 Design Requirements

The design requirements for the Mono Parallel Bridge Tied Load Appliction of the TAS5733L device is found in

表 26

表 26. Design Requirements for Mono Parallel Bridge Tied Load Application

PARAMETER

EXAMPLE

Low Power Supply

High Power Supply

3.3 V

8 V to 15 V

I²S Compliant Master

I²C Compliant Master

GPIO Control

Digital

(1)

Output Filters

Speaker

Inductor-Capacitor Low Pass Filter

2 Ω minimum.

(1) Refer to the application report Class-D Filter Design (SLOA119) for a detailed description on the filter design.

8.2.2.2 Detailed Design Procedure

Refer to the Detailed Design Procedure section.

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8.2.2.3 Application Performance Plots

CURVE TITLE

FIGURE

图 23

Output Power Vs Supply Voltage Mono PBTL Mode

Total Harmonic Distortion + Noise Vs Output Power Mono PBTL Mode

Total Harmonic Distortion + Noise Vs Frequency Mono PBTL Mode

Power Efficiency Vs Output Power Mono PBTL Mode

图 20

图 17

图 24

9 Power Supply Recommendations

To facilitate system design, the TAS5733L device requires only a 3.3-V supply in addition to the PVDD power-

stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry.

Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by

built-in bootstrap circuitry requiring only a few external capacitors.

To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed

as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRP_x),

and power-stage supply pins (PVDD). The gate-drive voltage (GVDD_REG) is derived from the PVDD voltage.

Place all decoupling capacitors as close to their associated pins as possible. In addition, avoid inductance

between the power-supply pins and the decoupling capacitors.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BSTRP_x) to the power-stage output pin (AMP_OUT_X). When the power-stage output is low, the bootstrap

capacitor is charged through an internal diode connected between the gate-drive regulator output pin

(GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is

shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. The

capacitors shown in Typical Applications ensure sufficient energy storage, even during minimal PWM duty

cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM

cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For

optimal electrical performance, EMI compliance, and system reliability, each PVDD pin should be decoupled with

a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5733L device is fully protected against erroneous power-stage turn-on due to parasitic gate charging.

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10 Layout

10.1 Layout Guidelines

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and

the layout of the supporting components used around them. The system level performance metrics, including

thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all

affected by the device and supporting component layout. Ideally, the guidance provided in the Application

Information section with regard to device and component selection can be followed by precise adherence to the

layout guidance shown in 图 52. The examples represent exemplary baseline balance of the engineering trade-

offs involved with laying out the device. The designs can be modified slightly as needed to meet the needs of a

given application. For example, in some applications, solution size can be compromised to improve thermal

performance through the use of additional contiguous copper near the device. Conversely, EMI performance can

be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and

additional filtering components.

10.1.1 Decoupling Capacitors

Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. The

placement of the capacitors applies to AVDD and PVDD. However, the capacitors on the PVDD net for the

TAS5733L device deserve special attention. The small bypass capacitors on the PVDD lines of the DUT must be

placed as close the PVDD pins as possible. Not only does placing these devices far away from the pins increase

the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device.

Placement of these components too far from the TAS5733L device may cause ringing on the output pins that can

cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum

Ratings table, damaging the device. For that reason, the capacitors on the PVDD net must be no further away

from their associated PVDD pins than what is shown in the example layouts in the Layout Example section.

10.1.2 Thermal Performance and Grounding

Follow the layout examples shown in the Layout Example section of this document to achieve the best balance

of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance

may be required due to design constraints which cannot be avoided. In these instances, the system designer

should ensure that the heat can get out of the device and into the ambient air surrounding the device.

Fortunately, the heat created in the device naturally travels away from the device and into the lower temperature

structures around the device.

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.

These tips should be followed to achieve that goal:

•

Avoid placing other heat-producing components or structures near the amplifier (including above or below in

the end equipment).

•

Use a higher layer count PCB if possible to provide more heat sinking capability for the TAS5733L device and

to prevent traces of copper signal and power planes from breaking up the contiguous copper on the top and

bottom layer.

•

Place the TAS5733L device away from the edge of the PCB when possible to ensure that heat can travel

away from the device on all four sides.

Avoid cutting off the flow of heat from the TAS5733L device to the surrounding areas with traces or via

strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular

to the device.

•

Unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads, orient it so that the narrow end of the passive component is facing the TAS5733L

device. Because the ground pins are the best conductors of heat in the package, maintain a contiguous

ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as

possible.

56

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

10.2 Layout Example

图 52. Layout Example (Stereo) - Top View Composite

图 53. Layout Example (Stereo) - Top Layer

图 54. Layout Example (Stereo) - Bottom Layer

57

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

Layout Example (接下页)

图 55. Layout Example (Mono) - Top View Composite

图 56. Layout Example (Mono) - Top Layer

图 57. Layout Example (Mono) - Bottom Layer

58

TAS5733L

www.ti.com.cn

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

11 器件和文档支持

11.1 商标

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

59

TAS5733L

ZHCSEX0A –MARCH 2016–REVISED MARCH 2016

www.ti.com.cn

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

60

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5733LDCAR

HTSSOP DCA

48

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DCA 48

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TAS5733LDCAR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DCA HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TAS5733LDCA

48

40

530

11.89

3600

4.9

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DCA 48

12.5 x 6.1, 0.5 mm pitch

HTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224608/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS5733LDCAR
厂家：	TEXAS INSTRUMENTS
描述：	具有 EQ 和 AGL 功能的 10W 立体声、20W 单声道、8V 至 16.5V、数字输入、开环 D 类音频放大器 \| DCA \| 48 \| 0 to 85 放大器光电二极管商用集成电路音频放大器
文件：	总70页 (文件大小：2910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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