TAS5768MDCA [TI]
具有 1SPW 的 50W 立体声、100W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类智能音频放大器 | DCA | 48 | -25 to 85;
| 型号： | TAS5768MDCA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1SPW 的 50W 立体声、100W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类智能音频放大器 | DCA | 48 | -25 to 85 放大器 光电二极管 商用集成电路 音频放大器 |
| 文件： | 总87页 (文件大小：3185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS5766M, TAS5768M
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
TAS576xM 2x50-W/4-Ω PurePath™智能放大器
1 特性
2 应用
1
•
PurePath 智能放大器：
•
•
•
•
•
音频接口盒
条形音箱
–
–
优化和保护动圈式扬声器
笔记本电脑
一体化计算机
数字电视
低音 Q 补偿和频率扩展：音量更高、低音增
强、清晰度更佳且保真度更高。
–
热量和偏移限制。
•
立体声 D 类放大器：
3 说明
–
–
–
–
–
–
–
宽电源范围：4.5V 至 26.4V
宽负载范围：2Ω 至 8Ω
TAS576xM PurePath 智能放大器不仅可增强低音效果
和音质保真度，还可提供更高的音量，同时将扬声器驱
动至其热限值和机械限值。
高输出电流：2x 7.5A
峰值输出功率 2x 50W/4Ω
连续功率：2x 20W（不使用散热器）
电源、静音和待机开/关时无喀哒声和噼啪声
TAS576xM 包含两个桥接负载 (BTL) D 类放大器，峰
值功率高达 2x50W/4Ω。在热保护方面，该放大器针对
典型扬声器而设计，可处理扬声器音圈升温期间的高温
峰值，然后将其平均功率降至安全限值。
低输出噪声：<60µVrms（12V 供电时）；
<90µVrms（24V 供电时）
–
低总谐波失真和噪声 (THD+N)：< 0.02%
（1W/4Ω、1kHz 时）
该器件具有 4.5V 至 26.4V 宽电源范围，支持从双节锂
离子电池到固定 24V 电源各类不同的电源选项。
–
热保护、过流保护和短路保护
•
•
可配置的数字音频处理器。
降频混频和具有 10 个 BiQuad 的定制 EQ
数字音频接口：I2S 或时分复用 (TDM) 输入
凭借德州仪器 (TI) 的 PurePath Smart Amp 技术，可
更多地以峰值功率（而非平均额定功率）来驱动扬声
器，且不必担心因偏移或热过载而损坏扬声器。
–
–
–
44.1kHz 和 48kHz 快速 (FS)
器件信息(1)
可配置的数字输出
器件编号
TAS5766M
TAS5768M
封装
封装尺寸（标称值）
•
•
•
•
多段数模转换器 (DAC)，去抖动性能出色
集成高性能音频锁相环 (PLL)
I2C 控制
HTSSOP (48)
12.50mm x 6.10mm
VQFN (48)
7.00mm x 5.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
48 引脚 PowerPAD™散热薄型小外形尺寸
(HTSSOP) 或超薄型四方扁平无引线 (VQFN) 封装
智能放大器概览
Smart SOA
System Inputs
Smart Sense
Sensor Inputs
Smart Amp
Adaptive Control Algorithm
Smart Enhance
Smart Bass, Smart
DRP
Volume
EQ
Smart Protection
Thermal, Excursion
DIN
AMP
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLAS965
TAS5766M, TAS5768M
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
www.ti.com.cn
目录
7.5 Programming........................................................... 36
7.6 Register Maps......................................................... 38
Applications and Implementation ...................... 39
8.1 Application Information............................................ 39
8.2 Typical Applications ................................................ 40
Power Supply Recommendations...................... 47
9.1 AVDD, DVDD, CPVDD Supply ............................... 47
9.2 GVDD Supply.......................................................... 47
9.3 PVCC, AVCC Power Supply................................... 47
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 DC Electrical Characteristics .................................... 7
6.6 AC Electrical Characteristics..................................... 8
6.7 Electrical Characteristics........................................... 9
6.8 Timing Requirements - I2C Bus Timing .................. 10
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 20
8
9
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Examples................................................... 49
11 Register Map Information................................... 51
11.1 Detailed Register Map Descriptions...................... 51
12 器件和文档支持 ..................................................... 75
12.1 相关链接................................................................ 75
12.2 商标....................................................................... 75
12.3 静电放电警告......................................................... 75
12.4 术语表 ................................................................... 75
13 机械、封装和可订购信息....................................... 75
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (September 2014) to Revision D
Page
•
Added paragraph to clarify the 3-wire mode of I2S operation.............................................................................................. 41
Changes from Revision B (September 2014) to Revision C
Page
•
•
Added NOTE and additional descriptive text to Applications and Implementation section. ................................................ 39
Moved Detailed Register Map Descriptions section ............................................................................................................ 51
Changes from Revision A (June 2014) to Revision B
Page
•
Added descriptions for CDST[5] through CDST[0] in Register 94 (Hex 0x5E); and changed Bit 6 description from
CDST[6:0] to CDST[6]. ......................................................................................................................................................... 69
Changes from Original (September 2013) to Revision A
Page
•
•
•
将数据表更改为最新格式；将器件信息表添加到了第一页。 .................................................................................................. 1
添加了 TAS5768M 器件.......................................................................................................................................................... 1
添加了 RMT 封装选项............................................................................................................................................................. 1
2
Copyright © 2013–2018, Texas Instruments Incorporated
TAS5766M, TAS5768M
www.ti.com.cn
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
5 Pin Configuration and Functions
RMT Package
48-Pin VQFN
Top View
24
23
22
21
20
19
18
17
16
15
GND 25
PVCC 26
GVDD 27
GAIN/FSW 28
GND 29
14
13
12
11
10
9
GND
PVCC
AVCC
FAULT
GND
INNR 30
INNL
Thermal PAD
Connect to GND
INPR 31
8
INPL
DACR 32
AVDD 33
GND 34
7
DACL
VNEG
CAPM
GND
6
5
SDA 35
4
SCL 36
3
CAPP
CPVDD
DVDD
GPIO1 37
GPIO2 38
2
1
39
40
41
42
43
44
45
46
47
48
Copyright © 2013–2018, Texas Instruments Incorporated
3
TAS5766M, TAS5768M
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
www.ti.com.cn
DCA Package
48-Pin HTSSOP
Top View
BSNR
OUTNR
GND
1
2
3
4
5
6
7
8
9
48
BSNL
47 OUTNL
46 GND
OUTPR
BSPR
45 OUTPL
44 BSPL
43 PVCC
42 PVCC
41 AVCC
PVCC
PVCC
GVDD
GAIN/FSW
40
39
FAULT
GND
GND 10
11
12
13
14
38 INNL
37 INPL
36 DACL
35 VNEG
34 CAPM
33 GND
INNR
INPR
Thermal
PAD
DACR
AVDD
Connect
to GND
GND 15
SDA 16
SCL 17
32
CAPP
GPIO1 18
GPIO2 19
ADR2 20
GPIO3 21
SCLK 22
BCLK 23
DIN 24
31 CPVDD
30 DVDD
29 GND
28 LDOO
27 XSMT/UVP
26 ADR1
25 LRCLK
4
Copyright © 2013–2018, Texas Instruments Incorporated
TAS5766M, TAS5768M
www.ti.com.cn
SYMBOL
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
Pin Functions
HTTSOP
PIN No.
VQFN
PIN No.
TYPE(1)
DESCRIPTION
ADR1
ADR2
AVCC
AVDD
BCLK
26
20
41
14
23
45
39
12
33
42
I
I
LSB address select bit for I2C
2nd LSB address select bit for I2C
Analog Supply – connect to PVCC
Analog Supply
PI
PI
I
Audio data bit clock input
Boot strap negative Left channel output, connect to 220 nF X7R ceramic cap to
OUTNL
BSNL
BSNR
BSPL
BSPR
48
1
19
20
17
22
BST
BST
BST
BST
Boot strap negative Right channel output, connect to 220 nF X7R ceramic cap to
OUTNR
Boot strap positive Left channel output, connect to 220 nF X7R ceramic cap to
OUTPL
44
5
Boot strap positive Right channel output, connect to 220 nF X7R ceramic cap to
OUTPR
CAPM
CAPP
34
5
Charge pump flying capacitor pin for negative rail
Charge pump flying capacitor pin for positive rail
Charge pump power supply, 3.3 V
32
3
CPVDD
DACL
31
2
PI
O
O
I
36
7
Analog output from DAC left channel, ground centered
Analog output from DAC Right channel, ground centered
Audio data input
DACR
DIN
13
32
24
43
DVDD
FAULT
GAIN/FSW
30
1
PI
OD
I
Digital power supply, 3. 3 V
40
9
11
28
General fault reporting, Open Drain, High = normal operation, Low = fault condition
Sets power stage Gain and selects output switching frequency
3, 10, 15,
4, 10, 14, 15,
GND
29, 33, 39, 24, 25, 29, 34,
G
Ground
46
18
19
21
8
48
37
38
40
27
9
GPIO1
GPIO2
GPIO3
GVDD
INNL
I/O
I/O
I/O
PBY
I
General purpose digital input and output port
General purpose digital input and output port
General purpose digital input and output port
Internal Gate drive supply, connect 1uF to GND
Negative audio input for Left channel. Internally biased at 3 V
Negative audio input for Right channel. Internally biased at 3 V
Positive audio input for Left channel. Internally biased at 3 V
Positive audio input for Right channel. Internally biased at 3 V
Internal logic supply rail pin for decoupling, 1.8 V, connect 1 µF to GND
Audio data word clock input
38
11
37
12
28
25
47
2
INNR
30
8
I
INPL
I
INPR
31
47
44
18
21
16
23
I
LDOO
LRCLK
OUTNL
OUTNR
OUTPL
OUTPR
PBY
I
PO
PO
PO
PO
Negative Left channel output
Negative Right channel output
45
4
Positive Left channel output
Positive Right channel output
6, 7, 42,
43
PVCC
13, 26
PI
4.5-V to 26.4-V Power supply
SCL
17
22
16
36
41
35
I
Input clock for I2C
SCLK
SDA
I
System clock input (also referred to as master clock input)
Input data for I2C
I/O
Thermal
pad
49
49
G
Connect Thermal Pad to Ground
VNEG
35
27
6
PO
I
Negative charge pump rail pin for decoupling –3.3 V
Soft mute control : Soft mute (Low) / soft un-mute (High)
XSMT/UVP
46
(1) TYPE: BST=Boot Strap, PO=Power Output, G = General Ground, I= Input, O= Output, I/O = Input or Output, , PBY=Power Bypass, ,
PI=Power Input,.
Copyright © 2013–2018, Texas Instruments Incorporated
5
TAS5766M, TAS5768M
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
Supply Voltage: PVCC, AVCC
30
3.9
6.3
VCC
AVDD, DVDD, CPVDD
V
Input Voltage: INPL, INNL, INPR, INNR
V
VI
Input Voltage: GAIN/FSW, FAULT
Digital Input Voltage: DVDD=3.3V
Operating free-air temperature
–0.3 GVDD+0.3
V
–0.3
–40
–40
–40
–40
3.9
85
V
TA
TJ
°C
°C
°C
°C
Operating Junction temperature, digital die
Operating Junction temperature, power die
125
150
125
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001, all pins(2)
±2000
Electrostatic
discharge
(1)
V(ESD)
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(3)
±500
(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
3
TYP
MAX
26.4
3.6
UNIT
Vcc
Vdd
VIH
PVCC, AVCC
Supply Voltage
V
AVDD, DVDD, CPVDD
3.3
High level input voltage
Low level input voltage
Low level output voltage
2
V
V
V
VIL
0.8
0.8
VOL
FAULT, Rpullup = 100 kΩ, PVCC = 26 V
PVCC = 24 V
3.2
2.5
1.8
0.9
1.8
1.4
1.0
0.5
1
4
3
PVCC = 18 V
RL
Minimum load impedance
Ω
PVCC = 12 V
2
PVCC = 6 V
1
PVCC = 24 V
2.2
1.6
1.2
0.6
4.7
PVCC = 18 V
PBTL Minimum load
impedance
RL_PBTL
Ω
PVCC = 12 V
PVCC = 6 V
Lo
Output filter inductance
Minimum output filter inductance under short-circuit condition
µH
6
Copyright © 2013–2018, Texas Instruments Incorporated
TAS5766M, TAS5768M
www.ti.com.cn
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
6.4 Thermal Information
TAS576xM
RMT (48 PINS)
DCA (48 PINS)
THERMAL METRIC(1)
UNIT
2 LAYER
PCB(3)
4 LAYER PCB(2)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30
15
6
30
14
RθJC(top)
RθJB
13
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
6
0.6
13
ψJB
RθJC(bot)
1.9
0.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For the PCB layout see the TAS576xMRMTEVM User Guide. A 4 layer 60x60mm 1oc PCB was used
(3) For the PCB layout see the TAS576xMDCAEVM User Guide. A 2 layer 60x60mm 1oc PCB was used
6.5 DC Electrical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data, VCC
=
12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Class-D output offset voltage (measured
differentially)
Input is Bipolar Zero data
PVCC = 12 V, gain set to 14 dB
1
10
mV
| VOS |
PVCC = 24 V, gain set to 20 dB
1.5
15
mV
Drain-source on-state resistance, measured
pin to pin
RDS(on)
G
VCC = 24 V, Iout = 500 mA, TJ = 25°C
120
mΩ
Gain pin voltage < 3 V
Gain pin voltage > 3.3 V
XSMT = 2 V
13
19
14
20
15
21
dB
dB
ms
ms
V
Analog Gain from INxx to OUTxx
ton
Turn-on time
1.5
0.8
6.9
tOFF
GVDD
Turn-off time
XSMT = 0.8 V
Gate Drive Supply Voltage
IGVDD ≤ 200 µA
Copyright © 2013–2018, Texas Instruments Incorporated
7
TAS5766M, TAS5768M
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
www.ti.com.cn
6.6 AC Electrical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data, VCC
=
12V to 24V, RL = 4 Ω unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 mVPP ripple at 1 kHz, gain = 20 dB, zero input
signal
KSVR
Power supply ripple rejection
–60
dB
THD+N = 10%, 1 kHz, 24-V supply, 8-Ω load
THD+N = 10%, 1 kHz, 24-V supply, 4-Ω load
Ra = 100 kΩ, Rb = open
30
50
W
W
PO
Peak output power
8
Ra = 20 kΩ, Rb = 100 kΩ
10
Output switch frequency multiple of FS Gain
set to 14 dB
Fsw
Ra = 39 kΩ, Rb = 100 kΩ
12
Ra = 47 kΩ, Rb = 75 kΩ
16
Ra = 51 kΩ, Rb = 51 kΩ
8
Ra = 75 kΩ, Rb = 47 kΩ
10
Output switch frequency multiple of FS Gain
set to 20 dB
Fsw
Ra = 100 kΩ, Rb = 39 kΩ
12
Ra = 100kΩ, Rb = 20 kΩ
16
1W, 1 kHz, 4R load, 12 V supply
1W, 1 kHz, 8R load, 24 V supply
20-22 kHz, A-weighted, 14 dB gain, 12 V supply
20-22 kHz, A-weighted, 20 dB gain, 24 V supply
20-22 kHz, A-weighted, 14 dB gain, 12 V supply
20-22 kHz, A-weighted, 20 dB gain, 24 V supply
VO = 1 Vrms, 20 dB gain, 1 kHz, 4-Ω load
1 kHz, 10 ms, 3-Ω load, 24-V supply
0.05%
0.05%
60
THD+N
VN
Total Harmonic Distortion + Noise
Output integrated noise
µV
µV
dB
dB
dB
A
85
103
106
–90
7.5
SNR
Signal to Noise Ratio
Crosstalk
IP
Peak output current
8
Copyright © 2013–2018, Texas Instruments Incorporated
TAS5766M, TAS5768M
www.ti.com.cn
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
6.7 Electrical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data, VCC
=
12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resolution
16
24
32
Bits
DATA FORMAT (PCM MODE)
I2S, left justified, right justified
and TDM
Audio data interface format
Audio data bit length
Audio data format
16, 24, 32-bit acceptable
MSB First, 2s Complement
fS
Sampling frequency
8
48
kHz
CLOCKS
64, 128, 192, 256, 384, 512,
768, 1024, 1152, 1536, 2048, or
3072 FSCLK, up to 50MHz
System clock frequency
Clock divider uses fractional divide D>0, P=1
Clock divider uses integer divide D=0, P=1
6.7
1
20
20
MHz
MHz
PLL input frequency /SCL Clock
Frequency 400kHz)
DIGITAL INPUT/OUTPUT
Logic Family: 3.3V LVCMOS compatible
VIH
High level input voltage
0.7xDVDD
V
V
0.3 x
DVDD
VIL
low level input voltage
IIH
High level input current
low level input current
High level output voltage
VIN = VDD
VIN = 0 V
10
µA
µA
V
IIL
–10
VOH
IOH = –4 mA
0.8xDVDD
0.22 x
DVDD
VOL
low level output voltage
IOL = 4 mA
V
DAC DYNAMIC PERFORMANCE, MEASURED ON DACL and DACR
THD+N at –1dB
Dynamic range
–90
109
109
109
dB
dB
dB
dB
Signal to noise ratio
Channel separation
DAC ANALOG OUTPUT, MEASURED ON DACL and DACR
Output voltage
2.1
2%
Vrms
mV
Gain error
| % | of FSR
6%
6%
5
Gain mismatch, channel to channel | % | of FSR
1/2%
1
Bipolar zero error
|At bipolar zero|
POWER SUPPLY REQUIREMENTS
DVDD
AVDD
Digital Supply Voltage
3
3
3
3.3
3.3
3.3
12
12
0.5
11
24
0.2
20
32
30
50
3.6
3.6
3.6
15
V
Analog Supply Voltage
Charge-pump supply voltage
V
V
fs = 48 kHz, Input is Bipolar Zero data
fs = 48 kHz, Input is 1 kHz -1 dBFS data
fs = N/A, power Down Mode
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
IDD
DVDD supply current at 3.3V
15
0.8
16
fs = 48 kHz, Input is Bipolar Zero data
fs = 48 kHz, Input is 1kHz -1 dBFS data
fs = N/A, power Down Mode
AVDD/ CPVDD supply current at
3.3V
32
ICC
0.4
35
XSMT = 2 V, no load, PVCC = 12 V
XSMT = 2 V, no load, PVCC = 24 V
XSMT = 0.8 V, no load, PVCC = 12 V
XSMT = 0.8 V, no load, PVCC = 24 V
PVCC Quiescent supply current
50
PVCC Quiescent supply current in
shutdown mode
ICC(SD)
400
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MAX UNIT
6.8 Timing Requirements - I2C Bus Timing
MIN
Standard
Fast
100
kHz
400
tSCL
tBUF
tLOW
tHI
SCL clock frequency
Standard
Fast
4.7
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of th eSCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
µs
µs
µs
µs
µs
µs
1.3
Standard
Fast
4.7
1.3
Standard
Fast
4
0.6
Standard
Fast
4.7
tRS-SU
0.6
tS-HD
Standard
Fast
4
tRS-HD
0.6
Standard
Fast
0.25
tD-SU
0.1
Standard
Fast
0
0.9
µs
tD-HD
Data hold time
0
0.9
Standard
Fast
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
20+ 0.1CB
4
1
µs
tSCL-R
tSCL-R1
tSCL-F
tSDA-R
tSDA-F
tP-SU
Rise time of SCL signal
0.3
Standard
Fast
1
µs
Rise time of SCL signal after a repeated START condition and after an
acknowledge bit
0.3
Standard
Fast
1
µs
Fall time of SCL signal
0.3
Standard
Fast
1
µs
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
0.3
Standard
Fast
1
µs
0.3
Standard
Fast
µs
0.6
CB
tSP
Capacitive load for SDA and SCL line
Pulse width of spike suppressed
400
50
pF
ns
Fast
Noise margin at high level for each connected device (including
hysteresis)
VNH
0.2 VDD
V
Figure 1. Register Access Timing
10
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6.9 Typical Characteristics
All measurements taken at 1kHz, unless otherwise noted. Measurements were made using the TAS5766MDCA EVM.
10
10
Analog Gain =14dB
PO = 0.5W
PO = 1W
PO = 2.5W
Analog Gain =14dB
PO = 1W
PO = 2.5W
P
O = 5W
DAC Gain = −6dB
PVCC = 6V
TA = 25°C
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
RL = 4Ω
RL = 4Ω
1
1
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G002
G003
Figure 2. Total Harmonic Distortion + Noise vs Frequency
Figure 3. Total Harmonic Distortion + Noise vs Frequency
10
10
Analog Gain =20dB
PO = 1W
PO = 5W
PO = 10W
Analog Gain =20dB
PO = 1W
PO = 5W
PO = 10W
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 4Ω
RL = 8Ω
1
1
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G004
G005
Figure 4. Total Harmonic Distortion + Noise vs Frequency
Figure 5. Total Harmonic Distortion + Noise vs Frequency
10
10
Analog Gain = 14dB
Analog Gain = 14dB
DAC Gain = −6dB
PVCC = 6V
TA = 25°C
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
RL = 4Ω
RL = 4Ω
1
1
fs = 384kHz
fs = 384kHz
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
Output Power (W)
1
10
0.01
0.1
1
10
30
Output Power (W)
G006
G007
Figure 6. Total Harmonic Distortion + Noise vs Power
Figure 7. Total Harmonic Distortion + Noise vs Power
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Typical Characteristics (continued)
All measurements taken at 1kHz, unless otherwise noted. Measurements were made using the TAS5766MDCA EVM.
10
10
Analog Gain = 20dB
Analog Gain = 20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
RL = 4Ω
RL = 8Ω
1
1
fs = 384kHz
fs = 384kHz
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
30
Output Power (W)
Output Power (W)
G008
G009
Figure 8. Total Harmonic Distortion + Noise vs Power
Figure 9. Total Harmonic Distortion + Noise vs Power
10
10
Analog Gain = 14dB
Analog Gain = 14dB
DAC Gain = −6dB
PVCC = 6V
TA = 25°C
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
RL = 4Ω
RL = 4Ω
1
1
fs = 768kHz
fs = 768kHz
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
Output Power (W)
1
10
0.01
0.1
1
10
30
Output Power (W)
G010
G011
Figure 10. Total Harmonic Distortion + Noise vs Power
Figure 11. Total Harmonic Distortion + Noise vs Power
10
10
Analog Gain = 20dB
Analog Gain = 20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
RL = 4Ω
RL = 8Ω
1
1
fs = 768kHz
fs = 768kHz
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
30
Output Power (W)
Output Power (W)
G012
G013
Figure 12. Total Harmonic Distortion + Noise vs Power
Figure 13. Total Harmonic Distortion + Noise vs Power
12
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Typical Characteristics (continued)
All measurements taken at 1kHz, unless otherwise noted. Measurements were made using the TAS5766MDCA EVM.
30
360
300
240
180
120
60
30
360
300
240
180
120
60
Amplitude
Phase
Amplitude
Phase
25
25
20
20
15
15
10
10
5
5
0
0
0
0
−5
−60
−120
−180
−240
−300
−360
−5
−60
−120
−180
−240
−300
−360
−10
−15
−20
−25
−30
−10
−15
−20
−25
−30
Analog Gain =20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 4Ω
LCFILTER =680nF + 10 µH
fs=384kHz
Analog Gain =20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 4Ω
LCFILTER =330nF + 4.7 µH
fs=768kHz
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
G014
G015
Figure 14. Gain/Phase vs Frequency
Figure 15. Gain/Phase vs Frequency
50
45
40
35
30
25
20
15
10
5
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Analog Gain =20dB
Analog Gain =20dB
DAC Gain = 3dB
TA = 25°C
RL = 8Ω
DAC Gain = 3dB
TA = 25°C
RL = 4Ω
THD+N = 1%
THD+N = 10%
THD+N = 1%
THD+N = 10%
0
0
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
G016
G017
Thermally limited for dashed lines
Thermally limited for dashed lines
Figure 16. Maximum Output Power vs Supply Voltage
Figure 17. Maximum Output Power vs Supply Voltage
100
100
90
80
70
60
50
40
30
90
80
70
60
50
40
30
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 8Ω
fs = 384kHz
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 4Ω
fs = 384kHz
PVCC = 6
PVCC =12V
PVCC = 24V
PVCC = 6
PVCC =12V
PVCC = 24V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
Output Power (W)
G018
G019
Figure 18. Power Efficiency vs Output Power
Figure 19. Power Efficiency vs Output Power
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Typical Characteristics (continued)
All measurements taken at 1kHz, unless otherwise noted. Measurements were made using the TAS5766MDCA EVM.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 8Ω
fs = 768kHz
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 4Ω
fs = 768kHz
PVCC = 6
PVCC =12V
PVCC = 24V
PVCC = 6
PVCC =12V
PVCC = 24V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
Output Power (W)
Output Power (W)
G020
G021
Figure 20. Power Efficiency vs Output Power
Figure 21. Power Efficiency vs Output Power
0
0
Analog Gain =20dB
Analog Gain =20dB
−10
DAC Gain = 0dB
PVCC = 24V
DAC Gain = 0dB
−10
PVCC = 12VDC+100mVp−p
TA = 25°C
RL = 8Ω
−20
TA = 25°C
RL = 4Ω
−20
−30
−40
−30
−40
−50
−60
−70
−80
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−90
Right to Left
Left to Right
Left Channel
Right Channel
−100
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G022
G023
Figure 22. Crosstalk vs Frequency
Figure 23. Supply Ripple Rejection vs Frequency
120
100
90
80
70
60
50
40
30
20
10
0
Analog Gain =20dB
115
110
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
DAC Gain = 3dB
TA = 25°C
RL =3Ω
Analog Gain = 20dB
DAC Gain = 0dB
PVCC = 6
TA = 25°C
RL = 2Ω
PVCC =12V
PVCC = 24V
THD+N = 1%
THD+N = 10%
fs = 384kHz
0
0
5
10
15
20
25
30
35
40
45
50
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
Output Power (W)
G024
G025
Thermally limited for dashed lines
Figure 24. Power Efficiency (PBTL) vs Output Power
Figure 25. Maximum Output Power vs Supply Voltage
14
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Typical Characteristics (continued)
All measurements taken at 1kHz, unless otherwise noted. Measurements were made using the TAS5766MDCA EVM.
10
10
Analog Gain =14dB
PO = 1W
PO = 5W
PO =10W
Analog Gain =24dB
PO = 1W
PO = 10W
PO =25W
DAC Gain = 0dB
PVCC =12V
TA = 25°C
DAC Gain = 0dB
PVCC =24V
TA = 25°C
RL = 2Ω
RL = 4Ω
1
1
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G027
G028
Figure 26. Total Harmonic Distortion + Noise (PBTL)
vs Frequency
Figure 27. Total Harmonic Distortion + Noise (PBTL)
vs Frequency
10
10
Analog Gain = 14dB
Analog Gain = 20dB
DAC Gain = 0dB
PVCC = 12V
TA = 25°C
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 2Ω
1
RL =4Ω
1
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
1
10
50
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
G029
G030
Figure 28. Total Harmonic Distortion + Noise (PBTL)
vs Power
Figure 29. Total Harmonic Distortion + Noise (PBTL)
vs Power
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7 Detailed Description
7.1 Overview
The TAS576xM PurePath Smart Amp enhance the bass, sound fidelity and increased loudness by driving the
speaker to its thermal and mechanical limits.
The TAS576xM contains two BTL class-D amplifiers that supply up to 2 x 50W peak power into 4 Ω. The
amplifier is thermally designed to match the typical speaker so it can withstand high peaks for the time it takes
the speaker voice-coil to heat up; it then lowers the average power to safe operating limits.
The wide supply range of 4.5 V to 26.4 V enables the use of different power supply options from 2-cell Li-Ion
batteries to fixed 24-V supply.
The Smart Amp is available with two different class-D amplifier modulations: BD-mode in the TAS5766M; and,
1SPW-mode in the TAS5768M.
TI's PurePath Smart Amp technology allows speakers to be driven with more peak power than their average-
power rating, without damage to the speaker by voice coil over excursion or thermal overload.
Sophisticated speaker models (electro-mechanical-thermal) are used as a foundation for the protection and
enhancement of the system. This is done by modeling the loudspeaker in the on-chip miniDSP and running an
adaptive algorithm that modifies the output based on the modeled conditions of the speaker.
TI provides a PurePath Console (PPC) GUI, including a TI learning board that measures the loudspeaker
parameters. The PPC GUI generates the code for download to the device on boot-up.
Smart Amp technology in the TAS576xM uses information from the SOA (Safe Operating Area) characterization
details for the loudspeaker, as well as real-world temperature, and uses this data in an adaptive control algorithm
in order to control Smart Bass and Smart DRP (Dynamic Range Preservation). The protection side of the
algorithm is also used for thermal protection and mechanical voice coil excursion protection.
7.2 Functional Block Diagram
DVDD 3.3V
PVCC 4.5 to 26V
DOUT
(GPIO3)
OUTPR
OUTNR
Current
Segment
DAC
Closed
Loop
AMP
DIN
LRCLK
BCLK
I²S
Volume
&
Gain
EQ:
Serial
Audio
Port
10x
BiQuad
Mute & SD-Control
Control
Speaker
( SCLK )
Optional
High/Low-
pass
&
Mono
OUTNL
OUTPL
Enhancement
&
Protection
Current
Segment
DAC
Closed
Loop
AMP
mixer
Fully
Integrated PLL
Amplifier Gain & SW Freq adjust
Fault reporting
I²C
Adress
Mute
GPIO‘s
GAIN/
FAULT
FSW
SCL
SDA ADR1 ADR2
GPIO1 GPIO2
XSMT
/UVP
16
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7.3 Feature Description
7.3.1 Smart SOA
The "Safe Operating Area" (SOA) for a loudspeaker is based on its electro-mechanical-thermal model.
Depending on a speaker's inefficiency, some of the power is dissipated as heat rather than mechanical/acoustic
energy. By understanding the characteristics of the speaker, Smart Amp is able to drive the speaker harder,
without causing the speaker to thermally overload; or, suffer voice coil over-exclusion and fail. SMART SOA are
parameters that are differentiated by a PPC GUI into coefficients that the algorithm uses.
7.3.2 Smart BASS
Smart Bass is an intelligent True Bass Alignment algorithm. Smart Bass uses the combination of the speaker
model and a desired target response selected by the user to equalize the speaker in the bass region. This target
response is critical for the sound character and the user can apply the same target response to very different
speakers and get the same sound.
In conventional adaptive Bass Boost Algorithms, designers need to vary the amount of bass boost whenever the
output volume is changed. This approach is very much an "open loop" process. Smart Bass is a new proprietary
algorithm that combines: True bass extension (in bandwidth and amplitude) and Psycho-acoustic bass extension,
with a smart adaptive control.
Smart Bass varies the mix of True Bass extension and Psycho-acoustic bass extension in real time, depending
on the loudspeakers position in its SOA.
Smart Bass dynamically switches between True Bass and Psycho-acoustic extension based on a number of
parameters such as:
•
•
•
•
•
•
Capabilities and properties of the speaker, including Q compensation
Music type
Volume setting
Temperature
User preferences
Designer preferences
7.3.3 Smart Protection
The two main failure mechanisms for loudspeakers are over temperature and over excursion. By modeling the
current state of the speaker, Smart Protection adaptively changes various settings in Smart Amplifier to avoid
over temperature and over excursion. Design engineers must first provide details of the loudspeaker (driver and
enclosure) into the GUI. From there the appropriate coefficients are generated for the algorithm.
7.3.4 Implementing a Real World Design
Traditionally, system developers and hardware engineers use graphic equalizers in trial-and-error fashion to
boost the bass for each new speaker until the sound is right (or "good enough" in many cases). However, this
typically results in a strange combined response with too much phase shift. This process must be repeated every
time a new speaker is selected. The Smart Bass concept uses the GUI to select a desired target response takes
the speaker out of the equation. By this approach users can obtain a target response with minimum phase warp
and time domain ringing which gives a speedy and tight bass. Conversely, users can select a target response
that has lots of ringing to give a classical heavy ‘oomph’ bass.
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Feature Description (continued)
7.3.5 Modulation Schemes
7.3.5.1 BD-Modulation
The TAS5766M uses this modulation, it is a modulation scheme that allows operation without the classic LC
reconstruction filter when the amp is driving an inductive load with short speaker wires. Each output is switching
from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that
there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than
50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for
negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period,
reducing the switching current, which reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 30. BD-Modulation
18
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Feature Description (continued)
7.3.5.2 1SPW-Modulation
The TAS5768M uses this modulation, the 1SPW mode alters the normal modulation scheme in order to achieve
higher efficiency with a slight penalty in THD degradation and more attention required in the output filter
selection. In 1SPW mode the outputs operate at ~15% modulation during idle conditions. When an audio signal
is applied one output will decrease and one will increase. The decreasing output signal will quickly rail to GND at
which point all the audio modulation takes place through the rising output. The result is that only one output is
switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of
switching losses. The THD penalty in 1SPW mode is minimized by the high performance feedback loop. The
resulting audio signal at each half output has a discontinuity each time the output rails to GND. This can cause
ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of
filter used.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
Figure 31. 1SPW-Modulation
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7.4 Device Functional Modes
7.4.1 Device Protection System
The TAS576xM contains a complete set of protection circuits carefully designed to make system design efficient
as well as to protect the device against any kind of permanent failures due to short circuits, overload, over
temperature, and under-voltage. If an error is detected, the FAULT pin signals according to Table 1.
Table 1. TAS576xM Device Protections
TRIGGERING CONDITION
(TYPICAL VALUE)
LATCHED/
SELF-CLEARING
FAULT
FAULT
ACTION
Over Current
Output short or short to PVCC or GND
TJ > 150°C
Low
Low
Low
High
High
Output high impedance
Output high impedance
Output high impedance
Output high impedance
Output high impedance
Self-clearing
Self-clearing
Self-clearing
Self-clearing
Self-clearing
Over Temperature
Too High DC offset
Under Voltage on PVCC
Over voltage on PVCC
DC output voltage
PVCC < 4.5 V
PVCC > 27 V
7.4.1.1 Over Current Protection
The TAS576xM has protection from over current conditions caused by a short circuit or over load on the output
stage. The fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a high
impedance state when the over current is detected. The outputs are automatically re-engaged after a 1.3s off
time.
7.4.1.2 Thermal Protection
Thermal protection on the TAS576xM prevents damage to the device when the internal die temperature exceeds
150°C. There is a 15°C hysteresis on this trip point. When the die temperature exceeds the thermal trip point, the
device enters into the shutdown state and the outputs are put in high impedance mode. The outputs are
automatically re-engaged after a 1.3s off time if the temperature is below the trip point.
7.4.1.3 DC Protection
DC protection on the TAS576xM prevents damage to the attached speaker when the output DC voltage exceeds
20% of supply voltage. When the voltage exceeds the trip point, the device enters into the shutdown state and
the outputs are put in high impedance mode. The outputs are automatically re-engaged after a 0.65 s off time if
the voltage is below the trip point.
7.4.2 Reset and System Clock Functions
7.4.2.1 Power-On Reset Function
The TAS576xM includes a power-on reset function shown in Figure 32. With DVDD > 2.8 V, the power-on reset
function is enabled. After the initialization period, the TAS576xM is set to its default reset state.
Figure 32. Power-On Reset Timing, DVDD = 3.3V
20
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7.4.2.2 System Clock Input
The TAS576xM requires a system clock to operate the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCLK input (pin 12) and supports up to 50MHz. The TAS576xM
system-clock detection circuit automatically senses the system-clock frequency. The Smart AMP processing
block only supports 44.1 kHz and 48kHz sampling rates even though the hardware supports all the common
audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz–44.1 kHz–48kHz), (88.2 kHz–96 kHz), (176.4
kHz–192 kHz), and 384 kHz with ±4% tolerance.
Values in the parentheses are "grouped" when detected, e.g. 88.2 kHZ and 96 kHz are detected as "double
rate", 32 kHz, 44.1 kHz and 48 kHz will be detected as "single rate". The sampling frequency detector sets the
clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically.
Table 2 shows examples of system clock frequencies for common audio sampling rates.
SCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in
software mode by configuring various PLL and clock-divider registers. This programmability allows the device to
become a clock master and drive the host serial port with LRCLK and BCLK, from a non-audio related clock (for
example, using 12 MHz to generate 44.1 kHz (LRCLK) and 2.8224 MHz (BCLK) )
Figure 33 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise.
Table 2. System Master Clock Inputs for Audio Related Clocks
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING FREQUENCY
128 fs
5.6488
6.1440
192 fs
8.4672
9.2160
256 fs
11.2896
12.2880
384 fs
16.9344
18.4320
512 fs
22.5792
24.5760
768 fs
33.8688
36.8640
1024 fs
45.1584
49.1520
44.1 kHz
48 kHz
Figure 33. Timing Requirement for SCLK Input
Table 3. Timing Requirements for SCLK Input
MIN
MAX
UNIT
ns
tSCY
System clock pulse cycle time
20
8
1000
tSCLK System clock pulse width, High
H
ns
tSCLK System clock pulse width, Low
9
ns
L
7.4.3 System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the output.
The 3-wire source reduces the need for a high frequency SCLK, making PCB layout easier, and reduces high
frequency electromagnetic interference.
The user must set all the PLL registers and clock divider registers for referencing BCLK. See Clock Generation
and PLL for more information.
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Table 4. BCLK Rates (MHz) by LRCLK Sample Rate for
PLL Operation
BCLK (fS)
Sample f (kHz)
32
64
44.1
48
1.4112
1.536
2.8224
3.072
7.4.4 Clock Generation and PLL
The TAS576xM supports a wide range of options to generate the required clocks for the DAC section as well as
interface and other control blocks as shown in Figure 34.
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCLK or SCLK.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page
0, Register 13, D(6:4). The PLL reference clock can then be routed through highly-flexible clock dividers shown
in Table 5 to generate the various clocks required for the DAC, Negative Charge Pump (NCP), Internal modulator
and sections. The TAS576xM provides several programmable clock dividers to achieve a variety of sampling
rates for the DAC and clocks for the NCP, OSR, and the OSRCK for OSR must be set at 16fS frequency by
DOSR on Page0, Register 30, D(6:0).
If PLL functionality isn’t required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an
external SCLK is required.
Table 5. PLL Configuration Registers
CLOCK MULTIPLEXER
SRCREF
DIVIDER
DDSP
FUNCTION
PLL Reference
FUNCTION
BITS
Page 0, Register 13, D(6:4)
BITS
Clock divider
Page 0, Register 27, D(6:0)
Page 0, Register 28, D(6:0)
Page 0, Register 29, D(6:0)
Page 0, Register 30, D(6:0)
Page 0, Register 32, D(6:0)
Page 0, Register 33, D(7:0)
DDAC
DAC clock divider
NCP clock divider
OSR clock divider
External BCLK Div
External LRCLK Div
DNCOP
DOSR
DBCLK
DLRK
22
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Figure 34. PLL Clock Source and Clock Distribution
7.4.5 PLL Calculation
The TAS576xM has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the
audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the
PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN)
supports clock frequencies from 512 kHz to 50 MHz and is register programmable to enable generation of
required sampling rates with fine precision.
The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL
is enabled, the PLL output clock PLLCK is given by Equation 1:
PLLCKIN´R ´ J.D
PLLCKIN´R ´K
PLLCK =
or PLLCK =
P
P
(1)
R = 1, 2, 3,4, … 15, 16
J = 0 4,5,6, … 63 and D = 0000, 0001, 0002, … 9999
K = [J value].[D value]
P 0 1, 2, 3, … 15
R, J, D and P are programmable. J is the integer portion of K (the number to the left of the decimal point)
while D is the fraction portion of K (the number to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
•
•
•
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
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•
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied:
•
•
•
1 MHz ≤ ( PLLCKIN / P ) ≤20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
1 ≤ J ≤ 63
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:
•
•
•
•
6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
4 ≤ J ≤ 11
R = 1
When the PLL is enabled:
•
•
fS = (PLLCLKIN × K × R) / (2048 × P)
The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.
Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Values are written to the registers in Table 6.
Table 6. PLL Registers
DIVIDER
PLLE
FUNCTION
PLL enable
PLL P
BITS
Page 0, Register 4, D(0)
Page 0, Register 20, D(3:0)
Page 0, Register 21, D(5:0)
Page 0, Register 22, D(5:0)
Page 0, Register 23, D(7:0)
Page 0, Register 24, D(3:0)
PPDV
PJDV
PLL J
PDDV
PLL D
PRDV
PLL R
Table 7. PLL Configuration Recommendations
COLUMN
fS (kHz)
DESCRIPTION
Sampling frequency
RSCLK
Ration between sampling frequency and SCLK frequency (SCLK frequency = RSCLK x sampling frequency)
System master clock frequency at SCLK input (pin 22)
PLL VCO frequency as PLLCK
SCLK (MHz)
PLL VCO (MHz)
P
One of the PLL coefficients
PLL REF (MHz)
M = K × R
K = J.D
Internal reference clock frequency which is produced by SCLK / P
The final PLL multiplication factor computed from K and R as described in Equation 1
One of the PLL coefficients
R
One of the PLL coefficients
PLL fS
Ratio between fS and PLL VCO frequency (PLL VCO / fS)
Ratio between operating clock rate and fS (PLL fS / NMAC)
The clock divider value in Table 4
DSP fS
NMAC
DSP CLK (MHz)
MOD fS
The operating frequency as DSPCK in Clock Generation and PLL
Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
DAC operating frequency as DACCK in Clock Generation and PLL
DAC clock divider value in Table 4
MOD f(kHz)
NDAC
DOSR
OSR clock divider value in Table DOSR 7 for generating OSRCK in Clock Generation and PLL. DOSR must be
chosen so that MOD fS / DOSR = 16 for correct operation.
24
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Table 7. PLL Configuration Recommendations (continued)
COLUMN
NCP
DESCRIPTION
NCP (negative charge pump) clock divider value in Table 4
CP f
Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error
Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
●
●
This number is typically zero but can be non-zero especially when K is not an integer (D is % Error not zero).
This number may be non-zero only when the TAS576xM acts as a master
Table 8. Recommended Clock Divider Settings for PLL as Master Clock
44.1 kHz
RSCLK
SCLK (MHz)
PLL VCO (MHz)
P
32
1.4112
90.3168
1
64
2.8224
90.3168
1
128
5.6448
90.3168
1
192
8.4672
90.3168
3
256
11.2896
90.3168
2
384
16.9344
90.3168
3
512
22.5792
90.3168
3
768
1024
33.8688
45.1584
90.3168
90.3168
3
3
PLL REF (MHz)
M = K×R
K = J.D
1.4112
64
2.8224
32
5.6448
16
2.8224
32
5.6448
16
5.6448
16
7.526
12
11.29
15.053
8
6
32
16
16
32
16
16
12
8
1
6
1
R
2
2
1
1
1
1
1
PLL fS
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
DSP fS
NMAC
DSP CLK (MHz)
MOD fS
45.1584
128
5644.8
16
45.1584
128
5644.8
16
45.1584
128
45.1584
128
5644.8
16
45.1584
128
45.1584
128
45.1584
128
45.1584
128
5644.8
16
45.1584
128
5644.8
16
MOD f (kHz)
NDAC
5644.8
16
5644.8
16
5644.8
16
5644.8
16
DOSR
8
8
8
8
8
8
8
8
8
% ERROR
NCP
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
CP f (kHz)
1411.2
1411.2
1411.2
1411.2
48kHz
192
9.216
98.304
3
1411.2
1411.2
1411.2
1411.2
1411.2
RSCLK
SCLK (MHz)
PLL VCO (MHz)
P
32
1.536
98.304
1
64
3.072
98.304
1
128
6.144
98.304
1
256
12.288
98.304
2
384
18.432
98.304
3
512
24.576
98.304
3
768
36.864
98.304
3
1024
49.152
98.304
3
PLL REF (MHz)
M = K×R
K = J.D
1.536
64
3.072
32
6.144
16
3.072
32
6.144
16
6.144
16
8.192
12
12.288
8
16.384
6
32
16
16
32
16
16
12
8
6
R
2
2
1
1
1
1
1
1
1
PLL fS
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
2048
1024
2
DSP fS
NMAC
DSP CLK (MHz)
MOD fS
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
49.152
128
6144
16
MOD f (kHz)
NDAC
DOSR
8
8
8
8
8
8
8
8
8
% ERROR
NCP
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
CP f (kHz)
1536
1536
1536
1536
1536
1536
1536
1536
1536
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7.4.6 Audio Data Interface
7.4.6.1 Audio Serial Interface
The audio interface port is a 3-wire serial port with the signals LRCLK (pin 15), BCLK (pin 13), and DIN (pin 14).
BCLK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the
audio interface. Serial data is clocked into the TAS576xM on the rising edge of BCLK. LRCLK is the serial audio
left/right word clock.
Table 9. TAS576xM Audio Data Formats, Bit Depths and Clock rates
FORMAT
I2S/LJ
DATA BITS
32, 24, 20, 16
32, 24, 20, 16
LRCLK
SCH RATE
128–3072
128–3072
BCLK RATE
64, 48, 32
128, 265
44.1 or 48 kHz
44.1 or 48 kHz
TDM
The TAS576xM requires the synchronization of LRCLK and system clock, but does not require a specific phase
relation between LRCLK and system clock.
If the relationship between LRCLK and system clock changes more than ±5 SCLK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCLK and system clock is completed.
7.4.6.2 PCM Audio Data Formats and Timing
The TAS576xM supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected via Register (Pg0Reg40). All formats require binary 2s-complement, MSB-first audio data,
up to 32-bit audio data is accepted.
The TAS576xM also supports right-justified and TDM. I2S, LJ, RJ, and TDM are selected using Register
(Pg0Reg40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default
setting is I2S and 24 bit word length. The I2S slave timing is shown in Figure 35.
Figure 35. TAS576xM Serial Audio Timing – Slave
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Table 10. Audio Interface Slave Timing
MIN
40
16
16
8
MAX
UNIT
ns
tBCY
tBCL
tBCH
tBL
BCLK pulse Cycle Time
BCLK pulse Width LOW
ns
BCLK pulse Width HIGH
BCLK Rising Edge to LRCLK Edge
BCLK frequency at DVDD = 3.3V
LRCLK Edge to BCLK Rising Edge
DATA set Up time
ns
ns
tBCLK
tLB
24.576
MHz
ns
8
8
8
tDS
ns
tDH
DATA Hold Time
ns
tDOD
DATA delay time from BCLK falling edge
15
ns
The TAS576xM can act as an I2S master, generating BCLK and LRCLK as outputs from the SCLK input.
Table 11. I2S Master Mode Registers
REGISTER
FUNCTION
Page 0, register 9, D(0), D(4) and D85)
Register 32, D(6:0)
I2S master Mode select
BCLK divider and LRCLK divider
Register 33, D(7:0)
The I2S master timing is shown in Figure 36 and Table 12.
Figure 36. TAS576xM Serial Audio Timing - Master
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Table 12. Audio Interface Master Timing
MIN
40
16
16
8
MAX
UNIT
ns
tBCY
tBCL
tBCH
tBL
BCLK pulse Cycle Time
BCLK pulse Width LOW
BCLK pulse Width HIGH
BCLK Rising Edge to LRCLK Edge
BCLK frequency at DVDD = 3.3V
LRCLK Edge to BCLK Rising Edge
DATA set Up time
ns
ns
ns
tBCLK
tLB
24.576
MHz
ns
8
8
8
tDS
ns
tDH
DATA Hold Time
ns
tDOD
DATA delay time from BCLK falling edge
15
ns
Figure 37. Left Justified Audio Data Format
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Figure 38. I2S Audio Data Format
Figure 39. Right Justified Audio Data Format
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Figure 40. TDM Audio Data Format
Figure 41. TDM 2 Audio Data Format
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Figure 42. TDM 3 Audio Data Format
7.4.7 TAS576xM Audio Processing Options
7.4.7.1 Overview
The TAS576xM features a configurable miniDSP core. The algorithms for the miniDSP are loaded into the device
after power up. The miniDSP has direct access to the digital stereo audio stream, offering the possibility for
advanced DSP algorithms with very low group delay. The miniDSP can run up to 1024 instructions on every
audio sample at a 48 kHz sample rate.
The TAS576xM Smart Amplifier uses a mix of code sources. ROM based process flow and RAM based process
flow. In the program, different algorithms are called from ROM – such as EQ, DRC and Zero Crossing volume
control enabling a faster program load.
7.4.7.2 miniDSP Instruction Register
Registers on Register Pages 152-169 are 25-bit instructions for the miniDSP engine. For details, see Table 21.
Seven (7) bits of Instr(32:25) in Base register +0 are reserved bits. 1 bit of Instr(24) – (LSB) in Base register +0 is
MSB bit of 25-bit instruction. These instructions control miniDSP operation. When the fully programmable
miniDSP mode is enabled and the DAC channel is powered up, the read and write access to these registers is
disabled
7.4.7.3 Digital Output
The TAS576xM supports an SDOUT output. This can be selected within the process flow, and driven out of a
GPIO pin selected in the register map (e.g. Page 0 / Register 80). The I2S output can be fed back to the signal
host and used for echo cancellation.
7.4.7.4 Software
Software selection for the TAS576xM is supported through TI's comprehensive PurePath Console Development
Environment; a powerful, easy-to-use tool designed specifically to simplify development on the TAS576xM
platform. Visit the TAS576xM product folder on www.ti.com to learn more about PurePath Console and the latest
status on available, ready-to-use DSP algorithms.
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7.4.7.5 Process Flow
An example of the default Process Flow available for the TAS576xM in the PurePath Console target is shown
below:
I2S
Input
DACL
Stereo
Volume
Control
Mono
Bass
Mix
Left/Right
DAC
Analog Output
DIN
10
BiQuads
Smart
Amp
DACR
GPIO3
(SDOUT)
I2S
Output
Left
Right
Figure 43. Example Process Flow
This process flow has from input to output:
• Volume block, from -110 db to +6 dB with 0.5 dB steps, including a fixed gain block of 0dB to 12 dB gain
• monobass mixer – mixes the bass into mono below the set frequency, useful for systems where left and right
speaker shares the same cabinet volume, bypassed when not needed.
• 10 Biquads for filtering and EQ. The PPC GUI have an advanced biquad control where various filter and eq
options can be set and controlled.
• SmartAmp block, containing all the blocks for bass Q compensation, bass alignment, excursion control and
power limited
• Digital monitor output enabled on GPIO3
7.4.7.6 Zero Data Detect
The TAS576xM has a zero-detect function. When the device detects the continuous zero data for both L-ch and
R-cn, or separate L-cn and R-ch, Analog mutes are set to both OUTL and OUTR, or separate OUTL and OUTR.
These are controlled by Page0, Register 65, D(2:1) as shown in Table 13.
Continuous Zero data cycles are counted by LRCLK, and the threshold of decision for analog mute can be set by
Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 14. Default values are 0 for both
channels.
Table 13. Zero Detection Mode
ATMUTECTL
VALUE
FUNCTION
Independently L-ch or R-ch are zero data for zero detection
Both L-ch and R-ch have to be zero data for zero detection
Zero detection and analog mute are disabled for R-ch
Zero detection and analog mute are enabled for R-ch
Zero detection and analog mute are disabled for L-ch
Zero detection and analog mute are enabled for L-ch
0
Bit:2
1 (Default)
0
Bit:1
Bit:0
1 (Default)
0
1 (Default)
Table 14. Zero Data Detection Time
ATMUTETIML /ATMUTETIMR
NUMBER of LRCLKs
1024
TIME at 48 kHz
21 ms
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
5120
106 ms
10240
213 ms
25600
533 ms
51200
1.07 sec
2.13 sec
5.33 sec
10.66 sec
102400
256000
512000
32
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7.4.7.7 Power Save Modes
The TAS576xM offers two power-save modes; standby and power-down.
When a clock error (SCLK, BCLK, and LRCLK) or clock halt is detected, the TAS576xM automatically enters
standby mode. The DAC and power amplifier are also powered down. The device can also be placed in standby
mode via software command.
When BCLK and LRCLK remain at a low level for more than 1 second, the TAS576xM automatically enters
power-down mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition
to those disabled in standby mode. The device can also be placed in power-down mode via I2C command.
When expected Audio clocks (SCLK, BCLK, LRCLK) are applied to the TAS576xM, the device starts its power-
up sequence automatically.
Table 15. Power Save Parameter Programming
REGISTER
Page 0, register 2, D(4)
DESCRIPTION
I2C standby-mode command
I2C power-down command
Page 0, register 2, D(0)
Page 0, register 2, D(4) and D(0)
Page 0, register 44, D(2:0)
I2C power-up sequence command (required after I2C standby or power-down command)
Detection time of BCLK and LRCLK halt
7.4.7.8 XSMT Pin (Soft Mute/Soft Un-Mute)
An external digital host controls the TAS576xM soft mute function by driving the XSMT pin with a specific
minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The TAS576xM requires tr and tf times of
less than 20ns. In the majority of applications, this is no problem, however, traces with high capacitance may
have issues.
When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp begins. –1dB
attenuation is then applied every sample time from 0dBFS to –104dBFS.
When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are
applied every sample time from –104dBFS to 0dBFS.
Figure 44. XSMT Timing for Soft Mute and Soft Un-Mute
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7.4.7.9 External Power Sense Undervoltage Protection Mode
The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV back light, or 12-VDC
system supply using a voltage divider created with two resistors. See Figure 45.
* If the XSMT pin makes a transition from “1” to “0” over 6ms or more, the
device switches into external undervoltage protection mode. This mode uses
two trigger levels.
* When the XSMT pin level reaches 2 V, soft mute process begins.
* When the XSMT pin level reaches 1.2 V, analog mute engages, regardless
of digital audio level, and analog shutdown begins. (DAC and related
circuitry powers down).
Figure 45. External Power
Sense
A timing diagram describing this is shown in Figure 46.
NOTE
The XSMT input pin voltage range is from –0.3 V to DVDD + 0.3 V.The ratio of external
resistors must produce a voltage within this input range. Any increase in power supply
(such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD
+0.3V.
For example, if the TAS576xM is monitoring a 12 V input, and dividing the voltage by 4, then the voltage at
XSMT during ideal power supply conditions is 3 V. A voltage spike higher than 14.4 V causes a voltage greater
than 3.6 V (DVDD+0.3) on the XSMT pin, potentially damaging the device. Providing the divider is set
appropriately, any DC voltage can be monitored.
Figure 46. XSMT Timing for Undervoltage Protection
7.4.7.10 Recommended Power Down Sequence
With inadequate system design, the TAS576xM can exhibit pop on power down. Pops are caused by the device
not having enough time to detect power loss and start the muting process.
The TAS576xM evaluation board avoids audible pop with an electrolytic decoupling capacitor. This capacitor
provides enough time between data loss from USB or S/PDIF and power supply loss for the muting process to
take place.
The TAS576xM has two auto-mute functions to mute the device upon power loss (intentional or unintentional).
34
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7.4.7.10.1 XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, then closely followed by a hard
analog mute. This process takes 150 sample times (ts) + 0.2 mS.
7.4.7.10.2 Clock Error Detect
When clock error is detected on the incoming data clock, the TAS576xM family switches to an internal oscillator,
and continues to the drive the output, while attenuating the data from the last known value. Once this process is
complete, the TAS576xM outputs are pulled to ground with 30kΩ.
7.4.7.10.3 Planned Shutdown
These auto-muting processes can be manipulated by system designs to mute before power loss in the following
ways: Assert XSMT low 150ts + 0.2 ms before power is removed, shown in Figure 47.
Figure 47. Assert XSMT Low Example
Stop I2S clocks (SCLK, BCLK, LRCLK) 3ms before power down as shown in Figure 48 below:
Figure 48. Stop I2S Clocks Example
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7.5 Programming
7.5.1 I2C Interface and Slave Address
The TAS576xM supports the I2C serial bus and the data transmission protocol for standard and fast mode as a
slave device.
Table 16. I2C pins and Functions
SIGNAL
SDA
PIN
16
17
20
26
I/O
DESCRIPTION
I2C data
I/O
SCL
I
I
I
I2C clock
ADR2
ADR1
I2C address 2
I2C address 1
7.5.2 Slave Address
Table 17. I2C Slave Address
Address
0x98
D7
D6
D5
D4
D3
ADR2
ADR1
R/W
0
0
1
1
0
1
0
1
0x9A
1
0
0
1
1
x
0x9C
0x9E
The TAS576xM has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory
preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user
defined by the ADR1 and ADR0 pins. A maximum of four TAS576xMs can be connected on the same bus at one
time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E. Each TAS576xM responds when it receives its own
slave address.
7.5.3 Register Address Auto-Increment Mode
Auto-increment mode allows multiple sequential register locations to be written to or read back in a single
operation, and is especially useful for block write and read operations.
Figure 49. Auto Increment Mode
7.5.4 Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit,
data if write or acknowledge if read, and stop condition. The TAS5766M supports only slave receivers and slave
transmitters.
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Figure 50. Packet Protocol
Table 18. Read / Write Operation – Basic I2C Framework
Transmitter
Write
M
St
M
St
M
M
W/
M
S
M
S
M
S
S
ACK
M
M
Sp
S
Data Type
Slave
address
ACK
S
DATA
S
ACK
M
DATA
S
ACK
M
Transmitter
Read
M
Data Type
Slave
R/
ACK
DATA
ACK
DATA
ACK
NACK
Sp
address
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition
7.5.5 Write Register
A master can write to any TAS576xM registers using single or multiple accesses. The master sends a
TAS576xM slave address with a write bit, a register address with auto-increment bit, and the data. If auto-
increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the
data is received properly, the index register is incremented by 1 automatically. When the index register reaches
0x7F, the next value is 0x0. The following table shows the write operation.
Table 19. Write Operation
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave
addr
W
ACK
inc
reg
addr
ACK
Write
data1
ACK
Write
data2
ACK
ACK
Sp
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition; W = Write; ACK = Acknowledge
7.5.5.1 Read Register
A master can read the TAS576xM register. The value of the register address is stored in a indirect index register
in advance. The master sends a TAS576xM slave address with a read bit after storing the register address. Then
the TAS576xM transferes the data which the index points to. When auto-increment is enabled, the index register
is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. The following
table shows the read operation.
Table 20. Read Operation
Transmitter
M
M
M
S
M
S
M
M
M
S
S
M
M
M
Data Type St Slave
addr
W
ACK inc
reg
addr
ACK
Sr
Slave
addr
R
ACK
data
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R 0 read;
NACK = Acknowledge
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7.6 Register Maps
In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255
for next read or write command.
Table 21. Register Map Summary(1)
Register
Description
Register No
Description
No
Page 0
0
44
Clock missing detection period
Auto mute time
Reserved
Page Select register
Analog control register
Standby, Powerdown requests
Mute
59
1
60-64
65-66
67-82
83-85
86,87
88,89
90
2
Auto mute enable and delay
Reserved
3
4
PLL Lock Flag, PLL enable
Reserved
GPIOn output selection
GPIO control
5
6
Reserved
Reserved
7
De-emphasis enable, SDOUT select
GPIO enables & Mute Control
BCLK, LRCLK configuration
DSP GPIO Input
DSP overflow
8
91-94
95-107
108
Sample rate status
Reserved
9
10
Analog mute monitor
Reserved
11
Reserved
109-118
119
12
Master Mode BCLK, LRCLK reset
PLL clock source select
Reserved
GPIO input
13
120
Auto mute flags
Reserved
14-19
20-24
25,26
27
121-125
Page 1
1
PLL dividers
Reserved
Reserved
DSP clock divider
DAC clock divider
NCP clock divider
OSR clock divider
Reserved
2
Analog gain control
Reserved
28
3,4
29
5
Undervoltage protection
Analog mute control
Analog gain boost
REF BG Fast
30
6
31
7
32,33
34
Master mode dividers
FS speed mode
8
9-15
Page 44
Reserved
35,36
IDAC number of DSP clock cycles available in one
audio frame)
37
Ignore various errors
Reserved
1
Coefficient memory (CRAM) control
38,39
40,41
42
Pages 44-52
Pages 62-70
Coefficient buffer – A (256 coeffs x 24 bits)
Coefficient buffer – B (256 coeffs x 24 bits)
I2S configuration
DAC data path
Pages 152-186 Instruction buffer (1024 instruction x 24 bits),
I512 – I1023 are reserved
43
Reserved
Pages 187-255 Reserved
(1) See Detailed Register Map Descriptions.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
One of the most significant benefits of the TAS5766M device is the ability to be used in a variety of applications.
This section details the information needed to configure the device for several popular configurations and
provides guidance on integrating the TAS5766M device into the larger system.
8.1.1 External Component Selection Criteria
The Supporting Component Requirements table in each application description section lists the details of the
supporting required components in each of the System Application Schematics.
Where possible, the supporting component requirements have been consolidated to minimize the number of
unique components which are used in the design. Component list consolidation is a method to reduce the
number of unique part numbers in a design, to ease inventory management, and reduce the manufacturing steps
during board assembly. For this reason, some capacitors are specified at a higher voltage than what would
normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply
net.
In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of
that value into a single component type. Similarly, a several unique resistors, having all the same size and value
but with different power ratings can be consolidated by using the highest rated power resistor for each instance
of that resistor value.
While this consolidation may seem excessive, the benefits of having fewer components in the design may far
outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere
in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the
capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of
the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.
8.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
Because the layout is important to the overall performance of the circuit, the package size of the components
shown in the component list were intentionally chosen to allow for proper board layout, component placement,
and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane
extends from the TAS5766M device between two pads of a surface mount component and into to the
surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or
larger package sizes, it is highly recommended that the package size remain identical to that used in the
application circuit as shown. This consistency ensures that the layout and routing can be matched very closely,
optimizing thermal, electromagnetic, and audio performance of the TAS5766M device in circuit in the final
system.
8.1.3 Amplifier Output Filtering
The TAS5766M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
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Application Information (continued)
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that do not have other circuits which are sensitive to EMI,
a simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are
commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors may be preferred due to audio characteristics. Refer to the application report SLOA119 for a
detailed description on proper component selection and design of an L-C filter based upon the desired load and
response.
8.2 Typical Applications
8.2.1 Stereo Application
+
SDA
1 mF
470 nF
4R
-
SCL
20k
Rb
Ra
3.3V
10mH
SCLK
BCLK
DIN
470 nF
220 nF
100k
PVCC
10mH
220 nF
RIGHT
1 mF
LRCLK
1 mF
1 mF 1 mF
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Power Pad œ Connect to GND
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
220 nF
1 mF
10k
1 mF
1 mF 1 mF
1 mF
1 mF
1 mF
LEFT
220 nF
3.3V
10mH
3.3V
10k
FAULT
-
PVCC
10mH
4R
+
4.5V-26.5V
470 nF
470 nF
470 mF
Figure 51. Typical Stereo Application
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Typical Applications (continued)
8.2.1.1 Design Requirements
The device is configured to have 20 dB analog gain and switch at 768kHz, by the resistor network on the
GAIN/FSW pin 9.
I2C slave address is set to default 0x98, as a result of the two address pins (ADR1, pin 26 and ADR2, pin 20) set
to ground.
In this setup a master clock is supplied to the device on pin 22 (SCLK). the device can also run with 3-wire I2S
by setting the PLL registers as shown in the Clock Generation and PLL section.
When the device is configured to operate in 3-wire mode of operation where BCLK is used as reference to PLL
(NO SCLK), TI recommends shorting PIN23 (BCLK) and PIN22 (SCLK) and configuring the device to use SCLK
as PLL reference.
8.2.1.2 Detailed Design Procedure
For the stereo (BTL) PCB layout, see examples in the Layout section.
A 2.0 system generally refers to a system in which there are two full range speakers without a separate amplifier
path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to
the amplifier via the digital input signal. These two channels are amplified and then sent to two separate
speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover
network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
It is important to note that the SmartAmp Flows which have been developed for specifically for stereo
applications will apply the same equalizer curves to the left channel and the right channel. This minimizes the
needed RAM capabilities of the SmartAmp.
When two signals that are not two separate signals, but instead are derived from a single signal which is
separated into low frequency and high frequency by the signal processor, the application is commonly referred to
as 1.1 or Bi-Amped systems. The 2.0 (Stereo BTL) System application is shown in Figure 51.
8.2.1.2.1 Gain Setting and Output Switch Frequency
The analog class-D amplifier gain of the TAS576xM is set by the voltage divider connected to the GAIN/FSW
control pin. Output Stage switch frequency multiplication is also controlled by the same pin, giving a ratio of 8,
10, 12 or 16x the I2S input sample rate. An internal ADC is used to detect the 8 input states. The first four stages
sets the GAIN to 14 dB, while the next four stages sets the GAIN to 20 dB.
A gain setting of 14 dB is recommended for supply voltages of 12V and lower, while a gain of 20 dB is
recommended for supply voltages up to 26.4 V. Table 22 shows the recommended resistor values and the state
and gain:
Table 22. Gain and FSW
Ra
(to GND)
Rb
(to GVDD)
INPUT
IMPEDANCE
FSW –
RATIO TO LRCLK
FSW w.
44.1 kHz
FSW w.
48 kHz
GAIN
10 0kΩ
20 kΩ
38 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
20 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
60 kΩ
14 dB
14 dB
14 dB
14 dB
20 dB
20 dB
20 dB
20 dB
8
353 kHz
441 kHz
529 kHz
706 kHz
353 kHz
441 kHz
529 kHz
706 kHz
384 kHz
480 kHz
576 kHz
768 kHz
384 kHz
480 kHz
576 kHz
768 kHz
10
12
16
8
60 kΩ
10
12
16
60 kΩ
60 kΩ
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8.2.1.2.2 Gain Setting and Supply Voltage
If the TAS576xM is to be used in systems operating below 6 V it is recommended to change the maximum DAC
output voltage from the nominal 2 Vrms FS(0 dB) to 1 Vrms FS (–6 dB), by setting register 2 on page 1 D4(Lch) /
D0(Rch), Table 23.
Table 23. GAIN and Supply Voltage
SUPPLY VOLTAGE RANGE
4.5 V – 6 V
GAIN (via GAIN/FSW pin)
DAC OUTPUT at FS
1 Vrms
Page 1 / Register 2
00010001
default
14 dB
14 dB
20 dB
6 V – 12 V
2 Vrms
12 V – 26 V
2 Vrms
default
8.2.1.2.3 DAC to AMP AC Coupling
The TAS576xM uses an external ac-coupling capacitor between DACx output and AMP INPx input and a
capacitor from INNx to ground for minimum dc-offset and click & pop during power on/off. Shown as C13, C14,
C19 & C20 in the drawing here.
The AMP INNPx and INNMx input stage is a fully differential input stage and the input impedance changes with
the gain setting from 120 kΩ at 14 dB gain to 60 kΩ at 20 dB gain. The tolerance of the input resistor value is
±20%.
The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-
off frequency:
C13
C14
13 12 11
Current
Segment
DAC
-
AMP
+
Current
Segment
DAC
+
-
AMP
36 37 38
C19
C20
Figure 52. DAC to AMP AC Coupling
If a flat bass response is required down to 20Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 24 lists the recommended ac-coupling capacitors for the two gain step over a range of desired system high
pass filter frequency.
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Table 24. F3dB Versus Input AC-Coupling Capacitors
GAIN
14 dB
20 dB
INPUT IMPEDANCE
120 kΩ
0.1 µF
13 Hz
26 Hz
0.22 µF
6 Hz
0.33 µF
4 Hz
0.47 µF
3 Hz
1 µF
2.2 µF
0.6 Hz
1.2 Hz
1.3 Hz
2.7 Hz
60 kΩ
12 Hz
8 Hz
6 Hz
The input capacitors used should be a type with low leakage, like film or quality ceramic X5R or X7R with high
voltage rating. If a polarized type is used the negative connection should face the DACx output pins. INPx and
INMx are biased at 3Vdc.
8.2.1.2.4 Bootstrap Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 16 V, must be
connected from each output to its corresponding bootstrap input. See the application circuit diagram in 智能放大
器概览.
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
8.2.1.3 BTL Application Curves
The following graphs shows the frequency response with different output filter configurations: Figure 53: 4-Ω load
with 680 nF and 10-µH output filter, Figure 54: 4-Ω load with 330 nF and 4.7-µH inductor. Both setups are using
220 nF for the DAC-to-amp AC coupling capacitor.
30
25
360
300
240
180
120
60
30
25
360
300
240
180
120
60
Amplitude
Phase
Amplitude
Phase
20
20
15
15
10
10
5
5
0
0
0
0
−5
−60
−120
−180
−240
−300
−360
−5
−60
−120
−180
−240
−300
−360
−10
−15
−20
−25
−30
−10
−15
−20
−25
−30
Analog Gain =20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 4Ω
LCFILTER =680nF + 10 µH
fs=384kHz
Analog Gain =20dB
DAC Gain = 0dB
PVCC = 24V
TA = 25°C
RL = 4Ω
LCFILTER =330nF + 4.7 µH
fs=768kHz
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
G014
G015
Figure 53. Gain/Phase vs Frequency
Figure 54. Gain/Phase vs Frequency
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100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 8Ω
fs = 384kHz
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 4Ω
PVCC = 6
PVCC =12V
PVCC = 24V
PVCC = 6
PVCC =12V
PVCC = 24V
fs = 384kHz
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
Output Power (W)
G018
G019
Figure 55. Power Efficiency vs Output Power
Figure 56. Power Efficiency vs Output Power
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 8Ω
fs = 768kHz
20
10
0
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 4Ω
fs = 768kHz
PVCC = 6
PVCC =12V
PVCC = 24V
PVCC = 6
PVCC =12V
PVCC = 24V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
Output Power (W)
Output Power (W)
G020
G021
Figure 57. Power Efficiency vs Output Power
Figure 58. Power Efficiency vs Output Power
8.2.2 Mono/PBTL Application
The TAS576xM can be configured in MONO mode enabling up to 100 W peak output power into 2-Ω speaker.
This is done by:
•
Connect INPL and INNL directly to GND (without capacitors) this sets the device in Mono mode during power
up.
•
Connect OUTNR and OUTPR together for the positive speaker terminal and OUTPL and OUTNL together for
the negative terminal
In mono mode the right DAC channel, DACR, is used as input for the speaker amplifier, INPR. The left channel
DACL can be used for a external AMP if more channels and power is needed.
The combined output can source up to 15A – so be careful to select inductors that can handle that level of
current, if inductors with that high saturation current is not available, the PBTL connection can be made after the
inductors, this setup is shown in the PBTL application section.
44
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
SDA
SCL
1 mF
Positive Output
20k
Rb
Ra
3.3V
10mH
SCLK
BCLK
DIN
1 mF
100k
PVCC
10mH
220 nF
1 mF
LRCLK
1 mF
220 nF
1 mF 1 mF
Optional
single
inductor
connection
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+
2R
Power Pad œ Connect to GND
-
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
220 nF
Optional
single
1 mF
10k
1 mF
1 mF 1 mF
1 mF
inductor
connection
220 nF
3.3V
3.3V
10k
10mH
10mH
FAULT
PVCC
Negative output
DAC_L
4.5V-26.5V
1 mF
470 mF
DAC Left output
for optional
external AMP
Figure 59. Mono/PBTL Application
8.2.2.1 Design Requirements
See Stereo Application Design Requirements.
8.2.2.2 PBTL Application Curves
Figure 60 shows power efficiency of the TAS5766MDCAEVM configured in PBTL mode as described in section
Mono/PBTL Application.
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100
90
80
70
60
50
40
30
20
10
Analog Gain = 20dB
DAC Gain = 0dB
TA = 25°C
RL = 2Ω
PVCC = 6
PVCC =12V
PVCC = 24V
fs = 384kHz
0
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
G024
Figure 60. Power Efficiency (PBTL) vs Output Power
8.2.3 QFN BTL Application Diagram
1 mF
20k Rb
3.3V
SDA
SCL
100k
Ra
PVCC
1 mF
GPIO1
GPIO2
1 mF
1 mF 1 mF
30
36
35
29
26
25
38
37
34
33
32
31
28
27
RIGHT
39
40
41
42
43
44
45
46
47
48
GND 24
OUTPR 23
BSPR 22
OUTNR 21
BSNR 20
BSNL 19
OUTNL 18
BSPL 17
ADR2
10mH
GPIO3
GPIO3
SCK
470 nF
+
4R
-
SCLK
BCLK
DIN
220 nF
10mH
BCK
470 nF
DIN
Thermal PAD
Connect to GND
220 nF
220 nF
LRCLK
LRCLK
ADR1
XSMT/UVP
LDOO
GND
10mH
+
4R
-
10k
220 nF
470 nF
OUTPL 16
GND 15
10mH
470 nF
1 mF
LEFT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3.3V
3.3V
PVCC
4.5V-26.5V
1 mF
1 mF 1 mF
1 mF
1 mF
10k
470 mF
1 mF
FAULT
Figure 61. QFN BTL Application
46
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8.2.3.1 Design Requirements
See the Stereo Design Requirements section.
9 Power Supply Recommendations
The TAS576xM requires two power supplies; a low voltage 3.3 V nominal for the pins, AVDD, DVDD and
CPVDD and a high power supply, 4.5 V to 26.5 V for the pins PVCC and AVCC.
There is no requirement for sequencing of DVDD and PVCC, either supplies can ramp first.
9.1 AVDD, DVDD, CPVDD Supply
The AVDD Supply is used to power the DAC analog output stage, and needs a well regulated and filtered 3.3-V
supply voltage. The DVDD Supply is used to power the digital circuitry for I2S input, I2C input, GPIO blocks and
the audio DSP. DVDD needs a well regulated and filtered 3.3-V supply voltage.
9.2 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It is also used to supply the
GAIN/FSW voltage divider. Decouple GVDD with a X7R ceramic 1-µF capacitor to GND. The GVDD supply is
not intended to be used for external supply. It is recommended to limit the current consumption by using resistor
voltage dividers for GAIN/FSW of 100 kΩ or more.
9.3 PVCC, AVCC Power Supply
The TAS576xM high performance class-D audio system requires adequate power supply decoupling to ensure
the output total harmonic distortion (THD) and noise is as low as possible.
Optimum decoupling is achieved by placing a good quality low equivalent-series-resistance (ESR) ceramic
capacitor larger than 220nF as close to the device PVCC pins and system ground plane as possible.
For filtering lower frequency signals and handling the switching ripple current, a larger aluminum electrolytic
capacitor of 470μF or greater placed near the audio power amplifier is recommended. The 470-μF capacitor also
serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs.
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10 Layout
10.1 Layout Guidelines
The TAS576xM can be used with a small, inexpensive ferrite bead output filter when speaker are placed with
short internal wires and supply voltages are 12 V or lower, for systems with longer wires or higher than 12V
supply voltage LC filtering is recommended.
Class-D switching edges are fast and swithced currents are high so it is necessary to take care when planning
the layout of the printed circuit board. The following suggestions will help to meet audio, thermal and EMC
requirements
•
TAS576xM uses the PCB for heatsinking therefore the powerPad need to be soldered to the PCB and
adquate cobber area and cobber via's connecting the top, bottom and internal layers should be used.
•
Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVDD
and AVCC pins as possible, on the TAS576xM a 1-µF high-quality ceramic capacitor is used. Large (470 μF
or greater) bulk power supply decoupling capacitors should be placed near the TAS576xM on the PVDD
supplies. Local, high-frequency bypass capacitors should be placed as close to the DVDD, AVDD and
CPVDD pins as possible.
•
Keep the current loop from each of the outputs through the output inductor and the small filter cap and back
to GND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
•
•
Grounding — A big common GND plane is recommended. The PVDD decoupling capacitors should connect
to GND. The TAS576xM power pad should be connected to GND
Output filter — remember to select inductors that can handle the high short circuit current of the device. The
LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be
grounded
The EVM user guide available on www.ti.com shows both schematic, bill of material and more detailed layout
plots including gerber files.
48
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10.2 Layout Examples
TOP Layer
Supply Decoupling:
Bulk Capacitor for good audio
decoupling
Thermal considerations:
Wide open areas for
thermal flow
1uF ceramic SMD caps close
to PVCC pins
Lots of via‘s to connect
Top and bottom layer
Short trace loop on boot strap
capacitors
No wires cutting the GND
layer and obstructing
the thermal flow
Direct low impedance traces
for PVCC and output traces
Ceramic SMD caps close to
GVDD, DVDD, CPVDD
Traces are star routed
away from the device
leading to better thermal
design
Bottom Layer
EMI considerations:
Top layer is filled with GND
Solid GND plane for low
impedance return path
Lots of via‘s to connect
top and bottom layer
C-RC snubber circuits
directly the connector pads
Via‘s along the PCB egde
Figure 62. HTTSOP PCB Layout Example
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Layout Examples (continued)
TOP Layer
Supply Decoupling:
Bulk Capacitor for good audio
decoupling
Thermal considerations:
Connect thermal pad to top
GND plane at the corners
Short trace loop on boot strap
capacitors
Traces are star routed
away from the device
leading to better thermal
design
1uF ceramic SMD caps close
to PVCC pins
Direct low impedance traces
for PVCC and output traces
Ceramic SMD caps close to
GVDD, DVDD, CPVDD
Bottom Layer
Thermal considerations:
EMI considerations:
Wide open areas for
thermal flow
C-RC snubber circuits
directly the connector pads
Lots of via‘s to connect
Top layer is filled with GND
Top and bottom layer
Solid GND plane for low
impedance return path
No wires cutting the GND
layer and obstructing
the thermal flow
Lots of via‘s to connect
top and bottom layer
Via‘s along the PCB egde
Figure 63. VQFN PCB Layout Example
50
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
11 Register Map Information
11.1 Detailed Register Map Descriptions
Register Map Summary
Page 0
Dec
1
Hex
0x01
0x02
0x03
0x04
0x07
0x08
0x09
0x0A
0x0C
0x0D
0x14
0x15
0x16
0x17
0x18
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x22
0x23
0x24
0x25
0x28
0x29
0x2A
0x2B
0x2C
0x3B
0x41
0x42
0x52
0x53
0x54
0x55
0x56
0x57
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x6C
0x76
0x77
0x78
0x79
b7
RSV
b6
RSV
b5
RSV
b4
RSTM
RQST
RQML
PLCK
b3
RSV
b2
RSV
b1
RSV
b0
RSTR
2
RSV
RSV
RSV
RSV
RSV
RSV
RQPD
3
RSV
RSV
RSV
RSV
RSV
RSV
RQMR
PLLE
4
RSV
RSV
RSV
RSV
RSV
RSV
7
RSV
RSV
RSV
DEMP
MUTEOE
BCKO
DSPG4
RSV
RSV
RSV
RSV
SDSL
8
RSV
RSV
G3OE
BCKP
DSPG5
RSV
G1OE
RSV
G2OE
RSV
RSV
RSV
9
RSV
RSV
RSV
LRKO
10
12
13
20
21
22
23
24
27
28
29
30
32
33
34
35
36
37
40
41
42
43
44
59
65
66
82
83
84
85
86
87
90
91
92
93
94
95
108
118
119
120
121
DSPG7
RSV
DSPG6
RSV
DSPG3
RSV
DSPG2
RSV
DSPG1
RBCK
RSV
DSPG0
RLRK
RSV
RSV
RSV
SREF
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PPDV3
PJDV3
PDDV3
PDDV3
PRDV3
DDSP3
DDAC3
DNCP3
DOSR3
DBCK3
DLRK3
RSV
PPDV2
PJDV2
PDDV2
PDDV2
PRDV2
DDSP2
DDAC2
DNCP2
DOSR2
DBCK2
DLRK2
RSV
PPDV1
PJDV1
PDDV1
PDDV1
PRDV1
DDSP1
DDAC1
DNCP1
DOSR1
DBCK1
DLRK1
FSSP1
IDAC_MSB1
IDAC_LSB1
DCAS
ALEN1
AOFS1
AUPR1
PSEL1
CMDP1
AMTR1
AMLE
PPDV0
PJDV0
PDDV0
PDDV0
PRDV0
DDSP0
DDAC0
DNCP0
DOSR0
DBCK0
DLRK0
FSSP0
IDAC_MSB0
IDAC_LSB0
IPLK
RSV
RSV
PJDV5
PDDV5
PDDV5
RSV
PJDV4
PDDV4
PDDV4
RSV
RSV
RSV
PDDV7
RSV
PDDV6
RSV
RSV
DDSP6
DDAC6
DNCP6
DOSR6
DBCK6
DLRK6
RSV
DDSP5
DDAC5
DNCP5
DOSR5
DBCK5
DLRK5
RSV
DDSP4
DDAC4
DNCP4
DOSR4
DBCK4
DLRK4
I16E
RSV
RSV
RSV
RSV
DLRK7
RSV
IDAC_MSB7
IDAC_LSB7
RSV
IDAC_MSB6
IDAC_LSB6
IDFS
IDAC_MSB5
IDAC_LSB5
IDBK
IDAC_MSB4
IDAC_LSB4
IDSK
IDAC_MSB3
IDAC_LSB3
IDCH
IDAC_MSB2
IDAC_LSB2
IDCM
RSV
RSV
AFMT1
AOFS5
AUPL1
RSV
AFMT0
AOFS4
AUPL0
PSEL4
RSV
RSV
RSV
ALEN0
AOFS0
AUPR0
PSEL0
CMDP0
AMTR0
AMRE
AOFS7
RSV
AOFS6
RSV
AOFS3
RSV
AOFS2
RSV
RSV
RSV
PSEL3
RSV
PSEL2
CMDP2
AMTR2
ACTL
RSV
RSV
RSV
RSV
AMTL2
RSV
AMTL1
RSV
AMTL0
RSV
RSV
RSV
RSV
ADLY7
RSV
ADLY6
RSV
ADLY5
RSV
ADLY4
RSV
ADLY3
G2SL3
G1SL3
MTSL3
G3SL3
GOUT3
GINV3
R1OV
DTSR3
RSV
ADLY2
G2SL2
G1SL2
MTSL2
G3SL2
GOUT2
GINV2
L2OV
ADLY1
G2SL1
G1SL1
MTSL1
G3SL1
RSV
ADLY0
G2SL0
G1SL0
MTSL0
G3SL0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
GOUT5
GINV5
RSV
GOUT4
GINV4
L1OV
RSV
RSV
RSV
RSV
RSV
RSV
R2OV
SFOV
RSV
DTFS2
RSV
DTFS1
RSV
DTFS0
RSV
DTSR2
RSV
DTSR1
RSV
DTSR0
DTBR_MSB
DTBR_LSB0
CDST0
CERF
RSV
DTBR_LSB7
RSV
DTBR_LSB6
CDST6
RSV
DTBR_LSB5
CDST5
RSV
DTBR_LSB4
CDST4
LTSH
DTBR_LSB3
CDST3
RSV
DTBR_LSB2
CDST2
CKMF
RSV
DTBR_LSB1
CDST1
CSRF
RSV
RSV
RSV
ADLM
RSV
ADRM
RSV
RSV
AMLM
PSTM1
RSV
AMRM
PSTM0
RSV
BOTM
RSV
RSV
PSTM3
3
PSTM2
2
RSV
GPIN5
RSV
RSV
RSV
RSV
AMFL
RSV
RSV
RSV
AMFR
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DAMD
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Detailed Register Map Descriptions (continued)
Register Map Summary (continued)
Page 1
Dec
Hex
0x02
0x05
0x06
0x07
0x08
b7
b6
b5
b4
b3
b2
b1
RSV
UEPD
RSV
RSV
RSV
b0
2
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
LAGN
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RAGN
UIPD
AMCT
AGBR
RSV
5
6
RSV
7
AGBL
RBGF
8
Page 44
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
1
0x01
RSV
RSV
RSV
RSV
ACRM
AMDC
ACRS
ACSW
11.1.1 Page 0 Registers
Page 0 / Register 1 (Hex 0x01)
Dec
Hex
b7
b6
b5
b4
RSTM
0
b3
b2
b1
b0
RSTR
0
1
0x01
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RSTM
Reset Modules
This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM
content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode.
Default value: 0
0: Normal
1: Reset modules
Reset Registers
RSTR
This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution
source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode
(resetting registers when the DAC is running is prohibited and not supported).
Default value: 0
0: Normal
1: Reset mode registers
52
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Page 0 / Register 2 (Hex 0x02)
Dec
Hex
b7
b6
b5
b4
RQST
0
b3
b2
b1
b0
RQPD
0
2
0x02
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RQST
Standby Request
When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system
enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump
and digital power supply.
Default value: 0
0: Normal operation
1: Standby mode
RQPD
Powerdown Request
When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be
minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This
mode has higher precedence than the standby mode, i.e. setting this bit along with bit 4 for standby mode will
result in the DAC going into powerdown mode.
Default value: 0
0: Normal operation
1: Powerdown mode
Page 0 / Register 3 (Hex 0x03)
Dec
Hex
b7
b6
b5
b4
RQML
0
b3
b2
b1
b0
RQMR
0
3
0x03
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RQML
Mute Left Channel
This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid
pop/click noise.
Default value: 0
0: Normal volume
1: Mute
RQMR
Mute Right Channel
This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid
pop/click noise.
Default value: 0
0: Normal volume
1: Mute
Page 0 / Register 4 (Hex 0x04)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
PLLE
1
4
0x04
RSV
RSV
RSV
PLCK
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PLCK
PLL Lock Flag (Read Only)
This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the
PLL is not locked.
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0: The PLL is locked
1: The PLL is not locked
PLLE
PLL Enable
This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the
SCK.
Default value: 1
0: Disable PLL
1: Enable PLL
Page 0 / Register 7 (Hex 0x07)
Dec
Hex
b7
b6
b5
b4
DEMP
0
b3
b2
b1
b0
SDSL
0
7
0x07
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DEMP
De-Emphasis Enable
This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1kHz sampling rate, but
can be changed by reprogramming the appropriate coeffients in RAM.
Default value: 0
0: De-emphasis filter is disabled
1: De-emphasis filter is enabled
SDOUT Select
SDSL
This bit selects what is being output as SDOUT via GPIO pins.
Default value: 0
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
Page 0 / Register 8 (Hex 0x08)
Dec
Hex
b7
b6
b5
G3OE
0
b4
MUTEOE
0
b3
G1OE
0
b2
G2OE
0
b1
b0
8
0x08
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G3OE
GPIO3 Output Enable
This bit sets the direction of the GPIO3 pin
Default value: 0
0: GPIO3 is input
1: GPIO3 is output
MUTEOE
MUTE Control Enable
This bit enables MUTE of speaker amplifier
Default value: 0
0: MUTE control disable
1: MUTE control enable
GPIO1 Output Enable
This bit sets the direction of the GPIO1 pin
Default value: 0
G1OE
0: GPIO1 is input
1: GPIO1 is output
G2OE
GPIO2 Output Enable
54
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This bit sets the direction of the GPIO2 pin
Default value: 0
0: GPIO2 is input
1: GPIO2 is output
Page 0 / Register 9 (Hex 0x09)
Dec
Hex
b7
b6
b5
BCKP
0
b4
BCKO
0
b3
b2
b1
b0
LRKO
0
9
0x09
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
BCKP
BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges
are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the
BCK.
Default value: 0
0: Normal BCK mode
1: Inverted BCK mode
BCK Output Enable
BCKO
This bit sets the BCK pin direction to output for I2S master mode operation. In I2S master mode the device
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate
(normally 64FS)
Default value: 0
0: BCK is input (I2S slave mode)
1: BCK is output (I2S master mode)
LRCLK Output Enable
LRKO
This bit sets the LRCK pin direction to output for I2S master mode operation. In I2S master mode the device
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1FS for LRCK.
Default value: 0
0: LRCK is input (I2S slave mode)
1: LRCK is output (I2S master mode)
Page 0 / Register 10 (Hex 0x0A)
Dec
Hex
b7
DSPG7
0
b6
DSPG6
0
b5
DSPG5
0
b4
DSPG4
0
b3
DSPG3
0
b2
DSPG2
0
b1
DSPG1
0
b0
DSPG0
0
10
0x0A
Reset Value
DSPG[7:0]
DSP GPIO Input
The DSP accepts a 24-bit external control signals input. The value set in this register will go to bit 16:8 of this
external input.
Default value: 00000000
Page 0 / Register 12 (Hex 0x0C)
Dec
Hex
0x0C
b7
b6
b5
b4
b3
b2
b1
RBCK
0
b0
RLRK
0
12
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
Copyright © 2013–2018, Texas Instruments Incorporated
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
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RSV
Reserved
Reserved. Do not access.
Master Mode BCK Divider Reset
RBCK
This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode BCK clock divider is reset
1: Master mode BCK clock divider is functional
Master Mode LRCK Divider Reset
RLRK
This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode LRCK clock divider is reset
1: Master mode LRCK clock divider is functional
Page 0 / Register 13 (Hex 0x0D)
Dec
Hex
b7
b6
b5
b4
SREF
0
b3
b2
b1
b0
13
0x0D
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
SREF
PLL Reference
This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.
Default value: 0
0: The PLL reference clock is SCK
1: The PLL reference clock is BCK
Page 0 / Register 20 (Hex 0x14)
Dec
Hex
b7
b6
b5
b4
b3
PPDV3
0
b2
PPDV2
0
b1
PPDV1
0
b0
PPDV0
0
20
0x14
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PPDV[3:0]
PLL P
These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.
Default value: 0000
0000: P=1
0001: P=2
...
1110: P=15
1111: Prohibited (do not set this value)
Page 0 / Register 21 (Hex 0x15)
Dec
Hex
0x15
b7
b6
b5
PJDV5
0
b4
PJDV4
0
b3
PJDV3
0
b2
PJDV2
0
b1
PJDV1
0
b0
PJDV0
0
21
RSV
RSV
Reset Value
56
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RSV
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
Reserved
Reserved. Do not access.
PLL J
PJDV[5:0]
These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set
mode.
Default value: 000000
000000: Prohibited (do not set this value)
000001: J=1
000010: J=2
...
111111: J=63
Page 0 / Register 22 (Hex 0x16)
Dec
Hex
b7
b6
b5
PDDV5
0
b4
PDDV4
0
b3
PDDV3
0
b2
PDDV2
0
b1
PDDV1
0
b0
PDDV0
0
22
0x16
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PDDV[5:0]
PLL D (MSB)
Most-significant 6 bits to set the D part of the overall PLL multiplication factor J.D * R These bits are ignored in
clock auto set mode.
Default value: 000000
0 (in decimal): D=0000
1 (in decimal): D=0001
...
9999 (in decimal): D=9999
others: Prohibited (do not set)
Page 0 / Register 23 (Hex 0x17)
Dec
Hex
0x17
b7
PDDV7
0
b6
PDDV6
0
b5
PDDV5
0
b4
PDDV4
0
b3
PDDV3
0
b2
PDDV2
0
b1
PDDV1
0
b0
PDDV0
0
23
Reset Value
PDDV[7:0]
PLL D (LSB)
Least-significant 8 bits to set the D part of the overall PLL multiplication factor J.D * R.
Default value: 00000000
0 (in decimal): D=0000
1 (in decimal): D=0001
...
9999 (in decimal): D=9999
others: Prohibited (do not set)
Page 0 / Register 24 (Hex 0x18)
Dec
Hex
0x18
b7
b6
b5
b4
b3
PRDV3
0
b2
PRDV2
0
b1
PRDV1
0
b0
PRDV0
0
24
RSV
RSV
RSV
RSV
Reset Value
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www.ti.com.cn
RSV
Reserved
Reserved. Do not access.
PLL R
PRDV[3:0]
These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto
set mode.
Default value: 0000
0000: R=1
0001: R=2
...
1111: R=16
Page 0 / Register 27 (Hex 0x1B)
Dec
Hex
0x1B
b7
b6
DDSP6
0
b5
DDSP5
0
b4
DDSP4
0
b3
DDSP3
0
b2
DDSP2
0
b1
DDSP1
0
b0
DDSP0
0
27
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DDSP[6:0]
DSP Clock Divider
These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 28 (Hex 0x1C)
Dec
Hex
0x1C
b7
b6
DDAC6
0
b5
DDAC5
0
b4
DDAC4
0
b3
DDAC3
0
b2
DDAC2
0
b1
DDAC1
0
b0
DDAC0
0
28
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DDAC[6:0]
DAC Clock Divider
These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 29 (Hex 0x1D)
Dec
Hex
0x1D
b7
b6
DNCP6
0
b5
DNCP5
0
b4
DNCP4
0
b3
DNCP3
0
b2
DNCP2
0
b1
DNCP1
0
b0
DNCP0
0
29
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DNCP[6:0]
NCP Clock Divider
These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode.
Default value: 0000000
58
Copyright © 2013–2018, Texas Instruments Incorporated
TAS5766M, TAS5768M
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 30 (Hex 0x1E)
Dec
Hex
b7
b6
DOSR6
0
b5
DOSR5
0
b4
DOSR4
0
b3
DOSR3
0
b2
DOSR2
0
b1
DOSR1
0
b0
DOSR0
0
30
0x1E
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DOSR[6:0]
OSR Clock Divider
These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 32 (Hex 0x20)
Dec
Hex
0x20
b7
b6
DBCK6
0
b5
DBCK5
0
b4
DBCK4
0
b3
DBCK3
0
b2
DBCK2
0
b1
DBCK1
0
b0
DBCK0
0
32
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DBCK[6:0]
Master Mode BCK Divider
These bits set the SCK divider value to generate I2S master BCK clock.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 33 (Hex 0x21)
Dec
Hex
0x21
b7
DLRK7
0
b6
DLRK6
0
b5
DLRK5
0
b4
DLRK4
0
b3
DLRK3
0
b2
DLRK2
0
b1
DLRK1
0
b0
DLRK0
0
33
Reset Value
DLRK[7:0]
Master Mode LRCK Divider
These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock.
Default value: 00000000
00000000: Divide by 1
00000001: Divide by 2
...
11111111: Divide by 256
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Page 0 / Register 34 (Hex 0x22)
Dec
Hex
b7
b6
b5
b4
I16E
0
b3
b2
b1
FSSP1
0
b0
FSSP0
0
34
0x22
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
I16E
Reserved
Reserved. Do not access.
16x Interpolation
This bit enables or disables the 16x interpolation mode
Default value: 0
0: 8x interpolation
1: 16x interpolation
FSSP[1:0]
FS Speed Mode
These bits select the FS operation mode, which must be set according to the current audio sampling rate.
These bits are ignored in clock auto set mode.
Default value: 00
00: Single speed (FS ≤ 48 kHz)
01: Double speed (48 kHz < FS ≤ 96 kHz)
10: Quad speed (96 kHz < FS ≤ 192 kHz)
11: Octal speed (192 kHz < FS ≤ 384 kHz)
Page 0 / Register 35 (Hex 0x23)
Dec
Hex
0x23
b7
b6
b5
b4
b3
b2
b1
b0
35
IDAC_MSB7
0
IDAC_MSB6
0
IDAC_MSB5
0
IDAC_MSB4
0
IDAC_MSB3
0
IDAC_MSB2
0
IDAC_MSB1
0
IDAC_MSB0
1
Reset Value
IDAC_MSB[7:0]
IDAC (MSB)
Most-significant 8 bits to specify the number of DSP clock cycles available in one audio frame. The value
should match the DSP clock FS ratio. These bits are ignored in clock auto set mode.
Default value: 00000001
Page 0 / Register 36 (Hex 0x24)
Dec
Hex
b7
IDAC_LSB7
0
b6
IDAC_LSB6
0
b5
IDAC_LSB5
0
b4
IDAC_LSB4
0
b3
IDAC_LSB3
0
b2
IDAC_LSB2
0
b1
IDAC_LSB1
0
b0
IDAC_LSB0
0
36
0x24
Reset Value
IDAC_LSB[7:0]
IDAC (LSB)
Least-significant 8 bits to specify the number of DSP clock cycles available in one audio frame.
Default value: 00000000
Page 0 / Register 37 (Hex 0x25)
Dec
Hex
b7
b6
IDFS
0
b5
IDBK
0
b4
IDSK
0
b3
IDCH
0
b2
IDCM
0
b1
DCAS
0
b0
IPLK
0
37
0x25
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
IDFS
Ignore FS Detection
This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error.
Default value: 0
0: Regard FS detection
60
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IDBK
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
1: Ignore FS detection
Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS
and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.
Default value: 0
0: Regard BCK detection
1: Ignore BCK detection
Ignore SCK Detection
IDSK
IDCH
IDCM
This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some
error margin are allowed. When ignored, an SCK error will not cause a clock error.
Default value: 0
0: Regard SCK detection
1: Ignore SCK detection
Ignore Clock Halt Detection
This bit controls whether to ignore the SCK halt (static or frequency is lower than acceptable) detection. When
ignored an SCK halt will not cause a clock error.
Default value: 0
0: Regard SCK halt detection
1: Ignore SCK halt detection
Ignore LRCK/BCK Missing Detection
This bit controls whether to ignore the LRCK/BCK missing detection. The LRCK/BCK need to be in low state
(not only static) to be deemed missing. When ignored an LRCK/BCK missing will not cause the DAC go into
powerdown mode.
Default value: 0
0: Regard LRCK/BCK missing detection
1: Ignore LRCK/BCK missing detection
Disable Clock Divider Autoset
DCAS
This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration,
the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock
detectors might also need to be disabled.
Default value: 0
0: Enable clock auto set
1: Disable clock auto set
Ignore PLL Lock Detection
IPLK
This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock
error. The PLL lock flag at Page 0 / Register 4, bit 4 is always correct regardless of this bit.
Default value: 0
0: PLL unlocks raise clock error
1: PLL unlocks are ignored
Page 0 / Register 40 (Hex 0x28)
Dec
Hex
b7
b6
b5
AFMT1
0
b4
AFMT0
0
b3
b2
b1
ALEN1
1
b0
ALEN0
0
40
0x28
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AFMT[1:0]
I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
Default value: 00
00: I2S
01: DSP
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10: RTJ
11: LTJ
ALEN[1:0]
I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
Default value: 10
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
Page 0 / Register 41 (Hex 0x29)
Dec
Hex
0x29
b7
AOFS7
0
b6
AOFS6
0
b5
AOFS5
0
b4
AOFS4
0
b3
AOFS3
0
b2
AOFS2
0
b1
AOFS1
0
b0
AOFS0
0
41
Reset Value
AOFS[7:0]
I2S Shift
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as
the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample.
Default value: 00000000
00000000: offset = 0 BCK (no offset)
00000001: ofsset = 1 BCK
00000010: offset = 2 BCKs
...
11111111: offset = 256 BCKs
Page 0 / Register 42 (Hex 0x2A)
Dec
Hex
0x2A
b7
b6
b5
AUPL1
0
b4
AUPL0
1
b3
b2
b1
AUPR1
0
b0
AUPR0
1
42
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AUPL[1:0]
Left DAC Data Path
These bits control the left channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
Right DAC Data Path
AUPR[1:0]
These bits control the right channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
Page 0 / Register 43 (Hex 0x2B)
Dec
Hex
0x2B
b7
b6
b5
b4
PSEL4
0
b3
PSEL3
0
b2
PSEL2
0
b1
PSEL1
0
b0
PSEL0
1
43
RSV
RSV
RSV
Reset Value
62
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RSV
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
Reserved
Reserved. Do not access.
DSP Program Selection
PSEL[4:0]
These bits select the DSP program to use for audio processing.
Default value: 00001
00000: Reserved (do not set)
00001: 8x/4x/2x FIR interpolation filter with de-emphasis
00010: Reserved (do not set)
00011: Reserved (do not set)
00100: Reserved (do not set)
00101: Reserved (do not set)
00110: Reserved (do not set)
00111: Reserved (do not set)
01000: Reserved (do not set)
11111: User program in RAM
others: Reserved (do not set)
Page 0 / Register 44 (Hex 0x2C)
Dec
Hex
b7
b6
b5
b4
b3
b2
CMDP2
0
b1
CMDP1
0
b0
CMDP0
0
44
0x2C
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
CMDP[2:0]
Clock Missing Detection Period
These bits set how long both BCK and LRCK keep low before the audio clocks deemed missing and the DAC
transitions to powerdown mode.
Default value: 000
000: about 1 second
001: about 2 seconds
010: about 3 seconds
...
111: about 8 seconds
Page 0 / Register 59 (Hex 0x3B)
Dec
Hex
0x3B
b7
b6
AMTL2
0
b5
AMTL1
0
b4
AMTL0
0
b3
b2
AMTR2
0
b1
AMTR1
0
b0
AMTR0
0
59
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AMTL[2:0]
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left channel before the channel can be auto
muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
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www.ti.com.cn
110: 5.33 sec
111: 10.66 sec
AMTR[2:0]
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto
muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
110: 5.33 sec
111: 10.66 sec
Page 0 / Register 65 (Hex 0x41)
Dec
Hex
b7
b6
b5
b4
b3
b2
ACTL
1
b1
AMLE
0
b0
AMRE
0
65
0x41
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
ACTL
Auto Mute Control
This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection
is set with Page 0 / Register 59.
Default value: 1
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted.
Auto Mute Left Channel
AMLE
AMRE
This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and
the Page 0 / Register 65, bit 2 is set to 1, the left channel will also never be auto muted.
Default value: 0
0: Disable right channel auto mute
1: Enable right channel auto mute
Auto Mute Right Channel
This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and
the Page 0 / Register 65, bit 2 is set to 1, the right channel will also never be auto muted.
Default value: 0
0: Disable left channel auto mute
1: Enable left channel auto mute
Page 0 / Register 66 (Hex 0x42)
Dec
Hex
b7
ADLY7
0
b6
ADLY6
0
b5
ADLY5
0
b4
ADLY4
1
b3
ADLY3
0
b2
ADLY2
1
b1
ADLY1
0
b0
ADLY0
0
66
0x42
Reset Value
ADLY[7:0]
AMUTE Delay
These bits control the delay before the complete digital mute to the assertion of analog mute. This is to allow
the non-mute audio samples to completely flow out through analog parts before the assertion of the analog
mute.
Default value: 00010100
00000000: No delay
64
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
00000001: 1 LRCK delay
00000010: 2 LRCK delay
...
11111111: 255 LRCK delay
Page 0 / Register 82 (Hex 0x52)
Dec
Hex
b7
b6
b5
b4
b3
G2SL3
0
b2
G2SL2
0
b1
G2SL1
0
b0
G2SL0
0
82
0x52
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G2SL[3:0]
GPIO2 Output Selection
These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set
to output mode at Page 0 / Register 8.
Default value: 0000
0000: off (low)
0001: DSP GPIO2 output
0010: Register GPIO2 output (Page 0 / Register 86, bit 2)
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock changing or clock missing)
0111: Serial audio interface data output (SDOUT)
1000: Analog mute flag for left channel (low active)
1001: Analog mute flag for right channel (low active)
1010: PLL lock flag
1011: Charge pump clock
1100: DAC clock
1101: MiniDSP clock/4
1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
Page 0 / Register 83 (Hex 0x53)
Dec
Hex
0x53
b7
b6
b5
b4
b3
G1SL3
0
b2
G1SL2
0
b1
G1SL1
0
b0
G1SL0
0
83
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G1SL[3:0]
GPIO1 Output Selection
These bits select the signal to output to GPIO1. To actually output the selected signal, the GPIO1 must be set
to output mode at Page 0 / Register 8.
Default value: 0000
0000: off (low)
0001: DSP GPIO1 output
0010: Register GPIO1 output (Page 0 / Register 86, bit 3)
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock changing or clock missing)
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0111: Serial audio interface data output (SDOUT)
1000: Analog mute flag for left channel (low active)
1001: Analog mute flag for right channel (low active)
1010: PLL lock flag
1011: Charge pump clock
1100: DAC clock
1101: MiniDSP clock/4
1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
Page 0 / Register 84 (Hex 0x54)
Dec
Hex
b7
b6
b5
b4
b3
MTSL3
0
b2
MTSL2
0
b1
MTSL1
0
b0
MTSL0
0
84
0x54
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
MTSL[3:0]
MUTE Output Selection
These bits select the signal to output to MUTE. To actually output the selected signal, the MUTE must be set to
output mode at Page 0 / Register 8.
Default value: 0000
0000: off (low)
0001: DSP MUTE output
0010: Register MUTE output (Page 0 / Register 86, bit 4)
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock changing or clock missing)
1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
Page 0 / Register 85 (Hex 0x55)
Dec
Hex
0x55
b7
b6
b5
b4
b3
G3SL3
0
b2
G3SL2
0
b1
G3SL1
0
b0
G3SL0
0
85
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G3SL[3:0]
GPIO3 Output Selection
These bits select the signal to output to GPIO3. To actually output the selected signal, the GPIO3 must be set
to output mode at Page 0 / Register 8.
Default value: 0000
0000: off (low)
0001: DSP GPIO3 output
0010: Register GPIO3 output (Page 0 / Register 86, bit 5)
0011: Auto mute flag (asserted when both L and R channels are auto muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock changing or clock missing)
0111: Serial audio interface data output (SDOUT)
66
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
1000: Analog mute flag for left channel (low active)
1001: Analog mute flag for right channel (low active)
1010: PLL lock flag
1011: Charge pump clock
1100: DAC clock
1101: MiniDSP clock/4
1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
Page 0 / Register 86 (Hex 0x56)
Dec
Hex
b7
b6
b5
GOUT5
0
b4
GOUT4
0
b3
GOUT3
0
b2
GOUT2
0
b1
b0
86
0x56
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GOUT[5:0]
GPIO Output Control
This bit controls the GPIO3 output when the selection at Page 0 / Register 85 is set to 0010 (register output)
Default value: 000000
0: Output low
1: Output high
Page 0 / Register 87 (Hex 0x57)
Dec
Hex
b7
b6
b5
GINV5
0
b4
GINV4
0
b3
GINV3
0
b2
GINV2
0
b1
b0
87
0x57
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GINV[5:0]
GPIO Output Inversion
This bit controls the polarity of GPIO3 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 000000
0: Non-inverted
1: Inverted
Page 0 / Register 90 (Hex 0x5A)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
90
0x5A
RSV
RSV
RSV
L1OV
R1OV
L2OV
R2OV
SFOV
Reset Value
RSV
Reserved
Reserved. Do not access.
L1OV
Left1 Overflow (Read Only)
This bit indicates whether the left channel of DSP first output port has overflow. This bit is sticky and is cleared
when read.
0: No overflow
1: Overflow occurred
R1OV
Right1 Overflow (Read Only)
The bit indicates whether the right channel of DSP first output port has overflow. This bit is sticky and is cleared
when read.
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0: No overflow
1: Overflow occurred
Left2 Overflow (Read Only)
L2OV
R2OV
SFOV
This bit indicates whether the left channel of DSP second output port has overflow. This bit is sticky and is
cleared when read.
0: No overflow
1: Overflow occurred
Right2 Overflow (Read Only)
The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is
cleared when read.
0: No overflow
1: Overflow occurred
Shifter Overflow (Read Only)
This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky
and is cleared when read.
0: No overflow
1: Overflow occurred
Page 0 / Register 91 (Hex 0x5B)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
91
0x5B
RSV
DTFS2
DTFS1
DTFS0
DTSR3
DTSR2
DTSR1
DTSR0
Reset Value
RSV
Reserved
Reserved. Do not access.
DTFS[2:0]
Detected FS (Read Only)
These bits indicate the currently detected audio sampling rate.
000: Error (Out of valid range)
001: 8 kHz
010: 16 kHz
011: 32-48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
DTSR[3:0]
Detected SCK Ratio (Read Only)
These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error,
clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK
ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The
absolute SCK frequency must also be lower than 50 MHz.
0000: Ratio error (The SCK ratio is not allowed)
0001: SCK = 32 FS
0010: SCK = 48 FS
0011: SCK = 64 FS
0100: SCK = 128 FS
0101: SCK = 192 FS
0110: SCK = 256 FS
0111: SCK = 384 FS
1000: SCK = 512 FS
1001: SCK = 768 FS
1010: SCK = 1024 FS
1011: SCK = 1152 FS
1100: SCK = 1536 FS
68
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ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
1101: SCK = 2048 FS
1110: SCK = 3072 FS
Page 0 / Register 92 (Hex 0x5C)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
92
0x5C
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DTBR_MSB
Reset Value
RSV
Reserved
Reserved. Do not access.
Detected BCK Ratio (MSB) (Read Only)
DTBR_MSB
Most significant of 9 bits that indicate the currently detected BCK ratio, that is, the number of BCK clocks in one
audio frame. Note that for extreme case of BCK = 1 FS (which is not usable anyway), the detected ratio will be
unreliable.
Page 0 / Register 93 (Hex 0x5D)
Dec
Hex
0x5D
b7
b6
b5
b4
b3
b2
b1
b0
93
DTBR_LSB7
DTBR_LSB6
DTBR_LSB5
DTBR_LSB4
DTBR_LSB3
DTBR_LSB2
DTBR_LSB1
DTBR_LSB0
Reset Value
DTBR_LSB[7:0]
Detected BCK Ratio (LSB) (Read Only)
Least significant of 8 bits that indicate the currently detected BCK ratio.
Page 0 / Register 94 (Hex 0x5E)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
94
0x5E
RSV
CDST6
CDST5
CDST4
CDST3
CDST2
CDST1
CDST0
Reset Value
RSV
Reserved
Reserved. Do not access.
CDST[6]
Clock Detector Status (Read Only)
This bit indicates whether the SCK clock is present or not.
0: SCK is present
1: SCK is missing (halted)
CDST[5]
CDST[4]
CDST[3]
CDST[2]
Clock Detector Status (Read Only)
This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
0: PLL is locked
1: PLL is unlocked
Clock Detector Status (Read Only)
This bit indicates whether the both LRCK and BCK are missing (tied low) or not.
0: LRCK and/or BCK is present
0: LRCK and BCK are missing
Clock Detector Status (Read Only)
This bit indicates whether the combination of current sampling rate and SCK ratio is valid for clock auto set.
0: The combination of FS/SCK ratio is valid
1: Error (clock auto set is not possible)
Clock Detector Status (Read Only)
This bit indicates whether the SCK is valid or not. The SCK ratio must be detectable to be valid. There is a
limitation with this flag; that is, when the low period of LRCK is less than or equal to 5 BCKs, this flag will be
asserted (SCK invalid reported).
0: SCK is valid
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1: SCK is invalid
Clock Detector Status (Read Only)
CDST[1]
CDST[0]
This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-256FS
to be valid.
0: BCK is valid
1: BCK is invalid
Clock Detector Status (Read Only)
This bit indicates whether the audio sampling rate is valid or not. The sampling rate must be detectable to be
valid. There is a limitation with this flag; that is, when this flag is asserted and $0/37$ is set to ignore all
asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported
anymore).
0: Sampling rate is valid
1: Sampling rate is invalid
Page 0 / Register 95 (Hex 0x5F)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
95
0x5F
RSV
RSV
RSV
LTSH
RSV
CKMF
CSRF
CERF
Reset Value
RSV
Reserved
Reserved. Do not access.
LTSH
Latched Clock Halt (Read Only)
This bit indicates whether SCK halt has occurred. The bit is cleared when read.
0: SCK halt has not occurred
1: SCK halt has occurred since last read
Clock Missing (Read Only)
CKMF
CSRF
CERF
This bit indicates whether the LRCK and BCK are missing (tied low).
0: LRCK and/or BCK is present
1: LRCK and BCK are missing
Clock Resync Request (Read Only)
This bit indicates whether the clock resynchronization is in progress.
0: Not resynchronizing
1: Clock resynchronization is in progress
Clock Error (Read Only)
This bit indicates whether a clock error is being reported.
0: Clock is valid
1: Clock is invalid (Error)
Page 0 / Register 108 (Hex 0x6C)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
108
0x6C
RSV
RSV
ADLM
ADRM
RSV
RSV
AMLM
AMRM
Reset Value
RSV
Reserved
Reserved. Do not access.
AMUTEZ dummy left monitor (Read Only)
ADLM
This bit is a monitor for left channel dummy output analog mute status.
0: Mute
1: Unmute
ADRM
AMUTEZ dummy right monitor (Read Only)
This bit is a monitor for right channel dummy output analog mute status.
70
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AMLM
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
0: Mute
1: Unmute
Left Analog Mute Monitor (Read Only)
This bit is a monitor for left channel analog mute status.
0: Mute
1: Unmute
AMRM
Right Analog Mute Monitor (Read Only)
This bit is a monitor for right channel analog mute status.
0: Mute
1: Unmute
Page 0 / Register 118 (Hex 0x76)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
118
0x76
BOTM
RSV
RSV
RSV
PSTM3
PSTM2
PSTM1
PSTM0
Reset Value
RSV
Reserved
Reserved. Do not access.
BOTM
DSP Boot Done Flag (Read Only)
This bit indicates whether the DSP boot is completed.
0: DSP is booting
1: DSP boot completed
Power State (Read Only)
These bits indicate the current power state of the DAC.
0000: Powerdown
PSTM[3:0]
0001: Wait for CP voltage valid
0010: Calibration
0011: Calibration
0100: Volume ramp up
0101: Run (Playing)
0110: Reserved
0111: Volume ramp down
1000: Standby
Page 0 / Register 119 (Hex 0x77)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
119
0x77
RSV
RSV
GPIN5
RSV
3
2
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GPIN[5:0]
GPIO Input States (Read Only)
This bit indicates the logic level at GPIO3 pin.
0: Low
1: High
Page 0 / Register 120 (Hex 0x78)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
120
0x78
RSV
RSV
RSV
AMFL
RSV
RSV
RSV
AMFR
Reset Value
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RSV
Reserved
Reserved. Do not access.
AMFL
Auto Mute Flag for Left Channel (Read Only)
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
AMFR
Auto Mute Flag for Right Channel (Read Only)
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
Page 0 / Register 121 (Hex 0x79)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
DAMD
0
121
0x79
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DAC Mode
DAMD
This bit controls the DAC mode.
Default value: 0
0: Mode1
1: Mode2
11.1.2 Page 1 Registers
Page 1 / Register 2 (Hex 0x02)
Dec
Hex
b7
b6
b5
b4
LAGN
0
b3
b2
b1
b0
RAGN
0
2
0x02
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
LAGN
Analog Gain Control for Left Channel
This bit controls the left channel analog gain.
Default value: 0
0: 0 dB
1:-6 dB
RAGN
Analog Gain Control for Right Channel
This bit controls the right channel analog gain.
Default value: 0
0: 0 dB
1: -6 dB
Page 1 / Register 5 (Hex 0x05)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
UEPD
0
b0
UIPD
0
5
0x05
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
72
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RSV
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
Reserved
Reserved. Do not access.
External UVP Control
UEPD
This bit enables or disables detection of power supply drop via XSMUTE pin (External Under Voltage
Protection).
Default value: 0
0: Enabled
1: Disabled
UIPD
Internal UVP Control
This bit enables or disables internal detection of AVDD voltage drop (Internal Under Voltage Protection).
Default value: 0
0: Enabled
1: Disabled
Page 1 / Register 6 (Hex 0x06)
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
AMCT
1
6
0x06
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AMCT
Analog Mute Control
This bit enables or disables analog mute following digital mute.
Default value: 1
0: Enabled
1: Disabled
Page 1 / Register 7 (Hex 0x07)
Dec
Hex
b7
b6
b5
b4
AGBL
0
b3
b2
b1
b0
AGBR
0
7
0x07
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AGBL
Analog +10% Gain for Left Channel
This bit enables or disables amplitude boost mode for left channel.
Default value: 0
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude
Analog +10% Gain for Right Channel
This bit enables or disables amplitude boost mode for right channel.
Default value: 0
AGBR
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude
Page 1 / Register 8 (Hex 0x08)
Dec
Hex
b7
b6
b5
b4
RBGF
0
b3
b2
b1
b0
8
0x08
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
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RSV
Reserved
Reserved. Do not access.
REF BG Fast
RBGF
This bit controls the bandgap voltage ramp up speed.
Default value: 0
0: Normal ramp up, ~50ms with external capacitance = 1uF
1: Fast ramp up, ~1ms with external capacitance = 1 uF
11.1.3 Page 44 Registers
Page 44 / Register 1 (Hex 0x01)
Dec
Hex
b7
b6
b5
b4
b3
b2
AMDC
0
b1
b0
ACSW
0
1
0x01
RSV
RSV
RSV
RSV
ACRM
ACRS
Reset Value
RSV
Reserved
Reserved. Do not access.
ACRM
Active CRAM Monitor (Read Only)
This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive
mode is enabled, this bit has no meaning.
0: CRAM A is being used by the DSP
1: CRAM B is being used by the DSP
Adaptive Mode Control
AMDC
This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial
interface when the DSP is disabled (DAC in standby state), while when the DSP is enabled (DAC is run state)
the CRAM A can only be accessed by the DSP and the CRAM B can only be accessed by the serial interface,
or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM A and B can be
accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be
accessed by serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.
Default value: 0
0: Adaptive mode disabled
1: Adaptive mode enabled
ACRS
ACSW
Active CRAM Selection (Read Only)
This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer,
and can accessed by serial interface (SPI/I2C)
0: CRAM A is active and being used by the DSP
1: CRAM B is active and being used by the DSP
Switch Active CRAM
This bit is used to request switching roles of the two buffers, i.e. switching the active buffer role between CRAM
A and CRAM B. This bit is cleared automatically when the switching process completed.
Default value: 0
0: No switching requested or switching completed
1: Switching is being requested
74
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TAS5766M, TAS5768M
www.ti.com.cn
ZHCSDC1D –SEPTEMBER 2013–REVISED OCTOBER 2018
12 器件和文档支持
12.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 25. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TAS5766M
TAS5768M
12.2 商标
PurePath, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2013–2018, Texas Instruments Incorporated
75
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5766MDCA
TAS5766MDCAR
TAS5766MRMTR
TAS5766MRMTT
TAS5768MDCA
TAS5768MDCAR
TAS5768MRMTR
TAS5768MRMTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
VQFN
DCA
DCA
RMT
RMT
DCA
DCA
RMT
RMT
48
48
48
48
48
48
48
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
TAS5766M
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TAS5766M
5766M
VQFN
250
40
RoHS & Green
RoHS & Green
5766M
HTSSOP
HTSSOP
VQFN
TAS5768M
TAS5768M
5768M
2000 RoHS & Green
3000 RoHS & Green
VQFN
250
RoHS & Green
5768M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5766MDCAR
TAS5766MRMTR
TAS5766MRMTT
TAS5768MDCAR
TAS5768MRMTR
TAS5768MRMTT
HTSSOP DCA
48
48
48
48
48
48
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
24.4
16.4
16.4
24.4
16.4
16.4
8.6
5.25
5.25
8.6
13.0
7.25
7.25
13.0
7.25
7.25
1.8
1.45
1.45
1.8
12.0
8.0
24.0
16.0
16.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
VQFN
VQFN
RMT
RMT
8.0
HTSSOP DCA
2000
3000
250
12.0
8.0
VQFN
VQFN
RMT
RMT
5.25
5.25
1.45
1.45
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS5766MDCAR
TAS5766MRMTR
TAS5766MRMTT
TAS5768MDCAR
TAS5768MRMTR
TAS5768MRMTT
HTSSOP
VQFN
DCA
RMT
RMT
DCA
RMT
RMT
48
48
48
48
48
48
2000
3000
250
350.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
185.0
350.0
367.0
185.0
43.0
38.0
35.0
43.0
38.0
35.0
VQFN
HTSSOP
VQFN
2000
3000
250
VQFN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TAS5766MDCA
TAS5768MDCA
DCA
DCA
HTSSOP
HTSSOP
48
48
40
40
530
530
11.89
11.89
3600
3600
4.9
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
RMT0048A
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
7.15
6.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.6
3.5 0.1
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
24
15
14
25
SYMM
49
5.5 0.1
2X 5.2
1
38
0.26
0.14
44X 0.4
48X
39
48
PIN 1 ID
0.1
C A B
0.5
0.3
0.05
48X
4224155/A 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMT0048A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.5)
(1.5) TYP
(0.6) TYP
SEE SOLDER MASK
DETAIL
39
48
48X (0.6)
48X (0.2)
1
38
44X (0.4)
(2.5) TYP
(5.5)
(1.32)
TYP
(R0.05) TYP
SYMM
(6.8)
49
(
0.2) TYP
VIA
25
14
15
24
SYMM
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224155/A 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RMT0048A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2)
48
39
48X (0.6)
48X (0.2)
1
38
44X (0.4)
(1.32)
(0.66)
(6.8)
49
SYMM
(R0.05) TYP
12X (1.12)
14
25
12X (1)
15
24
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 49
70% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224155/A 02/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DCA 48
12.5 x 6.1, 0.5 mm pitch
HTSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224608/A
www.ti.com
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