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TAS5780M

ZHCSFY4 –DECEMBER 2016

TAS5780M 采用 96kHz 处理架构的数字输入、闭环 D 类放大器

1 特性

2 应用

1

•

灵活的音频 I/O 配置

•

液晶显示屏 (LCD)、发光二极管 (LED) TV 和多用

途监视器

–

支持 I²S、TDM、LJ 和 RJ 数字输入

•

条形音箱、扩展坞和 PC 音频

无线低音炮、蓝牙扬声器和有源扬声器

支持采样速率

立体声桥接负载 (BTL) 或单声道并行桥接负载

(PBTL) 运行

3 说明

–

1SPW 放大器调制

TAS5780M 器件是一款高性能、立体声闭环 D 类放大

器，集成采用 96kHz 架构的音频处理器。为实现数模

转换，该器件采用了应用 Burr-Brown™技术的高性能

数模转换器 (DAC) 该器件仅需两个电源：一个是用于

低压电路的 DVDD，另一个是用于高压电路的

PVDD。它采用标准的 I²C 通信软件控制端口实现控

制。

支持三线制数字音频接口（无需 MCLK）

•

高性能闭环架构（PVDD = 12V，R_SPK

8Ω，SPK_GAIN = 20dB）

=

–

空闲声道噪声 = 62μVRMS (A-Wtd)

总谐波失真 + 噪声 (THD+N) = 0.2% (1W/1kHz)

信噪比 (SNR) = 100dB A-Wtd（以THD+N =

1% 为基准）

固定功能处理特性

输出金属氧化物半导体场效应晶体管 (MOSFET) 的

90mΩ r_DS(on)兼顾散热性能与器件成本，二者相得益

彰。此外，该器件采用耐热增强型 48 引脚薄型小外形

尺寸 (TSSOP)，在现代消费类电子器件的较高工作环

境温度下展现出优异的性能。

–

12 个 BiQuad

–

12 个 BiQuad 实现快速变换的内部存储区切

换

双波段高级动态范围压缩 (DRC) + 自动增益限

制 (AGL)

器件信息⁽¹⁾

–

动态参数均衡 (DPEQ)

采样速率转换器 (SRC) 支持的频率包括

32kHz、44.1kHz、48kHz、88.2kHz、96kHz

器件型号

TAS5780M

封装

封装尺寸（标称值）

TSSOP (48)

12.50mm x 6.10mm

–

96kHz 处理器采样

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

•

通信特性

–

通过 I²C 端口实现软件模式控制

两个地址选择引脚 – 多达 4 个器件

兼具稳定性和可靠性

–

时钟误差和短路保护

过热和过流保护

简化框图

10% THD+N 时的功率与 PVDD 间的关系 ⁽¹⁾

DVDD

PVDD

80

High Voltage

Supply Domain

8 W Load Peak

6 W Load Peak

4 W Load Peak

6 W Load Continous

4 W Load Continous

Low-Voltage Supply Domain

Fixed-Function

Processing

High Performance

Stereo DAC

Closed Loop Stereo

Class D Amplifier

60

40

20

0

Serial

Audio In

001100

1101

Analog

Audio Out

PWM

Modulator

Power

Stage

Serial Audio

Out

µCDSP Core

TI

Burr-Brown Audio

Hardware

Control Port

Software Control Port

I²C Communication

GPIO/Status

5

10

15

Supply Voltage (V)

20

24

D002

(1) 在 TAS5780MEVM 电路板中进行了测试。

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASEG7

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

9.3 Feature Description................................................. 32

9.4 Device Functional Modes........................................ 54

9.5 Programming........................................................... 55

10 Application and Implementation........................ 67

10.1 Application Information.......................................... 67

10.2 Typical Applications ............................................. 69

11 Power Supply Recommendations ..................... 78

11.1 Power Supplies ..................................................... 78

12 Layout................................................................... 80

12.1 Layout Guidelines ................................................. 80

12.2 Layout Example .................................................... 82

13 Register Maps...................................................... 88

13.1 Registers - Page 0 ................................................ 88

13.2 Registers - Page 1 .............................................. 149

13.3 Registers - Page 253 .......................................... 156

13.4 DSP Memory Map............................................... 189

14 器件和文档支持 ................................................... 198

14.1 器件支持.............................................................. 198

14.2 接收文档更新通知 ............................................... 198

14.3 社区资源.............................................................. 199

14.4 商标..................................................................... 199

14.5 静电放电警告....................................................... 199

14.6 Glossary.............................................................. 199

15 机械、封装和可订购信息..................................... 199

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

6.1 Internal Pin Configurations........................................ 5

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics......................................... 10

7.6 Power Dissipation Characteristics .......................... 14

7.7 MCLK Timing ......................................................... 19

7.8 Serial Audio Port Timing – Slave Mode.................. 19

7.9 Serial Audio Port Timing – Master Mode................ 20

7.10 I²C Bus Timing – Standard ................................... 20

7.11 I²C Bus Timing – Fast........................................... 20

7.12 SPK_MUTE Timing .............................................. 21

7.13 Typical Characteristics.......................................... 23

Parametric Measurement Information ............... 30

Detailed Description ............................................ 31

9.1 Overview ................................................................. 31

9.2 Functional Block Diagram ....................................... 31

7

8

9

4 修订历史记录

日期

修订版本

注释

2016 年 12 月

*

最初发布。

2

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

5 Device Comparison Table

DEVICE NAME

MODULATION STYLE

PROCESSING TYPE

TAS5780MDCA

1SPW (Ternary)

100 MIPs, Fixed-Function (Uses single ROM image of process flow)

50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to

create several process flows)

TAS5754MDCA

TAS5756MDCA

1SPW (Ternary)

50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to

create several process flows)

BD Modulation

6 Pin Configuration and Functions

DCA Package

48-Pin TSSOP with PowerPAD™

Top View

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

BSTRPA–

SPK_OUTA–

PGND

BSTRPB–

SPK_OUTB–

PGND

SPK_OUTA+

BSTRPA+

PVDD

SPK_OUTB+

BSTRPB+

PVDD

GVDD_REG

SPK_GAIN/FREQ

AGND

PVDD

SPK_FAULT

PGND

10

11

12

13

14

15

16

17

SPK_INA–

SPK_INA+

DAC_OUTA

AVDD

SPK_INB–

SPK_INB+

DAC_OUTB

CPVSS

AGND

CN

SDA

GND

SCL

CP

PowerPAD^TM

18

19

GPIO0

CPVDD

DVDD

RESET

20

21

22

23

24

29

28

27

26

25

ADR1

DGND

GPIO2

DVDD_REG

SPK_MUTE

ADR0

MCLK

SCLK

SDIN

LRCK/FS

Pin Functions

INTERNAL

TERMINATION

TYPE⁽¹⁾

DESCRIPTION

NAME

ADR0

ADR1

NO.

26

20

10

15

14

Sets the LSB of the I²C address to 0 if pulled to GND, to 1 if pulled to DVDD

DI

Sets the second LSB of the I²C address to 0 if pulled to GND, to 1 if pulled to DVDD

AGND

AVDD

G

P

—

Ground reference for analog circuitry⁽²⁾

Power supply for internal analog circuitry

Figure 2

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =

Power, G = Ground (0 V)

(2) This pin should be connected to the system ground.

3

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Pin Functions (continued)

INTERNAL

TERMINATION

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for

the high-side gate drive for SPK_OUTA–

BSTRPA–

1

P

Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for

the high-side gate drive for SPK_OUTA+

BSTRPA+

BSTRPB–

BSTRPB+

5

Figure 3

Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for

the high-side gate drive for SPK_OUTB–

48

44

Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for

the high-side gate drive for SPK_OUTB+

CN

34

32

31

35

13

36

29

30

P

Figure 14

Figure 13

Figure 2

Negative pin for capacitor connection used in the line-driver charge pump

Positive pin for capacitor connection used in the line-driver charge pump

Power supply for charge pump circuitry

CP

CPVDD

CPVSS

DAC_OUTA

DAC_OUTB

DGND

P

Figure 14

–3.3-V supply generated by charge pump for the DAC

Single-ended output for Channel A of the DAC

AO

G

Figure 8

Single-ended output for Channel B of the DAC

—

Ground reference for digital circuitry. Connect this pin to the system ground.

Power supply for the internal digital circuitry

DVDD

P

Figure 2

Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided

as a connection point for filtering capacitors for this supply and must not be used to power any

external circuitry.

DVDD_REG

28

P

Figure 15

—

GND

33

18

21

G

Ground pin for device. This pin should be connected to the system ground.

GPIO0

GPIO2

DI/O

General purpose input/output pins (GPIOx). Refer to GPIO registers for configuration.

Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of

output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and

must not be used to power any external circuitry.

GVDD_REG

8

P

Figure 5

Word select clock for the digital signal that is active on the serial port's input data line. In I²S, LJ, and

RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds

to the frame sync boundary.

LRCK/FS

MCLK

25

DI/O

DI

Figure 11

22

3

Master clock used for internal clock tree and sub-circuit and state machine clocking

PGND

39

46

6

G

—

Ground reference for power device circuitry. Connect this pin to the system ground.

7

PVDD

41

42

43

19

17

23

16

24

11

12

38

37

40

P

Figure 1

Power supply for internal power circuitry

RESET

DI

Figure 17

Figure 10

Figure 11

Figure 9

Device reset input. Pull down to reset, pull up to activate device.

I²C serial control port clock

SCL

SCLK

DI/O

D1

AI

Bit clock for the digital signal that is active on the input data line of the serial data port

I²C serial control port data

SDA

SDIN

Figure 11

Data line to the serial data port

SPK_INA–

SPK_INA+

SPK_INB–

SPK_INB+

SPK_FAULT

Negative pin for differential speaker amplifier input A

Positive pin for differential speaker amplifier input A

Negative pin for differential speaker amplifier input B

Positive pin for differential speaker amplifier input B

Fault pin which is pulled low when an overcurrent or overtemperature fault occurs

AI

Figure 7

AI

DO

Figure 16

Figure 6

SPK_GAIN/F

REQ

9

AI

Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device.

SPK_OUTA–

SPK_OUTA+

SPK_OUTB–

SPK_OUTB+

2

4

AO

Negative pin for differential speaker amplifier output A

Positive pin for differential speaker amplifier output A

Negative pin for differential speaker amplifier output B

Positive pin for differential speaker amplifier output B

Figure 4

47

45

4

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Pin Functions (continued)

INTERNAL

TERMINATION

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and

pulled high (connected to DVDD) to unmute the device.

SPK_MUTE

PowerPAD

27

I

Figure 12

—

Provides both electrical and thermal connection from the device to the board. A matching ground pad

must be provided on the PCB and the device connected to it through solder. For proper electrical

operation, this ground pad must be connected to the system ground.

—

G

6.1 Internal Pin Configurations

DVDD

PVDD

3.3 V ESD

30 V ESD

Figure 1. PVDD Pins

Figure 2. AVDD, DVDD and CPVDD Pins

PVDD

GVDD

PVDD

BSTRPxx

7 V ESD

SPK_OUTxx

Figure 3. BSTRPxx Pins

Figure 4. SPK_OUTxx Pins

5

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Internal Pin Configurations (continued)

GVDD

PVDD

10 Ω

GVDD

10 kΩ

SPK_GAIN/FREQ

7 V ESD

Figure 5. GVDD_REG Pin

Figure 6. SPK_GAIN/FREQ Pin

AVDD

SPK_INxx

7 V ESD

Gain Switch

CPVSS

DAC_OUTA

Figure 7. SPK_INxx Pins

Figure 8. DAC_OUTx Pins

DVDD

SDA

DVDD

SCL

3.3 V

ESD

3.3 V

ESD

Figure 9. SDA Pin

Figure 10. SCL Pin

6

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Internal Pin Configurations (continued)

DVDD

MCLK

SCLK

SPK_MUTE

3.3 V

ESD

SDIN

3.3 V

ESD

LRCK/FS

Figure 11. SCLK, BCLK, SDIN, and LRCK/FS Pins

Figure 12. SPK_MUTE Pin

CVPDD

GND

CN

3.3 V

ESD

CP

3.3 V

ESD

CPVSS

3.3 V

ESD

Figure 13. CP Pin

Figure 14. CN and CPVSS Pins

DVDD

100 Ω

SPK_FAULT

DVDD_REG

28 V

ESD

1.8 V

ESD

Figure 15. DVDD_REG Pin

Figure 16. SPK_FAULT Pin

7

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Internal Pin Configurations (continued)

DVDD

RESET

3.3 V

ESD

Figure 17. RESET Pin

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

DVDD, AVDD,

Low-voltage digital, analog, charge pump supply

CPVDD

–0.3

3.9

V

PVDD

PVDD supply

–0.3

–0.5

–0.3

–25

–40

30

V

V_I(AmpCtrl)

V_I(DigIn)

V_{I(SPK_INxx)}

V_{I(SPK_OUTxx)}

Input voltage for SPK_GAIN/FREQ and SPK_FAULT pins

DVDD referenced digital inputs⁽²⁾

V_GVDD+ 0.3

V_DVDD+ 0.5

V

Analog input into speaker amplifier

Voltage at speaker output pins

6.3

32

V

Ambient operating temperature, T_A

Operating junction temperature, digital die

Operating junction temperature, power die

Storage temperature

85

°C

125

165

125

T_J

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

8

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

7.3 Recommended Operating Conditions

Free-air room temperature 25°C (unless otherwise noted)

MIN

NOM

MAX

3.63

26.4

UNIT

DVDD, AVDD, CPVDD

2.9

V_(POWER)

Power supply inputs

V

PVDD

4.5

BTL Mode

PBTL Mode

3

2

Ω

V

R_SPK

Minimum speaker load

V_IH(DigIn)

V_IL(DigIn)

Input logic high for DVDD referenced digital inputs⁽¹⁾⁽²⁾

Input logic low for DVDD referenced digital inputs⁽¹⁾⁽³⁾

0.9 × V_DVDD

V_DVDD

0

0.1 × V_DVDD

Minimum inductor value in LC filter under short-circuit

condition

L_OUT

1

4.7

µH

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) The best practice for driving the input pins of the TAS5780M device is to power the drive circuit or pullup resistor from the same supply

which provides the DVDD power supply.

(3) The best practice for driving the input pins of the TAS5780M device low is to pull them down, either actively or through pulldown

resistors to the system ground.

7.4 Thermal Information

TAS5780M

DCA (TSSOP)

48 PINS

THERMAL METRIC⁽¹⁾

UNIT

JEDEC

STANDARD

2-LAYER PCB

JEDEC

STANDARD

4-LAYER PCB

TAS5780MEVM

4-LAYER PCB

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

41.8

14.4

9.4

27.6

14.4

9.4

19.4

14.4

9.4

2

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JB

8.1

9.3

4.8

N/A

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

9

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM board and Audio

Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to

768 kHz unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O

Input logic high current level

for DVDD referenced digital

input pins⁽¹⁾

|IIH|1

V_IN(DigIn)= V_DVDD

10

µA

Input logic low current level

for DVDD referenced digital

input pins⁽¹⁾

|IIL|1

V_IH1

V_IL1

V_IN(DigIn)= 0 V

–10

Input logic high threshold for

DVDD referenced digital

inputs⁽¹⁾

70%

80%

V_DVDD

Input logic low threshold for

DVDD referenced digital

inputs⁽¹⁾

30%

V_DVDD

Output logic high voltage

level⁽¹⁾

V_OH(DigOut)

V_OL(DigOut)

I_OH= 4 mA

V_DVDD

Output logic low voltage

level⁽¹⁾

I_OH= –4 mA

22%

0.8

Output logic low voltage level

for SPK_FAULT

V_{OL(SPK_FAULT)}

GVDD_REG

With 100-kΩ pullup resistor

V

GVDD regulator voltage

7

I²C CONTROL PORT

Allowable load capacitance

for each I²C Line

C_L(I2C)

400

pF

f_SCL(fast)

f_SCL(slow)

Support SCL frequency

No wait states, fast mode

No wait states, slow mode

400

100

kHz

Noise margin at High level for

each connected device

(including hysteresis)

V_NH

0.2 × V_DD

V

MCLK AND PLL SPECIFICATIONS

D_MCLKAllowable MCLK duty cycle

f_MCLKSupported MCLK frequencies Up to 50 MHz

40%

128

60%

512

(2)

f_S

Clock divider uses fractional divide

D > 0, P = 1

6.7

1

20

f_PLL

PLL input frequency

MHz

Clock divider uses integer divide

D = 0, P = 1

SERIAL AUDIO PORT

Required LRCK/FS to SCLK

rising edge delay

t_DLY

5

ns

D_SCLK

f_S

f_SCLK

Allowable SCLK duty cycle

Supported input sample rates

Supported SCLK frequencies

SCLK frequency

40%

8

60%

96

kHz

(2)

32

64

f_S

Either master mode or slave mode

24.576

MHz

SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)

SPK_GAIN/FREQ voltage < 3 V,

see Adjustable Amplifier Gain and Switching

20

Frequency Selection

A_{V(SPK_AMP)}

Speaker amplifier gain

dBV

SPK_GAIN/FREQ voltage > 3.3 V,

see Adjustable Amplifier Gain and Switching

Frequency Selection

26

±1

Typical variation of speaker

amplifier gain

ΔA_{V(SPK_AMP)}

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK,RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) A unit of f_Sindicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the

TAS5780M device.

10

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM board and Audio

Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to

768 kHz unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Switching frequency depends on voltage

presented at SPK_GAIN/FREQ pin and the

clocking arrangement, including the incoming

sample rate, see Adjustable Amplifier Gain and

Switching Frequency Selection

Switching frequency of the

speaker amplifier

f_{SPK_AMP}

176.4

768

kHz

Injected Noise = 50 Hz to 60 Hz, 200 mV_P-P, Gain

= 26 dB, input audio signal = digital zero

K_SVR

Power supply rejection ratio

60

dB

V_PVDD= 24 V, I_{(SPK_OUT)}= 500 mA, T_J= 25°C,

includes PVDD/PGND pins, leadframe, bondwires

and metallization layers.

Drain-to-source on resistance

of the individual output

MOSFETs

120

r_DS(on)

mΩ

V_PVDD= 24 V, I_{(SPK_OUT)}= 500 mA, T_J= 25°C

90

SPK_OUTxx overcurrent

error threshold

OCE_THRES

OTE_THRES

7.5

A

Overtemperature error

threshold

165

1.3

°C

Time required to clear

overcurrent error after error

condition is removed.

OCE_CLRTIME

s

Time required to clear

overtemperature error after

error condition is removed.

OTE_CLRTIME

1.3

PVDD overvoltage error

threshold

OVE_THRES(PVDD)

UVE_THRES(PVDD)

27

V

PVDD undervoltage error

threshold

4.3

SPEAKER AMPLIFIER (STEREO BTL)

Measured differentially with zero input data,

SPK_GAIN/FREQ pin configured for 20 dB gain,

V_PVDD= 12 V

2

5

|V_OS

|

Amplifier offset voltage

mV

Measured differentially with zero input data,

SPK_GAIN/FREQ pin configured for 26 dB gain,

V_PVDD= 24 V

15

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω, A-

Weighted

49

59

81

82

14

8

V_PVDD= 15 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω, A-

Weighted

I_CN(SPK)

Idle channel noise

µV_RMS

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 4 Ω,

THD+N = 0.1%

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω,

THD+N = 0.1%

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%

23

13

34

20

40

33

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

P_O(SPK)

Output Power (Per Channel)

W

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

11

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM board and Audio

Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to

768 kHz unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

103

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

102

103

Signal-to-noise ratio

(referenced to 0 dBFS input

signal)

SNR

dB

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

105

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

0.021%

0.022%

0.02%

0.037%

0021%

0.028%

0.027%

0.038%

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

Total harmonic distortion and

noise

THD+N_SPK

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω,

Input Signal 250 mVrms,

1-kHz Sine, across f(S)

–90

–102

–93

V_PVDD= 15 V, SPK_GAIN = 26 dBV, R_SPK= 8 Ω,

Input Signal 250 mVrms,

1-kHz Sine, across f(S)

Cross-talk (worst case

between left-to-right and

right-to-left coupling)

X-talk_SPK

dB

V_PVDD= 19 V, SPK_GAIN = 26 dBV, R_SPK= 8 Ω,

Input Signal 250 mVrms,

1-kHz Sine, across f(S)

V_PVDD= 24 V, SPK_GAIN = 26 dBV, R_SPK= 8 Ω,

Input Signal 250 mVrms,

–93

1-kHz Sine, across f(S)

SPEAKER AMPLIFIER (MONO PBTL)

Measured differentially with zero input data,

SPK_GAIN/FREQ pin configured for 20 dB gain,

V_PVDD= 12 V

0.7

4

|V_OS

|

Amplifier offset voltage

mV

Measured differentially with zero input data,

SPK_GAIN/FREQ pin configured for 26 dB gain,

V_PVDD= 24 V

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω, A-

Weighted

48

49

83

82

V_PVDD= 15 V, SPK_GAIN = 20 dB, RSPK = 8 Ω,

A-Weighted

I_CN

Idle channel noise

µV_RMS

V_PVDD= 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω,

A-Weighted

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted

12

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM board and Audio

Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to

768 kHz unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 2 Ω,

THD+N = 0.1%, Unless otherwise noted

30

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 4 Ω,

THD+N = 0.1%, Unless otherwise noted

16

9

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω,

THD+N = 0.1%

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

THD+N = 0.1%, Unless otherwise noted

44

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%, Unless otherwise noted

22

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

13

P_O

Output power (per channel)

W

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

THD+N = 0.1%, Unless otherwise noted

50

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%, Unless otherwise noted

36

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

20

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

THD+N = 0.1%, Unless otherwise noted

40

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

THD+N = 0.1%, Unless otherwise noted

61

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

THD+N = 0.1%

34

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

105

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

104

Signal-to-noise ratio

(referenced to 0 dBFS input

signal)

SNR

dB

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

105

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω, A-

Weighted, –120 dBFS Input

107

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 2 Ω,

P_O= 1 W, f = 1kHz

0.014%

0.011%

0.014%

0.015%

0.013%

0.015%

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 12 V, SPK_GAIN = 20 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 15 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

Total harmonic distortion and

noise

THD+N

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

0.018%

0.012%

0.020%

P_O= 1 W, f = 1kHz

V, R_SPK= 4 Ω, P_O= 1 W, f = 1kHz

V_PVDD= 19 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 2 Ω,

P_O= 1 W, f = 1kHz

0.028%

0.02%

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 4 Ω,

P_O= 1 W, f = 1kHz

V_PVDD= 24 V, SPK_GAIN = 26 dB, R_SPK= 8 Ω,

P_O= 1 W, f = 1kHz

0.027%

13

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

7.6 Power Dissipation Characteristics

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

21.30

21.33

21.30

21.33

21.34

21.36

2.08

(mA)

59.70

59.68

59.70

58.82

58.81

12.41

0.730

0.740

59.7

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.355

0.352

0.056

0.057

0.017

0.018

0.400

0.401

0.378

0.398

0.056

0.057

0.018

Idle

Mute

384

Standby

Powerdown

Idle

2.11

2.17

2.03

2.04

2.06

7.4

20

27.48

27.49

24.46

27.50

27.51

27.52

2.04

59.73

59.72

58.8

Mute

58.8

58.81

12.41

0.73

768

Standby

Powerdown

2.08

2.11

2.06

2.07

0.74

2.08

0.74

(1) Mute: B0-P0-R3-D0,D4 = 1

(2) Standby: B0-P0-R2-D4 = 1

(3) Power down: B0-P0-R2-D0 = 1

(4) I_PVDDrefers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current

draw were removed.

(5) I_DVDDrefers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the

DUT current draw were removed.

14

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

24.33

24.32

24.36

24.32

24.37

3.58

(mA)

59.74

59.70

58.81

58.82

58.84

12.40

12.41

12.42

0.74

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.467

0.464

0.465

0.081

0.042

0.538

0.537

0.528

0.535

0.080

0.081

0.042

Idle

Mute

384

Standby

Powerdown

Idle

3.57

3.58

3.52

0.74

3.54

0.74

11.1

20

30.70

30.65

30.67

3.072

30.69

3.54

59.70

59.72

59.71

58.80

58.81

12.40

12.41

12.42

0.74

Mute

768

Standby

Powerdown

3.54

3.58

3.53

0.74

3.55

0.74

15

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

25.07

25.08

25.10

25.12

25.08

25.11

3.92

(mA)

59.72

59.73

59.71

58.84

58.82

12.40

12.41

0.75

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.498

0.496

0.495

0.088

0.049

0.573

0.570

0.087

0.088

0.049

Idle

Mute

384

Standby

Powerdown

Idle

3.93

3.94

3.87

3.85

0.74

3.87

0.75

12

20

31.31

31.29

31.31

31.33

31.32

3.88

59.72

59.71

59.74

58.80

58.81

12.40

12.41

0.75

Mute

768

Standby

Powerdown

3.90

3.91

3.89

3.91

0.74

3.88

0.75

16

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

27.94

27.91

27.75

27.98

27.94

27.88

5.09

(mA)

59.73

59.75

59.69

58.84

58.87

58.85

12.41

0.74

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.616

0.613

0.614

0.613

0.612

0.117

0.118

0.119

0.078

0.080

0.693

0.690

0.117

0.118

0.078

0.079

Idle

Mute

384

Standby

Powerdown

Idle

5.12

5.19

5.02

5.06

0.74

5.14

0.74

15

26

33.05

33.03

33.08

33.03

33.04

33.05

5.07

59.7

59.72

59.68

58.81

58.80

12.41

0.74

Mute

768

Standby

Powerdown

5.09

5.14

5.02

5.04

0.74

5.09

0.74

17

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

32.27

32.19

32.08

32.27

32.24

32.22

6.95

(mA)

59.77

59.76

59.75

58.85

58.87

58.86

12.40

12.42

12.41

0.74

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.830

0.828

0.826

0.827

0.826

0.177

0.178

0.137

0.138

0.139

0.883

0.882

0.879

0.880

0.879

0.177

0.178

0.137

0.138

Idle

Mute

384

Standby

Powerdown

Idle

6.93

7.00

6.89

6.90

0.74

6.96

0.73

19.6

26

34.99

34.95

34.97

34.96

34.98

34.96

6.93

59.74

59.71

58.85

58.83

58.81

12.40

12.42

12.41

0.74

Mute

768

Standby

Powerdown

6.93

6.98

6.84

6.89

0.74

6.90

0.73

18

TAS5780M

www.ti.com.cn

ZHCSFY4 –DECEMBER 2016

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

36.93

36.87

36.77

36.94

36.89

36.85

8.73

(mA)

59.80

59.81

59.76

58.91

58.89

58.90

12.40

0.74

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

1.084

1.082

1.080

1.081

1.080

1.079

0.250

0.210

0.211

1.081

1.082

1.081

1.079

1.078

0.249

0.250

0.210

Idle

Mute

384

Standby

Powerdown

Idle

8.72

8.71

8.64

8.66

0.74

8.69

0.73

24

26

36.84

36.86

36.83

36.85

36.84

36.82

8.66

59.73

59.76

59.78

58.85

58.84

58.83

12.40

0.74

Mute

768

Standby

Powerdown

8.68

8.71

8.63

8.64

0.74

8.65

0.73

7.7 MCLK Timing

See Figure 18.

MIN

20

9

NOM

MAX

UNIT

t_MCLK

t_MCLKHMCLK pulse width, high

t_MCLKLMCLK pulse width, low

MCLK period

1000

ns

9

7.8 Serial Audio Port Timing – Slave Mode

See Figure 19.

MIN

1.024

40

16

8

NOM

MAX

UNIT

MHz

ns

f_SCLK

t_SCLK

t_SCLKL

t_SCLKH

t_SL

SCLK frequency

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

SCLK rising to LRCK/FS edge

LRCK/FS Edge to SCLK rising edge

Data setup time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

ns

t_LS

8

ns

t_SU

8

ns

t_DH

8

ns

t_DFS

15

ns

19

TAS5780M

ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

7.9 Serial Audio Port Timing – Master Mode

See Figure 20.

MIN NOM

MAX

UNIT

ns

t_SCLK

t_SCLKL

t_SCLKH

t_LRD

SCLK period

40

16

–10

8

SCLK pulse width, low

ns

SCLK pulse width, high

ns

LRCK/FS delay time from to SCLK falling edge

Data setup time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

20

15

ns

t_SU

ns

t_DH

8

ns

t_DFS

ns

7.10 I²C Bus Timing – Standard

MIN

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

100

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

4.7

t_LOW

4.7

µs

t_HI

High period of the SCL clock

4

4.7

µs

t_RS-SU

t_S-HD

t_D-SU

t_D-HD

t_SCL-R

t_SCL-R1

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

Setup time for (repeated) START condition

Hold time for (repeated) START condition

Data setup time

µs

4

µs

250

ns

Data hold time

0

900

1000

ns

Rise time of SCL signal

20 + 0.1C_B

4

ns

Rise time of SCL signal after a repeated START condition and after an acknowledge bit

Fall time of SCL signal

ns

Rise time of SDA signal

ns

Fall time of SDA signal

ns

Setup time for STOP condition

µs

7.11 I²C Bus Timing – Fast

See Figure 21.

MIN

MAX

UNIT

kHz

µs

ns

f_SCL

SCL clock frequency

400

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

1.3

t_LOW

t_HI

High period of the SCL clock

600

t_RS-SU

t_RS-HD

t_D-SU

t_D-HD

t_SCL-R

t_SCL-R1

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

t_SP

Setup time for (repeated)START condition

Hold time for (repeated)START condition

Data setup time

600

ns

600

ns

100

ns

Data hold time

0

900

300

ns

Rise time of SCL signal

20 + 0.1C_B

600

ns

Rise time of SCL signal after a repeated START condition and after an acknowledge bit

Fall time of SCL signal

ns

Rise time of SDA signal

ns

Fall time of SDA signal

ns

Setup time for STOP condition

Pulse width of spike suppressed

ns

50

ns

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ZHCSFY4 –DECEMBER 2016

7.12 SPK_MUTE Timing

See Figure 22.

MIN

MAX

20

UNIT

ns

t_r

t_f

Rise time

Fall time

20

ns

t

MCLKH

"H"

0.7 × V

DVDD

0.3 × V

DVDD

"L"

t

MCLKL

MCLK

Figure 18. Timing Requirements for MCLK Input

LRCK/FS

(Input)

0.5 × DVDD

t

SCLKL

SCLKH

t

LS

SCLK

(Input)

t

SL

SCLK

DATA

(Input)

0.5 × DVDD

t

DH

SU

t

DFS

DATA

(Output)

Figure 19. MCLK Timing Diagram in Slave Mode

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ZHCSFY4 –DECEMBER 2016

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t_BCL

t

BCL

t

SCLK.

SCLK

(Input)

0.5 × DVDD

t

LRD

SCLK

LRCK/FS

(Input)

t

DFS

DATA

(Input)

0.5 × DVDD

t

DH

SU

DATA

(Output)

0.5 × DVDD

Figure 20. MCLK Timing Diagram in Master Mode

Repeated

START

STOP

t

P-SU

t

D-SU

D-HD

SDA-F

SDA-R

t

BUF.

SDA

t

SP

SCL-R.

RS-HD

t

LOW.

SCL

t

HI.

t

RS-SU

t

SCL-F.

S-HD.

Figure 21. I²C Communication Port Timing Diagram

0.9 × DV

0.1 × DV

DD

SPK_MUTE

t

r

t

f

< 20 ns

<20ns

Figure 22. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin

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7.13 Typical Characteristics

All performance plots were taken using the TAS5780MEVM Board at room temperature, unless otherwise noted.

The term "traditional LC filter" refers to the output filter that is present by default on the TAS5780MEVM Board.

Table 1. Quick Reference Table

OUTPUT

CONFIGURATIONS

PLOT TITLE

FIGURE NUMBER

Frequency Response

Figure 34

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Output Power vs PVDD

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

Efficiency vs Output Power

Bridge Tied Load (BTL)

Configuration Curves

Efficiency vs Output Power

Idle Current Draw (Filterless) vs PVDD

Crosstalk vs. Frequency

PVDD PSRR vs Frequency

DVDD PSRR vs Frequency

AVDD PSRR vs Frequency

CPVDD PSRR vs Frequency

Output Power vs PVDD

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

Efficiency vs Output Power

Parallel Bridge Tied

Load (PBTL)

Configuration

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7.13.1 Bridge Tied Load (BTL) Configuration Curves

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5780MEVM

board and Audio Precision System 2722 with Analog Analyzer filter set to 40-kHz brickwall filter. All

measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, unless

otherwise noted. For both the BTL plots and the PBTL plots, the LC filter used was 4.7 µH / 0.68 µF. Return to

Quick Reference Table.

80

60

40

20

0

10

8 W Load Peak

4 W Load

6 W Load

8 W Load

6 W Load Peak

4 W Load Peak

6 W Load Continous

4 W Load Continous

1

0.1

0.01

0.001

5

10

15

20

24

20

100

1k

10k

40k

Supply Voltage (V)

Frequency (Hz)

D002

D003

A_{V(SPK_AMP)}= 26 dBV

A_{V(SPK_AMP)}= 20 dBV

P_O= 1 W

V_PVDD= 12 V

Figure 23. Output Power vs PVDD – BTL

Figure 24. THD+N vs Frequency – BTL

10

1

10

1

4 W Load

6 W Load

8 W Load

4 W Load

6 W Load

8 W Load

0.1

0.01

0.001

20

100

1k

10k

40k

20

100

1k

10k

40k

Frequency (Hz)

D004

D005

A_{V(SPK_AMP)}= 20 dBV

P_O= 1 W

V_PVDD= 15 V

A_{V(SPK_AMP)}= 26 dBV

P_O= 1 W

V_PVDD= 18 V

Figure 25. THD+N vs Frequency – BTL

Figure 26. THD+N vs Frequency – BTL

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10

1

4 W Load

6 W Load

8 W Load

4 W Load

6 W Load

8 W Load

1

0.1

0.01

0.001

20

0.001

100

1k

10k

40k

10m

100m

1

10

30

Frequency (Hz)

Output Power (W)

D006

D007

A_{V(SPK_AMP)}= 26 dBV

P_O= 1 W

V_PVDD= 24 V

A_{V(SPK_AMP)}= 20 dBV

V_PVDD= 12 V

Figure 27. THD+N vs Frequency – BTL

Figure 28. THD+N vs Power – BTL

10

1

10

1

4 W Load

6 W Load

8 W Load

4 W Load

6 W Load

8 W Load

0.1

0.01

0.001

10m

100m

1

10

40

10m

100m

1

10

50

Output Power (W)

D008

D009

A_{V(SPK_AMP)}= 20

dBV

V_PVDD= 15 V

A_{V(SPK_AMP)}= 26

dBV

V_PVDD=

18 V

Figure 29. THD+N vs Power – BTL

Figure 30. THD+N vs Power – BTL

10

100

90

80

70

60

50

40

30

20

10

0

4 W Load

6 W Load

8 W Load

1

0.1

0.01

Gain = 20 dB, PWM Freq = 384 kHz

Gain = 26 dB, PWM Freq = 384 kHz

Gain = 20 dB, PWM Freq = 768 kHz

Gain = 26 dB, PWM Freq = 768 kHz

0.001

10m

100m

1

10

50

10

15

20

Output Power (W)

Supply Voltage (V)

D010

D011

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V

R_SPK= 4 Ω

Figure 31. THD+N vs Power – BTL

Figure 32. Idle Channel Noise vs PVDD – BTL

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ZHCSFY4 –DECEMBER 2016

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100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PV_DD= 12 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

PV_DD= 12 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

0

20

40

60

80

0

20

40

60

80

Output Power (W)

D012

D013

R_SPK= 4 Ω

R_SPK= 6 Ω

Figure 33. Efficiency vs Output Power – BTL

Figure 34. Efficiency vs Output Power – BTL

100

90

80

70

60

50

40

30

20

10

0

60

50

40

30

20

10

0

PV_DD= 12 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

0

20

40

60

80

5

10

15

20

25

Output Power (W)

Supply Voltage (V)

D014

D015

R_SPK= 8 Ω

f_{SPK_AMP}= 768 kHz

R_SPK= 8 Ω

Figure 35. Efficiency vs Output Power – BTL

Figure 36. Idle Current Draw (Filterless) vs V_PVDD– BTL

0

Ch 1 to Ch 2

Ch 2 to Ch 1

Left Channel

Right Channel

-20

-40

-20

-40

-60

-80

-60

-80

-100

-120

-100

20

100

1k

10k

40k

100

1k

10k

40k

Frequency (Hz)

Frequency

D016

D017

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V + 250 mVac

Figure 37. Crosstalk vs Frequency – BTL

Figure 38. PVDD PSRR vs Frequency – BTL

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0

-20

Left Channel

Right Channel

Left Channel

Right Channel

-20

-40

-60

-80

-40

-60

-80

-100

20

-100

100

1k

10k

40k

20

100

1k

10k

40k

Frequency

D018

D019

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V

V_DVDD= 3.3 V + 250 mVac

V_AVDD= 3.3 V + 250 mVac

Figure 39. DVDD PSRR vs Frequency – BTL

Figure 40. AVDD PSRR vs Frequency – BTL

0

-20

28

24

20

16

12

Left Channel

Right Channel

-40

-60

-80

-100

20

100

1k

10k

40k

20

100

1k

10k

40k

Frequency

Frequency (Hz)

D020

D001

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 24 V

A_{V(SPK_AMP)}= 20 dB

PVDD = 12 V

V_CPVDD= 3.3 V + 250 mVac

Figure 41. CPVDD PSRR vs Frequency – BTL

Figure 42. Frequency Response

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7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

Return to Quick Reference Table.

160

10

1

4 W Load Peak

2 W Load

3 W Load

4 W Load

3 W Load Peak

140

120

100

80

2 W Load Peak

3 W Load Continous

2 W Load Continous

0.1

60

40

0.01

20

0

0.001

5

10

15

Supply Voltage (V)

20

24

20

100

1k

10k

40k

Frequency (Hz)

D021

D022

A_{V(SPK_AMP)}= 26 dBV

A_{V(SPK_AMP)}= 20 dBV

P_O= 1 W

V_PVDD= 12 V

Figure 43. Output Power vs PVDD – PBTL

Figure 44. THD+N vs Frequency – PBTL

10

1

10

1

2 W Load

3 W Load

4 W Load

2 W Load

3 W Load

4 W Load

0.1

0.01

0.001

20

100

1k

10k

40k

20

100

1k

10k

40k

Frequency (Hz)

D023

D024

A_{V(SPK_AMP)}= 20 dBV

P_O= 1 W

V_PVDD= 15 V

A_{V(SPK_AMP)}= 26 dBV

P_O= 1 W

V_PVDD= 18 V

Figure 45. THD+N vs Frequency – PBTL

Figure 46. THD+N vs Frequency – PBTL

10

1

10

1

2 W Load

3 W Load

4 W Load

2 W Load

3 W Load

4 W Load

0.1

0.01

0.001

20

100

1k

10k

40k

10m

100m

1

10

50

Frequency (Hz)

Output Power (W)

D025

D026

A_{V(SPK_AMP)}= 26 dBV

P_O= 1 W

V_PVDD= 24 V

A_{V(SPK_AMP)}= 20 dBV

V_PVDD= 12 V

Figure 47. THD+N vs Frequency – PBTL

Figure 48. THD+N vs Power – PBTL

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10

1

2 W Load

3 W Load

4 W Load

2 W Load

3 W Load

4 W Load

1

0.1

0.01

0.001

10m

0.001

100m

1

10

80

10m

100m

1

10

100

Output Power (W)

D027

D028

A_{V(SPK_AMP)}= 20 dBV

V_PVDD= 15 V

A_{V(SPK_AMP)}= 26 dBV

V_PVDD= 18 V

Figure 49. THD+N vs Power – PBTL

Figure 50. THD+N vs Power – PBTL

100

90

80

70

60

50

40

30

20

10

0

10

1

2 W Load

3 W Load

4 W Load

0.1

0.01

Gain = 20 dB, PWM Freq = 384 kHz

Gain = 26 dB, PWM Freq = 384 kHz

Gain = 20 dB, PWM Freq = 768 kHz

Gain = 26 dB, PWM Freq = 768 kHz

0.001

10m

100m

1

10

150

5

10

15

20

25

Output Power (W)

Supply Voltage (V)

D029

D030

A_{V(SPK_AMP)}= 20 dBV

V_PVDD= 24 V

R_SPK= 4 Ω

Figure 51. THD+N vs Power – PBTL

Figure 52. Idle Channel Noise vs PVDD – PBTL

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PV_DD= 12 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

0

20

40

60

80

100

0

20

40

60

80

100

Output Power (W)

D031

D032

A_{V(SPK_AMP)}= 26

dBV

R_SPK= 2 Ω

A_{V(SPK_AMP)}= 20

dBV

R_SPK= 3 Ω

Figure 53. Efficiency vs Output Power – PBTL

Figure 54. Efficiency vs Output Power

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ZHCSFY4 –DECEMBER 2016

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100

90

80

70

60

50

40

30

20

10

0

PV_DD= 12 V

PV_DD= 15 V

PV_DD= 18 V

PV_DD= 24 V

0

20

40

60

80

Output Power (W)

D033

A_{V(SPK_AMP)}= 20 dBV

R_SPK= 4 Ω

Figure 55. Efficiency vs Output Power

8 Parametric Measurement Information

PARAMETER

Stereo BTL

Mono PBTL

FIGURE

图 84

图 85

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9 Detailed Description

9.1 Overview

The TAS5780M device integrates 4 main building blocks together into a single cohesive device that maximizes

sound quality, flexibility, and ease of use. The 4 main building blocks are listed below:

•

A stereo audio DAC, boasting a strong Burr-Brown heritage with a highly flexible serial audio port.

A µCDSP audio processing core, with a pre-programmed ROM image.

A flexible closed-loop amplifier capable of operating in stereo or mono, at several different switching

frequencies, and with a variety of output voltages and loads.

An I²C control port for communication with the device

•

The device requires only two power supplies for proper operation. A DVDD supply is required to power the low-

voltage digital and analog circuitry. Another supply, called PVDD, is required to provide power to the output stage

of the audio amplifier. The operating range for these supplies is shown in the Recommended Operating

Conditions table.

Communication with the device is accomplished through the I²C control port. A speaker amplifier fault line is also

provided to notify a system controller of the occurrence of an overtemperature, overcurrent, overvoltage, or

undervoltage. Two digital GPIO pins are available for use. In the fixed function ROM image of the TAS5780M,

the GPIO2 pin is used as an SDOUT terminal. The other GPIO is unused.

The µCDSP audio processing core is pre-programmed with a configurable DSP program. The RD GUI provides a

means by which to manipulate the controls associated with that Process Flow.

9.2 Functional Block Diagram

Internal

Voltage

Supplies

Charge

Pump

Internal Gate

Drive Regulator

1.8-V

Regulator

Internal Voltage

Supplies

Closed Loop Class D Amplifier

Gate

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

Full Bridge

Power

Stage A

µCDSP

Output

Current

Monitoring

and

Analog

to

Drives

MCLK

SCLK

Fixed-

Function

ROMProcess

Flow

PWM

Modulator

Full Bridge

Power

Stage B

Gate

Drives

Protection

DAC

Serial

Audio

Port

LRCK/FS

SDIN

Clock Monitoring

and Error Protection

Die Temperature

Monitoring and Protection

Error Reporting

SDOUT

Internal Control Registers and State Machines

GPIO0 RESET GPIO2

SPK_GAIN/FREQ

SCL

SDA

ADR0

ADR1

SPK_MUTE

SPK_SD SPK_FAULT

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9.3 Feature Description

9.3.1 Power-on-Reset (POR) Function

The TAS5780M device has a power-on reset function. The power-on reset feature resets all of the registers to

their default configuration as the device is powering up. When the low-voltage power supply used to power

DVDD, AVDD, and CPVDD exceeds the POR threshold, the device sets all of the internal registers to their

default values and holds them there until the device receives valid MCLK, SCLK, and LRCK/FS toggling for a

period of approximately 4 ms. After the toggling period has passed, the internal reset of the registers is removed

and the registers can be programmed via the I²C Control Port.

9.3.2 Device Clocking

The TAS5780M devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface in one form or another.

f_S

(24-bit)

16 f_S

(24-bit)

128 f_S

(~8-bit)

Serial Audio

Interface

(Input)

µCDSP

(including

interpolator)

Delta

Sigma

Modulator

I to V

Line

Driver

Current

Segments

+

Audio

In

Audio

Out

Charge Pump

CPCK

DSPCK

OSRCK

DACCK

LRCK/FS

Figure 56. Audio Flow with Respective Clocks

Figure 56 shows the basic data flow at basic sample rate (f_S). When the data is brought into the serial audio

interface, the data is processed, interpolated and modulated to 128 × f_Sbefore arriving at the current segments

for the final digital to analog conversion.

Figure 57 shows the clock tree.

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Feature Description (continued)

PLLEN

(P0-R4)

MCLK

SREF

Divider

(P0-R13)

DDSP (P0-R27)

SCLK

GPIO

MCLK

SDAC

(P0-R14)

PLL

K × R/P

PLLCKIN

PLLCK

K = J.D

J = 1,2,3,…..,62,63

D= 0000,0001,….,9998,9999

R= 1,2,3,4,….,15,16

DACCK (DAC Clock )

MCLK

GPIO

Divider

CPCK (Charge Pump Clock )

DNCP (P0-R29)

P= 1,2,….,127,128

DDAC

(P0-R28)

Divider

OSRCK

(Oversampling

Ratio Clock )

Divider

MUX

DOSR

(P0-R30)

Divide

by 2

I16E (P0-R34)

Figure 57. TAS5780M Clock Distribution Tree

The Serial Audio Interface typically has 4 connection pins which are listed as follows:

•

MCLK (System Master Clock)

SCLK (Bit Clock)

LRCK/FS (Left Right Word Clock and Frame Sync)

SDIN (Input Data)

The output data, SDOUT, is presented on one of the GPIO pins.

See the GPIO Port and Hardware Control Pins section)

The device has an internal PLL that is used to take either MCLK or SCLK and create the higher rate clocks

required by the DSP and the DAC clock.

In situations where the highest audio performance is required, bringing MCLK to the device along with SCLK and

LRCK/FS is recommended. The device should be configured so that the PLL is only providing a clock source to

the DSP. All other clocks are then a division of the incoming MCLK. To enable the MCLK as the main source

clock, with all others being created as divisions of the incoming MCLK, set the DAC CLK source Mux (SDAC in

Figure 57) to use MCLK as a source, rather than the output of the MCLK/PLL Mux.

9.3.3 Serial Audio Port

9.3.3.1 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the

appropriate pins. To configure the device in master mode, first put the device into reset, then use registers

SCLKO and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSCLK and RLRK

(P0-R12). Finally, exit reset.

Figure 58 shows a simplified serial port clock tree for the device in master mode.

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Feature Description (continued)

Audio Related System Clock (MCLK)

MCLK

SCLK

SCLKO (Bit Clock Output In Master Mode)

Divider

Q1 = 1...128

LRCK/FS (LR Clock or Frame Sync Output In

Master Mode

Divider

LRCK/FS

Q1 = 1...128

Figure 58. Simplified Clock Tree for MCLK Sourced Master Mode

In master mode, MCLK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer

divisions of MCLK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the

PLL in standalone mode. The PLL should be configured to ensure that the on-chip processor can be driven at

the maximum clock rate. The master mode of operation is described in the Clock Master from a Non-Audio Rate

Master Clock section.

When used with audio rate master clocks, the register changes that should be done include switching the device

into master mode, and setting the divider ratio. An example of the master mode of operations is using 24.576

MHz MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz

sample rate clock output. In master mode, the DAC section of the device is also running from the PLL output.

The TAS5780M device is able to meet the specified audio performance while using the internal PLL. However,

using the MCLK CMOS oscillator source will have less jitter than the PLL.

To switch the DAC clocks (SDAC in the Figure 57) the following registers should be modified

•

Clock Tree Flex Mode (P253-R63 and P253-R64)

DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MCLK input, and OSR is set to whatever the

DAC source is)

•

The DAC clock divider should be 16 f_S.

–

16 × 48 kHz = 768 kHz

24.576 MHz (MCLK in) / 768 kHz = 32

Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives

0x00 = 1, therefore 32 must be converter to 0x1F (31dec).

9.3.3.2 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running a 96-kHz sampling system. Given the clock tree for the device (shown in

Figure 57), a non-audio clock rate cannot be brought into the MCLK to the PLL in master mode. Therefore, the

PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

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Feature Description (continued)

Non-Audio MCLK

GPOIx

PLL

GPOIy

New

Audio

MCLK

Master Mode

SLCK Integer

Divider

SCLK

Out

SCLK

Master Mode

LRCK/FS

Integer Divider

LRCK/FS

Out

LRCK/FS

Figure 59. Generating Audio Clocks Using Non-Audio Clock Sources

The clock flow through the system is shown in Figure 59. The newly generated MCLK must be brought out of the

device on a GPIO pin, then brought into the MCLK pin for integer division to create SCLK and LRCK/FS outputs.

NOTE

Pull-up resistors should be used on SCLK and LRCK/FS in master mode to ensure the

device remains out of sleep mode.

9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)

The TAS5780M device requires a system clock to operate the digital interpolation filters and advanced segment

DAC modulators. The system clock is applied at the MCLK input and supports up to 50 MHz. The TAS5780M

device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling

frequencies in the bands of 32 kHz, (44.1 – 48 kHz), (88.2 – 96 kHz) are supported.

NOTE

Values in the parentheses are grouped when detected, for example, 88.2 kHz and 96 kHz

are detected as double rate, 32 kHz, 44.1 kHz and 48 kHz are detected as single rate and

so on.

In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and

PLL to drive the µCDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the

Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common

audio sampling rates.

MCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by

configuring various PLL and clock-divider registers directly. In slave mode, auto clock mode should be disabled

using P0-R37. Additionally, the user can be required to ignore clock error detection if external clocks are not

available for some time during configuration or if the clocks presented on the pins of the device are invalid. The

extended programmability allows the device to operate in an advanced mode in which the device becomes a

clock master and drive the host serial port with LRCK/FS and SCLK, from a non-audio related clock (for

example, using a setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SCLK]).

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Feature Description (continued)

Table 2 shows the timing requirements for the system clock input. For optimal performance, use a clock source

with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master

Mode section.

Table 2. System Master Clock Inputs for Audio Related Clocks

SYSTEM CLOCK FREQUENCY (f_MCLK) (MHz)

SAMPLING

FREQUENCY

64 f_S

128 f_S

1.024⁽²⁾

2.048⁽²⁾

4.096⁽²⁾

5.6488⁽²⁾

6.144⁽²⁾

11.2896⁽²⁾

12.288⁽²⁾

192 f_S

1.536⁽²⁾

3.072⁽²⁾

6.144⁽²⁾

8.4672⁽²⁾

9.216⁽²⁾

16.9344

18.432

256 f_S

2.048

384 f_S

3.072

512 f_S

4.096

8 kHz

16 kHz

32 kHz

44.1 kHz

48 kHz

88.2 kHz

96 kHz

4.096

6.144

8.192

12.288

16.9344

18.432

33.8688

36.864

16.384

22.5792

24.576

45.1584

49.152

See⁽¹⁾

11.2896

12.288

22.5792

24.576

(1) This system clock rate is not supported for the given sampling frequency.

(2) This system clock rate is supported by PLL mode.

9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)

9.3.3.4.1 Clock Generation using the PLL

The TAS5780M device supports a wide range of options to generate the required clocks as shown in Figure 57.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SCLK or MCLK, a

GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-

R13, D[6:4]. The TAS5780M device provides several programmable clock dividers to achieve a variety of

sampling rates. See Figure 57.

If PLL functionality is not required, set the PLLEN value on P0-R4, D[0] to 0. In this situation, an external master

clock is required.

Table 3. PLL Configuration Registers

CLOCK MULTIPLEXER

REGISTER

SREF

FUNCTION

PLL Reference

BITS

B0-P0-R13-D[6:4]

DDSP

Clock divider

B0-P0-R27-D[6:0]

B0-P0-R32-D[6:0]

B0-P0-R33-D[7:0]

DSCLK

DLRK

External SCLK Div

External LRCK/FS Div

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9.3.3.4.2 PLL Calculation

The TAS5780M device has an on-chip PLL with fractional multiplication to generate the clock frequency required

by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of

clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to

50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, D[0]. When the PLL is enabled, the

PLL output clock PLLCK is given by Equation 1:

PLLCKIN x R x J.D

P

PLLCKIN x R x K

P

PLLCK =

or PLLCK =

where

•

R = 1, 2, 3,4, ... , 15, 16

J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999

K = [J value].[D value]

P = 1, 2, 3, ... 15

(1)

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while

D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

9.3.3.4.2.1 Examples:

•

If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 14.03, then J = 14, D = 0300

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

•

1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

•

6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

4 ≤ J ≤ 11

R = 1

When the PLL is enabled,

•

f_S= (PLLCLKIN × K × R) / (2048 × P)

The value of N is selected so that f_S× N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and f_S= 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and f_S= 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 4.

Table 4. PLL Registers

DIVIDER

PLLE

FUNCTION

PLL enable

PLL P

BITS

P0-R4, D[0]

PPDV

PJDV

P0-R20, D[3:0]

P0-R21, D[5:0]

P0-R22, D[5:0]

P0-R23, D[7:0]

P0-R24, D[3:0]

PLL J

PDDV

PRDV

PLL D

PLL R

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Table 5. PLL Configuration Recommendations

EQUATIONS

f_S(kHz)

DESCRIPTION

Sampling frequency

R_MCLK

Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)

System master clock frequency at MCLK input (pin 20)

MCLK (MHz)

PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 57

One of the PLL coefficients in Equation 1

PLL REF (MHz) Internal reference clock frequency which is produced by MCLK / P

P

M = K × R

K = J.D

R

The final PLL multiplication factor computed from K and R as described in Equation 1

One of the PLL coefficients in Equation 1

PLL f_S

DSP f_S

NMAC

Ratio between f_Sand PLL VCO frequency (PLL VCO / f_S)

Ratio between operating clock rate and f_S(PLL f_S/ NMAC)

The clock divider value in Table 3

DSP CLK (MHz) The operating frequency as DSPCK in Figure 57

MOD f_S

Ratio between DAC operating clock frequency and f_S(PLL f_S/ NDAC)

MOD f (kHz)

NDAC

DAC operating frequency as DACCK in

DAC clock divider value in Table 3

OSR clock divider value in Table 3 for generating OSRCK in Figure 57. DOSR must be chosen so that MOD f_S/ DOSR =

16 for correct operation.

DOSR

NCP

CP f

NCP (negative charge pump) clock divider value in Table 3

Negative charge pump clock frequency (f_S× MOD f_S/ NCP)

Percentage of error between PLL VCO / PLL f_Sand f_S(mismatch error).

% Error

•

This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).

This value can be non-zero only when the TAS5780M device acts as a master.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL.

Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

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9.3.3.5 Serial Audio Port – Data Formats and Bit Depths

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN

(pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift

register of the audio interface. Serial data is clocked into the TAS5780M device on the rising edge of SCLK. The

LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

Table 7. TAS5780M Audio Data Formats, Bit Depths and Clock Rates

MAXIMUM LRCK/FS

FREQUENCY (kHz)

FORMAT

DATA BITS

MCLK RATE (f_S)

SCLK RATE (f_S)

I²S/LJ/RJ

32, 24, 20, 16

Up to 96

128 to 3072 (≤ 50 MHz)

128 to 3072

64, 48, 32

125, 256

Up to 48

TDM

32, 24, 20, 16

96

128 to 512

The TAS5780M device requires the synchronization of LRCK/FS and system clock, but does not require a

specific phase relation between LRCK/FS and system clock.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and system clock is completed.

If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and SCLK is completed.

9.3.3.5.1 Data Formats and Master/Slave Modes of Operation

The TAS5780M device supports industry-standard audio data formats, including standard I²S and left-justified.

Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio

data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 60 through Figure 65.

The TAS5780M device also supports right-justified, and TDM data. I²S, LJ, RJ, and TDM are selected using

Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted.

Default setting is I²S and 24 bit word length. The I²S slave timing is shown in Figure 20.

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS5780M device can act as an I²S master, by generating SCLK and

LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or

Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing

requirements in Master Mode. For Slave Mode timing, please refer to the Serial Audio Port Timing – Slave Mode

section.

Table 8. I²S Master Mode Registers

REGISTER

FUNCTION

P0-R9-B0, B4, and B5

P0-R32-D[6:0]

I²S Master mode select

SCLK divider and LRCK/FS divider

P0-R33-D[7:0]

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1 t_{S .}

Right-channel

Left-channel

LRCK/FS

SLCK

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

…

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

1

2

24

2

23 24

DATA

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Figure 60. Left Justified Audio Data Format

1 t_{S .}

LRCK/FS

SLCK

Left-channel

Right-channel

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

…

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

23 24

1

23 24

DATA

LSB

MSB

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 61. I²S Audio Data Format

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The following data formats are only available in software mode.

1 /f_{S .}

Right-channel

Left-channel

LRCK/FS

SLCK

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

DATA

…

1

2

15 16

1

2

15 16

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

1

2

24

1

2

23 24

DATA

MSB

LSB

MSB

LSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 62. Right Justified Audio Data Format

1 /f_{S .}

LRCK/FS

SLCK

…

Audio data word = 16-bit, Offset = 0

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

Data Slot 2

LSB

MSB

LSB

MSB

Audio data word = 24-bit, Offset = 0

-

,

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

LSB

MSB

Audio data word = 32-bit, Offset = 0

…

1

2

31 32

LSB

1

2

31 32

LSB

DATA

MSB

TDM Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 63. TDM 1 Audio Data Format

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1 /f_{S .}

OFFSET = 1

LRCK/FS

SLCK

…

Audio data word = 16-bit, Offset = 1

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = 1

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = 1

…

1

2

31 32

LSB

1

2

31 32

DATA

Data Slot 1

Data Slot 2

LSB

MSB

TDM Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 64. TDM 2 Audio Data Format

1 /f_{S .}

OFFSET = n

LRCK/FS

SLCK

…

Audio data word = 16-bit, Offset = n

…

1

2

15 16

1

2

15 16

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = n

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = n

…

1

2

31 32

LSB

1

2

31 32

LSB

DATA

Data Slot 1

Data Slot 2

MSB

TDM Data Format with OFFSET = N

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 65. TDM 3 Audio Data Format

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9.3.3.6 Input Signal Sensing (Power-Save Mode)

The TAS5780M device has a zero-detect function. The zero-detect function can be applied to both channels of

data as an AND function or an OR function, via controls provided in the control port in P0-R65-D[2:1].Continuous

Zero data cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59,

D[6:4] for the data which is clocked in on the left frame of an I²S signal or Slot 1 of a TDM signal and P0-R59,

D[2:0] for the data which is clocked in on the right frame of an I²S signal or Slot 2 of a TDM signal as shown in

Table 10. Default values are 0 for both channels.

In Hardware mode, the device uses default values.

Table 9. Zero Detection Mode

ATMUTECTL

VALUE

FUNCTION

Zero data triggers for the two channels for zero detection are

ORed together.

0

Bit : 2

Zero data triggers for the two channels for zero detection are

ANDed together.

1 (Default)

0

Zero detection and analog mute are disabled for the data

clocked in on the right frame of an I²S signal or Slot 2 of a

TDM signal.

Bit : 1

Bit : 0

Zero detection analog mute are enabled for the data clocked in

on the right frame of an I²S signal or Slot 2 of a TDM signal.

1 (Default)

0

Zero detection analog mute are disabled for the data clocked

in on the left frame of an I²S signal or Slot 1 of a TDM signal.

Zero detection analog mute are enabled for the data clocked in

on the left frame of an I²S signal or Slot 1 of a TDM signal.

1 (Default)

Table 10. Zero Data Detection Time

ATMUTETIML OR ATMA

NUMBER OF LRCK/FS CYCLES

TIME at 48 kHz

21 ms

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1024

5120

106 ms

10240

25600

51200

102400

256000

512000

213 ms

533 ms

1.066 secs

2.133 secs

5.333 secs

10.66 secs

9.3.4 Enable Device

To play audio after the device is powered up or reset the device must be enabled by writing book 0x00, page

0x00, register 0x02 to 0x00.

9.3.4.1 Example

The following is a sample script for enabling the device:

#Enable DUT

w 90 00 00 #Go to page 0

w 90 7f 00 #Go to book 0

w 90 02 00 #Enable device

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9.3.5 Volume Control

9.3.5.1 DAC Digital Gain Control

A basic DAC digital gain control with range between 24 dB and –103 dB and mute is available on each channels

by P0-R61-D[7:0] for SPK_OUTB± and P0-R62-D[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB

step programmability over most gain and attenuation ranges. Table 11 lists the detailed gain versus programmed

setting for the basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the

same time or independently by P0-R61-D[1:0] . When D[1:0] set 00 (default), independent control is selected.

When D[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When D[1:0] set 10, SPK_OUTA± volume

controls the volume for both channels. To set D[1:0] to 11 is prohibited.

Table 11. DAC Digital Gain Control Settings

GAIN

SETTING

GAIN

(dB)

BINARY DATA

COMMENTS

0

1

0000-0000

0000-0001

24.0

23.5

Positive maximum

.

46

47

48

49

50

51

0010-1110

0010-1111

0011-0000

0011-0001

0011-0010

0011-0011

1.0

0.5

0.0

No attenuation (default)

–0.5

–1.0

–1.5

.

253

254

255

1111-1101

1111-1110

1111-1111

–102.5

–103

Negative maximum

–

Negative infinite (Mute)

∞

Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, D[7:6] and D[3:2] as shown in

Table 12. Also ramp-up step and ramp-down step can be controlled by P0-R63, D[5:4] and D[1:0] as shown in

Table 13.

Table 12. Ramp Up or Down Frequency

RAMP UP

SPEED

RAMP DOWN

FREQUENCY

EVERY N f_S

COMMENTS

EVERY N f_S

COMMENTS

00

01

10

11

1

Default

00

01

10

11

1

Default

2

4

Direct change

Table 13. Ramp Up or Down Step

RAMP UP

STEP

RAMP DOWN

COMMENTS

STEP dB

COMMENTS

STEP

00

01

10

11

4.0

2.0

1.0

0.5

00

01

–4.0

–2.0

–1.0

–0.5

Default

10

11

Default

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9.3.5.1.1 Emergency Volume Ramp Down

Emergency ramp down of the volume is provided for situations such as I²S clock error and power supply failure.

Ramp-down speed is controlled by P0-R64-D[7:6]. Ramp-down step can be controlled by P0-R64-D[5:4]. Default

is ramp-down by every f_Scycle with –4dB step.

9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection

The voltage divider between the GVDD_REG pin and the SPK_GAIN/FREQ pin is used to set the gain and

switching frequency of the amplifier. Upon start-up of the device, the voltage presented on the SPK_GAIN/FREQ

pin is digitized and then decoded into a 3-bit word which is interpreted inside the TAS5780M device to

correspond to a given gain and switching frequency. In order to change the SPK_GAIN or switching frequency of

the amplifier, the PVDD must be cycled off and on while the new voltage level is present on the

SPK_GAIN/FREQ pin.

Because the amplifier adds gain to both the signal and the noise present in the audio signal, the lowest gain

setting that can meet voltage-limited output power targets should be used. Using the lowest gain setting ensures

that the power target can be reached while minimizing the idle channel noise of the system. The switching

frequency selection affects three important operating characteristics of the device. The three affected

characteristics are the power dissipation in the device, the power dissipation in the inductor, and the target output

filter for the application.

Higher switching frequencies typically result in slightly higher power dissipation in the TAS5780M device and

lower dissipation in the inductor in the system, due to decreased ripple current through the inductor and

increased charging and discharging current in device and parasitic capacitances. Switching at the higher of the

available switching frequencies will result in lower overall dissipation in the system and lower operating

temperature of the inductors. However, the thermally limited power output of the device can be decreased in this

situation, because some of the TAS5780M device thermal headroom will be absorbed by the higher switching

frequency. Conversely inductor heating can be reduced by using the higher switching frequency to reduce the

ripple current.

Another advantage of increasing the switching frequency is that the higher frequency carrier signal can be filtered

by an L-C filter with a higher corner frequency, leading to physically smaller components. Use the highest

switching frequency that continues to meet the thermally limited power targets for the application. If thermal

constraints require heat reduction in the TAS5780M device, use a lower switching rate.

The switching frequency of the speaker amplifier is dependent on an internal synchronizing signal, (f_SYNC), which

is synchronous with the sample rate. The rate of the synchronizing signal is also dependent on the sample rate.

Refer to Table 14 below for details regarding how the sample rates correlate to the synchronizing signal.

Table 14. Sample Rates vs Synchronization Signal

SAMPLE RATE

[kHz]

f_SYNC

[kHz]

8

16

32

96

48

96

192

11.025

22.05

44.1

88.2

Table 15 summarizes the de-code of the voltage presented to the SPK_GAIN/FREQ pin. The voltage presented

to the SPK_GAIN/FREQ pin is latched in upon startup of the device. Subsequent changes require power cycling

the device. A gain setting of 20 dB is recommended for nominal supply voltages of 13 V and lower, while a gain

of 26 dB is recommended for supply voltages up to 26.4 V. Table 15 shows the voltage required at the

SPK_GAIN/FREQ pin for various gain and switching scenarios as well some example resistor values for meeting

the voltage range requirements.

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Table 15. Amplifier Switching Mode vs. SPK_GAIN/FREQ Voltage

V_{SPK_GAIN/FREQ}(V)

RESISTOR EXAMPLES

AMPLIFIER

SWITCHING

FREQUENCY MODE

R100 (kΩ): RESISTOR TO

GROUND

R101 (kΩ): RESISTOR TO

GVDD_REG

GAIN MODE

MIN

MAX

6.61

5.44

7

Reserved

8 × f_SYNC

R100 = 750

R101 = 150

6.6

R100 = 390

R101 = 150

4.67

3.89

3.11

2.33

1.56

0.78

0

5.43

4.66

3.88

3.1

6 × f_SYNC

5 × f_SYNC

4 × f_SYNC

8 × f_SYNC

6 × f_SYNC

5 × f_SYNC

4 × f_SYNC

26 dBV

R100 = 220

R101 = 150

R100 = 150

R101 = 150

R100 = 100

R101 = 150

R100 = 56

R101 = 150

2.32

1.55

0.77

20 dBV

R100 = 33

R101 = 150

R100 = 8.2

R101 = 150

9.3.7 Error Handling and Protection Suite

9.3.7.1 Device Overtemperature Protection

The TAS5780M device continuously monitors die temperature to ensure the temperature does not exceed the

OTE_THRESlevel specified in the Recommended Operating Conditions table. If an OTE event occurs, the

SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This

is a non-latched error and the device will attempt to self clear after OTE_CLRTIMEhas passed.

9.3.7.2 SPK_OUTxx Overcurrent Protection

The TAS5780M device continuously monitors the output current of each amplifier output to ensure the output

current does not exceed the OCE_THRESlevel specified in the Recommended Operating Conditions table. If an

OCE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance,

signifying a fault. This is a non-latched error and the device will attempt to self clear after OCE_CLRTIMEhas

passed.

9.3.7.3 Internal V_AVDDUndervoltage-Error Protection

The TAS5780M device internally monitors the AVDD net to protect against the AVDD supply dropping

unexpectedly. To enable this feature, P1-R5-B0 is used.

9.3.7.4 Internal V_PVDDUndervoltage-Error Protection

If the voltage presented on the PVDD supply drops below the UVE_THRES(PVDD)value listed in the Recommended

Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error,

which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions

table, the device resumes normal operation.

9.3.7.5 Internal V_PVDDOvervoltage-Error Protection

If the voltage presented on the PVDD supply exceeds the OVE_THRES(PVDD)value listed in the Recommended

Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing

error, which means that once the PVDD level drops below the level listed in the Recommended Operating

Conditions table, the device will resume normal operation.

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NOTE

The voltage presented on the PVDD supply only protects up to the level described in the

Recommended Operating Conditions table for the PVDD voltage. Exceeding the absolute

maximum rating may cause damage and possible device failure, because the levels

exceed that which can be protected by the OVE protection circuit.

9.3.7.6 External Undervoltage-Error Protection

The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack

in portable device, by using a voltage divider created with two resistors (see Figure 66).

•

If the SPK_MUTE pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external

undervoltage protection mode, which uses two trigger levels.

•

When the SPK_MUTE pin level reaches 2 V, soft mute process begins.

When the SPK_MUTE pin level reaches 1.2 V, analog output mute engages, regardless of digital audio level,

and analog output shutdown begins.

Figure 67 shows a timing diagram for external undervoltage error protection.

NOTE

The SPK_MUTE input pin voltage range is provided in the Recommended Operating

Conditions table. The ratio of external resistors must produce a voltage within the provided

input range. Any increase in power supply (such as power supply positive noise or ripple)

can pull the SPK_MUTE pin higher than the level specified in the Recommended

Operating Conditions table, potentially causing damage to or failure of the device.

Therefore, any monitored voltage (including all ripple, power supply variation, resistor

divider variation, transient spikes, and others) must be scaled by the resistor divider

network to never drive the voltage on the SPK_MUTE pin higher than the maximum level

specified in the Recommended Operating Conditions table.

When the divider is set correctly, any DC voltage can be monitored. Figure 66 shows a 12-V example of how the

SPK_MUTE is used for external undervoltage error protection.

V_DD

12 V

7.25 kΩ

SPK_MUTE

2.75 kΩ

Figure 66. SPK_MUTE Used in External Undervoltage Error Protection

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Digital attenuation followed by analog mute

Analog mute

SPK_MUTE

0.9 × DV

DD

2.0 V

1.2 V

0.1 × DV

DD

t

f

Figure 67. SPK_MUTE Timing for External Undervoltage Error Protection

9.3.7.7 Internal Clock Error Notification (CLKE)

When a clock error is detected on the incoming data clock, the TAS5780M device switches to an internal

oscillator and continues to the drive the DAC, while attenuating the data from the last known value. Once this

process is complete, the DAC outputs will be hard muted to the ground and the class D PWM output will stop

switching. The clock error can be monitored at B0-P0-R94 and R95. The clock error status bits are non-latching,

except for MCLK halted B0-P0-R95-D[4] and CERF B0-P0-R95-D[0] which are cleared when read.

9.3.8 GPIO Port and Hardware Control Pins

Internal Data

(P0-R82)

GPIOx Output Enable

P0-R8

GPIOx Output Inversion

P0-R87

GPIOx Output Selection

P0-R82

Off (low)

DSP GPIOx output

Register GPIOx output (P0-R86)

Auto mute flag (Both A and B)

Auto mute flag (Channel B)

Auto mute flag (Channel A)

Clock invalid flag

Mux

GPIOx

Mux

Serial Audio Data Output

Analog mute flag for B

Analog mute flag for A

PLL lock flag

Charge Pump Clock

Under voltage flag 1

Under voltage flag 2

PLL output/4

GPIOx Input State

Monitoring

(P0-R119)

To µCDSP

To Clock Tree

Figure 68. GPIO Port

9.3.9 I²C Communication Port

The TAS5780M device supports the I²C serial bus and the data transmission protocol for standard and fast mode

as a slave device. Because the TAS5780M register map spans several books and pages, the user must select

the correct book and page before writing individual register bits or bytes. Changing from book to book is

accomplished by first changing to page 0x00 by writing 0x00 to register 0x00 and then writing the book number

to register 0x7f of page 0. Changing from page to page is accomplished via register 0x00 on each page. The

register value selects the register page, from 0 to 255.

9.3.9.1 Slave Address

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Table 16. I²C Slave Address

MSB

1

LSB

0

1

ADR2

ADR1

R/ W

The TAS5780M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are

factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be

user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus

at one time, which gives a range of 0x90, 0x92, 0x94 and 0x96, as detailed in Table 17. Each TAS5780M device

responds when it receives the slave address.

Table 17. I²C Address Configuration via ADR0 and ADR1 Pins

ADR1

ADR0

I²C SLAVE ADDRESS [R/W]

0

1

0

1

0

1

0x90

0x92

0x94

0x96

9.3.9.2 Register Address Auto-Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single

operation, and is especially useful for block write and read operations. The TAS5780M device supports auto-

increment mode automatically. Auto-increment stops at page boundaries.

9.3.9.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit,

data if write or acknowledge if read, and stop condition. The TAS5780M device supports only slave receivers and

slave transmitters.

SDA

SCL

9

1–7

8

9

1–8

9

1–8

9

Sp

St

Slave address

R/W

ACK

DATA

ACK

DATA

ACK

Start

condition

Stop

condition

R/W: Read operation if 1; otherwise, write operation

ACK: Acknowledgement of a byte if 0

DATA: 8 bits (byte)

Figure 69. Packet Protocol

Table 18. Write Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

Sp

Table 19. Read Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

9.3.9.4 Write Register

A master can write to any TAS5780M device registers using single or multiple accesses. The master sends a

TAS5780M device slave address with a write bit, a register address, and the data. If auto-increment is enabled,

the address is that of the starting register, followed by the data to be transferred. When the data is received

properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next

value is 0x0. Table 20 shows the write operation.

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Table 20. Write Operation

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

reg

addr

write

data 1

write

data 2

St

slave addr

W

ACK

inc

ACK

Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

9.3.9.5 Read Register

A master can read the TAS5780M device register. The value of the register address is stored in an indirect index

register in advance. The master sends a TAS5780M device slave address with a read bit after storing the

register address. Then the TAS5780M device transfers the data which the index register points to. When auto-

increment is enabled, the index register is incremented by 1 automatically. When the index register reaches

0x7F, the next value is 0x0. Table 21 lists the read operation.

Table 21. Read Operation

Transmitter

Data Type

M

S

M

S

M

S

M

slave

addr

reg

addr

slave

addr

St

W

ACK

inc

ACK

Sr

R

ACK

data

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition;

W = Write; R = Read; NACK = Not acknowledge

9.3.9.6 DSP Book, Page, and Register Update

The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has

several registers.

9.3.9.6.1 Book and Page Change

To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.

On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to

change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book

number to register 0x7f on page 0. To change between pages in a book, simply write the page number to

register 0x00.

9.3.9.6.2 Swap Flag

The swap flag is used to copy the audio coefficient from the host memory to the DSP memory. The swap flag

feature is important to maintain the stability of the BQs. A BQ is a closed-loop system with 5 coefficients. To

avoid instability in the BQ in an update transition between two different filters, update all five parameters within

one audio sample. The internal swap flag insures all 5 coefficients for each filter are transferred from host

memory to DSP memory occurs within an audio sample. The swap flag stays high until the full host buffer is

transferred to DSP memory. Updates to the Host buffer should not be made while the swap flag is high.

All writes to book 0x8C from page 0x1B and register 0x58 through page 0x22 and register 0x1C require the swap

flag. The swap flag is located in book 0x8C, page 0x01, and register 0x10 and must be set to 0x00 00 00 01 for

a swap.

9.3.9.6.3 Example Use

The following is a sample script for using the DSP host memory to change the fine volume on the device on I²C

slave address 0x90 to the default value of 0 dB:

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 21 #Go to page 0x21

w 90 21 48 00 00 00 #Fine volume Left

w 90 21 4C 00 00 00 #Fine volume Right

#Run the swap flag for the DSP to work on the new coefficients

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 01 #Go to page 0x01

w 90 10 00 00 00 01 #Swap flag

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9.4 Device Functional Modes

Because the TAS5780M device is a highly configurable device, numerous modes of operation can exist for the

device. For the sake of succinct documentation, these modes are divided into two modes:

•

Fundamental operating modes

Secondary usage modes

Fundamental operating modes are the primary modes of operation that affect the major operational

characteristics of the device, which are the most basic configurations that are chosen to ensure compatibility with

the intended application or the other components that interact with the device in the final system. Some

examples of the operating modes are the communication protocol used by the control port, the output

configuration of the amplifier, or the Master/Slave clocking configuration.

The fundamental operating modes are described starting in the Serial Audio Port Operating Modes section.

Secondary usage modes are best described as modes of operation that are used after the fundamental operating

modes are chosen to fine tune how the device operates within a given system. These secondary usage modes

can include selecting between left justified and right justified Serial Audio Port data formats, or enabling some

slight gain/attenuation within the DAC path. Secondary usage modes are accomplished through manipulation of

the registers and controls in the I²C control port. Those modes of operation are described in their respective

register/bit descriptions and, to avoid redundancy, are not included in this section.

9.4.1 Serial Audio Port Operating Modes

The serial audio port in the TAS5780M device supports industry-standard audio data formats, including I²S, Time

Division Multiplexing (TDM), Left-Justified (LJ), and Right-Justified (RJ) formats. To select the data format that

will be used with the device, controls are provided on P0-R40. The timing diagrams for the serial audio port are

shown in the Serial Audio Port Timing – Slave Mode section, and the data formats are shown in the Serial Audio

Port – Data Formats and Bit Depths section.

9.4.2 Communication Port Operating Modes

The TAS5780M device is configured via an I²C communication port. The device does not support a hardware

only mode of operation, nor Serial Peripheral Interface (SPI) communication. The I²C Communication Protocol is

detailed in the I²C Communication Port section. The I²C timing requirements are described in the I²C Bus

Timing – Standard and I²C Bus Timing – Fast sections.

9.4.3 Speaker Amplifier Operating Modes

The TAS5780M device can be used in two different amplifier configurations:

•

Stereo Mode

Mono Mode

9.4.3.1 Stereo Mode

The familiar stereo mode of operation uses the TAS5780M device to amplify two independent signals, which

represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented

on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is

presented on the SPK_OUTxx outputs can be changed according to the Audio Process Flow which is used and

the configuration of registers P0-R42-D[5:4] and P0-R42-D[1:0]. The familiar stereo mode of operation is shown

in .

By default, the TAS5780M device is configured to output the Right frame of a I²S input on the Channel A output

and the left frame on the Channel B output.

9.4.3.2 Mono Mode

The mono mode of operation is used to describe operation in which the two outputs of the device are placed in

parallel with one another to increase the power sourcing capabilities of the audio output channel. This is also

known as Parallel Bridge Tied Load (PBTL).

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Device Functional Modes (continued)

On the output side of the TAS5780M device, the summation of the devices can be done before the filter in a

configuration called Pre-Filter PBTL. However, the two outputs may be required to merge together after the

inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less

expensive inductors to be used because the current is divided between the two inductors. This process is called

Post-Filter PBTL. Both variants of mono operation are shown in Figure 70 and Figure 71.

[

CL[Ç

[

{tY_hÜÇ!+

CL[Ç

{tY_hÜÇ!+

/

CL[Ç

/

CL[Ç

{tY_hÜÇ!-

[

CL[Ç

{tY_hÜÇ!-

/

CL[Ç

{tY_hÜÇ.+

/

CL[Ç

[

CL[Ç

{tY_hÜÇ.-

/

CL[Ç

{tY_hÜÇ.+

[

CL[Ç

[

CL[Ç

{tY_hÜÇ.-

/

CL[Ç

Figure 70. Pre-Filter PBTL

Figure 71. Post-Filter PBTL

On the input side of the TAS5780M device, the input signal to the mono amplifier can be selected from the any

slot in a TDM stream or the left or right frame from an I²S, LJ, or RJ signal. The TAS5780M device can also be

configured to amplify some mixture of two signals, as in the case of a subwoofer channel which mixes the left

and right channel together and sends the mixture through a low-pass filter to create a mono, low-frequency

signal.

The mono mode of operation is shown in the Mono (PBTL) Systems section.

9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port

The digital audio serial port in the TAS5780M device can be configured to receive clocks from another device as

a serial audio slave device. The slave mode of operation is described in the Clock Slave Mode with SCLK PLL to

Generate Internal Clocks (3-Wire PCM) section. If no system processor is available to provide the audio clocks,

the TAS5780M device can be placed into Master Mode. In master mode, the TAS5780M device provides the

clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation

within the TAS5780M device, see the Serial Audio Port Operating Modes section.

9.5 Programming

9.5.1 Audio Processing Features

The TAS5780M device includes audio processing to optimize the audio performance of the audio system into

which they are integrated. The TAS5780M device has 12 Biquad Filters for speaker response tuning, One dual

band DPEQ to dynamically adjust the equalization curve that is applied to low-level signal and the curve that is

applied to high level signals. A 2-band advanced DRC + AGL structure limits the output power of the amplifier for

two regions while controlling the peaking that can occur in the crossover region during compression. A fine

volume control is provided to finely adjust the output level of the amplifier based upon the system level

considerations faced by the product development engineer.

The TAS5780M device has two signal monitoring options available, the level meter and the serial data out signal.

The level meter monitors the signal level through an alpha filter and presents the signal in an I²C register. The

level meter signal is taken before the 4x interpolation which occurs before the digital-to-analog conversion.

The SDOUT signal can be presented on any one of the GPIOx pins. Customarily, as is the case in all of the TI

evaluation hardware for the TAS5780M device, GPIO2 is used.

The details of the audio processing flow, including the I²C control port registers associated with each block, are

shown in .

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Programming (continued)

Audio Path

32 Bit Data Path & Coefficients

High level

BQ

Band-Split

High (1BQ)

Input Scale

& Mix

SRC

Main EQ

12 BQs

Adv.

DRC

Gain

Analog

DAC w/

Audio Input

from Serial

Port

1.31

32/48k

to

96kHz

1.31

5.27

Gain

Scale

DPEQ

Control

THD

Boost

Fine

Volume

4x

Int.

Sense

BQ

Out to

Amp

AGL

L&R or

L+R

2

Gain Cntrl

+

Dual bank

Log.

Style

Band-Split

Low (1BQ)

Gain

Low level

BQ

I²C

Register

Level

Meter

Bypass

Mux

Audio Out to

Serial Port

Figure 72. Fixed-Function Process Flow found in the TAS5780M

9.5.2 Processing Block Description

The processing block shown in the above is comprised of the following major blocks:

•

Input scale and mixer

Sample Rate Converter (SRC)

Parametric Equalizers (PEQs)

BQs Gain Scale

Dynamic Parametric Equalizer (DPEQ)

Two-Band Dynamic Ranger Control (DRC)

Automatic Gain Limiter (AGL)

Fine Volume

Level Meter

THD Management

9.5.2.1 Input Scale and Mixer

The input mixer can be used to mix the left and right channel input signals as shown in Figure 73. The input

mixer has four coefficients, which control the mixing and gains of the input signals. When mixing and scaling the

input signals, ensure that at maximum input level the input mixer outputs don't exceed 0 dBFS, which will

overdrive the SRC inputs.

L2L

Gain

Audio left in

Audio left out

+

L2R

Gain

R2L

Gain

R2R

Gain

Audio right in

Audio right out

+

Figure 73. Input Scale and Mixer

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Programming (continued)

9.5.2.1.1 Example

The following is a sample script for setting up the both left and right channels for (½L + ½R) or (L + R) / 2:

w 90 00 00 # Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 21 #Go to page 0x21

w 90 50 00 40 26 E7 #Input mixer left in to left out gain

w 90 54 00 40 26 E7 #Input mixer right in to left out gain

w 90 58 00 40 26 E7 #Input mixer left in to right out gain

w 90 5C 00 40 26 E7 #Input mixer right in to right out gain

#Run the swap flag for the DSP to work on the new coefficients

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 01 #Go to page 0x05

w 90 10 00 00 00 01 #Swap flag

9.5.2.2 Sample Rate Converter

The sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample rates. These

input sample rates are converted to 88.2 or 96 kHz sample rate. The sample rate detection doesn’t distinguish

between sample rates from 32 to 48 kHz. These sample rates are treated as 48 kHz by the sample rate

converter. The detected sample rate can be read at book 0x78 page 0x0C register 0x5C. The input sample rate

is 88.2 or 96 kHz at register 0x5C which reads 0x00 00 00 01. The input sample rate is 32 to 48 kHz at register

0x5C which reads 0x00 00 00 02. Input sample rate 32 kHz requires changing the interpolation setting from 2x to

3x by writing B0-P0-R37-D7 to 1. The device must be placed in standby mode for this change to take effect.

Table 22. Sample Rate Detection

SAMPLING RATE (KHZ)

B0-P0-R91-D[6:4]

8

001

010

011

100

16

32 – 48

88.2 – 96

Even though the sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample

rates, the TAS5780M device supports all input sample rates shown in Table 22 in 1x interpolation mode, base

rate processing.

The SRC input should not be overdriven. Making the maximum signal level into the SRC –0.5dBFs is

recommended to prevent overdriving the SRC and causing audio artifacts. The input scale and mixer can be

used to attenuate or boost the maximum input signal to –0.5dBFs. The processing block has several blocks after

the SRC where the signal can be compensate for any gain attenuation done in the input mixer and scale block to

prevent over driving the SRC.

9.5.2.3 Parametric Equalizers (PEQ)

The device supports 12 individual tuned PEQs for left channel and 12 individual tuned PEQs for the right

channel. The PEQs are implemented using cascaded “direct form 1” BQs structures as shown in Figure 74.

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Inst1_B0

Inst2_B0

X

Inst3_B0

BIQUADIN_D

X

+

2*Inst1_B1

2*Inst1_A1

2*Inst2_B1

X

2*Inst2_A1

2*Inst3_B1

z^-1

X

z^-1

Inst1_B2

Inst1_A2

Inst2_B2

X

Inst2_A2

Inst3_B2

X

Instance 1

Instance 2

Figure 74. Cascaded BQ Structure

Instance 3

b₀+ b Z^-1+ b₂Z^-2

a₀+ a₁Z^-1+ a₂Z^-2

1

H(z) =

(2)

All BQ coefficients are normalized with a0 to insure that a0 is equal to 1. The structure requires 5 BQ coefficients

as shown in Table x. Any BQ with coefficients greater than 1 undergoes gain scaling as described in BQ Gain

Scale.

Table 23. BQ Coefficients Normalization

BQ COEFFICIENT FOR TAS5780M

COEFFICIENT CALCULATION

B0_DSP

B1_DSP

B2_DSP

A1_DSP

A2_DSP

b0 / a0

b1 / (a0 × 2)

b2 / a0

–a1 / (a0 × 2)

–a2 / a0

9.5.2.4 BQ Gain Scale

Main EQ

12 BQs

Gain

Scale

Figure 75. PEQs and BQs Gain Scale Block

The BQ coefficients format is as follows: The first BQ has B0 = 5.x, B1 = 6.x, B2 = 5.x, A1 = 2.x, and A2 = 1.x.

The rest of the BQ have this format: B0 = 1.x, B1 = 2.x, B2 = 1.x, A1 = 2.x, and A2 = 1.x. This formatting

maintains the highest possible resolution and noise performance. The 1.31 format restricts the ability to do high

gains within the BQs and as a result requires gain compensation for the restriction. When generating BQ

coefficients, ensure none of the BQ coefficients is greater than 1 by implementing gain compensation. The Gain

compensation reduces the BQ coefficients gain to ensure all BQ coefficients are less than 1. The reduced gain is

then reapplied in the subsequent gain scale block.

Gain compensation takes the maximum value of B0_DSP, B1_DSP, and B2_DSP after the BQ normalization

shown in Table 23 is implemented. All the B coefficients are divided by maximum B coefficient value then

multiplied by 0.999999999534339 (the nearest two’s complement 32-bit number to 1). The following calculations

are done for each BQ in the PEQ block:

Max _ k = max(B0 _ DSP, B1_ DSP, B2 _ DSP)

(3)

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k _ BQX = Max _ k

B0 _ DSP

(4)

(5)

(6)

(7)

B0 _ DSP =

B1_ DSP =

B2 _ DSP =

k _ BQX

B1_ DSP

k _ BQX

B2 _ DSP

k _ BQX

The calculations above insure all DSP BQ coefficients are in a 1.31 format. The reduced gains in the BQ 1.31

format is compensation for in the gain scale block. The following calculation is done for each channel.

k_BQ = k_BQ1 × k_BQ2 × k_BQ3 × k_BQ4 × k_BQ5 × k_BQ6 × k_BQ7 × k_BQ8 × k_BQ9 × k_BQ10 × k_BQ11 ×

k_BQ12

(8)

The calculated k_BQ compensation value is then applied to the BQ gain scale in an 8.24 format. The BQ gain

scale can also be used for volume control before the DRCs. The block can be considered as BQ gain scale and

volume gain block. When the BQ gain scale block is used for volume control the coefficient value must be

calculated as follows:

Volume

20

Gain _ BQ _V =10

´k _ BQ

where

•

Volume is in dB

(9)

The BQ gain scale coefficients are located in book 0x8C, page 0x1F register 0x58 for left and register 0x5C for

right.

The Bypass EQ Mux allows the user to bypass all processing. The Bypass EQ mux is at Page 0x21, Register

0x64. The Gang Left / Right mux forces the left processing to be the same as the right processing. The Gang

Left / Right Mux is located at Page 0x21, Register 0x68.

9.5.2.5 Dynamic Parametric Equalizer (DPEQ)

The dynamic parametric equalizer mixes the audio signals routed through two paths containing one BQ each

based upon the signal level detected by the sense path, as shown in Figure 76. The sense path contains one

BQ, which can be used to focus the DPEQ sensing on a specific frequency bandwidth. An alpha filter structure is

used to sense the energy in the sense path and setting the dynamic mixing ratios.

High level

BQ

DPEQ

Sense

Control

+

BQ

Low level

BQ

Figure 76. DPEQ Signal Path

The dynamic mixing is controlled by offset, gain, and alpha coefficients in a 1.31 format. The alpha coefficient

controls the average time constant in ms of the signal data in the sense path. The offset and gain coefficients

control the dynamic mixing thresholds shown in Figure 77.

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GAIN

Low Path Mix

1

0

High Path Mix

T1

T2

FS

SENSE LEVEL

Figure 77. Dynamic Mixing

The offset, gain and alpha coefficients are calculated as follows:

T1

T1_ Linear =10²⁰

(10)

(11)

T 2-6

20

T2 _ Linear =10

where

•

T2 ≥ –20 dB

T 2

T2 _ Linear =10²⁰

where

•

T2 < –20 dB

(12)

(13)

Offset = -T1_ Linear

1

Gain =

32(T2 _ Linear -T1_ Linear)

-1000

(14)

Alpha =1- e^{time constant´Fs}

where

•

T1 and T2 are in dB

The time constant is in ms

(15)

The DPEQ control coefficients are located in book 0x8C, page0x20. Register 0x58 is alpha coefficient, register

0x5C is gain coefficient and register 0x60 is offset coefficient.

The high level path BQ, low level path BQ, and sense path BQ coefficients use a 1.31 format as shown in

Table 25. The DPEQ BQs don't have a gain scale to compensate for any BQ gain reduction due to the

requirements of the 1.31 format. During tuning, the reduced gain can be compensated by using the BQ gain

scale or the DRC offset coefficient.

The DPEQ sense gain scale is located in the sensing path. The DPEQ sense gain scale can be used to shift the

dynamic mixing thresholds by changing the signal level in the sensing path. A positive dB gain shifts the dynamic

mixing thresholds down by the gain amount and a negative dB gain shifts the dynamic mixing thresholds up by

the gain amount.

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9.5.2.6 Two-Band Dynamic Range Control

The Dynamic Range Control (DRC) is a feed-forward mechanism that can be used to automatically control the

audio signal amplitude or the dynamic range within specified limits. The dynamic range control is done by

sensing the audio signal level using an estimate of the alpha filter energy then adjusting the gain based on the

region and slope parameters that are defined. The Dynamic Range Control is shown in Figure 78.

Adv.

DRC

Mixer

gain

Band-Split

High (1BQ)

+

Log.

Style

Band-Split

Low (1BQ)

Mixer

gain

Figure 78. Dynamic Range Control

The DRCs have seven programmable transfer function parameters each: k0, k1, k2, T1, T2, OFF1, and OFF2.

The T1 and T2 parameters specify thresholds or boundaries of the three compression or expansion regions in

terms of input level. The Parameters k0, k1, and k2 define the gains or slopes of curves for each of the three

regions. The parameters OFF1 and OFF2 specify the offset shift relative 1:1 transfer function curve at the

thresholds T1 and T2 respectively shown in Figure 79.

0

OFF2

-25

K2

K1

OFF1

-50

K0

-75

-100

T1

T2

-125

-100

-75

-50

-25

0

Input (dB)

Figure 79. DRC Transfer Function Example Plot

The two-band dynamic range control is comprised of two DRCs that can be spilt into two bands using the BQ at

the input of each band. The frequency where the two bands are spilt is referred to as the crossover frequency.

The crossover frequency is the cut off frequency for the low pass filter used to create the low band and the cut

off frequency for the high pass filter used to create the high band.

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Attack

time

Decay

time

Gain

t1

t2

Time

Figure 80. DRC Attack and Decay

The DRC in each band is equipped with individual energy, attack, and decay time constants. The DRC time

constants control the transition time of changes and decisions in the DRC gain during compression or expansion.

The energy, attack, and decay time constants affect the sensitivity level of the DRC. The shorter the time

constant, the more aggressive the DRC response and vice versa.

9.5.2.7 Automatic Gain Limiter

The Automatic Gain Limiter (AGL) is a feedback mechanism that can be used to automatically control the audio

signal amplitude or dynamic range within specified limits. The automatic gain limiting is done by sensing the

audio signal level using an alpha filter energy structure shown in Figure 82 at the output of the AGL then

adjusting the gain based on the whether the signal level is above or below the defined threshold. Three decisions

made by the AGL are engage, disengage, or do nothing. The rate at which the AGL engages or disengages

depends on the attack and release settings, respectively.

1:1 Transfer Function

Implemented Transfer Function

T

Input Level (dB)

M0091-04

Figure 81. AGL Transfer Function Example Plot

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Alpha Filter Structure

S

α

–1

ω

Z

Figure 82. AGL Alpha Filter Structure

9.5.2.7.1 Softening Filter Alpha (AEA)

•

AEA = 1 – e^{–1000 / (fs × User_AE)}

e ≈ 2.718281828

Fs = sampling frequency

User_AE = user input step size

9.5.2.7.2 Softening Filter Omega (AEO)

•

AEO = 1 – AEA

9.5.2.7.3 Attack Rate

•

Attack rate = 2 (AA + Release rate)

AA = 1000 × User_Ad / Fs

User_Ad = user input attack step size

9.5.2.7.4 Release Rate

•

Release rate = 1000 × User_Rd / Fs

User_Rd = user input release step size

NOTE

The release duration (User_Rd) should be longer than the attack duration (User_Ad).

9.5.2.7.5 Attack Threshold

•

Attack Threshold = user input level in dB

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Threshold

INPUT

Threshold

OUTPUT

Attack Rate

Release Rate

W0003-01

Figure 83. AGL Attack and Release

The Attack Threshold AGL coefficients are shown in .

9.5.2.8 Fine Volume

The fine volume block after the AGL can be used to provide additional fine volume steps from –192 dB to 6 dB in

a 2.30 format. The Fine Coefficients are shown in .

9.5.2.9 THD Boost

A boost scalar and fine volume together can be used for clipping. The THD boost block allows the user to

programmatically increase the THD by clipping at an operating point earlier than that defined by the supply rails.

9.5.2.10 Level Meter

The level meter uses an energy estimator with a programmable time constant to adjust the sensitivity level based

on signal frequency and desired accuracy level. The level meter outputs of both left and right channels are

written to a 32-bit sub address location in a 1.31 format as shown in . The BypassToLevelMeter Bit in Book 8C,

Page 0x21, Register 0x70 can be used to switch the input to the Level Meter from the audio before processing to

audio post-processing.

9.5.3 Other Processing Block Features

9.5.3.1 Number Format

The data processing path is 32 bits with 32-bit coefficients. The coefficients use the two’s complement digital

number format.

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Table 24. Two’s Complement Format

BITS

TWO'S COMPLEMENT VALUE

0111 1111

0111 1110

0000 0010

0000 0001

0000 0000

1111 1111

1111 1110

1000 0010

1000 0001

1000 0000

127

126

2

1

0

–1

–2

–126

–127

–128

9.5.3.1.1 Coefficient Format Conversion

The device uses 32 bit two’s complement number formats. The calculated 4 byte register values are shown

below in an 8 digit hex value.

Table 25. Sample Calculations for 1.31 Format

dB

0

Linear

1

Decimal

Hex (1.31 Format)

7FFFFFFF

2147483648

1073741824

214748364

–6

–20

0.5

40000000

0.1

0CCCCCCC

D = 2³¹× L, D < 2³¹

x

L = 10^(x/20)

Dec2Hex(D, 8)⁽¹⁾

D = 2³¹, D ≥ 2³¹

(1) Dec2Hex(D, 8), where 8 represents 8 nibbles or 38 bits.

Please note that for a 1.31 format the linear value cannot be greater than 1 or decimal value 232.

Table 26. Sample Calculations for B.A Format

dB

Linear

Decimal

Hex (1.31 Format)

D = 2^A× L, D < 2^{(B + A - 1)}

x

L = 10^(x/20)

Dec2Hex(D, 8)

D = 2^{(B + A - 1)}, D ≥ 2^{(B + A - 1)}

9.5.4 Checksum

The TAS5780M device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum

and an Exclusive (XOR) checksum. Both checksums work on every register write, except for book switch register

and page switching register, 0x7F and 0x00, respectively. Register reads do not change checksum, but writes to

even nonexistent registers will change the checksum. Both checksums are 8-bit checksums and both are

available together simultaneously. The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00)

to their respective 4-byte register locations.

9.5.4.1 Cyclic Redundancy Check (CRC) Checksum

The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell

delineation, (1 + x¹+ x²+ x⁸). A major advantage of the CRC checksum is that it is input order sensitive.

The CRC supports all I²C transactions, excluding book and page switching. The CRC checksum is read from

register 0x7E on any page of book 0x00 (B0_Page x_Reg 126). If the book isn’t Book 0, the CRC checksum is

only valid on page 0x00 register 0x7E (Page 0_Reg 126). The CRC checksum can be reset by writing 0x00 00

00 00 to the same register locations where the CRC checksum is valid.

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9.5.4.2 Exclusive or (XOR) Checksum

The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with

the previous 8-bit checksum register value. XOR supports only YMEM, which is located in Book 0x8C and

excludes page switching and all registers in Page 0x00 of Book 0x8C. XOR checksum is read from location

register 0x7D on page 0x00 of book 0x8C (B140_Page 0_Reg 125). The XOR Checksum can be reset by writing

0x00 00 00 00 to the same register location where it is read.

Table 27. XOR Truth Table

INPUT

OUTPUT

A

0

1

B

0

1

0

1

0

1

0

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section details the information required to configure the device for several popular configurations and

provides guidance on integrating the TAS5780M device into the larger system.

10.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the

supporting required components in each of the System Application Schematics.

Where possible, the supporting component requirements have been consolidated to minimize the number of

unique components which are used in the design. Component list consolidation is a method to reduce the

number of unique part numbers in a design, to ease inventory management, and to reduce the manufacturing

steps during board assembly. For this reason, some capacitors are specified at a higher voltage than what would

normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply

net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of

that value into a single component type. Similarly, several unique resistors that have all the same size and value

but different power ratings can be consolidated by using the highest rated power resistor for each instance of that

resistor value.

While this consolidation can seem excessive, the benefits of having fewer components in the design can far

outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere

in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the

capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of

the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.

10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components

shown in the component list was intentionally chosen to allow for proper board layout, component placement,

and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane

extensions from the TAS5780M device and into to the surrounding copper for increased heat-sinking of the

device. While components may be offered in smaller or larger package sizes, it is highly recommended that the

package size remain identical to the size used in the application circuit as shown. This consistency ensures that

the layout and routing can be matched very closely, which optimizes thermal, electromagnetic, and audio

performance of the TAS5780M device in circuit in the final system.

10.1.3 Amplifier Output Filtering

The TAS5780M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the

PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive

element L and a capacitive element C to make up the 2-pole filter.

The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current

waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several

system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a

simple ferrite bead or a ferrite bead plus a capacitor can replace the traditional large inductor and capacitor that

are commonly used. In other high-power applications, large toroid inductors are required for maximum power and

film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design

(SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon

the desired load and response.

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Application Information (接下页)

10.1.4 Programming the TAS5780M

The TAS5780M device includes an I²C compatible control port to configure the internal registers of the

TAS5780M device. The control console software provided by TI is required to configure the device. More details

regarding programming steps, and a few important notes are available below and also in the design examples

that follow.

10.1.4.1 Resetting the TAS5780M Registers and Modules

The TAS5780M device has several methods by which the device can reset the register, interpolation filters, and

DAC modules. The registers offer the flexibility to do these in or out of shutdown as well as in or out of standby.

However, there can be issues if the reset bits are toggled in certain illegal operation modes.

Any of the following routines can be used with no issue:

•

Reset Routine 1

–

Place device in Standby

Reset modules

Reset Routine 2

–

Place device in Standby + Power Down

Reset registers

Reset Routine 3

–

Place device in Power Down

Reset registers

Reset Routine 4

–

Place device in Standby

Reset registers

Reset Routine 5

–

Place device in Standby + Power Down

Reset modules + Reset registers

Reset Routine 6

–

Place device in Power Down

Reset modules + Reset registers

Reset Routine 7

–

Place device in Standby

Reset modules + Reset registers

Two reset routines are not supported and should be avoided. If used, they can cause the device to become

unresponsive. These unsupported routines are shown below.

•

Unsupported Reset Routine 1 (do not use)

–

Place device in Standby + Power Down

Reset modules

•

Unsupported Reset Routine 2 (do not use)

–

Place device in Power Down

Reset modules

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10.2 Typical Applications

10.2.1 2.0 (Stereo BTL) System

For the stereo (BTL) PCB layout, see 图 89.

A 2.0 system refers to a system in which there are two full range speakers without a separate amplifier path for

the speakers which reproduce the low-frequency content. In this system, two channels are presented to the

amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers. In

some cases, the amplified signal is further separated based upon frequency by a passive crossover network after

the L-C filter. Even so, the application is considered 2.0.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the

audio for the left channel and the other channel containing the audio for the right channel. While certainly the two

channels can contain any two audio channels, such as two surround channels of a multi-channel speaker

system, the most popular occurrence in two channels systems is a stereo pair.

图 84 shows the 2.0 (Stereo BTL) system application.

PVDD

R100

750k

R101

150k

C103

1µF

C100

0.1µF

C101

22µF

C102

22µF

GND

C104

To System Processor

3.3V

0.22µF

L100

L101

2.0-SDA

2.0-SCL

2.0-SPK_OUTA+

2.0-GPIO0

2.0_RESET

2.0-SDOUT

2.0-MCLK

2.0-SCLK

2.0-SDIN

2.0-OUTA+

2.0-OUTA-

C105

1µF

C106

2.2µF

C107

2.2µF

3.3V

2.0-SPK_OUTA-

C108

C109

0.1µF

C110

0.1µF

0.22µF

GND

U100

TAS5780M

GND

PAD

GND

C111

2.0-LRCK/FS

0.22µF

L102

L103

GND

2.0-SPK_OUTB-

2.0-OUTB-

2.0-OUTB+

C112

1µF

C113

2.2µF

C114

2.2µF

3.3V

2.0-SPK_OUTB+

C115

C116

0.1µF

C117

0.1µF

C118

1µF

C119

1µF

C120

1µF

GND

PVDD

0.22µF

GND

2.0-SPK_MUTE

2.0-SPK_FAULT

GND

C121

0.1µF

C122

22µF

C123

22µF

GND

图 84. 2.0 (Stereo BTL) System Application Schematic

10.2.1.1 Design Requirements

•

Power supplies:

–

3.3-V supply

5-V to 24-V supply

Communication: host processor serving as I²C compliant master

External memory (such as EEPROM and flash) used for coefficients

•

The requirements for the supporting components for the TAS5780M device in a Stereo 2.0 (BTL) system is

provided in 表 28.

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表 28. Supporting Component Requirements for Stereo 2.0 (BTL) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

U100

TAS5780M

48 Pin TSSOP

0402

Digital-input, closed-loop class-D amplifier

1%, 0.063 W

R100

See the Adjustable

Amplifier Gain and

Switching Frequency

Selection section

R101

0402

1%, 0.063 W

L100, L101, L102,

L103

See the Amplifier Output Filtering section

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C100, C121

0.1 µF

0.22 µF

0.68 µF

0402

0603

C104, C108, C111,

C115

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C109, C110, C116,

C117

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

0805

0603

(this body size

chosen to aid in trace Voltage rating must be > 16 V

routing)

Ceramic, 1 µF, ±10%, X7R

C103

1 µF

C105, C118, C119,

C120

0402

Ceramic, 1 µF, 6.3V, ±10%, X5R

Ceramic, 2.2 µF, ±10%, X5R

At a minimum, voltage rating must be > 10V, however higher

voltage caps have been shown to have better stability under DC

bias. Refer to the guidance provided in the TAS5780M for

suggested values.

C106, C107, C113,

C114

2.2 µF

22 µF

0402

0805

C101, C102, C122,

C123

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout, and routing given in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the

high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they

are given precedent as design trade-offs are made is recommended.

–

For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is

necessary, go to the E2E forum to request a layout review.

10.2.1.2.2 Step Two: System Level Tuning

•

Use the TAS5780MEVM evaluation module and the PPC3 app to configure the desired device settings.

Tune the end equipment by following the instructions in SLAU694

10.2.1.2.3 Step Three: Software Integration

•

Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

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10.2.1.3 Application Curves

表 29 shows the application specific performance plots for Stereo 2.0 (BTL) systems.

表 29. Relevant Performance Plots

PLOT TITLE

Output Power vs PVDD

FIGURE NUMBER

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 39

Figure 40

Figure 41

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

Efficiency vs Output Power

DVDD PSRR vs. Frequency

AVDD PSRR vs. Frequency

C_PVDDPSRR vs. Frequency

10.2.2 Mono (PBTL) Systems

For the mono (PBTL) PCB layout, see 图 91.

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge

Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the

loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5780M

device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the

amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while

the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an

audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed

together and sent through a low-pass filter to create a single audio signal which contains the low frequency

information of the two channels. Conversely, advanced digital signal processing can create a low-frequency

signal for a multichannel system, with audio processing which is specifically targeted on low-frequency effects.

Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency

signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate

channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL

configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo

BTL + External Mono Amplifier) Systems section. shows the Mono (PBTL) system application

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PVDD

R200

750k

R201

150k

C204

390µF

C200

1µF

C201

0.1µF

C202

1µF

C203

22µF

GND

To System Processor

3.3V

MONO-SDA

MONO-SCL

C208

MONO-GPIO0

MONO_RESET

MONO-SDOUT

MONO-MCLK

MONO-SCLK

MONO-SDIN

0.22µF

L200

C205

1µF

C206

2.2µF

C207

2.2µF

MONO-SPK_OUTA

C209

MONO_OUT+

C220

0.1µF

0.22µF

GND

U200

TAS5780M

GND

PAD

GND

C214

MONO-LRCK/FS

0.22µF

L201

GND

MONO-SPK_OUTB

C215

MONO_OUT-

C210

1µF

R202

49.9k

C221

0.1µF

3.3V

0.22µF PVDD

C211

1µF

C212

1µF

C213

1µF

GND

C219

390µF

C216

0.1µF

C217

1µF

C218

22µF

MONO-SPK_MUTE

MONO-SPK_FAULT

GND

图 85. Mono (PBTL) System Application Schematic

10.2.2.1 Design Requirements

•

Power supplies:

–

3.3-V supply

5-V to 24-V supply

Communication: Host processor serving as I²C compliant master

External memory (EEPROM, flash, and others) used for coefficients.

•

The requirements for the supporting components for the TAS5780M device in a Mono (PBTL) system is provided

in 表 30.

表 30. Supporting Component Requirements for Mono (PBTL) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

U200

TAS5780M

48 Pin TSSOP

0402

Digital-input, closed-loop class-D amplifier with 96kHz processing

R200

See the Adjustable

Amplifier Gain and

Switching Frequency

Selection section

1%, 0.063 W

R201

0402

R202

0402

L200, L201

See theAmplifier Output Filtering section

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C216, C201

0.1 µF

0.22 µF

0.68 µF

0402

0603

0805

C208, C209, C214,

C215

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

C220, C221

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表 30. Supporting Component Requirements for Mono (PBTL) Systems (接下页)

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

0603

(this body size

chosen to aid in trace Voltage rating must be > 16 V

routing)

Ceramic, 1 µF, ±10%, X7R

C200

1 µF

C205, C211, C213,

C212

1 µF

0402

Ceramic, 1 µF, 6.3 V, ±10%, X5R

0805

C202, C217, C352,

C367

(this body size

Ceramic, 1 µF, ±10%, X5R

1 µF

chosen to aid in trace Voltage rating must be > 1.45 × V_PVDD

routing)

Ceramic, 2.2 µF, ±10%, X5R

At a minimum, voltage rating must be > 10V, however higher

C206, C207

C203, C218

2.2 µF

0402

voltage caps have been shown to have better stability under DC

bias please follow the guidance provided in the TAS5780M for

suggested values.

22 µF

0805

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

390 µF

10 × 10

Aluminum, 390 µF, ±20%, 0.08-Ω

Voltage rating must be > 1.45 × V_PVDDAnticipating that this

application circuit would be followed for higher power subwoofer

applications, these capacitors are added to provide local current

sources for low-frequency content. These capacitors can be

reduced or even removed based upon final system testing, including

critical listening tests when evaluating low-frequency designs.

C204, C219

10.2.2.2 Detailed Design Procedure

10.2.2.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout, and routing given in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the

high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they

are given precedent as design trade-offs are made is recommended.

–

For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is

necessary, go to the E2E forum to request a layout review.

10.2.2.2.2 Step Two: System Level Tuning

•

Use the TAS5780MEVM evaluation module and the PPC3 app to configure the desired device settings.

10.2.2.2.3 Step Three: Software Integration

•

Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

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10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems

表 31 shows the application specific performance plots for Mono (PBTL) Systems

表 31. Relevant Performance Plots

PLOT TITLE

Output Power vs PVDD

FIGURE NUMBER

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

Efficiency vs Output Power

10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems

图 93 shows the PCB Layout for the 2.1 System.

To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the

system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the

subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other

channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is

referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a

popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.

10.2.3.1 Advanced 2.1 System (Two TAS5780M devices)

In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was

done in the high-frequency channels. To accomplish this, two TAS5780M devices are used — one for the high

frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can

be sent from the TAS5780M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept

the same digital input as the stereo, which might come from a central systems processor. 图 86 shows the 2.1

(Stereo BTL + External Mono Amplifier) system application.

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PVDD

R300

750k

R301

150k

C303

1µF

C300

0.1µF

C301

22µF

C302

22µF

GND

C304

To System Processor

3.3V

0.22µF

L300

L301

2.1-SDA

2.1-SCL

2.1-SPK_OUT1A+

2.1-GPIO0_HF

2.1_RESET

2.1-HF_OUTA+

2.1-HF_OUTA-

C305

1µF

C306

2.2µF

C307

2.2µF

2.1-MCLK

2.1-SCLK

2.1-SDIN

3.3V

2.1-SPK_OUT1A-

C308

C309

0.1µF

C310

0.1µF

0.22µF

GND

U300

TAS5780M

GND

PAD

GND

C311

2.1-LRCK/FS

0.22µF

L302

GND

2.1-SPK_OUT1B-

2.1-HF_OUTB-

2.1-HF_OUTB+

L303

C312

1µF

C313

2.2µF

C314

2.2µF

3.3V

2.1-SPK_OUT1B+

C315

C316

0.1µF

C317

0.1µF

C318

1µF

C319

1µF

C320

1µF

GND

PVDD

0.22µF

GND

2.1-SPK_MUTE

2.1-SPK_FAULT

GND

C321

0.1µF

C322

22µF

C323

22µF

GND

PVDD

R350

750k

R351

150k

C354

390µF

C350

1µF

C351

0.1µF

C352

1µF

C353

22µF

GND

3.3V

C358

2.1-GPIO0_LF

2.1_RESET

2.1-SDOUT_LF

0.22µF

L350

C355

1µF

C356

2.2µF

C357

2.2µF

2.1-SPK_OUT2A

C359

2.1_LF+

C370

0.1µF

0.22µF

GND

U301

TAS5780M

GND

PAD

GND

C364

0.22µF

2.1-SPK_OUT2B

C365

L351

GND

2.1_LF-

C360

1µF

R352

49.9k

C371

0.1µF

3.3V

0.22µF PVDD

C361

1µF

C362

1µF

C363

1µF

GND

C369

390µF

C366

0.1µF

C367

1µF

C368

22µF

GND

图 86. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic

10.2.3.2 Design Requirements

•

Power supplies:

–

3.3-V supply

5-V to 24-V supply

Communication: Host processor serving as I²C compliant master

External memory (EEPROM, flash, and others) used for coefficients.

•

The requirements for the supporting components for the TAS5780M device in a 2.1 (Stereo BTL + External Mono

Amplifier) system is provided in 表 32.

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表 32. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

U300

TAS5780M

48 Pin TSSOP

0402

Digital-input, closed-loop class-D amplifier 96kHz Processing

R300, R350

R301, R351

R352

See the Adjustable

Amplifier Gain and

Switching Frequency

Selection section

1%, 0.063 W

0402

L300, L301, L302,

L303

See the Amplifier Output Filtering section

L350, L351

C394, C395, C396,

C397, C398, C399

0.01 µF

0.1 µF

0603

0402

Ceramic, 0.01 µF, 50 V, +/-10%, X7R

C300, C321, C351,

C366

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C304, C308, C311,

C315, C358, C359,

C364, C365

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

0.22 µF

0603

C309, C310, C316,

C317, C370, C371

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

0.68 µF

1 µF

0805

0603

C303, C350, C312,

C360

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C305, C318, C319,

C320, C355, C361,

C363, C312, C362

1 µF

0402

Ceramic, 1 µF, 6.3V, ±10%, X5R

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C352, C367

1 µF

2.2 µF

22 µF

390 µF

0805

0402

0805

C306, C307, C313,

C314, C356, C357,

Ceramic, 2.2 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

C301, C302, C322,

C323, C353, C368

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

Aluminum, 390 µF, ±20%, 0.08 Ω

Voltage rating must be > 1.45 × V_PVDD

C354, C369

10 × 10

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10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

表 33 shows the application specific performance plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

表 33. Relevant Performance Plots

DEVICE

PLOT TITLE

FIGURE NUMBER

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 38

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Figure 39

Figure 40

Figure 41

Figure 43

Output Power vs PVDD

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

U300

Efficiency vs Output Power

PVDD PSRR vs Frequency

Output Power vs PVDD

THD+N vs Frequency, V_PVDD= 12 V

THD+N vs Frequency, V_PVDD= 15 V

THD+N vs Frequency, V_PVDD= 18 V

THD+N vs Frequency, V_PVDD= 24 V

THD+N vs Power, V_PVDD= 12 V

THD+N vs Power, V_PVDD= 15 V

THD+N vs Power, V_PVDD= 18 V

THD+N vs Power, V_PVDD= 24 V

Idle Channel Noise vs PVDD

U301

Efficiency vs Output Power

DVDD PSRR vs. Frequency

U300

and

U301

AVDD PSRR vs. Frequency

C_PVDDPSRR vs. Frequency

Powerdown Current Draw vs. PVDD

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11 Power Supply Recommendations

11.1 Power Supplies

The TAS5780M device requires two power supplies for proper operation. A high-voltage supply called PVDD is

required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-

voltage power supply which is called DVDD is required to power the various low-power portions of the device.

The allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating

Conditions table. The two power supplies do not have a required powerup sequence. The power supplies can be

powered on in any order. TI recommends waiting 100 ms to 240 ms for the DVDD power supplies to stabilize

before starting I²C communication and providing stable I²S clock before enabling the device outputs.

AVDD

Internal Analog Circuitry

Internal Mixed

Signal Circuitry

Internal Digital

Circuitry

+

DVDD

DVDD_REG

External Filtering/Decoupling

œ

LDO

CPVDD

CPVSS

External Filtering/Decoupling

Charge

Pump

DAC Output Stage

(Positive)

DAC Output Stage

(Negative)

Output Stage

Power Supply

Gate Drive

Voltage

PVDD

GVDD_REG

External Filtering/Decoupling

Linear

Regulator

+

PVDD

œ

图 87. Power Supply Functional Block Diagram

11.1.1 DVDD Supply

The DVDD supply that is required from the system is used to power several portions of the device. As shown in

图 87, it provides power to the DVDD pin, the CPVDD pin, and the AVDD pin. Proper connection, routing, and

decoupling techniques are highlighted in the Application and Implementation section and the Layout Example

section) and must be followed as closely as possible for proper operation and performance. Deviation from the

guidance offered in the TAS5780M device Application and Implementation section can result in reduced

performance, errant functionality, or even damage to the TAS5780M device.

Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.

To simplify the power supply requirements for the system, the TAS5780M device includes an integrated low-

dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD

supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass

capacitor. It is important to note that the linear regulator integrated in the device has only been designed to

support the current requirements of the internal circuitry, and should not be used to power any additional external

circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and

operation of the device.

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Power Supplies (接下页)

The outputs of the high-performance DACs used in the TAS5780M device are ground centered, requiring both a

positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output

stage is taken from the AVDD pin, which is connected to the DVDD supply provided by the system. A charge

pump is integrated in the TAS5780M device to generate the negative low-voltage supply. The power supply input

for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of a filter capacitor

on the negative low-voltage supply. As is the case with the other supplies, the component selection, placement,

and routing of the external components for these low voltage supplies are shown in the TAS5780M and should

be followed as closely as possible to ensure proper operation of the device.

11.1.2 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which

provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the TAS5780MEVM and must be followed as closely as possible for proper operation and

performance. Due to the high-voltage switching of the output stage, it is particularly important to properly

decouple the output power stages in the manner described in the TAS5780M deviceApplication and

Implementation . Lack of proper decoupling, like that shown in the Application and Implementation , results in

voltage spikes which can damage the device.

A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker

amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG

pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to

note that the linear regulator integrated in the device has only been designed to support the current requirements

of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on

this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.

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12 Layout

12.1 Layout Guidelines

12.1.1 General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and

the layout of the supporting components used around them. The system level performance metrics, including

thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all

affected by the device and supporting component layout.

Ideally, the guidance provided in the applications section with regard to device and component selection can be

followed by precise adherence to the layout guidance shown in Layout Example. These examples represent

exemplary baseline balance of the engineering trade-offs involved with laying out the device. These designs can

be modified slightly as needed to meet the needs of a given application. In some applications, for instance,

solution size can be compromised to improve thermal performance through the use of additional contiguous

copper near the device. Conversely, EMI performance can be prioritized over thermal performance by routing on

internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is

recommended to start from the guidance shown in the Layout Example section and work with TI field application

engineers or through the E2E community to modify it based upon the application specific goals.

12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This

applies to DVDD, AVDD, CPVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5780M

device deserve special attention.

The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as

possible. Not only does placing these devices far away from the pins increase the electromagnetic interference in

the system, but doing so can also negatively affect the reliability of the device. Placement of these components

too far from the TAS5780M device can cause ringing on the output pins that can cause the voltage on the output

pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the

device. For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD

pins than what is shown in the example layouts in the Layout Example section

12.1.3 Optimizing Thermal Performance

Follow the layout examples shown in the Layout Example section of this document to achieve the best balance

of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance

can be required due to design constraints which cannot be avoided. In these instances, the system designer

should ensure that the heat can get out of the device and into the ambient air surrounding the device.

Fortunately, the heat created in the device naturally travels away from the device and into the lower temperature

structures around the device.

12.1.3.1 Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.

These tips should be followed to achieve that goal:

•

Avoid placing other heat producing components or structures near the amplifier (including above or below in

the end equipment).

•

If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5780M device

and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top

and bottom layer.

•

Place the TAS5780M device away from the edge of the PCB when possible to ensure that heat can travel

away from the device on all four sides.

Avoid cutting off the flow of heat from the TAS5780M device to the surrounding areas with traces or via

strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular

to the device.

•

Unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads, orient it so that the narrow end of the passive component is facing the TAS5780M

device.

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Layout Guidelines (接下页)

•

Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane

from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

12.1.3.2 Stencil Pattern

The recommended drawings for the TAS5780M device PCB foot print and associated stencil pattern are shown

at the end of this document in the package addendum. Additionally, baseline recommendations for the via

arrangement under and around the device are given as a starting point for the PCB design. This guidance is

provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all

other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this

guidance may be too conservative and advanced PCB design techniques may be used to improve thermal

performance of the system.

注

The customer must verify that deviation from the guidance shown in the package

addendum, including the deviation explained in this section, meets the customer’s quality,

reliability, and manufacturability goals.

12.1.3.2.1 PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the

shape and position of the copper patterns to which the TAS5780M device will be soldered. This footprint can be

followed directly from the guidance in the package addendum at the end of this data sheet. It is important to

make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5780M

device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5780M

device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the

device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)

present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away

from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the

Layout Example section, this interface can benefit from improved thermal performance.

注

Vias can obstruct heat flow if they are not constructed properly.

More notes on the construction and placement of vias as as follows:

•

Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.

Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the

additional cost of filled vias.

•

The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding

planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,

minimum spacing should be determined by the voltages present on the planes surrounding the via and

minimized wherever possible.

•

Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding

area. This arrangement is shown in the Layout Example section.

Ensure that vias do not cut off power current flow from the power supply through the planes on internal

layers. If needed, remove some vias that are farthest from the TAS5780M device to open up the current path

to and from the device.

12.1.3.2.1.1 Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste

on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity

and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most

cases, the aperture for each of the component pads is almost the same size as the pad itself.

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Layout Guidelines (接下页)

However, the thermal pad on the PCB is large and depositing a large, single deposition of solder paste would

lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder

paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This

structure is called an aperture array, and is shown in the Layout Example section. It is important that the total

area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the

area of the thermal pad itself.

12.2 Layout Example

12.2.1 2.0 (Stereo BTL) System

图 88. 2.0 (Stereo BTL) 3-D View

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Layout Example (接下页)

图 89. 2.0 (Stereo BTL) Top Copper View

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Layout Example (接下页)

12.2.2 Mono (PBTL) System

图 90. Mono (PBTL) 3-D View

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Layout Example (接下页)

图 91. Mono (PBTL) Top Copper View

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Layout Example (接下页)

12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems

图 92. 2.1 (Stereo BTL + Mono PBTL) 3-D View

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Layout Example (接下页)

图 93. 2.1 (Stereo BTL + Mono PBTL) Top Copper View

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13 Register Maps

13.1 Registers - Page 0

13.1.1 Register 1 (0x01)

Figure 94. Register 1 (0x01)

7

6

5

4

3

2

1

0

Reserved

R/W

RSTM

R/W

Reserved

R/W

RSTR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Register 1 (0x01) Field Descriptions

Bit

7-5

4

Field

Type

Reset

Description

Reserved

RSTM

Reserved

R/W

0

Reset Modules – This bit resets the interpolation filter and the DAC modules. Since the

DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit

is auto cleared and can be set only in standby mode.

0: Normal

1: Reset modules

3-1

0

Reserved

RSTR

Reserved

R/W

0

Reset Registers – This bit resets the mode registers back to their initial values. The

RAM content is not cleared, but the execution source will be back to ROM. This bit is

auto cleared and must be set only when the DAC is in standby mode (resetting

registers when the DAC is running is prohibited and not supported).

0: Normal

1: Reset mode registers

13.1.2 Register 2 (0x02)

Figure 95. Register 2 (0x02)

7

6

5

4

3

2

1

0

DSPR

R/W

Reserved

R/W

RQST

R/W

Reserved

R/W

RQPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Register 2 (0x02) Field Descriptions

Bit

Field

Type

Reset

Description

7

DSPR

R/W

1

DSP reset – When the bit is made 0, DSP will start powering up and send out data.

This needs to be made 0 only after all the input clocks are (ASI,MCLK,PLLCLK) are

settled so that DMA channels do not go out of sync.

0: Normal operation

1: Reset the DSP

6-5

4

Reserved

RQST

R/W

Reserved

0

Standby Request – When this bit is set, the DAC will be forced into a system standby

mode, which is also the mode the system enters in the case of clock errors. In this

mode, most subsystems will be powered down but the charge pump and digital power

supply.

0: Normal operation

1: Standby mode

3-1

Reserved

R/W

Reserved

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ZHCSFY4 –DECEMBER 2016

Table 35. Register 2 (0x02) Field Descriptions (continued)

Bit

Field

RQPD

Type

Reset

Description

0

R/W

0

Powerdown Request – When this bit is set, the DAC will be forced into powerdown

mode, in which the power consumption would be minimum as the charge pump is also

powered down. However, it will take longer to restart from this mode. This mode has

higher precedence than the standby mode, i.e. setting this bit along with bit 4 for

standby mode will result in the DAC going into powerdown mode.

0: Normal operation

1: Powerdown mode

13.1.3 Register 3 (0x03)

Figure 96. Register 3 (0x03)

7

6

5

4

3

2

1

0

SYNC

RO

SDZE

RO

SDZS

RO

RQML

R/W

Reserved

R/W

RQMR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Register 3 (0x03) Field Descriptions

Bit

Field

Type

Reset

Description

7

SYNC

RO

sync_sig_to_dig – This is the clock signal to BackEnd. The clock frequency when

device is running is 98.304 Mhz/1024 = 96 ksps

6

5

4

SDZE

SDZS

RQML

RO

R/W

sdz_oe_to_dig – Backend IO buffer tristate signal. Will be asserted when LDO input

and LDO output PORs are both detected

0: SYNC and SDZ buffers are tristated

1: SYNC and SDZ buffers are enabled

sdz_sig_to_dig – Backend Power up signal. Will be asserted when AVDD & CPVDD

PORs are detected and Line amplifiers are unmuted

0: BackEnd is shutdown

1: BackEnd is powered up

0

Mute Left Channel – This bit issues soft mute request for the left channel. The volume

will be smoothly ramped down/up to avoid pop/click noise.

0: Normal volume

1: Mute

3-1

0

Reserved

RQMR

R/W

Reserved

Mute Right Channel – This bit issues soft mute request for the right channel. The

volume will be smoothly ramped down/up to avoid pop/click noise.

0: Normal volume

1: Mute

13.1.4 Register 4 (0x04)

Figure 97. Register 4 (0x04)

7

6

5

4

PLCK

R

3

2

1

0

PLLE

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Register 4 (0x04) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

PLCK

Reserved

0

PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is

disabled this bit always shows that the PLL is not locked.

0: The PLL is locked

1: The PLL is not locked

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Table 37. Register 4 (0x04) Field Descriptions (continued)

Bit

3-1

0

Field

Type

R/W

R

Reset

Description

Reserved

PLLE

Reserved

1

PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the

master clock will be switched to the MCLK.

0: Disable PLL

1: Enable PLL

13.1.5 Register 5 (0x05)

Figure 98. Register 5 (0x05)

7

6

5

4

3

2

1

0

Reserved

R/W

OSSL

RO

OSPD

RO

Reserved

R/W

OSAD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. Register 5 (0x05) Field Descriptions

Bit

7-6

5

Field

Type

R/W

RO

Reset

Description

Reserved

OSSL

Reserved

Oscillator Clock Selected – This bit, when set, indicates that the internal oscillator is

being selected as the master clock and that the system is in emergency state where

the normal system clock is not available/reliable.

0: Oscillator clock is not selected

1: Oscillator clock is being selected

4

OSPD

RO

Oscillator Powerdown Status – This bit, when set, indicates that the oscillator is being

powered down, as a result of setting the oscillator to auto disable mode and the

oscillator clock is not needed/selected.

0: Oscillator is active

1: Oscillator is powered down

3-1

0

Reserved

OSAD

R/W

Reserved

1

Oscillator Auto Disable – This bit sets the oscillator to auto disable mode, in which the

oscillator is powered down when it is not needed anymore. By disabling the oscillator,

both power consumption and potential interference is reduced.

0: Oscillator is always active

1: Oscillator is auto disabled (Powered down when not in use)

13.1.6 Register 6 (0x06)

Figure 99. Register 6 (0x06)

7

6

5

4

3

2

1

0

Reserved

R/W

OI2C

R/W

DBPG

R/W

FRMD

R/W

FSMI

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. Register 6 (0x06) Field Descriptions

Bit

7-5

4

Field

Type

Reset

Description

Reserved

OI2C

Reserved

R/W

0

old_i2c_mode_reg_r – In Hans, I2C is always in auto increment mode. In old device

MSB during control word decides whether is auto-increment mode or not. Writing this

bit as 1 enables the older mode.

0: Register Auto increment enabled by default

1: Register auto increment mode enabled based on the MSB value sent during address

portion of I2C protocol

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Table 39. Register 6 (0x06) Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

DBPG

R/W

0

Page auto increment disable – Disable page auto increment mode. for non -zero

books. When end of page is reached it goes back to 8th address location of next page

when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in

older part.

0: Enable Page auto increment

1: Disable Page auto increment

2

FRMD

R/W

0

SPI register read frame delay – When reading non-zero memory locations there is 1

frame delay between address and actual data. Which is read. By making this bit even

for book0 register read there will be 1 frame delay to make it consistent across all

books

0: No frame delay for SPI read for Book0 registers.

1: 1 frame delay for SPI read for Book0 registers.

1

0

FSMI

R/W

0

SPI MISO function sel:

00: SPI_MISO

01: GPIO3 Others: Reserved (Do not set)

Reserved

These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set

as GPIO, register readout via SPI is not possible.

13.1.7 Register 7 (0x07)

Figure 100. Register 7 (0x07)

7

6

5

4

3

2

1

0

Reserved

R/W

DEMP

R/W

Reserved

R/W

SDSL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. Register 7 (0x07) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

DEMP

Reserved

0

De-Emphasis Enable – This bit enables or disables the de-emphasis filter. The default

coefficients are for 44.1 kHz sampling rate, but can be changed by reprogramming the

appropriate coeffients in RAM.

0: De-emphasis filter is disabled

1: De-emphasis filter is enabled

3-1

0

Reserved

SDSL

R/W

Reserved

0

SDOUT Select – This bit selects what is being output as SDOUT via GPIO pins.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

13.1.8 Register 8 (0x08)

Figure 101. Register 8 (0x08)

7

6

5

4

3

2

1

0

Reserved

R/W

G2OE

R/W

MUTEOE

R/W

G0OE

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 41. Register 8 (0x08) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

G2OE

Reserved

0

GPIO2 Output Enable – This bit sets the direction of the GPIO2

0: GPIO2 is input

1: GPIO2 is output

4

3

MUTEOE

G0OE

R/W

0

MUTE Control Enable – This bit sets an enable of MUTE control

from PCM to TPA

0: MUTE control disable

1: MUTE control enable

GPIO0 Output Enable – This bit sets the direction of the GPIO0

0: GPIO0 is input

1: GPIO0 is output

Reserved

2

Reserved

R/W

0

1-0

Reserved

13.1.9 Register 9 (0x09)

Figure 102. Register 9 (0x09)

7

6

5

4

3

2

1

0

Reserved

R/W

SCLKP

R/W

SCLKO

R/W

Reserved

R/W

LRCLKFSO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Register 9 (0x09) Field Descriptions

Bit

7-6

5

Field

Type

Reset

Description

Reserved

SCLKP

Reserved

R/W

0

SCLK Polarity – This bit sets the inverted SCLK mode. In inverted SCLK mode, the

DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the

SCLK. Normally they are assumed to be aligned to the falling edge of the SCLK.

0: Normal SCLK mode

1: Inverted SCLK mode

4

SCLKO

R/W

0

SCLK Output Enable – This bit sets the SCLK pin direction to output for I2S master

mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and

LRCLK, and the external source device provides the DIN according to these clocks.

Use P0-R32 to program the division factor of the MCLK to yield the desired SCLK rate

(normally 64 FS)

0: SCLK is input (I2S slave mode)

1: SCLK is output (I2S master mode)

3-1

0

Reserved

LRKO

Reserved

R/W

0

LRCLK Output Enable – This bit sets the LRCLK pin direction to output for I2S master

mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and

LRCLK, and the external source device provides the DIN according to these clocks.

Use P0-R33 to program the division factor of the SCLK to yield 1 FS for LRCLK.

0: LRCLK is input (I2S slave mode)

1: LRCLK is output (I2S master mode)

13.1.10 Register 10 (0x0A)

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Figure 103. Register 10 (0x0A)

7

6

5

4

3

2

1

0

DSPG

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Register 10 (0x0A) Field Descriptions

Bit

Field

Type

Reset

Description

7

DSPG

R/W

0

DSP GPIO Input – this 8 bit bus reaches the DSP input port.

DSP s/w can access these bits for getting any direct

control/input from host ny means of this register write

6-0

Reserved

R/W

0

Reserved

13.1.11 Register 12 (0x0C)

Figure 104. Register 12 (0x0C)

7

6

5

4

3

2

1

0

Reserved

R/W

RDSP

R/W

RDAC

R/W

RNCP

R/W

ROSR

R/W

RSYN

R/W

RSCLK

R/W

RLRK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. Register 12 (0x0C) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

RDSP

Reserved

6

1

RST uCDSP clock – This bit, when set to 0 will reset the DSP clock divider and thus,

halt the DSP clock.

0: DSP clock divider is reset

1: DSP clock divider is functional

5

4

3

RDAC

RNCP

ROSR

R/W

1

RST DAC clock – This bit, when set to 0 will reset the DAC clock divider and thus, halt

the DAC clock and its derivatives.

0: DAC clock divider is reset

1: DAC clock divider is functional

RST NCP clock – This bit, when set to 0 will reset the OSR clock divider and thus, halt

the OSR clock.

0: OSR clock divider is reset

1: OSR clock divider is functional

RSTOSR clock – This bit, when set to 0 will reset the clock synchronizer and thus, halt

the DAC clock and its derivatives. When this bit is set to 1, the dividers un-reset will

take place synchronized to the beginning of audio frame.

0: DAC clock and its derivatives are stopped asynchronously

1: DAC clock and its derivatives started synchronized to the beginning of audio frame

2

1

0

RSYN

RSCLK

RLRK

R/W

1

0

1

RST clock sync – This bit, when set to 0 will reset the clock synchronizer and thus, halt

the DAC clock and its derivatives. When this bit is set to 1, the dividers un-reset will

take place synchronized to the beginning of audio frame.

0: DAC clock and its derivatives are stopped asynchronously

1: DAC clock and its derivatives started synchronized to the beginning of audio frame

Master Mode SCLK Divider Reset – This bit, when set to 0, will reset the MCLK divider

to generate SCLK clock for I2S master mode. To use I2S master mode, the divider

must be enabled and programmed properly.

0: Master mode SCLK clock divider is reset

1: Master mode SCLK clock divider is functional

Master Mode LRCLK Divider Reset – This bit, when set to 0, will reset the SCLK

divider to generate LRCLK clock for I2S master mode. To use I2S master mode, the

divider must be enabled and programmed properly.

0: Master mode LRCLK clock divider is reset

1: Master mode LRCLK clock divider is functional

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13.1.12 Register 13 (0x0D)

Figure 105. Register 13 (0x0D)

7

6

5

4

3

2

1

0

Reserved

R/W

SREF

R/W

SREF

R/W

Reserved

R/W

SDSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. Register 13 (0x0D) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

SREF

6-5

4

0

PLL Reference:

SREF

DSP clock source – This bit select the source clock for internal PLL. This bit is ignored

and overriden in clock auto set mode.

0: The PLL reference clock is MCLK

1: The PLL reference clock is SCLK

010: The PLL reference clock is oscillator clock

011: The PLL reference clock is GPIO (selected using P0-R18)

Others: Reserved (PLL reference is muted)

3

Reserved

SDSP

R/W

Reserved

2-0

0

DAC clock source – These bits select the source clock for DSP clock divider.

000: Master clock (PLL/MCLK and OSC auto-select)

001: PLL clock

010: OSC clock

011: MCLK clock

100: SCLK clock

101: GPIO (selected using P0-R16)

Others: Reserved (muted)

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13.1.13 Register 14 (0x0E)

Figure 106. Register 14 (0x0E)

7

6

5

4

3

2

1

0

Reserved

R/W

SDAC

R/W

Reserved

R/W

SOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. Register 14 (0x0E) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

SDAC

0

Reserved

6-4

DAC clock source – These bits select the source clock for DAC clock divider.

000: Master clock (PLL/MCLK and OSC auto-select)

001: PLL clock 010: OSC clock

011: MCLK clock

100: SCLK clock

101: GPIO (selected using P0-R16)

Others: Reserved (muted)

3

Reserved

SOSR

R/W

0

Reserved

2-0

OSR clock source – These bits select the source clock for OSR clock divider.

000: DAC clock

001: Master clock (PLL/MCLK and OSC auto-select)

010: PLL clock

011: OSC clock

100: MCLK clock

101: SCLK clock

110: GPIO (selected using P0-R17)

Others: Reserved (muted)

13.1.14 Register 15 (0x0F)

Figure 107. Register 15 (0x0F)

7

6

5

4

3

2

1

0

Reserved

R/W

SNCP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. Register 15 (0x0F) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

SNCP

Reserved

0

NCP clock source – These bits select the source clock for CP clock divider.

000: DAC clock

001: Master clock (PLL/MCLK and OSC auto-select)

010: PLL clock

011: OSC clock

100: MCLK clock

101: SCLK clock

110: GPIO (selected using P0-R17)

Others: Reserved (muted)

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13.1.15 Register 16 (0x10)

Figure 108. Register 16 (0x10)

7

6

5

4

3

2

1

0

Reserved

R/W

GDSP

R/W

Reserved

R/W

GDAC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. Register 16 (0x10) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

GDSP

0

Reserved

6-4

GPIO Source for uCDSP clk – These bits select the GPIO pins as clock input source

when GPIO is selected as DSP clock divider source.

000: N/A

001: N/A

010: N/A

011: GPIO0

100: N/A

101: GPIO2

Others: Reserved (muted)

3

Reserved

GDAC

R/W

0

Reserved

2-0

GPIO Source for DAC clk – These bits select the GPIO pins as clock input source

when GPIO is selected as DAC clock divider source.

000: N/A

001: N/A

010: N/A

011: GPIO0

100: N/A

101: GPIO2

Others: Reserved (muted)

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13.1.16 Register 17 (0x11)

Figure 109. Register 17 (0x11)

7

6

5

4

3

2

1

0

Reserved

R/W

GNCP

R/W

Reserved

R/W

GOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. Register 17 (0x11) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

GNCP

0

Reserved

6-4

GPIO Source for NCP clk – These bits select the GPIO pins as clock input source

when GPIO is selected as CP clock divider source

000: N/A

001: N/A

010: Reserved

011: GPIO0

100: N/A

101: GPIO2

Others: Reserved (muted)

3

Reserved

GOSR

R/W

0

Reserved

2-0

GPIO Source for OSR clk – These bits select the GPIO pins as clock input source

when GPIO is selected as OSR clock divider source.

000: N/A

001: N/A

010: Reserved

011: GPIO0

100: N/A

101: GPIO2

Others: Reserved (muted)

13.1.17 Register 18 (0x12)

Figure 110. Register 18 (0x12)

7

6

5

4

3

2

1

0

Reserved

R/W

GREF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. Register 18 (0x12) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

GREF

0

Reserved

GPIO Source for PLL reference clk – These bits select the GPIO pins as clock input

source when GPIO is selected as the PLL reference clock source.

000: N/A

001: N/A

010: Reserved

011: GPIO0

100: N/A

101: GPIO2

Others: Reserved (muted)

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13.1.18 Register 19 (0x13)

Figure 111. Register 19 (0x13)

7

6

5

4

3

2

1

0

Reserved

R/W

AREN

R/W

Reserved

R/W

RQSY

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. Register 19 (0x13) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

AREN

Reserved

1

Auto resync enable – This bits enables or disables the DAC/CP clock auto

resynchronization with the beginning of audio frame. When enabled, the

resynchronization is carried out just before the DAC transitions from standby mode to

normal operation mode.

0: Auto resynchronization is disabled

1: Auto resynchronization is enabled

3-1

0

Reserved

RQSY

R/W

Reserved

0

This bit, when set to 1 will issue the clock resynchronization by synchronously resets

the DAC, CP and OSR clocks.

The actual clock resynchronization takes place when this bit is set back to 0, where the

DAC, CP and OSR clocks are resumed at the beginning of the audio frame.

0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame

1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process

13.1.19 Register 20 (0x14)

Figure 112. Register 20 (0x14)

7

6

5

4

3

2

1

0

Reserved

R/W

PPDV

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. Register 20 (0x14) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

PPDV

0

Reserved

6-3

PLL P – These bits set the PLL divider P factor. These bits are ignored in clock auto

set mode.

0000: P=1

0001: P=2

...

1110: P=15

1111: Prohibited (do not set this value)

2-1

0

Reserved

R/W

0

1

Reserved

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13.1.20 Register 21 (0x15)

Figure 113. Register 21 (0x15)

7

6

5

4

3

2

1

0

Reserved

R/W

PJDV

R/W

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. Register 21 (0x15) Field Descriptions

Bit

7-6

5-4

Field

Type

Reset

Description

Reserved

PJDV

0

Reserved

P/W

PLL J – These bits set the J part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

000000: Prohibited (do not set this value)

000001: J=1

000010: J=2

...

111111: J=63

3

P/W

1

0

Reserved

2-0

13.1.21 Register 22 (0x16)

Figure 114. Register 22 (0x16)

7

6

5

4

3

2

1

0

Reserved

R/W

PDDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. Register 22 (0x16) Field Descriptions

Bit

7-6

5-0

Field

Type

R/W

Reset

Description

Reserved

PDDV

Reserved

0

PLL D (MSB) – These bits set the D part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

0 (in decimal): D=0000

1 (in decimal): D=0001

...

9999 (in decimal): D=9999

Others: Prohibited (do not set)

99

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13.1.22 Register 23 (0x17)

Figure 115. Register 23 (0x17)

7

6

5

4

3

2

1

0

PDDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. Register 23 (0x17) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PDDV

R/W

0

PLL D (LSB) – These bits set the D part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

0 (in decimal): D=0000

1 (in decimal): D=0001

...

9999 (in decimal): D=9999

Others: Prohibited (do not set)

13.1.23 Register 24 (0x18)

Figure 116. Register 24 (0x18)

7

6

5

4

3

2

1

0

Reserved

R/W

PRDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. Register 24 (0x18) Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

Reserved

PRDV

Reserved

0

PLL R – These bits set the R part of the overall PLL multiplication factor J.D * R. These

bits are ignored in clock auto set mode.

0000: R=1

0001: R=2

...

1111: R=16

100

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13.1.24 Register 25 (0x19)

Figure 117. Register 25 (0x19)

7

6

5

4

3

2

1

0

PLCT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. Register 25 (0x19) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PLCT

R/W

0

PLL Lock Count – These bits set the number of consecutive PLL lock flags counted by

the feedback clock before PLL is declared locked.

The count value is updated when addr 26 is written, so it is recommended to update

addr 25 first and then addr 26.

13.1.25 Register 26 (0x1A)

Figure 118. Register 26 (0x1A)

7

6

5

4

3

2

1

0

PLCT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. Register 26 (0x1A) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

PLCT

1

0

PLL Lock Count – These bits set the number of consecutive PLL lock flags counted by

the feedback clock before PLL is declared locked.

6-0

The count value is updated when addr 26 is written, so it is recommended to update

addr 25 first and then addr 26.

13.1.26 Register 27 (0x1B)

Figure 119. Register 27 (0x1B)

7

6

5

4

3

2

1

0

Reserved

R/W

DDSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. Register 27 (0x1B) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

DDSP

Reserved

6-0

0

DSP Clock Divider – These bits set the source clock divider value for the DSP clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.27 Register 28 (0x1C)

101

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Figure 120. Register 28 (0x1C)

7

6

5

4

3

2

1

0

Reserved

R/W

DDAC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Register 28 (0x1C) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DDAC

Reserved

6-4

3-0

R/W

0

1

DAC Clock Divider – These bits set the source clock divider value for the DAC clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.28 Register 29 (0x1D)

Figure 121. Register 29 (0x1D)

7

6

5

4

3

2

1

0

Reserved

R/W

DNCP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Register 29 (0x1D) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DNCP

Reserved

6-2

1-0

R/W

0

1

NCP Clock Divider – These bits set the source clock divider value for the CP clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.29 Register 30 (0x1E)

Figure 122. Register 30 (0x1E)

7

6

5

4

3

2

1

0

Reserved

R/W

DOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. Register 30 (0x1E) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DOSR

Reserved

6-4

5-0

R/W

0

1

OSR Clock Divider – These bits set the source clock divider value for the OSR clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

102

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13.1.30 Register 31 (0x1F)

Figure 123. Register 31 (0x1F)

7

6

5

4

3

2

1

0

Reserved

R/W

DOFS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. Register 31 (0x1F) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DOFS

Reserved

6-3

2

R/W

0

1

0

Offset calibrator clock div – These bits set the source clock divider value for the offset

calibrator

0000000: Divide by 1

0000001: Divide by 2

...

1-0

1111111: Divide by 128

13.1.31 Register 32 (0x20)

Figure 124. Register 32 (0x20)

7

6

5

4

3

2

1

0

Reserved

R/W

DSCLK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. Register 32 (0x20) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

DSCLK

Reserved

6-0

0

Master Mode SCLK Divider – These bits set the MCLK divider value to generate I2S

master SCLK clock.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.32 Register 33 (0x21)

Figure 125. Register 33 (0x21)

7

6

5

4

3

2

1

0

DLRK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. Register 33 (0x21) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLRK

R/W

0

Master Mode LRCLK Divider – These bits set the I2S master SCLK clock divider value

to generate I2S master LRCLK clock

00000000: Divide by 1

00000001: Divide by 2

...

11111111: Divide by 256

103

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ZHCSFY4 –DECEMBER 2016

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13.1.33 Register 34 (0x22)

Figure 126. Register 34 (0x22)

7

6

5

4

3

2

1

0

Reserved

R/W

I16E

R/W

Reserved

R/W

FSSP

R/W

FSSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. Register 34 (0x22) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

I16E

Reserved

0

16x Interpolation – This bit enables or disables the 16x interpolation mode

0: 8x interpolation

1: 16x interpolation

3

2

Reserved

FSSP

R/W

Reserved

1

0

FS Speed Mode – These bits select the FS operation mode, which must be set

according to the current audio sampling rate. These bits are ignored in clock auto set

mode.

1-0

000: Reserved

001: Reserved

010: Reserved

011: 48 kHz

100: 88.2-96 kHz

101: Reserved

110: Reserved

111: 32kHz

13.1.34 Register 35 (0x23)

Figure 127. Register 35 (0x23)

7

6

5

4

3

2

1

0

INTFLAG

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. Register 35 (0x23) Field Descriptions

Bit

7-1

0

Field

Type

R/W

R

Reset

Description

Reserved

0

Reserved

Pin interrupt sticky flag – Sticky flag that reflects the pin interrupt value. Once read pin

interrupt and this register will automatically reset to 0. To mask which all faults/errors

can generate this interrupt use B0_P0_R45.

0: interrupt de-asserted

1: interrupt asserted

104

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13.1.35 Register 37 (0x25)

Figure 128. Register 37 (0x25)

7

6

5

4

3

2

1

0

Reserved

R/W

IDFS

R/W

IDBK

R/W

IDSK

R/W

IDCH

R/W

IDCM

R/W

DCAS

R/W

IPLK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. Register 37 (0x25) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

IDFS

Reserved

6

0

Ignore FS Detection – This bit controls whether to ignore the FS detection. When

ignored, FS error will not cause a clock error.

0: Regard FS detection

1: Ignore FS detection

5

4

3

2

IDBK

IDSK

IDCH

IDCM

R/W

0

Ignore SCLK Detection – This bit controls whether to ignore the SCLK detection

against LRCLK. The SCLK must be stable between 32 FS and 256 FS inclusive or an

error will be reported. When ignored, a SCLK error will not cause a clock error.

0: Regard SCLK detection

1: Ignore SCLK detection

Ignore MCLK Detection – This bit controls whether to ignore the MCLK detection

against LRCLK. Only some certain MCLK ratios within some error margin are allowed.

When ignored, an MCLK error will not cause a clock error.

0: Regard MCLK detection

1: Ignore MCLK detection

Ignore Clock Halt Detection – This bit controls whether to ignore the MCLK halt (static

or frequency is lower than acceptable) detection. When ignored an MCLK halt will not

cause a clock error.

0: Regard MCLK halt detection

1: Ignore MCLK halt detection

Ignore LRCLK/SCLK Missing Detection – This bit controls whether to ignore the

LRCLK/SCLK missing detection. The LRCLK/SCLK need to be in low state (not only

static) to be deemed missing. When ignored an LRCLK/SCLK missing will not cause

the DAC go into powerdown mode.

0: Regard LRCLK/SCLK missing detection

1: Ignore LRCLK/SCLK missing detection

1

DCAS

R/W

0

Disable Clock Divider Autoset – This bit enables or disables the clock auto set mode.

When dealing with uncommon audio clock configuration, the auto set mode must be

disabled and all clock dividers must be set manually.

Addtionally, some clock detectors might also need to be disabled. The clock autoset

feature will not work with PLL enabled in VCOM mode. In this case this feature has to

be disabled and the clock dividers must be set manually.

0: Enable clock auto set

1: Disable clock auto set

0

IPLK

R/W

0

Ignore PLL Lock Detection – This bit controls whether to ignore the PLL lock detection.

When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at P0-R4, bit

4 is always correct regardless of this bit.

0: PLL unlocks raise clock error

1: PLL unlocks are ignored

105

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13.1.36 Register 38 (0x26)

Figure 129. Register 38 (0x26)

7

6

5

4

3

2

1

0

BKCG

R/W

BKCB

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. Register 38 (0x26) Field Descriptions

Bit

Field

Type

Reset

Description

7-4

BKCG

R/W

1

BCLK count to good – These bits specify the number of consecutive valid SCLK counts

in LRCLK until the SCLK is deemed good. To be valid, the SCLK counts in LRCLK

should be between 32 and 256 inclusive and match the count at previous audio frame.

0000: One consecutive LRCLK

0001: Two consecutive LRCLKs

...

1111: 16 consecutive LRCLKs

3-2

1-0

BKCB

R/W

0

1

BCLK count to bad – These bits specify the number of consecutive invalid SCLK

counts in LRCLK until the SCLK is deemed bad. To be valid, the SCLK counts in

LRCLK should be between 32 and 256 inclusive and match the count at previous audio

frame.

0000: One consecutive LRCLK

0001: Two consecutive LRCLKs

...

1111: 16 consecutive LRCLKs

13.1.37 Register 39 (0x27)

Figure 130. Register 39 (0x27)

7

6

5

4

3

2

1

0

Reserved

R/W

MCLKT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. Register 39 (0x27) Field Descriptions

Bit

7-5

4-3

2

Field

Type

R/W

Reset

Description

Reserved

MCLKT

Reserved

0

1

0

MCLK tolerance – These bits specify the tolerance for MCLK counts in LRCLK. When

the MCLK count in LRCLK matches any valid ratio within this tolerance, it will be

deemed good

1-0

00000: tolerate ± 0 count

00001: tolerate ± 1 count

…

11111: tolerate ± 31 counts

106

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13.1.38 Register 40 (0x28)

Figure 131. Register 40 (0x28)

7

6

5

4

3

2

1

0

Reserved

R/W

AFMT

R/W

Reserved

R/W

ALEN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. Register 40 (0x28) Field Descriptions

Bit

7-6

5-4

Field

–

Type

Reset

Description

AFMT

R/W

0

I2S Data Format – These bits control both input and output audio interface formats for

DAC operation.

00: I2S

01: DSP

10: RTJ

11: LTJ

3-2

1

Reserved

ALEN

R/W

Reserved

1

0

I2S Word Length – These bits control both input and output audio interface sample

word lengths for DAC operation.

0

00: 16 bits

01: 20 bits

10: 24 bits

11: 32 bits

13.1.39 Register 41 (0x29)

Figure 132. Register 41 (0x29)

7

6

5

4

3

2

1

0

AOFS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. Register 41 (0x29) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

AOFS

R/W

0

I2S Shift – These bits control the offset of audio data in the audio frame for both input

and output. The offset is defined as the number of SCLK from the starting (MSB) of

audio frame to the starting of the desired audio sample.

00000000: offset = 0 SCLK (no offset)

00000001: ofsset = 1 SCLK

00000010: offset = 2 SCLKs

…

11111111: offset = 256 SCLKs

107

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13.1.40 Register 42 (0x2A)

Figure 133. Register 42 (0x2A)

7

6

5

4

3

2

1

0

Reserved

R/W

AUPL

R/W

Reserved

R/W

AUPR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. Register 42 (0x2A) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

AUPL

Reserved

0

1

Left DAC Data Path – These bits control the left channel audio data path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)

4

3-2

1

Reserved

AUPR

R/W

Reserved

0

1

Right DAC Data Path – These bits control the right channel audio data path

connection.

0

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

13.1.41 Register 43 (0x2B)

Figure 134. Register 43 (0x2B)

7

6

5

4

3

2

1

0

Reserved

R/W

PSEL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. Register 43 (0x2B) Field Descriptions

Bit

7-5

4-1

0

Field

Type

R/W

Reset

Description

Reserved

PSEL

Reserved

0

1

DSP Program Selection – These bits select the DSP program to use for audio

processing.

00000: Reserved

00001: Rom Mode 1

00010: Reserved

00011: Reserved

108

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13.1.42 Register 44 (0x2C)

Figure 135. Register 44 (0x2C)

7

6

5

4

3

2

1

0

Reserved

R/W

CLKM

R/W

CMDP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. Register 44 (0x2C) Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

Reserved

CLKM

Reserved

R/W

1

clk_missing_mode_hans_reg_r – Fallback option to change clock missing detection to

older PCM device. In Hans clock missing is detected whenever either BCLK or LRCLK

go missing. In older PCM device clock missing is detected whenever LRCLK or BCLK

are stuck to 1.

0 : Old mode of ASI clock missing detection

1: Hans mode of ASI clock missing detect

2-0

CMDP

R/W

0

Clock Missing Detection Period – These bits set how long both SCLK and LRCLK keep

low before the audio clocks deemed missing and the DAC transitions to powerdown

mode.

000: about 1 second

001: about 2 seconds

010: about 3 seconds

...

111: about 8 seconds

13.1.43 Register 45 (0x2D)

Figure 136. Register 45 (0x2D)

7

6

5

4

3

2

1

0

MSKP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. Register 45 (0x2D) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

MSKP

R/W

1

Mask for Pin interrupt generated by device (?)

To mask and selectively use the required faults alone to generate the interrupt

0 : No interrupt generated

1 : Allow interrupt to be generated

1 : No interrupt generated

1 : Allow interrupt to be generated

2 : No interrupt generated

1 : Allow interrupt to be generated

3 : No interrupt generated

1 : Allow interrupt to be generated

4 : No interrupt generated

1 : Allow interrupt to be generated

5 : No interrupt generated

1 : Allow interrupt to be generated

Mask for Pin interrupt generated by device (short-flag)

6 : No interrupt generated

1 : Allow interrupt to be generated

Mask for Pin interrupt generated by device (dsp_interrupt)

7 : No interrupt generated

1 : Allow interrupt to be generated

109

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13.1.44 Register 46 (0x2E)

Figure 137. Register 46 (0x2E)

7

6

5

4

3

2

1

0

Reserved

R/W

SDZF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. Register 46 (0x2E) Field Descriptions

Bit

7-1

0

Field

Type

R/W

Reset

Description

Reserved

SDZF

Reserved

1

Disable Force shutdown of Backend – This controls the Backed device shutdown

signal. When it is programmed 0 backend devi ce will be shutdown.

0 : Force shutdown of Backend

1 : Disable force shutdown of Backend

13.1.45 Register 47 (0x2F)

Figure 138. Register 47 (0x2F)

7

6

5

4

3

2

1

0

Reserved

R/W

DLSH

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. Register 47 (0x2F) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

DLSH

Reserved

0

Disable Last Sample Hold – This bit controls whether to hold the last sample at audio

interface in the event of clock error. The last known good sample is held to prevent

errorneous samples to flow through the DAC.

0: Enable last sample hold

1: Disable last sample hold

4-0

Reserved

R/W

Reserved

110

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13.1.46 Register 48 (0x30)

Figure 139. Register 48 (0x30)

7

6

5

4

3

2

1

0

Reserved

R/W

EDINT

R/W

INTSTAT

R/W

INTGPIO

R/W

DBCLK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. Register 48 (0x30) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

EDINT

Reserved

6

R/W

1

Edge detection of pin interrupt input – this bit controls whether to detect a positive edge

and send interrupt to dsp or reflect the pin value at the dsp_interrupt port

0: disable positive edge detect

1: enable positive edge detect

5

INTSTAT

INTGPIO

R/W

0

Enable active low for input pin interrupt – This controls whether input pin interrupt is

active low or active high.

0 : input pin interrupt is active high

1 : input pin interrupt is active low

4-2

GPIO for input pin interrupt – these bits control which GPIO to be used as the input pin

interrupt

000: pin interrupt disabled

001: pin interrupt = Input from RESERVED

010: pin interrupt = Input from RESERVED

011: Reserved

100: pin interrupt = Input from GPIO0

101: pin interrupt = Input from RESERVED

110: pin interrupt = Input from GPIO2

111: reserved

1-0

DBCLK

R/W

0

Pin debounce clock select – selects the clk frequency to be used for deboucing glitches

on pin before detecting a flip on the pin ( debouncing is done for 4 clock cycles of this

selected clock)

00: approx 1 ms clk used for debouncing

01: approx 500 µs clk used for debouncing

10: approx 125 µs clk used for debouncing

11: oscillator clk used for debouncing

13.1.47 Register 49 (0x31)

Figure 140. Register 49 (0x31)

7

6

5

4

3

2

1

0

Reserved

R/W

GSPGPI2

R/W

Reserved

R/W

GSPGPI0

R/W

GSPGPI1

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. Register 49 (0x31) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

GSPGPI2

0

Reserved

6

Enable GPIO2 value to propagate to DSP – Each bit when set high allows the

corresponding GPIO pin value to propagate to DSP as an input port bus

0 : GPIO2 value will not propagate to DSP

1 : GPIO2 value is allowed to propagate to DSP

5

4

Reserved

GSPGPI0

R/W

Reserved

0

Enable GPIO0 value to propagate to DSP – Each bit when set high allows the

corresponding GPIO pin value to propagate to DSP as an input port bus

0 : GPIO0 value will not propagate to DSP

1 : GPIO0 value is allowed to propagate to DSP

111

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ZHCSFY4 –DECEMBER 2016

www.ti.com.cn

Table 80. Register 49 (0x31) Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

Reserved

R/W

Reserved

13.1.48 Register 50 (0x32)

Figure 141. Register 50 (0x32)

7

6

5

4

3

2

1

0

Reserved

R/W

DSPMEM

R/W

DSPCOEF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. Register 50 (0x32) Field Descriptions

Bit

7-2

1

Field

Type

R/W

Reset

Description

Reserved

DSPMEM

0

Reserved

DSP boots from IRAM – When set DSP will boot from IRAM instead of IROM

0: boot DSP from IROM

1: boot DSP from IRAM

0

DSPCOEF

R/W

Use default coefficients from ZROM – This bit controls whether to use default

coefficients from ZROM or use the non-default coefficients downloaded to device by

the Host

0 : don't use default coefficients from ZROM

1 : use default coefficents from ZROM

112

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13.1.49 Register 51 (0x33)

Figure 142. Register 51 (0x33)

7

6

5

4

3

2

1

0

Reserved

R/W

DSPINT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. Register 51 (0x33) Field Descriptions

Bit

7-1

0

Field

Type

R/W

Reset

Description

Reserved

DSPINT

Reserved

Interrupt DSP – This bit can be set to generate an interrupt to DSP. Once the DSP

acknowledges this interrupt this bit will be automatically cleared

0: normal

1 : generate interrupt to DSP

13.1.50 Register 52 (0x34)

Figure 143. Register 52 (0x34)

7

6

5

4

3

2

1

0

Reserved

R/W

DSPRMEM

R/W

MEMCRYP

R/W

MEMCRC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. (Register 52 (0x34) Field Descriptions

Bit

7-4

3

Field

Type

R/W

Reset

Description

Reserved

DSPRMEM

0

Reserved

Enable read from IRAM,IROM,ZROM – This bit controls whether to allow reads to

IRAM, IROM and ZROM . When this bit is zero , read request to these memories will

give out a 0

0 : dis-allow read from IRAM,IROM and ZROM

1 : all reads from IRAM, IROM and ZROM

2

MEMCRYP

MEMCRC

R/W

0

Disable decryption – This bit controls whether to disable or enable decryption on the

content that is downloaded by Host into IRAM

0 : enable decryption

1 : disable decryption

1-0

CRC seed selection for Decryption – These bits control which seed to use for CRC

based decryption logic.

00 : use A5 hex as seed

01 : use B6 hex as seed

10 : use 94 hex as seed

11 : use E2 hex as seed

13.1.51 Register 53 (0x35)

Figure 144. Register 53 (0x35)

7

6

5

4

3

2

1

0

Reserved

R/W

RSTD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 84. Register 53 (0x35) Field Descriptions

Bit

7-1

0

Field

Type

R/W

WO

Reset

Description

Reserved

RSTD

Reserved

0

Reset decryption block – Setting this bit to '1' resets the decryption block and

reinitializes the CRC with the CRC seed. It is a self clearing bit.

'1' -> reset the decryption block

'0' -> decryption block is not reset

13.1.52 Register 59 (0x3B)

Figure 145. Register 59 (0x3B)

7

6

5

4

3

2

1

0

Reserved

R/W

AMTL

R/W

Reserved

R/W

AMTR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Register 59 (0x3B) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

AMTL

Reserved

6-4

0

Auto Mute Time for Left Channel – These bits specify the length of consecutive zero

samples at left channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

3

Reserved

AMTR

R/W

Reserved

2-0

0

Auto Mute Time for Right Channel – These bits specify the length of consecutive zero

samples at right channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

13.1.53 Register 60 (0x3C)

Figure 146. Register 60 (0x3C)

7

6

5

4

3

2

1

0

Reserved

R/W

PCTL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 86. Register 60 (0x3C) Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

Reset

Description

Reserved

PCTL

0

Reserved

Digital Volume Control – These bits control the behavior of the digital volume.

00: The volume for Left and right channels are independent

01: Right channel volume follows left channel setting

13.1.54 Register 61 (0x3D)

Figure 147. Register 61 (0x3D)

7

6

5

4

3

2

1

0

VOLL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Register 61 (0x3D) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

VOLL

R/W

0001000 Left Digital Volume – These bits control the left channel digital volume. The digital

0

volume is 24 dB to –103 dB in –0.5 dB step.

00000000: +24.0 dB

00000001: +23.5 dB

…

00101111: +0.5 dB

00110000: 0.0 dB

00110001: –0.5 dB

...

11111110: –103 dB

11111111: Mute

13.1.55 Register 62 (0x3E)

Figure 148. Register 62 (0x3E)

7

6

5

4

3

2

1

0

VOLR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Register 62 (0x3E) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

VOLR

R/W

0011000 Right Digital Volume – These bits control the right channel digital volume. The digital

0

volume is 24 dB to –103 dB in –0.5 dB step.

00000000: +24.0 dB

00000001: +23.5 dB

…

00101111: +0.5 dB

00110000: 0.0 dB

00110001: –0.5 dB

...

11111110: –103 dB

11111111: Mute

13.1.56 Register 63 (0x3F)

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Figure 149. Register 63 (0x3F)

7

6

5

4

3

2

1

0

VNDF

R/W

VNDS

R/W

VNUF

R/W

VNUS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Register 63 (0x3F) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VNDF

R/W

0

Digital Volume Normal Ramp Down Frequency – These bits control the frequency of

the digital volume updates when the volume is ramping down. The setting here is

applied to soft mute request, asserted by XSMUTE pin or P0-R3.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-2

1-0

VNDS

VNUF

VNUS

R/W

1

0

1

Digital Volume Normal Ramp Down Step – These bits control the step of the digital

volume updates when the volume is ramping down.

The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

Digital Volume Normal Ramp Up Frequency – These bits control the frequency of the

digital volume updates when the volume is ramping up.

The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly restore the volume (Instant unmute)

Digital Volume Normal Ramp Up Step – These bits control the step of the digital

volume updates when the volume is ramping up.

The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3.

00: Increment by 4 dB for each update

01: Increment by 2 dB for each update

10: Increment by 1 dB for each update

11: Increment by 0.5 dB for each update

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13.1.57 Register 64 (0x40)

Figure 150. Register 64 (0x40)

7

6

5

4

3

2

1

0

VEDF

R/W

VEDS

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Register 64 (0x40) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VEDF

R/W

0

Digital Volume Emergency Ramp Down Frequency – These bits control the frequency

of the digital volume updates when the volume is ramping down due to clock error or

power outage, which usually needs faster ramp down compared to normal soft mute.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-0

VEDS

R/W

1

Digital Volume Emergency Ramp Down Step – These bits control the step of the digital

volume updates when the volume is ramping down due to clock error or power outage,

which usually needs faster ramp down compared to normal soft mute.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

Reserved

13.1.58 Register 65 (0x41)

Figure 151. Register 65 (0x41)

7

6

5

4

3

2

1

0

Reserved

R/W

ACTL

R/W

AMLE

R/W

AMRE

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. Register 65 (0x41) Field Descriptions

Bit

7-3

2

Field

Type

R/W

Reset

Description

Reserved

ACTL

Reserved

1

Auto Mute Control**NOBUS** – This bit controls the behavior of the auto mute upon

zero sample detection. The time length for zero detection is set with P0-R59.

0: Auto mute left channel and right channel independently.

1: Auto mute left and right channels only when both channels are about to be auto

muted.

1

0

AMLE

AMRE

R/W

1

Auto Mute Left Channel**NOBUS** – This bit enables or disables auto mute on right

channel. Note that when right channel auto mute is disabled and the P0-R65, bit 2 is

set to 1, the left channel will also never be auto muted.

0: Disable right channel auto mute

1: Enable right channel auto mute

Auto Mute Right Channel**NOBUS** – This bit enables or disables auto mute on left

channel. Note that when left channel auto mute is disabled and the P0-R65, bit 2 is set

to 1, the right channel will also never be auto muted.

0: Disable left channel auto mute

1: Enable left channel auto mute

13.1.59 Register 66 (0x42)

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Figure 152. Register 66 (0x42)

7

6

5

4

3

2

1

0

ADLY

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. Register 66 (0x42) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADLY

R/W

0001100 AMUTE Delay – These bits control the delay before the complete digital mute to the

1

assertion of analog mute. This is to allow the non-mute audio samples to completely

flow out through analog parts before the assertion of the analog mute.

00000000: No delay

00000001: 1 LRCLK delay

00000010: 2 LRCLK delay

…

11111111: 255 LRCLK delay

13.1.60 Register 67 (0x43)

Figure 153. Register 67 (0x43)

7

6

5

4

3

2

1

0

DLPA

R/W

DRPA

R/W

DLPM

R/W

DRPM

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. Register 67 (0x43) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DLPA

R/W

0

Left DAC primary AC dither gain – These bits control the AC dither gain for left channel

primary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

5-4

3-2

DRPA

DLPM

R/W

0

Right DAC primary AC dither gain – These bits control the AC dither gain for right

channel primary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

Left DAC primary DEM dither gain – These bits control the dither gain for left channel

primary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

1-0

DRPM

R/W

0

Right DAC primary DEM dither gain – These bits control the dither gain for right

channel primary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

13.1.61 Register 68 (0x44)

Figure 154. Register 68 (0x44)

7

6

5

4

3

2

1

0

Reserved

R/W

DLPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

118

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Table 94. Register 68 (0x44) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

DLPD

Reserved

0

Left DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the left channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

13.1.62 Register 69 (0x45)

Figure 155. Register 69 (0x45)

7

6

5

4

3

2

1

0

DLPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. Register 69 (0x45) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLPD

R/W

0

Left DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the left channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

119

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13.1.63 Register 70 (0x46)

Figure 156. Register 70 (0x46)

7

6

5

4

3

2

1

0

DRPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. Register 70 (0x46) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRPD

R/W

0

Right DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the right channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

13.1.64 Register 71 (0x47)

Figure 157. Register 71 (0x47)

7

6

5

4

3

2

1

0

DRPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. Register 71 (0x47) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRPD

R/W

0

Right DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the right channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

120

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13.1.65 Register 72 (0x48)

Figure 158. Register 72 (0x48)

7

6

5

4

3

2

1

0

DLSA

R/W

DRSA

R/W

DLSM

R/W

RSM

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. Register 72 (0x48) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DLSA

R/W

01

Left DAC secondary AC dither gain – These bits control the AC dither gain for left

channel secondary DAC.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

5-4

DRSA

R/W

01

Right DAC secondary AC dither gain – These bits control the AC dither gain for right

channel secondary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

10: AC dither gain = 0.5

11: no AC dither

3-2

1-0

DLSM

DRSM

R/W

01

Left DAC secondary DEM dither gain – These bits control the dither gain for left

channel secondary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

Right DAC secondary DEM dither gain – These bits control the dither gain for right

channel secondary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

121

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13.1.66 Register 73 (0x49)

Figure 159. Register 73 (0x49)

7

6

5

4

3

2

1

0

DLSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. Register 73 (0x49) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLSD

R/W

0

Left DAC secondary DC dither – These bits control the DC dither amount to be added

to the lower part of the left channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

13.1.67 Register 74 (0x4A)

Figure 160. Register 74 (0x4A)

7

6

5

4

3

2

1

0

DLSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. Register 74 (0x4A) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLSD

R/W

0

Left DAC secondary DC dither – These bits control the DC dither amount to be added

to the lower part of the left channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

122

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13.1.68 Register 75 (0x4B)

Figure 161. Register 75 (0x4B)

7

6

5

4

3

2

1

0

DRSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 101. Register 75 (0x4B) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRSD

R/W

0000000 Right DAC secondary DC dither – These bits control the DC dither amount to be added

0

to the lower part of the right channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

13.1.69 Register 76 (0x4C)

Figure 162. Register 76 (0x4C)

7

6

5

4

3

2

1

0

DRSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 102. Register 76 (0x4C) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRSD

R/W

0000000 Right DAC secondary DC dither – These bits control the DC dither amount to be added

0

to the lower part of the right channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

123

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13.1.70 Register 78 (0x4E)

Figure 163. Register 78 (0x4E)

7

6

5

4

3

2

1

0

OLOF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 103. Register 78 (0x4E) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

OLOF

R/W

0000000 Left OFSCAL offset – These bits controls the amount of manual DC offset to be added

0

to the left channel DAC output. The additional offset would be approximately the

negative of the decimal value of this register divided by 4 in mV.

01111111 : –31.75 mV

01111110 : –31.50 mV

…

00000010 : –0.50 mV

00000001 : –0.25 mV

00000000 : 0.0 mV

11111111 : +0.25 mV

11111110 : +0.50 mV

…

10000000 : +32.0 mV

13.1.71 Register 79 (0x4F)

Figure 164. Register 79 (0x4F)

7

6

5

4

3

2

1

0

OROF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 104. Register 79 (0x4F) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

OROF

R/W

0

Right OFSCAL offset – These bits controls the amount of manual DC offset to be

added to the right channel DAC output. The additional offset would be approximately

the negative of the decimal value of this register divided by 4 in mV.

01111111 : –31.75 mV

01111110 : –31.50 mV

…

00000010 : –0.50 mV

00000001 : –0.25 mV

00000000 : 0.0 mV

11111111 : +0.25 mV

11111110 : +0.50 mV

…

10000000 : +32.0 mV

124

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13.1.72 Register 80 (0x50)

Figure 165. Register 80 (0x50)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 105. Register 80 (0x50) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.1.73 Register 81 (0x51)

Figure 166. Register 81 (0x51)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 106. Register 81 (0x51) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

125

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13.1.74 Register 82 (0x52)

Figure 167. Register 82 (0x52)

7

6

5

4

3

2

1

0

Reserved

R/W

G1SL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 107. Register 82 (0x52) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

Reserved

126

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ZHCSFY4 –DECEMBER 2016

13.1.75 Register 83 (0x53)

Figure 168. Register 83 (0x53)

7

6

5

4

3

2

1

0

Reserved

R/W

G0SL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 108. Register 83 (0x53) Register Field Descriptions

Bit

7-5

4-0

Field

Type

R/W

Reset

Description

Reserved

G0SL

Reserved

0

GPIO0 Output Selection – These bits select the signal to output to GPIO0. To actually

output the selected signal, the GPIO0 must be set to output mode at P0-R8.

0110: Clock invalid flag (clock error or clock changing or clock missing)

0111: Serial audio interface data output (SDOUT)

1000: Analog mute flag for left channel (low active)

1001: Analog mute flag for right channel (low active) 1010: PLL lock flag

1011: Charge pump clock

1100: Reserved

1101: Reserved

1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD

1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD **

INTERNAL **

1100: Short detection flag for left channel

1101: Short detection flag for right channel

10000: PLL clock/4

10001: Oscillator clock/4

10010: Impedance sense flag for left channel

10011: Impedance sense flag for right channel

10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V

10101: Offset calibration flag, asserted when the system is offset calibrating itself.

10110: Clock error flag

10111: Clock changing flag

11000: Clock missing flag

11001: Clock halt detection flag

11010: DSP boot done flag

11011: Charge pump voltage output valid flag (low active)

Others: N/A (zero)

13.1.76 Register 84 (0x54)

Figure 169. Register 84 (0x54)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 109. Register 84 (0x54) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.1.77 Register 85 (0x55)

127

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Figure 170. Register 85 (0x55)

7

6

5

4

3

2

1

0

Reserved

R/W

G2SL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 110. Register 85 (0x55) Register Field Descriptions

Bit

7-5

4-0

Field

Type

R/W

Reset

Description

Reserved

G2SL

0

Reserved

GPIO2 Output Selection – These bits select the signal to output to GPIO2. To actually

output the selected signal, the GPIO2 must be set to output mode at P0-R8.

0000: off (low)

0001: DSP GPIO2 output

0010: Register GPIO2 output (P0-R86, bit 5)

0011: Auto mute flag (asserted when both L and R channels are auto muted)

0100: Auto mute flag for left channel

0101: Auto mute flag for right channel

0110: Clock invalid flag (clock error or clock changing or clock missing)

0111: Serial audio interface data output (SDOUT)

1000: Analog mute flag for left channel (low active)

1001: Analog mute flag for right channel (low active)

1010: PLL lock flag

1011: Charge pump clock

1100: Reserved

1101: Reserved

1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD

1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD **

INTERNAL **

1100: Short detection flag for left channel

1101: Short detection flag for right channel

10000: PLL clock/4 10001: Oscillator clock/4

10010: Impedance sense flag for left channel

10011: Impedance sense flag for right channel

10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V

10101: Offset calibration flag, asserted when the system is offset calibrating itself.

10110: Clock error flag

10111: Clock changing flag

11000: Clock missing flag

11001: Clock halt detection flag

11010: DSP boot done flag

11011: Charge pump voltage output valid flag (low active)

Others: N/A (zero)

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13.1.78 Register 86 (0x56)

Figure 171. Register 86 (0x56)

7

6

5

4

3

2

1

0

Reserved

R/W

GOUT2

R/W

MUTE

R/W

GOUT0

R/W

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 111. Register 86 (0x56) Register Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

GOUT2

0

Reserved

GPIO Output Control – This bit controls the GPIO2 output when the selection at P0-

R85 is set to 0010 (register output)

0: Output low

1: Output high

4

3

MUTE

R/W

0

This bit controls the MUTE output when the selection at P0-R84 is set to 0010 (register

output).

0: Output low

1: Output high

GOUT0

Reserved

This bit controls the GPIO0 output when the selection at P0-R83 is set to 0010 (register

output)

0: Output low

1: Output high

2-0

Reserved

13.1.79 Register 87 (0x57)

Figure 172. Register 87 (0x57)

7

6

5

4

3

2

1

0

Reserved

R/W

GINV2

R/W

MUTE

R/W

GINV0

R/W

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 112. Register 87 (0x57) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

GINV2

0

Reserved

GPIO Output Inversion – This bit controls the polarity of GPIO2 output. When set to 1,

the output will be inverted for any signal being selected.

0: Non-inverted

1: Inverted

4

3

MUTE

R/W

0

This bit controls the polarity of MUTE output. When set to 1, the output will be inverted

for any signal being selected.

0: Non-inverted

1: Inverted

GINV0

This bit controls the polarity of GPIO0 output. When set to 1, the output will be inverted

for any signal being selected.

0: Non-inverted

1: Inverted

2-0

Reserved

13.1.80 Register 88 (0x58)

129

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Figure 173. Register 88 (0x58)

7

6

5

4

3

2

1

0

DIEI

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 113. Register 88 (0x58) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIEI

RO

0x84

Die ID, Device ID = 0x84

13.1.81 Register 89 (0x59)

Figure 174. Register 89 (0x59)

7

6

5

VSTL

R

4

VENTL

R

3

2

1

VSTR

R

0

VENR

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 114. Register 89 (0x59) Field Descriptions

Bit

7-6

5

Field

Type

R/W

R

Reset

Description

Reserved

VSTL

0

Reserved

Left Digital Volume Status – This bit indicates the status of the left channel digital

volume.

0: Digital volume is not changing

1: Digital volume is changing

4

VENTL

R

0

Left Digital Volume Complete Flag – This bit indicates whether the left channel digital

volume has reached its target volume.

0: The digital volume has not reached the target volume

1: The digital volume has reached the target volume

3-2

1

Reserved

VSTR

R/W

R

0

Reserved

Right Digital Volume Status – This bit indicates the status of the right channel digital

volume.

0: Digital volume is not changing

1: Digital volume is changing

0

VENR

R

0

Right Digital Volume Complete Flag – This bit indicates whether the right channel

digital volume has reached its target volume.

0: The digital volume has not reached the target volume

1: The digital volume has reached the target volume

13.1.82 Register 91 (0x5B)

Figure 175. Register 91 (0x5B)

7

6

5

DTFS

R

4

3

2

1

0

Reserved

R/W

DTSR

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

130

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Table 115. Register 91 (0x5B) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DTFS

0

Reserved

6-4

Detected FS – These bits indicate the currently detected audio sampling rate.

000: Error (Out of valid range)

001: 8 kHz

010: 16 kHz

011: 32-48 kHz

100: 88.2-96 kHz

101: 176.4-192 kHz

110: 384 kHz

3-0

DTSR

R

0

Detected MCLK Ratio – These bits indicate the currently detected MCLK ratio. Note

that even if the MCLK ratio is not indicated as error, clock error might still be flagged

due to incompatible combination with the sampling rate. Specifically the MCLK ratio

must be high enough to allow enough DSP cycles for minimal audio processing when

PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz.

0000: Ratio error (The MCLK ratio is not allowed)

0001: MCLK = 32 FS

0010: MCLK = 48 FS

0011: MCLK = 64 FS

0100: MCLK = 128 FS

0101: MCLK = 192 FS

0110: MCLK = 256 FS

0111: MCLK = 384 FS

1000: MCLK = 512 FS

1001: MCLK = 768 FS

1010: MCLK = 1024 FS

1011: MCLK = 1152 FS

1100: MCLK = 1536 FS

1101: MCLK = 2048 FS

1110: MCLK = 3072 FS

131

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13.1.83 Register 92 (0x5C)

Figure 176. Register 92 (0x5C)

7

6

5

4

3

2

1

0

Reserved

R/W

DTBR

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 116. Register 92 (0x5C) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DTBR

0

Reserved

1

Detected SCLK Ratio (MSB)

13.1.84 Register 93 (0x5D)

Figure 177. Register 93 (0x5D)

7

DTBR

R

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 117. Register 93 (0x5D) Field Descriptions

Bit

Field

Type

Reset

Description

7

DTBR

R

Detected SCLK Ratio (LSB) – These bits indicate the currently detected SCLK ratio,

i.e. the number of SCLK clocks in one audio frame. Note that for extreme case of

SCLK = 1 FS (which is not usable anyway), the detected ratio will be unreliable

6-0

Reserved

R/W

0

Reserved

132

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13.1.85 Register 94 (0x5E)

Figure 178. Register 94 (0x5E)

7

6

CDST6

R

5

CDST5

R

4

CDST4

R

3

CDST3

R

2

CDST2

R

1

CDST1

R

0

CDST0

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 118. Register 94 (0x5E) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

CDST6

0

Reserved

6

Clock Detector Status – This bit indicates whether the MCLK clock is present or not.

0: MCLK is present

1: MCLK is missing (halted)

5

CDST5

R

This bit indicates whether the PLL is locked or not. The PLL will be reported as

unlocked when it is disabled.

0: PLL is locked

1: PLL is unlocked

4

3

CDST4

CDST3

R

This bit indicates whether the both LRCLK and SCLK are missing (tied low) or not.

0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing

This bit indicates whether the combination of current sampling rate and MCLK ratio is

valid for clock auto set.

0: The combination of FS/MCLK ratio is valid

1: Error (clock auto set is not possible)

2

CDST2

R

This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable

to be valid. There is a limitation with this flag, that is, when the low period of LRCLK is

less than or equal to five SCLKs, this flag will be asserted (MCLK invalid reported).

0: MCLK is valid

1: MCLK is invalid

1

0

CDST1

CDST0

R

This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and

in the range of 32-256FS to be valid.

0: SCLK is valid

1: SCLK is invalid

This bit indicated whether the audio sampling rate is valid or not. The sampling rate

must be detectable to be valid. There is a limitation with this flag, that is when this flag

is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC

recovers, this flag will be de-asserted (sampling rate invalid not reported anymore).

0: Sampling rate is valid

1: Sampling rate is invalid

133

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13.1.86 Register 95 (0x5F)

Figure 179. Register 95 (0x5F)

7

6

5

4

LTSH

R

3

2

CKMF

R

1

CSRF

R

0

CERF

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 119. Register 95 (0x5F) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

LTSH

0

Reserved

Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is

cleared when read.

0: MCLK halt has not occurred

1: MCLK halt has occurred since last read

3

2

Reserved

CKMF

R/W

R

0

Reserved

Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low).

0: LRCLK and/or SCLK is present

1: LRCLK and SCLK are missing

1

0

CSRF

CERF

R

Clock Resync Request – This bit indicates whether the clock resynchronization is in

progress.

0: Not resynchronizing

1: Clock resynchronization is in progress

Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared

when read

0: Clock error has not occurred

1: Clock error has occurred.

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13.1.87 Register 96 (0x60)

Figure 180. Register 96 (0x60)

7

6

5

4

3

PDPM

R

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 120. Register 96 (0x60) Field Descriptions

Bit

7

Field

Type

R/W

RO

Reset

Description

Reserved

PDPM

0

Reserved

6-0

PLL P Monitor – These bits indicate the actually used value for PLL divider P. The

actual value is the auto set one when clock auto set is active and register set one when

clock auto set is disabled.

0000000: P = 1

0000001: P = 2

...

1111111: P = 128

13.1.88 Register 97 (0x61)

Figure 181. Register 97 (0x61)

7

6

5

4

3

2

1

0

Reserved

R/W

PDJM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 121. Register 97 (0x61) Field Descriptions

Bit

7-6

5-0

Field

Type

R/W

R

Reset

Description

Reserved

PDJM

0

Reserved

PLL J Monitor – These bits indicate the actually used value for PLL multiplication factor

J of the overall J.D × R. The actual value is the auto set one when clock auto set is

active and register set one when clock auto set is disabled.

000000: Error

000001: J = 1

000010: J = 2

...

111111: J = 63

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13.1.89 Register 98 (0x62)

Figure 182. Register 98 (0x62)

7

6

5

PDDM

R

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 122. Register 98 (0x62) Field Descriptions

Bit

7-6

5-0

Field

Type

R/W

R

Reset

Description

Reserved

PDDM

0

Reserved

PLL D Monitor (MSB) – These bits indicate the actually used value for PLL

multiplication factor D of the overall J.D × R. The actual value is the auto set one when

clock auto set is active and register set one when clock auto set is disabled.

0 (in decimal): D=0000

1 (in decimal): D=0001

....

9999 (in decimal): D=9999

Others: Error

13.1.90 Register 99 (0x63)

Figure 183. Register 99 (0x63)

7

6

5

4

3

2

1

0

Reserved

R/W

PDDM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 123. Register 99 (0x63) Field Descriptions

Bit

7-6

5

Field

Type

R/W

R

Reset

Description

Reserved

PDDM

0

Reserved

PLL D Monitor (LSB) – These bits indicate the actually used value for PLL

multiplication factor D of the overall J.D × R. The actual value is the auto set one when

clock auto set is active and register set one when clock auto set is disabled.

0 (in decimal): D=0000

1 (in decimal): D=0001

....

9999 (in decimal): D=9999

Others: Error

136

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13.1.91 Register 100 (0x64)

Figure 184. Register 100 (0x64)

7

6

5

4

3

2

1

0

Reserved

R/W

PDRM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 124. Register 100 (0x64)Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

R

Reset

Description

Reserved

PDRM

0

Reserved

PLL R Monitor – These bits indicate the actually used value for PLL multiplication factor

R of the overall J.D × R. The actual value is the auto set one when clock auto set is

active and register set one when clock auto set is disabled.

0000: R = 1

0001: R = 2

...

1111: R = 16

13.1.92 Register 101 (0x65)

Figure 185. Register 101 (0x65)

7

6

5

4

3

DDSM

R

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 125. Register 101 (0x65) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DDSM

0

Reserved

6-0

DSP clock divider monitor – These bits indicate the actually used value of the DSP

clock divider ratio. The actual value is the auto set one when clock auto set is active

and register set one when clock auto set is disabled.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.93 Register 102 (0x66)

Figure 186. Register 102 (0x66)

7

6

5

4

3

DDAM

R

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 126. Register 102 (0x66) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DDAM

0

Reserved

6-0

DAC clock divider monitor – These bits indicate the actually used value of the DAC

clock divider ratio. The actual value is the auto set one when clock auto set is active

and register set one when clock auto set is disabled.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.94 Register 103 (0x67)

Figure 187. Register 103 (0x67)

7

6

5

4

3

DCPM

R

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 127. Register 103 (0x67) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DCPM

0

Reserved

6-0

NCP clock divider monitor – These bits indicate the actually used value of the CP clock

divider ratio. The actual value is the auto set one when clock auto set is active and

register set one when clock auto set is disabled.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.95 Register 104 (0x68)

Figure 188. Register 104 (0x68)

7

6

5

4

3

DOSM

R

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 128. Register 104 (0x68) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DOSM

0

Reserved

6-0

OSR clock divider monitor – These bits indicate the actually used value of the OSR

clock divider ratio. The actual value is the auto set one when clock auto set is active

and register set one when clock auto set is disabled.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

13.1.96 Register 105 (0x69)

138

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ZHCSFY4 –DECEMBER 2016

Figure 189. Register 105 (0x69)

7

6

5

4

PENM

R

3

2

PRFM

R

1

0

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 129. Register 105 (0x69) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

PENM

Reserved

PLL enable monitor – This bit indicates whether the PLL is currently enabled.

0: PLL is disabled

1: PLL is enabled

3

Reserved

PRFM

R/W

R

Reserved

2-0

PLL Reference Monitor – These bits indicate the actual source for the PLL. The source

is auto set when clock auto set is active and register set when clock auto set is

disabled.

000: MCLK

001: SCLK

010: OSC

011: GPIO

Others: Reserved (mute)

13.1.97 Register 106 (0x6A)

Figure 190. Register 106 (0x6A)

7

CPPM

R

6

RFPM

R

5

LDPM

R

4

LBPM

R

3

LCPM

R

2

LOPM

R

1

ROPM

R

0

DAPM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 130. Register 106 (0x6A) Field Descriptions

Bit

Field

Type

Reset

Description

7

CPPM

R

CP PWRDN monitor – This bit is a monitor for CP powerdown status.

0: Powered down

1: Active

6

5

4

3

RFPM

LDPM

LBPM

LCPM

R

REF PWRDN monitor – This bit is a monitor for analog reference powerdown status.

0: Powered down

1: Active

Line Driver PWRDN monitor – This bit is a monitor for line driver powerdown status.

0: Powered down

1: Active

Line Bias PWRDN monitor – This bit is a monitor for line bias powerdown status.

0: Powered down

1: Active

Line CMFB2 PWRDN monitor – This bit is a monitor for line common feedback

powerdown status.

0: Powered down

1: Active

2

LOPM

R

L Output Stage PWRDN monitor – This bit is a monitor for left channel output stage

powerdown status.

0: Powered down

1: Active

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Table 130. Register 106 (0x6A) Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

ROPM

R

R Output Stage PWRDN monitor – This bit is a monitor for right channel output stage

powerdown status..

0: Powered down

1: Active

0

DAPM

R

DAC PWRDN monitor – This bit is a monitor for DAC powerdown status.

0: Powered down

1: Active

140

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13.1.98 Register 107 (0x6B)

Figure 191. Register 107 (0x6B)

7

OFPM

R

6

SSPM

R

5

ISPM

R

4

IWPM

R

3

LSPM

R

2

RSPM

R

1

DSRM

R

0

DERM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 131. Register 107 (0x6B) Field Descriptions

Bit

Field

Type

Reset

Description

7

OFPM

R

OFSCOMP PWRDN monitor – This bit is a monitor for offset compensator powerdown

status.

0: Powered down

1: Active

6

5

4

3

2

SSPM

ISPM

R

Short Protection PWRDN monitor – This bit is a monitor for short protector powerdown

status.

0: Powered down

1: Active

IMP sense PWRDN monitor – This bit is a monitor for impedance sensor powerdown

status.

0: Powered down

1: Active

IWPM

LSPM

RSPM

IMP whole PWRDN monitor – This bit is a monitor for whole impedance sensor circuitry

powerdown status.

0: Powered down

1: Active

L Short Protection RST monitor – This bit is a monitor for left channel short protector

reset status.

0: Reset

1: Active

R Short Protection RST monitor – This bit is a monitor for right channel short protector

reset status.

0: Reset

1: Active

1

0

DSRM

DERM

R

DSM RST monitor – This bit is a monitor for DAC modulator reset status.

0: Reset

1: Active

DEM RST monitor – This bit is a monitor for DAC DEM reset status.

0: Reset

1: Active

141

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13.1.99 Register 108 (0x6C)

Figure 192. Register 108 (0x6C)

7

6

5

ADLM

R

4

ADRM

R

3

2

1

AMLM

R

0

AMRM

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 132. Register 108 (0x6C) Field Descriptions

Bit

7-6

5

Field

Type

R/W

R

Reset

Description

Reserved

ADLM

0

Reserved

AMUTE dummy left monitor – This bit is a monitor for left channel dummy output

analog mute status.

0: Mute

1: Unmute

4

ADRM

R

AMUTE dummy right monitor – This bit is a monitor for right channel dummy output

analog mute status.

0: Mute

1: Unmute

3-2

1

Reserved

AMLM

R/W

R

0

Reserved

Left Analog Mute Monitor – This bit is a monitor for left channel analog mute status.

0: Mute

1: Unmute

0

AMRM

R

Right Analog Mute Monitor – This bit is a monitor for right channel analog mute status.

0: Mute

1: Unmute

13.1.100 Register 109 (0x6D)

Figure 193. Register 109 (0x6D)

7

6

5

4

SDTM

R

3

2

1

0

SHTM

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 133. Register 109 (0x6D) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

SDTM

0

Reserved

Short detect monitor – This bit indicates whether line output short is occuring.

0: Normal (No short)

1: Line output is being shorted

3-1

0

Reserved

SHTM

R/W

R

0

Reserved

Short detected monitor – This bit indicates whether line output short has occurred since

last read. This bit is sticky and is cleared when read.

0: No short

1: Line output short occurred

142

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13.1.101 Register 110 (0x6E)

Figure 194. Register 110 (0x6E)

7

6

5

4

3

2

1

0

DLCM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 134. Register 110 (0x6E) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLCM

R

Left DIFF control monitor – These bits indicate the final control value of the left channel

differential offset compensator. The value approximates the magnitude of the original

offset before calibration.

0000000: 0 mV

0000001: 0.25 mV

0000010: 0.50 mV

0000011: 0.75 mV

…

1111111: 63.75 mV

13.1.102 Register 111 (0x6F)

Figure 195. Register 111 (0x6F)

7

6

5

4

3

2

1

0

DRCM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 135. Register 111 (0x6F) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRCM

R

Right DIFF control monitor – These bits indicate the final control value of the right

channel differential offset compensator. The value approximates the magnitude of the

original offset before calibration.

0000000: 0 mV

0000001: 0.25 mV

0000010: 0.50 mV

0000011: 0.75 mV

…

1111111: 63.75 mV

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13.1.103 Register 112 (0x70)

Figure 196. Register 112 (0x70)

7

DLCS

R

6

5

4

3

2

CLCM

R

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 136. Register 112 (0x70) Field Descriptions

Bit

Field

Type

Reset

Description

7

DLCS

R

Left DIFF control sign – This bit indicates the polarity of DC offset at left channel before

calibration (the magnitude is indicated in R0/P110).

0: Negative

1: Positive

6-5

4-0

Reserved

CLCM

R/W

R

0

Reserved

Left CMFB control monitor – These bits indicate the final control value of the left

channel common feedback offset compensator. The value approximates the magnitude

of the original offset before calibration.

00000: 0 mV

00001: 0.25 mV

00010: 0.50 mV

…

11111: 7.75 mV

13.1.104 Register 113 (0x71)

Figure 197. Register 113 (0x71)

7

DRCS

R

6

5

4

3

2

CRCM

R

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 137. Register 113 (0x71) Field Descriptions

Bit

Field

Type

Reset

Description

7

DRCS

R

Right DIFF control sign – This bit indicates the polarity of DC offset at right channel

before calibration (the magnitude is indicated in R0-P111)

0: Negative

1: Positive

6-5

4-0

Reserved

CRCM

R/W

R

0

Reserved

Right CMFB control monitor – These bits indicate the final control value of the right

channel common feedback offset compensator. The value approximates the magnitude

of the original offset before calibration.

00000: 0 mV

00001: 0.25 mV

00010: 0.50 mV

…

11111: 7.75 mV

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13.1.105 Register 114 (0x72)

Figure 198. Register 114 (0x72)

7

6

5

4

3

2

1

0

Reserved

R/W

MTST

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 138. Register 114 (0x72) Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

R

Reset

Description

Reserved

MTST

0

Reserved

MUTE status – These bits indicate the output of the XSMUTE level decoder for

monitoring purpose.

11: 0.7 VDD ≤ XSMUTE

01: 0.3 VDD ≤ XSMUTE < 0.7 VDD

00: 0.3 VDD > XSMUTE

13.1.106 Register 115 (0x73)

Figure 199. Register 115 (0x73)

7

6

5

4

3

2

1

FSMM

R

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 139. Register 115 (0x73) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

R

Reset

Description

Reserved

FSMM

0

Reserved

FS Speed Mode Monitor – These bits indicate the actual FS operation mode being

used. The actual value is the auto set one when clock auto set is active and register

set one when clock auto set is disabled.

In Auto set,

000: error

001: 8 kHz

010: 16 kHz

011: 32-48 kHz

100: 88.2-96 kHz

101: 176.4-192 kHz

110: 384 kHz

111: reserved

In register set mode,

000: reserved

001: 8 kHz

010: 16 kHz

011: 48 kHz

100: 88.2-96 kHz

101: 176.4-192 kHz

110: 384 kHz

111: 32 kHz

145

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13.1.107 Register 118 (0x76)

Figure 200. Register 118 (0x76)

7

BOTM

R

6

5

4

3

2

1

0

Reserved

R/W

PSTM

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 140. Register 118 (0x76) Field Descriptions

Bit

Field

Type

Reset

Description

7

BOTM

R

DSP Boot Done Flag – This bit indicates whether the DSP boot is completed.

0: DSP is booting

1: DSP boot completed

6-4

3-0

Reserved

PSTM

R/W

R

Reserved

Power State – These bits indicate the current power state of the DAC.

000: Powerdown

0001: Wait for CP voltage valid

0010: Common feedback offset calibration

0011: Differential mode offset calibration

0100: Volume ramp up

0101: Run (Playing)

0110: Line output short and Low impedance

0111: Volume ramp down

1000: Standby

13.1.108 Register 119 (0x77)

Figure 201. Register 119 (0x77)

7

6

5

GPIN2

R

4

MUTE

R

3

GPIN0

R

2

Reserved

R

1

Reserved

R

0

Reserved

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 141. Register 119 (0x77) Field Descriptions

Bit

7-6

5

Field

Type

R/W

RO

Reset

Description

Reserved

GPIN2

0

Reserved

GPIO Input States – This bit indicates the logic level at GPIO2 pin.

0: Low

1: High

4

3

2

1

0

MUTE

GPIN0

RO

This bit indicates the logic level at MUTE pin.

0: Low

1: High

This bit indicates the logic level at GPIO0 pin.

0: Low

1: High

N/A

0: Low

1: High

N/A

0: Low

1: High

N/A

0: Low

1: High

146

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13.1.109 Register 120 (0x78)

Figure 202. Register 120 (0x78)

7

6

5

4

AMFL

R

3

2

1

0

AMFR

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 142. Register 120 (0x78) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

AMFL

0

Reserved

Auto Mute Flag for Left Channel – This bit indicates the auto mute status for left

channel.

0: Not auto muted

1: Auto muted

3-1

0

Reserved

AMFR

R/W

R

0

Reserved

Auto Mute Flag for Right Channel – This bit indicates the auto mute status for right

channel.

0: Not auto muted

1: Auto muted

147

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13.1.110 Register 121 (0x79)

Figure 203. Register 121 (0x79)

7

6

5

4

3

2

1

0

Reserved

R/W

DWAO

R/W

Reserved

R/W

DAMD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 143. Register 121 (0x79) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

DWAO

0

Reserved

DWA off – This bit controls the DWA rotation.

0: DWA is active (Rotation active)

1: DWA is disabled (No rotation)

3-2

1-0

Reserved

DAMD

R/W

0

Reserved

DAC Mode – This bit controls the DAC mode.

0: Mode1

1: Mode2

** INTERNAL ** (Mode1: Cascaded Galton,

Mode2: Cascaded DWA)

10: Non-cascaded Galton

11: Non-cascaded DWA

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13.2 Registers - Page 1

13.2.1 Register 1 (0x01)

Figure 204. Register 1 (0x01)

7

6

5

4

3

2

1

0

Reserved

R/W

REXT

R/W

Reserved

R/W

OSEL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 144. Register 1 (0x01) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

REF BG Ext - This bit controls what is output from the VCOM pin

0: AVDD divided voltage

1: Bandgap reference voltage

4

REXT

R/W

0

3-1

Reserved

Output Amplitude Type - This bit selects the output amplitude type. The clock autoset

feature will not work with PLL enabled in VCOM mode.

In this case this feature has to be disabled via P0-R37 and the clock dividers must be

set manually.

0

OSEL

R/W

0

0: VREF mode (Constant output amplitude against AVDD variation)

1: VCOM mode (Output amplitude is proportional to AVDD variation)

13.2.2 Register 2 (0x02)

Figure 205. Register 2 (0x02)

7

6

5

4

3

2

1

0

Reserved

R/W

LAGN

R/W

Reserved

R/W

RAGN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 145. Register 2 (0x02) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Analog Gain Control for Left Channel - This bit controls the left channel analog gain.

4

3-1

0

LAGN

R/W

0

0: 0 dB

1: -6 dB

Reserved

RAGN

Reserved

Analog Gain Control for Right Channel - This bit controls the right channel analog gain.

0: 0 dB

1: -6 dB

149

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13.2.3 Register 3 (0x03)

Figure 206. Register 3 (0x03)

7

6

5

4

3

2

1

0

Reserved

R/W

CPDY

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 146. Register 3 (0x03) Field Descriptions

Bit

Field

Type

Reset

Description

7-3

Reserved

R/W

0

Reserved

CP Delay -These bits control the delay of charge pump clock.

000: 65 ns

001: 90 ns

010: 115 ns

011: 140 ns

100: 165 ns

101: 190 ns

110: 215 ns

111: 240 ns

2-0

CPDY

R/W

0

13.2.4 Register 4 (0x04)

Figure 207. Register 4 (0x04)

7

6

5

4

3

2

1

0

Reserved

R/W

OPWR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 147. Register 4 (0x04) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

0

Reserved

Output Power - These bits control the power of output driver.

00: Normal power

1-0

OPWR

R/W

1

01: Increased power

10: More increased power

11: Maximum power

150

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13.2.5 Register 5 (0x05)

Figure 208. Register 5 (0x05)

7

6

5

4

3

2

1

0

Reserved

R/W

UEPD

R/W

UIPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 148. Register 5 (0x05) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

0

Reserved

External UVP Control - This bit enables or disables detection of power supply drop via

XSMUTE pin (External Under Voltage Protection).

0: Enabled

1: Disabled

1

0

UEPD

UIPD

R/W

0

Internal UVP Control - This bit enables or disables internal detection of AVDD voltage

drop (Internal Under Voltage Protection).

0: Enabled

1: Disabled

13.2.6 Register 6 (0x06)

Figure 209. Register 6 (0x06)

7

6

5

4

3

2

1

0

Reserved

R/W

AMCT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 149. Register 6 (0x06) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

Analog Mute Control -This bit enables or disables analog mute following digital mute.

0

AMCT

R/W

1

0: Disabled

1: Enabled

151

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13.2.7 Register 7 (0x07)

Figure 210. Register 7 (0x07)

7

6

5

4

3

2

1

0

Reserved

R/W

AGBL

R/W

Reserved

R/W

AGBR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 150. Register 7 (0x07) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Analog +10% Gain for Left Channel - This bit enables or disables amplitude boost

mode for left channel.

0: Normal amplitude

4

3-1

0

AGBL

R/W

0

1

1: +10% (+0.8 dB) boosted amplitude

Reserved

AGBR

Reserved

Analog +10% Gain for Right Channel - This bit enables or disables amplitude boost

mode for right channel.

0: Normal amplitude

1: +10% (+0.8 dB) boosted amplitude

13.2.8 Register 8 (0x08)

Figure 211. Register 8 (0x08)

7

6

5

4

3

2

1

0

Reserved

R/W

RBGF

R/W

Reserved

R/W

RCMF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 151. Register 8 (0x08) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

REF BG Fast - This bit controls the bandgap voltage ramp up speed.

0: Normal ramp up, ~50 ms with external capacitance = 1 µF

1: Fast ramp up, ~1 ms with external capacitance = 1 µF

4

3-1

0

RBGF

R/W

0

1

Reserved

RCMF

Reserved

VCOM Reference Ramp Up - This bit controls the VCOM voltage ramp up speed.

0: Normal ramp up, ~600 ms with external capacitance = 1 µF

1: Fast ramp up, ~3 ms with external capacitance = 1 µF

152

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13.2.9 Register 9 (0x09)

Figure 212. Register 9 (0x09)

7

6

5

4

3

2

1

0

Reserved

R/W

DEME

R/W

VCPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 152. Register 9 (0x09) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

0

Reserved

VCOM Pin as De-emphasis Control - This bit controls whether to use the

DEEMP/VCOM pin as De-emphasis control.

0: Disabled (DEEMP/VCOM is not used to control De-emphasis)

1: Enabled (DEEMP/VCOM is used to control De-emphasis)

1

0

DEME

VCPD

R/W

0

1

Power down control for VCOM - This bit controls VCOM powerdown switch.

0: VCOM is powered on

1: VCOM is powered down

13.2.10 Register 10 (0x0A)

Figure 213. Register 10 (0x0A)

7

6

5

4

3

2

1

0

Reserved

R/W

LBBG

R/W

Reserved

R/W

LBVC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 153. Register 10 (0x0A) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

0

Reserved

Line 1st stage bias ctrl<1> at BG mode - Applied when LSB of 0x01 at Page1=0

5-4

3-2

1-0

LBBG

R/W

1

0

1

0: low

1: high

Reserved

LBVC

Reserved

Line 1st stage bias ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1

0: low

1: high

153

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13.2.11 Register 11 (0x0B)

Figure 214. Register 11 (0x0B)

7

6

5

4

3

2

1

0

Reserved

R/W

CBBG

R/W

Reserved

R/W

CBVC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 154. Register 11 (0x0B) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

0

Reserved

CMFB bias ctrl<1> at BG mode - Applied when LSB of 0x01 at Page1=0

5-4

3-2

1-0

CBBG

R/W

1

0

0: low

1: high

Reserved

CBVC

Reserved

CMFB bias ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1

0: low

1: high

13.2.12 Register 12 (0x0C)

Figure 215. Register 12 (0x0C)

7

6

5

4

3

2

1

0

Reserved

R/W

SSBG

R/W

Reserved

R/W

SSVC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 155. Register 12 (0x0C) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

0

Reserved

Short protection sink ref current ctrl<1> at BG mode - Applied when LSB of 0x01at

Page1=0

0: low

1: high

5-4

3-2

1-0

SSBG

R/W

0

Reserved

SSVC

Reserved

Short protection sink ref current ctrl<1> at COM mode - Applied when LSB of 0x01 at

Page1=1

0: low

1: high

154

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13.2.13 Register 13 (0x0D)

Figure 216. Register 13 (0x0D)

7

6

5

4

3

2

1

0

Reserved

R/W

SRBG

R/W

SRVC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 156. Register 13 (0x0D) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

0

Reserved

Short protection source ref current ctrl<1> at BG mode - Applied when LSB of 0x01 at

Page1=0

0: low

1: high

SRBG

SRVC

4-2

1

R/W

1

0

1

Short protection source ref current ctrl<1> at COM mode - Applied when LSB of 0x01

at Page1=1

0: low

0

1: high

13.2.14 Register 14 (0x0E)

Figure 217. Register 14 (0x0E)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 157. Register 14 (0x0E) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.2.15 Register 15 (0x0F)

Figure 218. Register 15 (0x0F)

7

6

5

4

3

2

1

0

Reserved

R/W

CPCP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 158. Register 15 (0x0F) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

NCP clock digital delay control - This bit controls the CP clock phase delay against the

DAC clock.

0: 0 degree (no delay)

1: 180 degree delay

0

CPCP

R/W

1

155

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13.3 Registers - Page 253

13.3.1 Register 1 (0x01)

Figure 219. Register 1 (0x01)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 159. Register 1 (0x01) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.2 Register 2 (0x02)

Figure 220. Register 2 (0x02)

7

6

5

4

3

2

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 160. Register 2 (0x02) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.3 Register 3 (0x03)

Figure 221. Register 3 (0x03)

7

6

5

4

3

2

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 161. Register 3 (0x03 Field Descriptions)

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.4 Register 4 (0x04)

Figure 222. Register 4 (0x04)

7

6

5

4

3

2

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 162. Register 4 (0x04) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

156

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ZHCSFY4 –DECEMBER 2016

13.3.5 Register 5 (0x05)

Figure 223. Register 5 (0x05)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 163. Register 5 (0x05) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.6 Register 6 (0x06)

Figure 224. Register 6 (0x06)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 164. Register 6 (0x06) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.7 Register 7 (0x07)

Figure 225. Register 7 (0x07)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 165. Register 7 (0x07) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.8 Register 8 (0x08)

Figure 226. Register 8 (0x08)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 166. Register 8 (0x8) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

157

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13.3.9 Register 9 (0x09)

Figure 227. Register 9 (0x09)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 167. Register 9 (0x9) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.10 Register 10 (0x0A)

Figure 228. Register 10 (0x0A)

7

6

5

4

3

2

1

0

DRSV

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 168. Register 10 (0xA) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Dither Reserved - Performance adjustment dither setting when "RESERVED" bond

option is selected

DRSV

0

6-0

Reserved

13.3.11 Register 11 (0x0B)

Figure 229. Register 11 (0x0B)

7

6

5

4

3

2

1

0

D100

R/W

Reserved

R/W

OFSCAL0

R/W

OFSCAL1

R/W

OFSCAL2

R/W

OFSCAL3

R/W

OFSCAL4

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 169. Register 11 (0xB) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Dither Reserved - Performance adjustment dither setting when "RESERVED" bond

option is selected

D100

0

6-5

Reserved

Ofscal Bypass Filter - Select whether to bypass the front-end filter.

0: Front-end filter used.

4

OFSCAL0

R/W

0

1: Front-end filter bypassed.

Ofscal Full Span - Select whether to activate front-end filter half period (good for

majority type) or full period (good for averaging type).

0: Front-end filter is active last half of control period.

3

OFSCAL1

R/W

0

1: Front-end filter is active the whole control period.

Ofscal Average Filtering - Select the type of front-end filter.

0: Front-end filter is majority decision type

1: Front-end filter is averaging type

2

1

OFSCAL2

OFSCAL3

R/W

0

Ofscal Disable Fine Calibration - Select whether to do fine calibration.

0: Do 64-step coarse calibration followed by 32-step fine calibration.

1: Do 96-step coarse calibration only (no fine calibration).

Ofscal Disable Post Averaging - Select whether to use post-averaging on the integrator

output.

0: Final calibration control source is post-averaging result.

1: Final calibration control source is integrator output.

0

OFSCAL4

R/W

0

158

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13.3.12 Register 12 (0x0C)

Figure 230. Register 12 (0x0C)

7

6

5

4

3

2

1

0

D105

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 170. Register 12 (0x0C) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Dither 105 dB - Performance adjustment dither setting when "105dB" bond option is

selected

D105

0

6-0

Reserved

13.3.13 Register 13 (0x0D)

Figure 231. Register 13 (0x0D)

7

6

5

4

3

2

1

0

D110

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 171. Register 13 (0x0D) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Dither 115 dB - Performance adjustment dither setting when "110dB" bond option is

selected

D110

0

6-0

Reserved

159

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13.3.14 Register 14 (0x0E)

Figure 232. Register 14 (0x0E)

7

6

5

4

3

2

1

0

Reserved

R/W

SUMD

R/W

Reserved

R/W

SUAS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 172. Register 14 (0x0E) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

SUMD

0

Reserved

SpeedUp CLK missing detection

Reserved

3-1

0

Reserved

SUAS

SpeedUp Analog Sequence

13.3.15 Register 15 (0x0F)

Figure 233. Register 15 (0x0F)

7

6

5

4

3

2

1

0

Reserved

R/W

SDEN

R/W

Reserved

R/W

DSOC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 173. Register 15 (0x0F) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Short Detection Enable

0: Short detection enable

1: Short detection disable

4

SDEN

R/W

1

3-1

0

Reserved

DSOC

R/W

0

Reserved

Disable Subsequent Offset Cancellation

160

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13.3.16 Register 16 (0x10)

Figure 234. Register 16 (0x10)

7

6

5

4

3

2

1

0

Reserved

R/W

SWDA

R/W

Reserved

R/W

DPOL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 174. Register 16 (0x10) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

0

Reserved

Shuffle DWA of Galton - Shuffle DWA Outputs of Galton DEM

0,3: No shuffle

5

R/W

1

SDWA

1: Shuffle Internally

2: Global Shuffle

4

3-1

0

Reserved

DPOL

Reserved

Select DC dither polarity for the secandary DAC. Select DC dither polarity +4.0% or

-4.0% for the secondary DAC.

R/W

13.3.17 Register 17 (0x11)

Figure 235. Register 17 (0x11)

7

6

5

4

3

2

1

0

DLSC

R/W

Reserved

R/W

DRSC

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 175. Register 17 (0x11) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

DLSC

0

Left DAC Primary/Secondary Scale - Secondary to Primary scaling factor for left DAC

6-4

3

Reserved

DRSC

Reserved

Right DAC Primary/Secondary Scale - See DAC digital design spec

Reserved

2-0

Reserved

161

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13.3.18 Register 18 (0x12)

Figure 236. Register 18 (0x12)

7

6

5

4

3

2

1

0

LPA0

R/W

LPB1

R/W

LPB2

R/W

LPB3

R/W

RPA0

R/W

RPB1

R/W

RPB2

R/W

RPB3

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 176. Register 18 (0x12) Field Descriptions

Bit

Field

Type

Reset

Description

Left DAC primary a0 zero - Left DAC primary modulator coeff tweaks.

7

LPA0

R/W

0

0: normal

1: zero

Left DAC primary b1 zero

0: normal

1: zero

6

5

4

3

2

1

0

LPB1

LPB2

LPB3

RPA0

RPB1

RPB2

RPB3

R/W

0

Left DAC primary b2 zero

0: normal

1: zero

Left DAC primary b3 zero

0: normal

1: zero

Right DAC primary a0 zero - Right DAC primary modulator coeff tweaks

0: normal

1: zero

Right DAC primary b1 zero

0: normal

1: zero

Right DAC primary b2 zero

0: normal

1: zero

Right DAC primary b3 zero

0: normal

1: zero

162

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13.3.19 Register 19 (0x13)

Figure 237. Register 19 (0x13)

7

6

5

4

3

2

1

0

LPG1

R/W

Reserved

R/W

LPUB

R/W

Reserved

R/W

RPG1

R/W

Reserved

R/W

RPUB

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 177. Register 19 (0x13) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

LPG1

0

Left DAC primary g1 gain. Left DAC primary local loop gain

6

Reserved

LPUB

Reserved

5

Left DAC primary upper bits. Number of left DAC primary upper bits

4

Reserved

RPG1

Reserved

3

Right DAC primary g1 gain. Right DAC primary local loop gain

2

Reserved

RPUB

Reserved

1

Right DAC primary upper bits. Number of right DAC primary upper bits

Reserved

0

Reserved

163

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13.3.20 Register 20 (0x14)

Figure 238. Register 20 (0x14)

7

6

5

4

3

2

1

0

LSA0

R/W

LSB1

R/W

LSB2

R/W

LSB3

R/W

RSA0

R/W

RSB1

R/W

RSB2

R/W

RSB3

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 178. Register 20 (0x14) Field Descriptions

Bit

Field

Type

Reset

Description

Left DAC secondary a0 zero. Left DAC secondary modulator coeff tweaks.

7

LSA0

R/W

0

0: normal

1: zero

Left DAC secondary b1 zero

0: normal

1: zero

6

5

4

3

2

1

0

LSB1

LSB2

LSB3

RSA0

RSB1

RSB2

RSB3

R/W

0

Left DAC secondary b2 zero

0: normal

1: zero

Left DAC secondary b3 zero

0: normal

1: zero

Right DAC secondary a0 zero. Right DAC seconday modulator coeff tweaks.

0: normal

1: zero

Right DAC secondary b1 zero

0: normal

1: zero

Right DAC secondary b2 zero

0: normal

1: zero

Right DAC secondary b3 zero

0: normal

1: zero

164

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13.3.21 Register 21 (0x15)

Figure 239. Register 21 (0x15)

7

6

5

4

3

2

1

0

LSG1

R/W

Reserved

R/W

LSUB

R/W

Reserved

R/W

RSG1

R/W

Reserved

R/W

RSUB

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 179. Register 21 (0x15) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

LSG1

0

Left DAC secondary g1 gain. Left DAC secondary local loop gain

6

Reserved

LSUB

Reserved

5

Left DAC secondary upper bits. Number of left DAC secondary upper bits

4

Reserved

RSG1

Reserved

3

Right DAC secondary g1 gain. Right DAC secondary local loop gain

Reserved

2

Reserved

RSUB

1

Right DAC secondary upper bits. Number of right DAC secondary upper bits

Reserved

0

Reserved

13.3.22 Register 2 (0x16)

Figure 240. Register 22 (0x16)

7

6

5

4

3

2

1

0

Reserved

R/W

CPHY

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 180. Register 22 (0x16) Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

Reset

Description

Reserved

CPHY

0

1

Reserved

CP Hysterisis - Hysterisis control of VNEG Detector

13.3.23 Register 23 (0x17)

Figure 241. Register 23 (0x17)

7

6

5

4

3

2

1

0

Reserved

R/W

CPHY

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 181. Register 23 (0x17) Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

Reset

Description

Reserved

CPHY

0

1

Reserved

CP Hysterisis - Hysterisis control of VNEG Detector

165

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13.3.24 Register 24 (0x18)

Figure 242. Register 24 (0x18)

7

6

5

4

3

2

1

0

Reserved

R/W

OT33

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 182. Register 24 (0x18) Field Descriptions

Bit

7-3

2

Field

Type

R/W

Reset

Description

Reserved

0

1

0

Reserved

1

OT33

Bias current trimming for internal 3.3V oscillator. Bias current 00-111: ?-?uA

0

13.3.25 Register 25 (0x19)

Figure 243. Register 25 (0x19)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 183. Register 25 (0x19) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.26 Register 26 (0x1A)

Figure 244. Register 26 (0x1A)

7

6

5

4

3

2

1

0

RBTR

R/W

RCTR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 184. Register 26 (0x1A) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

0

1

0

6

RBTR

RCTR

REF BTrim. Trimming of bandgap reference voltage.

REF CTrim. Trimming of common voltage dividing AVDD.

5

4

3-0

166

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ZHCSFY4 –DECEMBER 2016

13.3.27 Register 27 (0x1B)

Figure 245. Register 27 (0x1B)

7

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 185. Register 27 (0x1B) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.28 Register 28 (0x1C)

Figure 246. Register 28 (0x1C)

7

6

5

4

3

2

1

0

Reserved

R/W

PLLR

R/W

Reserved

R/W

PTST

R/W

PVC1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 186. Register 28 (0x1C) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

PLL RST - Reset counter of all divider.

0: Reset

1: Normal operation

4

3-2

1

PLLR

R/W

1

0

Reserved

PTST

Reserved

PLL IREF TEST. IREF test mode enable/disable.

0: normal

1: test mode

PLL VCIC.

0

PVCI

R/W

0

0: Normal operation

1: Brings higher free-running frequency

13.3.29 Register 29 (0x1D)

Figure 247. Register 29 (0x1D)

7

6

5

4

3

2

1

0

PLL IREF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 187. Register 29 (0x1D) Field Descriptions

Bit

Field

Type

Reset

Description

Reference current control on test-mode.

00000000-11111111: ?? -??A

7-0

PLL IREF

R/W

0

167

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13.3.30 Register 30 (0x1E)

Figure 248. Register 30 (0x1E)

7

6

5

4

3

2

1

0

Reserved

R/W

PLLT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 188. Register 30 (0x1E) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

PLL TEST - Power up/down control for PFD in PLL at test mode.

0

PLLT

R/W

0

0: Power up

1: Power down

13.3.31 Register 31 (0x1F)

Figure 249. Register 31 (0x1F)

7

6

5

4

3

2

1

0

Reserved

R/W

LSFG

R/W

Reserved

R/W

LSPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 189. Register 31 (0x1F) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

LDO_SCPZ - LDO short flag.

0: Short state

1: Not short state

4

3-1

0

LSFG

R/W

0

Reserved

LSPD

Reserved

LDO SCPD - LDO power down behavior at short condition.

0: LDO is automatically power down if short state detects

1: Disable

168

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13.3.32 Register 32 (0x20)

Figure 250. Register 32 (0x20)

7

6

5

4

3

2

1

0

Reserved

R/W

UTM1

R/W

UTM2

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 190. Register 32 (0x20) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

0

Reserved

UVP TEST mode 1 - Change external threshold voltage.

0: VH=0.7xDVDD, VL=0.3xDVDD

1: VH=0.67xDVDD, VL=0.33xDVDD

1

0

UTM1

UTM2

R/W

UVP TEST mode 2 - Change reference source for internal AVDD detection.

0: Divided LDO_1p8 by resistor

0

1: Bandgap reference of UVP

13.3.33 Register 33 (0x21)

Figure 251. Register 33 (0x21)

7

6

5

4

3

2

1

0

Reserved

R/W

TST1

R/W

TST2

R/W

TST3

R/W

TST4

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 191. Register 33 (0x21) Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

0

Reserved

Analog test mode 1 - Line first stage load ctrl <0>

3

2

1

TST1

TST2

TST3

R/W

0

1

0: Disable

1: Enable

Analog test mode 2 - Line first stage load ctrl <1>0: Disable

1: Enable

Analog test mode 3 - Line slew rate ctrl <0>

0: Disable

1: Enable

Analog test mode 4 - Line slew rate ctrl <1>

0

TST4

R/W

1

0: Disable

1: Enable

169

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13.3.34 Register 34 (0x22)

Figure 252. Register 34 (0x22)

7

6

5

4

3

2

1

0

Reserved

R/W

RFPO

R/W

DLPO

R/W

LLPO

R/W

BLPO

R/W

CLPO

R/W

OLPO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 192. Register 34 (0x22) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

0

Reserved

REF PWRDN override. Power up/down control for whole bias current.

5

4

3

2

1

RFPO

DLPO

LLPO

BLPO

CLPO

R/W

0

0: normal

1: override

Lch DAC PWRDN override. Power up/down control for Lch current DAC.

0: normal

1: override

Lch Line Driver PWRDN override. Power up/down control for Lch line driver

0: normal

1: override

Lch Line Bias PWRDN override. Power up/down control for bais block of Lch line driver

0: normal

1: override

Lch Line CMFB2 PWRDN override. Power up/down control for CMFB of Lch line driver

0: normal

1: override

Lch Output Stage PWRDN override. Power up/down control for output stage of Lch line

driver

0: normal

1: override

0

OLPO

R/W

0

170

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ZHCSFY4 –DECEMBER 2016

13.3.35 Register 35 (0x23)

Figure 253. Register 35 (0x23)

7

6

5

4

3

2

1

0

GLPO

R/W

ALPO

R/W

ULPO

R/W

CPPO

R/W

FLPO

R/W

SLPO

R/W

ILPO

R/W

WLPO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 193. Register 35 (0x23) Field Descriptions

Bit

Field

Type

Reset

Description

Lch Gain control PWRDN override. Power up/down control for Lch gain control

7

GLPO

R/W

0

0: normal

1: override

Lch AMUTE override. Lch Analog Mute control.

6

5

4

ALPO

ULPO

CPPO

R/W

0

0: normal

1: override

Lch AMUTE dummy override. Lch Analog Mute control.

0: normal

1: override

CP PWRDN override. Power up/down control for negative charge pump.

0: normal

1: override

Lch OFSCOMP PWRDN override. Power up/down control for offset calibration block for

Lch line driver.

0: normal

1: override

3

2

1

0

FLPO

SLPO

ILPO

R/W

0

Lch Short Protection PWRDN override. Power up/down control for short protection of

Lch line driver.

0: normal

1: override

Lch IMP sense PWRDN override. Power up/down control for impedance sensing circuit

of Lch line driver.

0: normal

1: override

Lch IMP whole PWRDN override. Power up/down control for impedance sensing circuit

of Lch line driver at whole analog power down.

0: normal

WLPO

1: override

171

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13.3.36 Register 36 (0x24)

Figure 254. Register 36 (0x24)

7

6

5

4

3

2

1

0

Reserved

R/W

RFPS

R/W

DLPS

R/W

LLPS

R/W

BLPS

R/W

CLPS

R/W

OLPS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 194. Register 36 (0x24) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

0

Reserved

REF PWRDN state. Power up/down control for whole bias current.

5

4

3

2

1

RFPS

DLPS

LLPS

BLPS

CLPS

R/W

0

0: Power down

1: Power up

Lch DAC PWRDN state. Power up/down control for Lch current DAC.

0: Power down

1: Power up

Lch Line Driver PWRDN state. Power up/down control for Lch line driver.

0: Power down

1: Power up

Lch Line Bias PWRDN state .Power up/down control for bais block of Lch line driver.

0: Power down

1: Power up

Lch Line CMFB2 PWRDN state. Power up/down control for CMFB of Lch line driver.

0: Power down

1: Power up

Lch Output Stage PWRDN state. Power up/down control for output stage of Lch line

driver.

0: Power down

1: Power up

0

OLPS

R/W

0

172

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13.3.37 Register 37 (0x25)

Figure 255. Register 37 (0x25)

7

6

5

4

3

2

1

0

GLPS

R/W

ALPS

R/W

ULPS

R/W

CPPS

R/W

FLPS

R/W

SLPS

R/W

ILPS

R/W

WLPS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 195. Register 37 (0x25) Field Descriptions

Bit

Field

Type

Reset

Description

Lch Gain control PWRDN state. Power up/down control for Lch gain control.

7

GLPS

R/W

0

0: Power down

1: Power up

Lch AMUTE state. Lch Analog Mute control.

0: Power down

1: Power up

6

5

4

ALPS

ULPS

CPPS

R/W

0

Lch AMUTE dummy state. Lch Analog Mute control.

0: Power down

1: Power up

CP PWRDN state. Power up/down control for negative charge pump.

0: Power down

1: Power up

Lch OFSCOMP PWRDN state. Power up/down control for offset calibration block for

Lch line driver.

0: Power down

1: Power up

3

2

1

0

FLPS

SLPS

ILPS

R/W

0

Lch Short Protection PWRDN state. Power up/down control for short protection of Lch

line driver.

0: Power down

1: Power up

Lch IMP sense PWRDN state. Power up/down control for impedance sensing circuit of

Lch line driver.

0: Power down

1: Power up

Lch IMP whole PWRDN state. Power up/down control for impedance sensing circuit of

Lch line driver at whole analog power down.

0: Power down

WLPS

1: Power up

173

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13.3.38 Register 38 (0x26)

Figure 256. Register 38 (0x26)

7

6

5

4

3

2

1

0

Reserved

R/W

DRPO

R/W

LRPO

R/W

BRPO

R/W

CRPO

R/W

ORPO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 196. Register 38 (0x26) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Rch DAC PWRDN override. Power up/down control for Rch current DAC.

4

3

DRPO

LRPO

R/W

0

0: normal

1: override

Rch Line Driver PWRDN override. Power up/down control for Rch line driver.

0: normal

1: override

Rch Line Bias PWRDN override. Power up/down control for bais block of Rch line

driver.

0: normal

1: override

2

1

0

BRPO

CRPO

ORPO

R/W

0

Rch Line CMFB2 PWRDN override. Power up/down control for CMFB of Rch line

driver.

0: normal

1: override

Rch Output Stage PWRDN override. Power up/down control for output stage of Rch

line driver.

0: normal

1: override

174

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13.3.39 Register 39 (0x27)

Figure 257. Register 39 (0x27)

7

6

5

4

3

2

1

0

GRPO

R/W

ARPO

R/W

URPO

R/W

Reserved

R/W

FRPO

R/W

SRPO

R/W

IRPO

R/W

WRPO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 197. Register 39 (0x27) Field Descriptions

Bit

Field

Type

Reset

Description

Rch Gain control PWRDN override. Power up/down control for Rch gain control.

7

GRPO

R/W

0

0: normal

1: override

Rch AMUTE override. Rch Analog Mute control.

6

ARPO

R/W

0

0: normal

1: override

Rch AMUTE dummy override. Rch Analog Mute control.

5

4

URPO

R/W

0

0: normal

1: override

Reserved

Rch OFSCOMP PWRDN override. Power up/down control for offset calibration block

for Rch line driver.

0: normal

1: override

3

2

1

0

FRPO

SRPO

IRPO

R/W

0

Rch Short Protection PWRDN override. Power up/down control for short protection of

Rch line driver.

0: normal

1: override

Rch IMP sense PWRDN override. Power up/down control for impedance sensing circuit

of Rch line driver.

0: normal

1: override

Rch IMP whole PWRDN override. Power up/down control for Rch impedance sensing

circuit of Rch line driver at whole analog power down.

0: normal

WRPO

1: override

175

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13.3.40 Register 40 (0x28)

Figure 258. Register 40 (0x28)

7

6

5

4

3

2

1

0

Reserved

R/W

DRPS

R/W

LRPS

R/W

BRPS

R/W

CRPS

R/W

ORPS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 198. Register 40 (0x28) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Rch DAC PWRDN state. Power up/down control for Rch current DAC.

4

3

2

1

DRPS

LRPS

BRPS

CRPS

R/W

0

0: Power down

1: Power up

Rch Line Driver PWRDN state. Power up/down control for Rch line driver.

0: Power down

1: Power up

Rch Line Bias PWRDN state. Power up/down control for bais block of Rch line driver.

0: Power down

1: Power up

Rch Line CMFB2 PWRDN state. Power up/down control for CMFB of Rch line driver.

0: Power down

1: Power up

Rch Output Stage PWRDN state. Power up/down control for output stage of Rch line

driver.

0: Power down

1: Power up

0

ORPS

R/W

0

176

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ZHCSFY4 –DECEMBER 2016

13.3.41 Register 41 (0x29)

Figure 259. Register 41 (0x29)

7

6

5

4

3

2

1

0

GRPS

R/W

ARPS

R/W

URPS

R/W

Reserved

R/W

FRPS

R/W

SRPS

R/W

IRPS

R/W

WRPS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 199. Register 41 (0x29) Field Descriptions

Bit

Field

Type

Reset

Description

Rch Gain control PWRDN state. Power up/down control for Rch gain control.

7

GRPS

R/W

0

0: Power down

1: Power up

Rch AMUTE state. Rch Analog Mute control.

0: Power down

6

ARPS

R/W

0

1: Power up

Rch AMUTE dummy state. Rch Analog Mute control.

5

4

URPS

R/W

0

0: Power down

1: Power up

Reserved

Rch OFSCOMP PWRDN state. Power up/down control for offset calibration block for

Rch line driver.

0: Power down

1: Power up

3

2

1

0

FRPS

SRPS

IRPS

R/W

0

Rch Short Protection PWRDN state. Power up/down control for short protection of Rch

line driver.

0: Power down

1: Power up

Rch IMP sense PWRDN state. Power up/down control for impedance sensing circuit of

Rch line driver.

0: Power down

1: Power up

Rch IMP whole PWRDN state. Power up/down control for Rch impedance sensing

circuit of Rch line driver at whole analog power down.

0: Power down

1: Power up

WRPS

177

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13.3.42 Register 42 (0x2A)

Figure 260. Register 42 (0x2A)

7

6

5

4

3

2

1

0

Reserved

R/W

CMEN

R/W

Reserved

R/W

CMSL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 200. Register 42 (0x2A) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

CP operation mode control enable. Enable/Disable for charge pump mode select.

4

3-1

0

CMEN

R/W

0

1

0: Disable

1: Enable

Reserved

CMSL

Reserved

CP operation mode select. Charge pump mode select by register.

0: Normal operation

1: Constant current mode

13.3.43 Register 43 (0x2B)

Figure 261. Register 43 (0x2B)

7

6

5

4

3

2

1

0

Reserved

R/W

CHDP

R/W

Reserved

R/W

CHI4

R/W

HDEN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 201. Register 43 (0x2B) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

CHD power up/down control. Power up/down control for clock halt detector.

4

3-2

1

CHDP

R/W

1

0

0: Power down

1: Power up

Reserved

CHI4

Reserved

CHD current control override. x4 current control for clock halt detector.

0: Normal operation

1: x4 current operation

CHD detector enable/disable control. Enable/disable control for clock halt detector. At

'disable', output shows "1".

0: Enable

0

HDEN

R/W

0

1: Disable

178

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13.3.44 Register 44 (0x2C)

Figure 262. Register 44 (0x2C)

7

6

5

4

3

2

1

0

Reserved

R/W

LBPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 202. Register 44 (0x2C) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

LDO bandgap power up/down control. LDO bandgap power/up down control on Test

mode.

0: Power down

1: Power up

0

LBPD

R/W

0

13.3.45 Register 63 (0x3F)

Figure 263. Register 63 (0x3F)

7

6

5

4

3

2

1

0

PWD1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 203. Register 63 (0x3F) Field Descriptions

Bit

Field

Type

Reset

Description

Password1

First word of password.

Both words of password must be correctly set in order to unlock test registers.

7-0

PWD1

R/W

0

When locked, writing to test registers are inhibited and reading them will return 0.

13.3.46 Register 64 (0x40)

Figure 264. Register 64 (0x40)

7

6

5

4

3

2

1

0

PWD2

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 204. Register 64 (0x40) Field Descriptions

Bit

Field

Type

Reset

Description

Password2

First word of password.

Both words of password must be correctly set in order to unlock test registers.

When locked, writing to test registers are inhibited and reading them will return 0.

7-0

PWD2

R/W

0

179

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13.3.47 Register 65 (0x41)

Figure 265. Register 65 (0x41)

7

6

5

4

3

1

0

Reserved

R/W

TSEL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 205. Register 65 (0x41) Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

0

Reserved

Test Mode Selection (No longer need)

0: Normal

1:SCAN

2:IDDQ

3:VOH

4:VOL

3-0

TSEL

R/W

0

5: VIL

6:VIH

7:HI-Z

13.3.48 Register 70 (0x46)

Figure 266. Register 70 (0x46)

7

6

5

4

3

1

0

Left Channel DIFF Manual Offset (Q5.2)

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 206. Register 70 (0x46) Field Descriptions

Bit

Field

Type

Reset

Description

Add manual offset to the left channel DIFF offset compensator.

Observed offset delta:

0111111 : -15.75 mV

0111110 : -15.50 mV

0111101 : -15.25 mV

…

0000001 : -0.25 mV

0000000 : 0.0 mV

1111111 : 0.25 mV

…

Left Channel

DIFF Manual

Offset (Q5.2)

7-0

R/W

0

1000010 : 15.50 mV

1000001 : 15.75 mV

1000000 : 16.0 mV

180

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ZHCSFY4 –DECEMBER 2016

13.3.49 Register 71 (0x47)

Figure 267. Register 71 (0x47)

7

6

5

4

3

1

0

Left Channel CMFB Manual Offset (Q6.2)

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 207. Register 71 (0x47) Field Descriptions

Bit

Field

Type

Reset

Description

Add manual offset to the left channel CMFB offset compensator.

Observed offset delta:

0111111 : -31.75 mV

0111110 : -31.50 mV

0111101 : -31.25 mV

…

0000001 : -0.25 mV

0000000 : 0.0 mV

1111111 : 0.25 mV

…

Left Channel

CMFB Manual

Offset (Q6.2)

7-0

R/W

0

1000010 : 31.50 mV

1000001 : 31.75 mV

1000000 : 32.0 mV

13.3.50 Register 72 (0x48)

Figure 268. Register 72 (0x48)

7

6

5

4

3

1

0

Right Channel DIFF Manual Offset (Q5.2)

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 208. Register 72 (0x48) Field Descriptions

Bit

Field

Type

Reset

Description

Add manual offset to the right channel DIFF offset compensator.

Observed offset delta:

0111111 : -15.75 mV

0111110 : -15.50 mV

0111101 : -15.25 mV

…

0000001 : -0.25 mV

0000000 : 0.0 mV

1111111 : 0.25 mV

…

Right Channel

DIFF Manual

Offset (Q5.2)

7-0

R/W

0

1000010 : 15.50 mV

1000001 : 15.75 mV

1000000 : 16.0 mV

181

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13.3.51 Register 73 (0x49)

Figure 269. Register 73 (0x49)

7

6

5

4

3

1

0

Right Channel CMFB Manual Offset (Q6.2)

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 209. Register 73 (0x49) Field Descriptions

Bit

Field

Type

Reset

Description

Add manual offset to the right channel CMFB offset compensator.

Observed offset delta:

0111111 : -31.75 mV

0111110 : -31.50 mV

0111101 : -31.25 mV

…

0000001 : -0.25 mV

0000000 : 0.0 mV

1111111 : 0.25 mV

…

Right Channel

CMFB Manual

Offset (Q6.2)

7-0

R/W

0

1000010 : 31.50 mV

1000001 : 31.75 mV

1000000 : 32.0 mV

13.3.52 Register 74 (0x4A)

Figure 270. Register 74 (0x4A)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 210. Register 74 (0x4A) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.53 Register 75 (0x4B)

Figure 271. Register 75 (0x4B)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 211. Register 75 (0x4B) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

182

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ZHCSFY4 –DECEMBER 2016

13.3.54 Register 76 (0x4C)

Figure 272. Register 76 (0x4C)

7

6

5

4

3

1

0

Reserved

Left Channel

DIFF Monitor(8)

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 212. Register 76 (0x4C) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

This register shows the approximation of original / compensated left channel DIFF

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : -0.25 mV

…

Left Channel DIFF

Monitor(8)

0

R

1000010 : -63.50 mV

1000001 : -63.75 mV

1000000 : -64.0 mV

13.3.55 Register 77 (0x4D)

Figure 273. Register 77 (0x4D)

7

6

5

4

3

1

0

Left Channel DIFF Monitor(7:0)

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 213. Register 77 (0x4D) Field Descriptions

Bit

Field

Type

Reset

Description

This register shows the approximation of original / compensated left channel DIFF

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : -0.25 mV

…

Left Channel

DIFF Monitor(7:0)

7-0

R

1000010 : -63.50 mV

1000001 : -63.75 mV

1000000 : -64.0 mV

183

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13.3.56 Register 78 (0x4E)

Figure 274. Register 78 (0x4E)

7

6

5

4

3

1

0

Reserved

R/W

I048

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 214. Register 78 (0x4E) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

FS Det 48 kHz Min Range . Minimum OSC count in LRCLK for 48 kHz detection.

Decimal Value 863.

4-0

I048

R/W

0

13.3.57 Register 79 (0x4F)

Figure 275. Register 79 (0x4F)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 215. Register 79 (0x4F) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.58 Register 80 (0x50)

Figure 276. Register 80 (0x50)

7

6

5

4

3

1

0

Reserved

R/W

X048

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 216. Register 80 (0x50) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

FS Det 48 kHz Max Range. Minimum OSC count in LRCLK for 48 kHz detection.

Decimal Value 2479.

4-0

X048

R/W

0

13.3.59 Register 81 (0x51)

Figure 277. Register 81 (0x51)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 217. Register 81 (0x51) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

184

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ZHCSFY4 –DECEMBER 2016

13.3.60 Register 82 (0x52)

Figure 278. Register 82 (0x52)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 218. Register 82 (0x52) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.61 Register 83 (0x53)

Figure 279. Register 83 (0x53)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 219. Register 83 (0x53) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.62 Register 84 (0x54)

Figure 280. Register 84 (0x54)

7

6

5

4

3

1

0

Reserved

Left Channel

CMFB Monitor

(8)

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 220. Register 84 (0x54) Field Descriptions

Bit

Field

Type Reset

R/W

Description

7-1

Reserved

0

Reserved

This register shows the approximation of original / compensated left channel CMFB

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : -0.25 mV

…

Left Channel CMFB

Monitor(8)

0

R

1000010 : -63.50 mV

1000001 : -63.75 mV

1000000 : -64.0 mV

185

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ZHCSFY4 –DECEMBER 2016

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13.3.63 Register 85 (0x55)

Figure 281. Register 85 (0x55)

7

6

5

4

3

1

0

Left Channel CMFB Monitor (7:0)

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 221. Register 85 (0x55) Field Descriptions

Bit

Field

Type

Reset

Description

This register shows the approximation of original / compensated left channel CMFB

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : –0.25 mV

…

Left Channel

CMFB Monitor

(7:0)

7-0

R

1000010 : –63.50 mV

1000001 : –63.75 mV

1000000 : –64.0 mV

13.3.64 Register 86 (0x56)

Figure 282. Register 86 (0x56)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 222. Register 86 (0x56) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.65 Register 87 (0x57)

Figure 283. Register 87 (0x57)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 223. Register 87 (0x57) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

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13.3.66 Register 88 (0x58)

Figure 284. Register 88 (0x58)

7

6

5

4

3

1

0

Reserved

Right Channel

DIFF Monitor

(8)

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 224. Register 88 (0x58) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

This register shows the approximation of original / compensated right channel DIFF

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : -0.25 mV

…

Right Channel

DIFF Monitor (8)

0

R

1000010 : -63.50 mV

1000001 : -63.75 mV

1000000 : -64.0 mV

13.3.67 Register 89 (0x59)

Figure 285. Register 89 (0x59)

7

6

5

4

3

1

0

Right Channel DIFF Monitor (7:0)

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 225. Register 89 (0x59) Field Descriptions

Bit

Field

Type

Reset

Description

This register shows the approximation of original / compensated right channel DIFF

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : -0.25 mV

…

Right Channel

DIFF Monitor

(7:0)

7-0

R

1000010 : -63.50 mV

1000001 : -63.75 mV

1000000 : -64.0 mV

187

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13.3.68 Register 90 (0x5A)

Figure 286. Register 90 (0x5A)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 226. Register 90 (0x5A) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.69 Register 91 (0x5B)

Figure 287. Register 91 (0x5B)

7

6

5

4

3

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 227. Register 91 (0x5B) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Reserved

R/W

0

Reserved

13.3.70 Register 92 (0x5C)

Figure 288. Register 92 (0x5C)

7

6

5

4

3

1

0

Reserved

Right Channel

CMFB Monitor

(8)

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 228. Register 92 (0x5C) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

This register shows the approximation of original / compensated right channel CMFB

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : –0.25 mV

…

Right Channel

CMFB Monitor(8)

0

R

1000010 : –63.50 mV

1000001 : –63.75 mV

1000000 : –64.0 mV

188

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13.3.71 Register 93 (0x5D)

Figure 289. Register 93 (0x5D)

7

6

5

4

3

1

0

Right Channel CMFB Monito r(7:0)

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 229. Register 93 (0x5D) Field Descriptions

Bit

Field

Type

Reset

Description

This register shows the approximation of original / compensated right channel CMFB

offset.

Observed offset delta:

0111111 : 63.75 mV

0111110 : 63.50 mV

0111101 : 63.25 mV

…

0000001 : 0.25 mV

0000000 : 0.0 mV

1111111 : –0.25 mV

…

Right Channel

CMFB Monitor

(7:0)

7-0

R

1000010 : –63.50 mV

1000001 : –63.75 mV

1000000 : –64.0 mV

13.4 DSP Memory Map

Table 230. Memory Map — Book 0x78 (120)⁽¹⁾

SUB

ADDRESS

NUMBER OF BYTES /

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

FORMAT

LEVEL METER

4 / 1.31

0x54

0x58

0x0C

Level Meter Left Output

0x000000--

Level Meter Left Output

Level Meter Right

Output

Level Meter Right

Output

4 / 1.31

SECONDARY EQ LEFT 12 BQS

4 / 5.27

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x15

CH-L BQ 1 B0

CH-L BQ 1 B1

CH-L BQ 1 B2

CH-L BQ 1 A1

CH-L BQ 1 A2

CH-L BQ 2 B0

CH-L BQ 2 B1

CH-L BQ 2 B2

CH-L BQ 2 A1

CH-L BQ 2 A2

CH-L BQ 3 B0

CH-L BQ 3 B1

CH-L BQ 3 B2

CH-L BQ 3 A1

CH-L BQ 3 A2

CH-L BQ 4 B0

CH-L BQ 4 B1

CH-L BQ 4 B2

CH-L BQ 4 A1

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Left BQ coefficient

4 / 6.26

4 / 5.27

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

(1) The registers in this table do not require the swap flag to work

189

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DSP Memory Map (continued)

Table 230. Memory Map — Book 0x78 (120)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

FORMAT

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x15

0x16

CH-L BQ 4 A2

CH-L BQ 5 B0

CH-L BQ 5 B1

CH-L BQ 5 B2

CH-L BQ 5 A1

CH-L BQ 5 A2

CH-L BQ 6 B0

CH-L BQ 6 B1

CH-L BQ 6 B2

CH-L BQ 6 A1

CH-L BQ 6 A2

CH-L BQ 7 B0

CH-L BQ 7 B1

CH-L BQ 7 B2

CH-L BQ 7 A1

CH-L BQ 7 A2

CH-L BQ 8 B0

CH-L BQ 8 B1

CH-L BQ 8 B2

CH-L BQ 8 A1

CH-L BQ 8 A2

CH-L BQ 9 B0

CH-L BQ 9 B1

CH-L BQ 9 B2

CH-L BQ 9 A1

CH-L BQ 9 A2

CH-L BQ 10 B0

CH-L BQ 10 B1

CH-L BQ 10 B2

CH-L BQ 10 A1

CH-L BQ 10 A2

CH-L BQ 11 B0

CH-L BQ 11 B1

CH-L BQ 11 B2

CH-L BQ 11 A1

CH-L BQ 11 A2

CH-L BQ 12 B0

CH-L BQ 12 B1

CH-L BQ 12 B2

CH-L BQ 12 A1

CH-L BQ 12 A2

4 / 1.31

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Left BQ coefficient

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

SECONDARY EQ RIGHT 12 BQS

4 / 5.27

0x08

0x0C

0x10

0x17

CH-R BQ 1 B0

CH-R BQ 1 B1

CH-R BQ 1 B2

0x7FFFFFFF

0x00000000

Right BQ coefficient

4 / 6.26

4 / 5.27

190

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DSP Memory Map (continued)

Table 230. Memory Map — Book 0x78 (120)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

FORMAT

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x17

0x18

CH-R BQ 1 A1

CH-R BQ 1 A2

CH-R BQ 2 B0

CH-R BQ 2 B1

CH-R BQ 2 B2

CH-R BQ 2 A1

CH-R BQ 2 A2

CH-R BQ 3 B0

CH-R BQ 3 B1

CH-R BQ 3 B2

CH-R BQ 3 A1

CH-R BQ 3 A2

CH-R BQ 4 B0

CH-R BQ 4 B1

CH-R BQ 4 B2

CH-R BQ 4 A1

CH-R BQ 4 A2

CH-R BQ 5 B0

CH-R BQ 5 B1

CH-R BQ 5 B2

CH-R BQ 5 A1

CH-R BQ 5 A2

CH-R BQ 6 B0

CH-R BQ 6 B1

CH-R BQ 6 B2

CH-R BQ 6 A1

CH-R BQ 6 A2

CH-R BQ 7 B0

CH-R BQ 7 B1

CH-R BQ 7 B2

CH-R BQ 7 A1

CH-R BQ 7 A2

CH-R BQ 8 B0

CH-R BQ 8 B1

CH-R BQ 8 B2

CH-R BQ 8 A1

CH-R BQ 8 A2

CH-R BQ 9 B0

CH-R BQ 9 B1

CH-R BQ 9 B2

CH-R BQ 9 A1

CH-R BQ 9 A2

CH-R BQ 10 B0

CH-R BQ 10 B1

CH-R BQ 10 B2

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Right BQ coefficient

191

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DSP Memory Map (continued)

Table 230. Memory Map — Book 0x78 (120)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

FORMAT

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

0x50

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x18

CH-R BQ 10 A1

CH-R BQ 10 A2

CH-R BQ 11 B0

CH-R BQ 11 B1

CH-R BQ 11 B2

CH-R BQ 11 A1

CH-R BQ 11 A2

CH-R BQ 12 B0

CH-R BQ 12 B1

CH-R BQ 12 B2

CH-R BQ 12 A1

CH-R BQ 12 A2

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Right BQ coefficient

SECONDARY BQ GAIN SCALE AND VOLUME

0x08

0x0C

0x19

Left Gain

4 / 8.24

Gain

Right Gain

4 / 8.24

BANK SWITCH

0x08

0x14

Left Gain

4 / 32.0

0x00000000

Needs swap flag to run -

Table 231. Memory Map — Book 0x8C (140)⁽¹⁾

SUB

ADDRESS

NUMBER OF BYTES /

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

FORMAT

DSP MEMORY UPDATE

4 / 32.0

0x10

0x01

DSP Memory Swap Flag

0x00000000

DSP Memory Swap Flag

MAIN EQ LEFT 12 BQS

4 / 5.27

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x1B

0x1C

CH-L BQ 1 B0

CH-L BQ 1 B1

CH-L BQ 1 B2

CH-L BQ 1 A1

CH-L BQ 1 A2

CH-L BQ 2 B0

CH-L BQ 2 B1

CH-L BQ 2 B2

CH-L BQ 2 A1

CH-L BQ 2 A2

CH-L BQ 3 B0

CH-L BQ 3 B1

CH-L BQ 3 B2

CH-L BQ 3 A1

CH-L BQ 3 A2

CH-L BQ 4 B0

CH-L BQ 4 B1

CH-L BQ 4 B2

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Left BQ coefficient

4 / 6.26

4 / 5.27

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

(1) Will be set to default anytime a DSP reset, CP error or device standby occurs. Clock errors and frequency changes cause DSP reset.

The clocks should be stable when using these mux in non-default state. Always poll muxes status and set muxes prior to use in

application. TI recommends that these muxes are repeatedly polled and refreshed during application in the event a DSP reset occurred

that cleared the muxes.

192

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Table 231. Memory Map — Book 0x8C (140)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

FORMAT

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

MAIN EQ RIGHT 12 BQS

4 / 5.27

4 / 6.26

4 / 5.27

4 / 2.30

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x1C

0x1D

CH-L BQ 4 A1

CH-L BQ 4 A2

CH-L BQ 5 B0

CH-L BQ 5 B1

CH-L BQ 5 B2

CH-L BQ 5 A1

CH-L BQ 5 A2

CH-L BQ 6 B0

CH-L BQ 6 B1

CH-L BQ 6 B2

CH-L BQ 6 A1

CH-L BQ 6 A2

CH-L BQ 7 B0

CH-L BQ 7 B1

CH-L BQ 7 B2

CH-L BQ 7 A1

CH-L BQ 7 A2

CH-L BQ 8 B0

CH-L BQ 8 B1

CH-L BQ 8 B2

CH-L BQ 8 A1

CH-L BQ 8 A2

CH-L BQ 9 B0

CH-L BQ 9 B1

CH-L BQ 9 B2

CH-L BQ 9 A1

CH-L BQ 9 A2

CH-L BQ 10 B0

CH-L BQ 10 B1

CH-L BQ 10 B2

CH-L BQ 10 A1

CH-L BQ 10 A2

CH-L BQ 11 B0

CH-L BQ 11 B1

CH-L BQ 11 B2

CH-L BQ 11 A1

CH-L BQ 11 A2

CH-L BQ 12 B0

CH-L BQ 12 B1

CH-L BQ 12 B2

CH-L BQ 12 A1

CH-L BQ 12 A2

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

Left BQ coefficient

0x58

0x5C

0x60

0x64

0x1D

CH-R BQ 1 B0

CH-R BQ 1 B1

CH-R BQ 1 B2

CH-R BQ 1 A1

0x7FFFFFFF

0x00000000

Right BQ coefficient

193

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www.ti.com.cn

Table 231. Memory Map — Book 0x8C (140)⁽¹⁾(continued)

SUB

PAGE

NUMBER OF BYTES /

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

ADDRESS

FORMAT

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x8C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x1D

0x1E

0x1F

CH-R BQ 1 A2

CH-R BQ 2 B0

CH-R BQ 2 B1

CH-R BQ 2 B2

CH-R BQ 2 A1

CH-R BQ 2 A2

CH-R BQ 3 B0

CH-R BQ 3 B1

CH-R BQ 3 B2

CH-R BQ 3 A1

CH-R BQ 3 A2

CH-R BQ 4 B0

CH-R BQ 4 B1

CH-R BQ 4 B2

CH-R BQ 4 A1

CH-R BQ 4 A2

CH-R BQ 5 B0

CH-R BQ 5 B1

CH-R BQ 5 B2

CH-R BQ 5 A1

CH-R BQ 5 A2

CH-R BQ 6 B0

CH-R BQ 6 B1

CH-R BQ 6 B2

CH-R BQ 6 A1

CH-R BQ 6 A2

CH-R BQ 7 B0

CH-R BQ 7 B1

CH-R BQ 7 B2

CH-R BQ 7 A1

CH-R BQ 7 A2

CH-R BQ 8 B0

CH-R BQ 8 B1

CH-R BQ 8 B2

CH-R BQ 8 A1

CH-R BQ 8 A2

CH-R BQ 9 B0

CH-R BQ 9 B1

CH-R BQ 9 B2

CH-R BQ 9 A1

CH-R BQ 9 A2

CH-R BQ 10 B0

CH-R BQ 10 B1

CH-R BQ 10 B2

CH-R BQ 10 A1

CH-R BQ 10 A2

CH-R BQ 11 B0

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

0x00000000

0x7FFFFFFF

Right BQ coefficient

194

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ZHCSFY4 –DECEMBER 2016

Table 231. Memory Map — Book 0x8C (140)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

FORMAT

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

4 / 2.30

4 / 1.31

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

0x50

0x54

0x1F

CH-R BQ 11 B1

CH-R BQ 11 B2

CH-R BQ 11 A1

CH-R BQ 11 A2

CH-R BQ 12 B0

CH-R BQ 12 B1

CH-R BQ 12 B2

CH-R BQ 12 A1

CH-R BQ 12 A2

0x00000000

0x7FFFFFFF

0x00000000

Right BQ coefficient

MAIN BQ GAIN SCALE AND VOLUME

0x58

0x5C

0x1F

Left Gain

4 / 8.24

0x01000000

Gain

Right Gain

4 / 8.24

DPEQ SENSE BQ

DPEQ sense BQ

coefficient

0x6C

0x70

0x74

0x78

0x7C

0x1F

BQ B0

BQ B1

BQ B2

BQ A1

BQ A2

4 / 1.31

0x7FFFFFFF

0x00000000

DPEQ sense BQ

coefficient

DPEQ sense BQ

coefficient

DPEQ sense BQ

coefficient

DPEQ sense BQ

coefficient

4 / 1.31

DPEQ HIGH LEVEL PATH BQ

4 / 1.31

DPEQ high BQ

coefficient

0x08

0x0C

0x10

0x14

0x18

0x20

BQ B0

BQ B1

BQ B2

BQ A1

BQ A2

0x7FFFFFFF

0x00000000

DPEQ high BQ

coefficient

4 / 1.31

DPEQ high BQ

coefficient

DPEQ high BQ

coefficient

DPEQ high BQ

coefficient

4 / 1.31

DPEQ LOW LEVEL PATH BQ

4 / 1.31

DPEQ low BQ

coefficient

0x1C

0x20

0x24

0x28

0x2C

0x20

BQ B0

BQ B1

BQ B2

BQ A1

BQ A2

0x7FFFFFFF

0x00000000

DPEQ low BQ

coefficient

4 / 1.31

DPEQ low BQ

coefficient

DPEQ low BQ

coefficient

DPEQ low BQ

coefficient

DRC 1 BQ

4 / 1.31

0x30

0x34

0x38

0x3C

0x40

0x20

BQ B0

BQ B1

BQ B2

BQ A1

BQ A2

0x9D8E8900

0x007BFC00

0x7040C300

0x9D8E8900

DRC 1 BQ coefficient

4 / 1.31

195

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Table 231. Memory Map — Book 0x8C (140)⁽¹⁾(continued)

SUB

PAGE

NUMBER OF BYTES /

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

ADDRESS

FORMAT

DRC 2 BQ

0x44

0x48

0x4C

0x50

0x54

0x20

BQ B0

4 / 1.31

0x70BCBF00

0x007BFC00

0x7040C300

0x9D8E8900

DRC 2 BQ coefficient

BQ B1

BQ B2

BQ A1

BQ A2

4 / 1.31

DPEQ CONTROL

DPEQ Sense Energy

Time constant

0x58

0x20

Alpha

4 / 1.31

0x02DEAD00

0x5C

0x60

0x20

Gain

4 / 1.31

0x74013901

0x0020C49B

DPEQ Threshold Gain

DPEQ Threshold Offset

Offset

4 / 1.31

LEVER METER

Level meter Energy

Time constant

0x64

0x20

Level Meter Alpha

4 / 1.31

0x00A7264A

DRC SUM

4 / 1.31

0x68

0x6C

0x20

DRC 1 sum

DRC 2 sum

0x7FFFFFFF

0x00000000

DRC1 Mixer Gain

DRC2 Mixer Gain

4 / 1.31

DRC 1

DRC1 Energy Time

constant

0x70

0x74

0x78

0x7C

0x08

0x0C

0x20

0x21

DRC1 Energy

DRC1 Attack

DRC1 Decay

K0_1

4 / 1.31

4 / 9.23

0x7FFFFFFF

0x00000000

DRC1 Attack Time

constant

DRC1 Decay Time

constant

DRC1 Region 1 Slope

(comp/Exp)

DRC1 Region 2 Slope

(comp/Exp)

K1_1

DRC1 Region 3 Slope

(comp/Exp)

K2_1

0x10

0x14

0x18

0x1C

0x21

T1_1

4 / 9.23

DRC 2

0xE7000000

0xFE800000

0x00000000

DRC1 Threshold 1

DRC1 Threshold 2

DRC1 Offset 1

T2_1

Offset 1

Offset 2

DRC1 Offset 2

DRC2 Energy Time

constant

0x20

0x24

0x28

0x2C

0x30

0x34

0x21

DRC2 Energy

DRC2 Attack

DRC2 Decay

K0_1

4 / 1.31

4 / 9.23

0x7FFFFFFF

0x00000000

DRC2 Attack Time

constant

DRC2 Decay Time

constant

DRC2 Region 1 Slope

(comp/Exp)

DRC2 Region 2 Slope

(comp/Exp)

K1_1

DRC2 Region 3 Slope

(comp/Exp)

K2_1

0x38

0x3C

0x40

0x44

0x21

T1_1

4 / 9.23

0xE7000000

0xFE800000

0x00000000

DRC2 Threshold 1

DRC2 Threshold 2

DRC2 Offset 1

T2_1

Offset 1

Offset 2

DRC2 Offset 2

196

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Table 231. Memory Map — Book 0x8C (140)⁽¹⁾(continued)

SUB

ADDRESS

NUMBER OF BYTES /

PAGE

REGISTER NAME

DEFAULT VALUE

DESCRIPTION

FORMAT

FINE VOLUME OUTPUT

Left Channel Fine

Volume Gain

0x48

0x4C

0x21

Fine volume left

Fine volume right

4 / 2.30

0x3FFFFFFF

Right Channel Fine

Volume Gain

4 / 2.30

INPUT MIXER

4 / 9.23

Left Channel Mixer Left

Input Gain

0x50

0x54

0x58

0x5C

0x21

Left in to left out

Right in to left out

Left in to right out

Right in to right out

0x00800000

0x00000000

0x00800000

Left Channel Mixer Right

Input Gain

4 / 9.23

Right Channel Mixer Left

Input Gain

Right Channel Mixer

Right Input Gain

4 / 9.23

DPEQ GAIN SCALE

4 / 6.26

DPEQ Sense Input Gain

Scale

0x60

0x21

DPEQ sense scale

0x40000000

BYPASS EQ MUX

0x64

0x68

0x6C

0x70

0x74

0x21

4 / 32.0

0x00000000

0x00400000

GANG LEFT / RIGHT EQ

4 / 32.0

BYPASS WORKLOAD TO SDOUT

4 /32.0

BYPASS TO LEVEL METER BIT

4 / 32.0

THD BOOST

4 / 9.23

AGL

0x78

0x7C

0x21

Attack Threshold

4 / 5.27

0x40000000

0x06153BD1

Threshold linear

AGL Alpha Time

constant

Softening Filter Alpha

4 / 1.31

AGL Attack Time

constant

0x08

0x22

Attack Rate

0x0001B4E8

0x0C

0x10

0x22

AGL Enable

Chomp

4 / 1.31

0x40000000

0x0020C49C

AGL Enable Mux

AGL Omega Time

constant

0x14

0x18

0x22

Softening Filter Omega

Release Rate

4 / 1.31

0x79EAC42F

0x00002BB1

AGL Release Time

constant

0x1C

0x22

Volume

4 / 1.31

0x7FFFFFFF

AGL Volume

197

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14 器件和文档支持

14.1 器件支持

14.1.1 器件命名规则

Glossary部分列出的术语是根据多项德州仪器

(TI)

计划定义的通用术语（包括常用的缩写和单词），符合

JEDEC、IPC、IEEE 等行业标准。本部分提供的术语定义了特定于本产品和文档、附属产品、或本产品使用的支

持工具和软件的单词、短语和缩写。如对定义和术语有其他疑问，请访问e2e 音频放大器论坛。

桥接负载 (BTL) 是一种输出配置，其中扬声器的两端分别连接一个半桥。

DUT 是指被测器件，用于区分其他器件。

闭环架构是一种拓扑结构，其中放大器监视输出引脚、对比输出信号与输入信号，并尝试修正输出信号的非线性。

动态控件是指系统或最终用户在正常使用时可更改的控件。

GPIO 是通用输入/输出引脚。该引脚是一个高度可配置的双向数字引脚，可执行系统所需的多种功能。

主机处理器（也称系统处理器、标量、主机或系统控制器）是指用作中央系统控制器的器件，可为其连接的器件提

供控制信息，从其上游器件采集音频源数据后分配给其他器件。该器件通常配置音频路径中音频处理器件（如

TAS5780M）的控件，从而根据频率响应、时间校准、目标声压级、系统安全工作区域和用户偏好优化扬声器的音

频输出。

HybridFlow 通过搭配使用 RAM 内置的元件和 ROM 内置的元件构成一款可配置器件，与完全可编程器件相比更

加易于使用，而且还能保持足够的灵活性以适应多种应用

最大持续输出功率是指放大器在 25°C 工作环境温度下可持续（不关断）提供的最大输出功率。测试该参数时，当

放大器温度达到热平衡点并且不再升高时停止测试

并行桥接负载 (PBTL) 是一种输出配置，其中扬声器的两端分别连接一对并行放置的半桥。

r_DS(on)是指放大器输出级中所用 MOSFET 的导通电阻。

静态控制/静态配置是指系统正常使用时不发生变化的控件。

过孔是指 PCB 中的镀铜通孔。

14.1.2 开发支持

有关 RDGUI 软件，请咨询当地的现场支持工程师。

14.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

198

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14.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.4 商标

Burr-Brown, PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

14.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

14.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

199

GENERIC PACKAGE VIEW

DCA 48

12.5 x 6.1, 0.5 mm pitch

HTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224608/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS5780MDCA
厂家：	TEXAS INSTRUMENTS
描述：	20W 立体声、40W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器 \| DCA \| 48 \| -25 to 85 放大器音频放大器
文件：	总205页 (文件大小：3760K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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