TAS6424LQDKQRQ1 [TI]
具有负载突降保护功能的汽车类 27W、2MHz、4 通道、4.5V 至 18V 数字输入 D 类音频放大器 | DKQ | 56 | -40 to 125;
| 型号： | TAS6424LQDKQRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有负载突降保护功能的汽车类 27W、2MHz、4 通道、4.5V 至 18V 数字输入 D 类音频放大器 | DKQ | 56 | -40 to 125 放大器 音频放大器 |
| 文件： | 总62页 (文件大小：2132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS6424L-Q1
ZHCSG71 –MARCH 2017
TAS6424L-Q1 27W、2MHz 数字输入 4 通道汽车用 D 类音频放大器（具
有负载突降保护和 I2C 诊断功能）
1 特性
2 应用
1
•
•
符合汽车应用 标准
•
•
汽车音响主机
汽车外部放大器模块
音频输入
–
–
–
4 通道 I2S 或 4/8 通道 TDM 输入
3 说明
输入采样率：44.1kHz、48kHz、96kHz
输入格式：16 位至 32 位 I2S 和 TDM
TAS6424L-Q1 器件是一款 4 通道数字输入 D 类音频
放大器，专为汽车音响主机和外部放大器模块而设计。
在 14.4V 电源电压条件下，当负载为 4Ω、THD+N 为
10% 时，该器件可提供 4 通道的 27W 输出功率；当
负载为 2Ω、THD+N 为 10% 时，该器件可提供 27W
的输出功率。。与传统的线性放大器解决方案相比，D
类拓扑技术显著提高了器件效率。输出开关频率既可以
设置为高于调幅 (AM) 频带，以消除 AM 频带干扰并降
低输出滤波需求及成本；也可以设置为低于 AM 频
带，以优化器件效率。
•
音频输出
–
4 通道桥接负载 (BTL)，可选并行桥接负载
(PBTL)
–
–
高达 2.1MHz 的输出开关频率
在 4Ω 负载、14.4V 电源电压和 10% THD 的条
件下，输出功率为 27W
–
–
在 2Ω 负载、14.4V 电源电压和 10% THD 的条
件下，输出功率为 27W
在 2Ω 负载、18V PBTL 和 10% THD 的条件
下，输出功率为 80W
4.5V 至 18V 的宽电源电压范围有助于将启停 应用中
的音频失真降至最低程度。
•
•
在 4Ω 负载和 14.4V 电源电压条件下的音频性能
–
输出功率为 1W 时的总谐波失真 + 噪声
(THD+N) < 0.03%
该器件融合了要求苛刻的 OEM 应用领域所需的 所有
功能。该器件具有内置负载诊断功能，用于检测和诊断
误接的输出，以及检测交流耦合的高频扬声器，以帮助
缩短制造过程中的测试时间。
–
–
42µVRMS 输出噪声
–90dB 串扰
负载诊断功能
–
–
–
–
–
输出负载开路和短路
该器件采用 56 引脚 HTSSOP PowerPAD ™封装，外
露散热焊盘朝上。
输出至电池短路或接地短路
线路输出检测高达 6kΩ
有关引脚兼容的 2 通道器件信息，请参阅 TAS6422-
Q1 器件。
无输入时钟时也可运行
用于高频扬声器检测的交流诊断功能
•
保护
器件信息(1)
–
–
–
–
–
–
–
输出限流
器件型号
封装
封装尺寸（标称值）
输出短路保护
40V 负载突降
可承受接地开路和电源开路
直流偏移
TAS6424L-Q1
HSSOP (56)
18.41mm × 7.49mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
PCB 区域
过热
欠压和过压
•
常规运行
–
评估模块 (EVM) 通过 CISPR25-L5 电磁兼容性
(EMC) 规范
–
–
–
4.5V 至 18V 电源电压
I2C 控制具有 4 个地址选项
削波检测和热警告
27 mm
25-W 4-channel
5.9 cm2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS809
TAS6424L-Q1
ZHCSG71 –MARCH 2017
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 25
9.5 Programming........................................................... 25
9.6 Register Maps......................................................... 29
10 Application and Implementation........................ 45
10.1 Application Information.......................................... 45
10.2 Typical Applications .............................................. 46
11 Power Supply Recommendations ..................... 52
12 Layout................................................................... 52
12.1 Layout Guidelines ................................................. 52
12.2 Layout Example .................................................... 54
12.3 Thermal Considerations........................................ 54
13 器件和文档支持 ..................................................... 55
13.1 文档支持................................................................ 55
13.2 接收文档更新通知 ................................................. 55
13.3 社区资源................................................................ 55
13.4 商标....................................................................... 55
13.5 静电放电警告......................................................... 55
13.6 Glossary................................................................ 55
14 机械、封装和可订购信息....................................... 56
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 10
7.7 Typical Characteristics............................................ 11
Parameter measurement Information ................ 13
Detailed description............................................. 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 15
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2017 年 3 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
TAS6424L-Q1
www.ti.com.cn
ZHCSG71 –MARCH 2017
5 Device Comparison Table
PART
CHANNEL
COUNT
POWER-SUPPLY
VOLTAGE RANGE
OUTPUT CURRENT
LIMIT
MAXIMUM PWM
FREQUENCY
INPUT TYPE
NUMBER
TAS6424L-Q1
TAS6424-Q1
TAS6422-Q1
TAS5414C-Q1
TAS5424C-Q1
Digital
Digital
4
4
2
4
4
4.5 V to 18 V
4.5 V to 26.4 V
4.5 V to 26.4 V
5.6 V to 24 V
5.6 v to 24 V
4.8 A
6.5 A
2.1 MHz
2.1 MHz
2.1 MHz
500 kHz
500 kHz
Digital
6.5 A
Analog, Single-Ended
Analog, Differential
12.7 A
12.7 A
Copyright © 2017, Texas Instruments Incorporated
3
TAS6424L-Q1
ZHCSG71 –MARCH 2017
www.ti.com.cn
6 Pin Configuration and Functions
DKQ Package
56-Pin HSSOP With Exposed Thermal Pad
Top View
GND
PVDD
VBAT
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PVDD
2
PVDD
3
BST_4P
OUT_4P
GND
AREF
4
VREG
VCOM
AVSS
5
6
OUT_4M
BST_4M
GND
7
AVDD
GVDD
GVDD
GND
8
9
BST_3P
OUT_3P
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MCLK
SCLK
OUT_3M
BST_3M
PVDD
FSYNC
SDIN1
SDIN2
GND
Thermal
Pad
PVDD
BST_2P
OUT_2P
GND
GND
VDD
OUT_2M
BST_2M
GND
SCL
SDA
I2C_ADDR0
I2C_ADDR1
STANDBY
MUTE
FAULT
WARN
GND
BST_1P
OUT_1P
GND
OUT_1M
BST_1M
PVDD
PVDD
Not to scale
4
Copyright © 2017, Texas Instruments Incorporated
TAS6424L-Q1
www.ti.com.cn
ZHCSG71 –MARCH 2017
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
4
AREF
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
DO
VREG and VCOM bypass capacitor return
AVDD
8
Voltage regulator bypass
AVSS
7
AVDD bypass capacitor return
BST_1M
BST_1P
BST_2M
BST_2P
BST_3M
BST_3P
BST_4M
BST_4P
FAULT
FSYNC
31
35
37
41
44
48
50
54
26
14
1
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Reports a fault (active low, open drain), 100-kΩ internal pullup resistor
Audio frame clock input
DI
11
17
18
28
33
36
39
46
49
52
9
GND
GND
Ground
Gate drive voltage regulator for channel 3 and 4, derived from VBAT input pin.
Gate drive voltage regulator for channel 1 and 2, derived from VBAT input pin.
GVDD
PWR
DI
10
22
23
12
25
32
34
38
40
45
47
51
53
2
I2C_ADDR0
I2C_ADDR1
MCLK
I2C address pins
DI
Audio master clock input
MUTE
DI
Mutes the device outputs (active low), 100-kΩ internal pulldown resistor
Negative output for the channel
Positive output for the channel
OUT_1M
OUT_1P
OUT_2M
OUT_2P
OUT_3M
OUT_3P
OUT_4M
OUT_4P
NO
PO
NO
PO
NO
PO
NO
PO
Negative output for the channel
Positive output for the channel
Negative output for the channel
Positive output for the channel
Negative output for the channel
Positive output for the channel
29
30
42
43
55
56
PVDD
PWR
PVDD voltage input (can be connected to battery)
(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/O = digital input
and output, NC = no connection
Copyright © 2017, Texas Instruments Incorporated
5
TAS6424L-Q1
ZHCSG71 –MARCH 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SCL
NO.
20
13
21
15
16
24
3
DI
DI
I2C clock input
SCLK
SDA
Audio bit and serial clock input
I2C data input and output
TDM data input and audio I2S data input for channels 1 and 2
Audio I2S data input for channels 3 and 4
Enables low power standby state (active Low), 100-kΩ internal pulldown resistor
Battery voltage input
DI/O
DI
SDIN1
SDIN2
STANDBY
VBAT
VCOM
VDD
DI
DI
PWR
PWR
PWR
PWR
DO
6
Bias voltage
19
5
3.3-V external supply voltage
VREG
WARN
Voltage regulator bypass
27
Clip and overtemperature warning (active low, open drain), 100-kΩ internal pullup resistor
Provides both electrical and thermal connection for the device. Heatsink must be connected to
GND.
Thermal Pad
—
GND
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–1
MAX
30
UNIT
PVDD, VBAT DC supply voltage relative to GND
V
V
VMAX
Transient supply voltage: PVDD, VBAT
Supply-voltage ramp rate: PVDD, VBAT
DC supply voltage relative to GND
t ≤ 400 ms exposure
40
VRAMP
VDD
75
V/ms
V
–0.3
3.5
±8
IMAX
Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND)
Pulsed supply current per PVDD pin (one shot) t < 100 ms
A
IMAX_PULSED
±12
A
Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE,
STANDBY, I2C_ADDRx)
VLOGIC
–0.3
VDD + 0.5
V
VGND
TJ
Maximum voltage between GND pins
Maximum operating junction temperature
Storage temperature
±0.3
150
150
V
–55
–55
°C
°C
Tstg
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100–002(1)
Charged-device model (CDM), per AEC Q100–011
±3000
±500
Electrostatic
V(ESD)
All pins
V
discharge
Corner pins (1, 28, 29 and 56)
±1000
(1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.
6
Copyright © 2017, Texas Instruments Incorporated
TAS6424L-Q1
www.ti.com.cn
ZHCSG71 –MARCH 2017
7.3 Recommended Operating Conditions
MIN
4.5
NOM
MAX
18
UNIT
V
PVDD
VBAT
VDD
TA
Output FET supply voltage
Battery supply voltage input
DC logic supply
Relative to GND
Relative to GND
Relative to GND
4.5
14.4
3.3
18
V
3.0
3.5
125
V
Ambient temperature
–40
°C
An adequate thermal design is
required
TJ
Junction temperature
–40
150
°C
BTL Mode
2
1
1
4
2
RL
Nominal speaker load impedance
Ω
PBTL Mode
I2C pullup resistance on SDA and SCL pins
External capacitance on bypass pins
RPU_I2C
CBypass
COUT
LO
4.7
1
10
kΩ
µF
µF
Pin 2, 3, 5, 6, 8, 9, 10, 19
External capacitance to GND on OUT pins
Limit set by DC-diagnostic timing
1
3.3
Minimum inductance at ISD current
levels
Output filter inductance
1
µH
7.4 Thermal Information
TAS6424L-Q1(2) TAS6424L-Q1(3)
THERMAL METRIC(1)
DKQ (HSSOP)
DKQ (HSSOP) UNIT
56 PINS
56 PINS
—
RθJA
Junction-to-ambient thermal resistance
—
1.1
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.7
—
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
ψJB
10
10
—
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) JEDEC Standard 4 Layer PCB.
(3) Measured using the TAS6424L-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.
7.5 Electrical Characteristics
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see 图 59 and 图 62
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE
IVBAT_IDLE
IPVDD_STBY
IVBAT_STBY
IVDD
PVDD idle current
All channels playing, no audio input
75
90
1
90
100
10
mA
mA
μA
VBAT idle current
All channels playing, no audio input
STANDBYActive, VDD = 0 V
PVDD standby current
VBAT standby current
VDD supply current
STANDBYActive, VDD = 0 V
4
10
μA
All channels playing, –60-dB signal
15
18
mA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C
4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C
2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C
2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C
20
25
20
25
30
40
35
45
50
60
60
75
22
27
22
27
33
45
40
50
52
62
65
80
PO_BTL
Output power per channel, BTL
W
Output power per channel in parallel mode,
PBTL
PO_PBTL
W
Copyright © 2017, Texas Instruments Incorporated
7
TAS6424L-Q1
ZHCSG71 –MARCH 2017
www.ti.com.cn
Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see 图 59 and 图 62
PARAMETER
Power efficiency
AUDIO PERFORMANCE
TEST CONDITIONS
MIN
TYP MAX UNIT
4 channels operating, 25-W output power/ch 4-Ω load, PVDD
= 14.4 V, TC = 25°C, including indcutor losses(1)
EFFP
86%
Zero input, A-weighting, gain level 1, PVDD = 14.4 V
Zero input, A-weighting, gain level 2, PVDD = 14.4 V
Zero input, A-weighting, gain level 3, PVDD = 18 V
Zero input, A-weighting, gain level 4, PVDD = 25 V
Gain level 1, Register 0x01, bit 1-0 = 00
42
55
μV
67
Vn
Output noise voltage
85
7.5
Gain level 2, Register 0x01, bit 1-0 = 01
15
GAIN
Peak output voltage/dBFS
V/FS
21
Gain level 3, Register 0x01, bit 1-0 = 10
Gain level 4, Register 0x01, bit 1-0 = 11
29
Crosstalk
PSRR
Channel crosstalk
PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz
-90
75
-75
dB
dB
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz
0.05
%
THD+N
GCH
Total harmonic distortion + noise
Channel-to-channel gain variation
0.02%
0
–0.5
0.5
dB
LINE OUTPUT PERFORMANCE
Vn_LINEOUT LINE output noise voltage
VO_LINEOUT LINE output voltage
Zero input, A-weighting, channel set to LINE MODE
0-dB input, channel set to LINE MODE
42
μV
5.5
VRMS
0.03
%
THD+N
Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE
0.01%
DIGITAL INPUT PINS
VIH
VIL
IIH
Input logic level high
70
%VDD
Input logic level low
30 %VDD
Input logic current, high
Input logic current, low
VI = VDD
VI = 0
15
µA
µA
IIL
–15
PWM OUTPUT STAGE
RDS(on)
FET drain-to-source resistance
Not including bond wire and package resistance
90
mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV
PVDD overvoltage shutdown
19.3
19.3
20
0.8
20
22
22
V
V
V
V
VPVDD_OV_HY
PVDD overvoltage shutdown hysteresis
VBAT overvoltage shutdown
S
VVBAT_OV
VVBAT_OV_HY
VBAT overvoltage shutdown hysteresis
0.6
S
UNDERVOLTAGE (UV) PROTECTION
VBATUV VBAT undervoltage shutdown
VBATUV_HYS VBAT undervoltage shutdown hysteresis
4
0.2
4
4.5
4.5
V
V
V
PVDDUV
PVDD undervoltage shutdown
PVDDUV_HY
PVDD undervoltage shutdown hysteresis
0.2
V
S
BYPASS VOLTAGES
VGVDD
VAVDD
VVCOM
VVREG
Gate drive bypass pin voltage
7
6
V
V
V
V
Analog bypass pin voltage
Common bypass pin voltage
Regulator bypass pin voltage
2.5
5.5
POWER-ON RESET (POR)
VPOR
VDD voltage for POR
VDD POR recovery hysteresis voltage
2.1
0.5
2.7
V
V
VPOR_HY
OVERTEMPERATURE (OT) PROTECTION
OTW(i) Channel overtemperature warning
150
°C
8
Copyright © 2017, Texas Instruments Incorporated
TAS6424L-Q1
www.ti.com.cn
ZHCSG71 –MARCH 2017
Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see 图 59 and 图 62
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
OTSD(i)
OTW
Channel overtemperature shutdown
Global junction overtemperature warning
Global junction overtemperature shutdown
Overtemperature hysteresis
175
130
160
15
°C
°C
°C
°C
Set by register 0x01 bit 5-6, default value
OTSD
OTHYS
LOAD OVER CURRENT PROTECTION
OC Level 1
3
3
4.8
6
ILIM
Overcurrent cycle-by-cycle limit
Overcurrent shutdown
A
A
OC Level 2
4.2
OC Level 1, Any short to supply, ground, or other channels
OC Level 2, Any short to supply, ground, or other channels
ISD
7
MUTE MODE
GMUTE
Output attenuation
100
7
dB
mV
CLICK AND POP
VCP
Output click and pop voltage
ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z
DC OFSET
VOFFSET
Output offset voltage
2
5
mV
DC DETECT
DCFAULT
Output DC fault protection
2
2.5
V
DIGITAL OUTPUT PINS
VOH
VOL
Output voltage for logic level high
I = ±2 mA
I = ±2 mA
90
%VDD
Output voltage for logic level low
10 %VDD
tDELAY_CLIPD
Signal delay when output clipping detected
20
μs
ET
LOAD DIAGNOSTICS
Maximum resistance to detect a short from
OUT pins to PVDD
S2P
S2G
500
Ω
Ω
Maximum resistance to detect a short from
OUT pins to ground
200
SL
Shorted load detection tolerance
Open load
Other channels in Hi-Z
Other channels in Hi-Z
All 4 Channels
±0.5
Ω
OL
40
70
Ω
TDC_DIAG
LO
DC diagnostic time
Line output
230
ms
kΩ
ms
6
TLINE_DIAG
Line output diagnostic time
40
25%
±0.5
520
Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω,
ACIMP
AC impedance accuracy
AC diagnostic time
Offset
Ω
TAC_DIAG
All 4 Channels
ms
I2C_ADDR PINS
Time delay needed for I2C address set-up
tI2C_ADDR
300
μs
(1) Tested with Output Inductor DFEG7030D-3R3M.
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7.6 Timing Requirements
Test conditions (unless otherwise noted): TC = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see 图 59 and 图 62
MIN
TYP MAX UNIT
I2C CONTROL PORT (See 图 22)
tBUS
Bus free time between start and stop conditions
1.3
0
μs
ns
μs
tHOLD1
tHOLD2
tSTART
tRISE
tFALL
tSU1
Hold time, SCL to SDA
Hold time, start condition to SCL
I2C startup time after VDD power on reset
Rise time, SCL and SDA
0.6
12
300
300
ms
ns
ns
ns
μs
μs
μs
μs
Fall time, SCL and SDA
Setup, SDA to SCL
100
0.6
0.6
0.6
1.3
tSU2
Setup, SCL to start condition
Setup, SCL to stop condition
Required pulse duration SCL High
Required pulse duration SCL Low
tSU3
tW(H)
tW(L)
SERIAL AUDIO PORT (See 图 16)
DMCLK
DSCLK
,
Allowable input clock duty cycle
45%
128
50%
55%
ƒMCLK
Supported MCLK frequencies: 128, 256, or 512
Maximum frequency
512
25
xFS
MHz
ns
ƒMCLK_Max
tSCY
tSCL
tSCH
trise/fall
tSF
SCLK pulse cycle time
40
16
16
4
SCLK pulse-with LOW
ns
SCLK pulse-with HIGH
ns
Rise and fall time
ns
SCLK rising edge to FSYNC edge
FSYNC rising edge to SCLK edge
DATA set-up time
8
ns
tFS
8
ns
tDS
8
ns
tDH
DATA hold time
8
ns
ci
Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2
10
30
12
pF
FSYNC = 44.1 kHz or 48 kHz
FSYNC = 96 kHz
Latency from input to output measured in FSYNC
sample count
TLA
10
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7.7 Typical Characteristics
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 59 and 图 62 (unless otherwise noted)
0
-20
0
-20
Ch 1 to Ch 2
Ch 2 to Ch 1
-40
-40
-60
-60
-80
-80
-100
-120
-100
20
100
1k
10k 20k
20
100
1k
10k
Frequency (Hz)
Frequency
D002
D068
PO = 1 W
PO = 1 W
图 2. PVDD PSRR vs Frequency
图 1. Crosstalk vs Frequency
10
1
0
-20
2 W Load
4 W Load
-40
-60
0.1
-80
0.01
-100
-120
0.001
20
100
1k
10k 20k
10
100
1k
10k
Frequency
Frequency (Hz)
D070
D001
PO = 1 W
图 3. VBAT PSRR vs Frequency
PO = 1 W
fSW = 2.1 MHz
图 4. THD+N vs Frequency
10
1
10
1
2 W Load
4 W Load
2 W Load
4 W Load
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
10
50
10
100
1k
10k
Output Power (W)
Frequency (Hz)
D056
D002
fSW = 2.1 MHz
PO = 1 W
18 V
fSW = 2.1 MHz
图 6. THD+N vs Power
图 5. THD+N vs Frequency
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Typical Characteristics (接下页)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 59 and 图 62 (unless otherwise noted)
160
Gain Level 1
Gain Level 2
Gain Level 3
Gain Level 4
150
140
130
120
110
100
90
80
70
60
50
50
40
30
20
10
0
2 W Load
4 W Load
40
30
20
10
0
5
7
9
11
13
15
17 18
Supply Voltage (V)
5
7
9
11
13
15
17 18
D062
Supply Voltage (V)
A-weighted Noise
fSW = 2.1 MHz
D059
10% THD
fSW = 2.1 MHz
图 8. Noise vs Supply voltage
图 7. Output Power vs Supply Voltage
100
95
90
85
80
75
70
65
50
40
30
20
10
0
60
6
FPWM = 2.1 MHz
15 18
8
10
12
14
16
18
Supply Voltage (V)
D026
5
10
Supply Voltage (V)
D071
图 10. VBAT Idle Current vs Voltage
图 9. PVDD Idle Current vs Voltage
5
4
3
2
1
0
10
1
2 W Load
4 W Load
0.1
0.01
0.001
5
10
15
18
10
100
1k
10k
Supply Voltage (V)
Frequency (Hz)
D073
D006
PO = 1 W
fSW = 2.1 MHz
图 11. PVDD Standby Current vs Voltage
图 12. PBTL THD+N vs Frequency
12
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Typical Characteristics (接下页)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 59 and 图 62 (unless otherwise noted)
10
90
80
70
60
50
40
30
20
10
0
2 W Load
4 W Load
1
0.1
0.01
2 W Load
4 W Load
0.001
5
10
15
18
10m
100m
1
10
100
Supply Voltage (V)
Output Power (W)
D079
D008
10 % THD
fSW = 2.1 MHz
fSW = 2.1 MHz
图 14. PBTL Output Power vs Voltage
图 13. PBTL THD+N vs Power
8 Parameter measurement Information
The parameters for the TAS6424L-Q1 device were measured using the circuit in 图 59.
For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6424L-Q1 EVM is used.
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9 Detailed description
9.1 Overview
The TAS6424L-Q1 device is a four-channel digital-input Class-D audio amplifier for use in the automotive
environment. The device is designed for vehicle battery operation. The design uses ultra-efficient class-D
technology developed by Texas Instruments specifically tailored for the automotive industry. This technology
allows for reduced power consumption, reduced PCB area, reduced heat, and reduced peak currents in the
electrical system. The device realizes an audio sound-system design with smaller size and lower weight than
traditional class-AB solutions.
The core design blocks are as follows:
•
•
•
•
•
•
•
•
•
•
Serial audio port
Clock management
High-pass filter and volume control
Pulse width modulator (PWM) with output stage feedback
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
9.2 Functional Block Diagram
VDD
VCOM VREG
VBAT
GVDD
PVDD
MUTE
Gate Drive
Regulator
Reference
Regulators
STANDBY
Digital Core
WARN
Closed Loop Class D Amplifier
OUT_1P
OUT_1M
Channel 1
Powerstage
FAULT
Digital to PWM
MCLK
SCLK
OUT_2P
OUT_2M
OUT_3P
OUT_3M
Channel 2
Powerstage
Serial
Audio
Port
Volume Control
-100 to +24 dB
0.5 dB steps
Gate
Drives
FSYNC
SDIN1
SDIN2
Channel 3
Powerstage
Clip
Detection
OUT_4P
OUT_4M
Channel 4
Powerstage
PLL and Clock
Management
Protection
DC Load Diagnostics
Short to GND
Short to Power
Open Load
Overcurrent Limit
Overcurrent
SCL
SDA
2
I C Control
Overtemperature
I2C_ADDR0
I2C_ADDR1
Overvoltage and Undervoltage
DC Detection
Shorted Load
AC Load Diagnostics
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9.3 Feature Description
9.3.1 Serial Audio Port
The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.
Settings for the serial audio port are programmed in the SAP control register (address 0x03), see the SAP
Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04] section.
图 15 shows the digital audio data connections for I2S and TDM8 mode for an eight channel system.
i2S
TDM8
SOC
MCLK
SOC
MCLK
Device A
MCLK
Device A
MCLK
SCLK
FSYNC
DATA1
DATA2
DATA3
DATA4
SCLK
SCLK
FSYNC
DATA
SCLK
FSYNC
SDIN1
SDIN2
FSYNC
SDIN1
SDIN2
Device B
Device B
MCLK
SCLK
MCLK
SCLK
FSYNC
SDIN1
SDIN2
FSYNC
SDIN1
SDIN2
图 15. Digital-Audio Data Connection
9.3.1.1 I2S Mode
I2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when the
data is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit
clock, SCLK, runs at 32 × fS or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from the
time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2s-
complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.
9.3.1.2 Left-Justified Timing
Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel
and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the right
channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on the
data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bit
clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right
(L/R) frame with zeros.
9.3.1.3 Right-Justified Timing
Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left
channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the
right channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on
the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always
clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the
rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.
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Feature Description (接下页)
9.3.1.4 TDM Mode
TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM
clocks are present. The device can be configured through I2C to use different stereo pairs in the TDM data
stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.
In TDM mode, the SCLK pin must be 128 or 256, depending on the TDM slot size. In TDM mode SCLK and
MCLK can be connected together. If SCLK and MCLK are connected together than FSYNC should be minimum
2 MCLK pulses long.
In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused
SDIN2 pin (pin 16) to ground. 表 1 lists register settings for the TDM channel selection.
表 1. TDM Channel Selection
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
1
2
3
4
5
6
7
8
0
1
0
1
0
0
1
1
CH1
—
CH2
—
CH3
—
CH4
—
—
CH1
—
—
CH2
—
—
CH3
—
—
CH4
—
CH3
—
CH4
—
CH1
—
CH2
—
CH3
CH4
CH1
CH2
If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to 表 2.
表 2. TDM Channel Selection in PBTL Mode
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
0x21
BIT 6
1
2
3
4
5
6
7
8
PBTL
CH1/2
PBTL
CH3/4
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
0
1
1
0
0
1
1
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
9.3.1.5 Supported Clock Rates
The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.
The device supports SCLK rates of 32 × fSor 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM
mode.
The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × fS.
The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x
and 512x 50% duty is not required.
16
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9.3.1.6 Audio-Clock Error Handling
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all
channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically
returns to the state it was in. See the Timing Requirements table for timing requirements.
FSYNC
(Input)
0.5 × DVDD
t
t
t
FS
SCH
SCL
SCLK
(Input)
0.5 × DVDD
t
t
SF
SCY
DATA
(Input)
0.5 × DVDD
t
t
DH
DS
图 16. Serial Audio Timing
1/f
S
FSYNC
SCLK
L-channel
R-channel
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
0
1
30 31
LSB
SDIN
MSB
LSB
MSB
图 17. Left-Justified Audio Data Format
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1/f
S
FSYNC
L-channel
R-channel
SCLK
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
LSB
0
1
30 31
SDIN
MSB
MSB
LSB
图 18. I2S Audio Data Format
18
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1/Fs (256 sbclks)
FSYNC
SCLK
SDIN (Left justified)
SDIN (I2S mode)
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
1
0
1
23
22
23
22
0
22
0
22
0
22
0
22
0
22
0
22
0
22
0
22
32 sbclks
32 sbclks
32 sbclks
32 sbclks
32 sbclks
32 sbclks
32 sbclks
32 sbclks
Audio Data Format: TDM8 mode
图 19. TDM8 Audio Data Format
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9.3.2 High-Pass Filter
Direct-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter to
remove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz, or 15 Hz to 30 Hz with
bits 0 through 3 in register 0x26. The default value of –3 dB is approximately 4 Hz for 44.1 kHz or 48 kHz and
approximately 8 Hz for 96 kHz sampling rates.
9.3.3 Volume Control and Gain
Each channel has a independent digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps.
The volume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1,
2, 4, or 8 FSYNC cycles.
The peak output-voltage swing is also configurable in the gain control register through I2C. The four gain settings
are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expected PVDD operation
to optimize output noise and dynamic range performance.
9.3.4 High-Frequency Pulse-Width Modulator (PWM)
The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is an
advanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching rate
is synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48× the
input-sample rate. The option to switch at high frequency allows the use of smaller and lower cost external
filtering components. 表 3 lists the switch frequency options for bits 4 through 6 in the miscellaneous control 2
register (address 0x02).
表 3. Output Switch Frequency Option
INPUT SAMPLE RATE
BIT 6:4 SETTINGS
010 to 100
000
001
101
110
111
44.1 kHz
48 kHz
96 kHz
352.8 kHz
384 kHz
384 kHz
441 kHz
480 kHz
480 kHz
RESERVED
RESERVED
RESERVED
1.68 MHz
1.82 MHz
1.82 MHz
1.94 MHz
2.11 MHz
2.11 MHz
2.12 MHz
Not supported
Not supported
9.3.5 Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power-
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected at
pin 9 and pin 10.
The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for the
proper operation of the high side NMOS transistors. A 1 µF ceramic capacitor of quality X7R or better, rated for
at least 16 V, must be connected from each output to the corresponding bootstrap input (see the application
circuit diagram in 图 59). The bootstrap capacitors connected between the BST pins and corresponding output
function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each
high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high keeping the high-side
MOSFETs turned on.
9.3.6 Power FETs
The BTL output for each channel comprises four N-channel 90-mΩ FETs for high efficiency and maximum power
transfer to the load. These FETs are designed to handle the fast switching frequency and large voltage transients
during load dump.
20
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9.3.7 Load Diagnostics
The device incorporates both DC-load and AC-load diagnostics which are used to determine the status of the
load. The DC diagnostics are turned on by default but if a fast startup without diagnostics is required the DC
diagnostics can be bypassed through I2C. The DC diagnostics runs when any channel is directed to leave the Hi-
Z state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually to run on any or
all channels. DC Diagnostics can be started from any operating condition but if the channel is in play state then
the time to complete the diagnostic is longer because the device must ramp down the audio signal of that
channel before transitioning to the Hi-Z state. The DC diagnostics are available as soon as the device supplies
are within the recommended operating range. The DC diagnostics do not rely on the audio input clocks to be
available to function. DC Diagnostic results are reported for each channel separately through the I2C registers.
9.3.7.1 DC Load Diagnostics
The DC load diagnostics are used to verify the load connected. The DC diagnostics consists of four tests: short-
to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests trigger if
the impedance to GND or a power rail is below that specified in the Specifications section. The diagnostic
detects a short to vehicle battery even when the supply is boosted. The SL test has an I2C-configurable threshold
depending on the expected load to be connected. Because the speakers connected to each channel might be
different, each channel can be assigned a unique threshold value. The OL test reports if the select channel has a
load impedance greater than the limits in the Specifications section.
Open Load
Open Load Detected
OL Maximum
Open Load (OL)
Detection Threshold
Normal or Open Load
May Be Detected
OL Minimum
SL Maximum
SL Minimum
Normal Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Shorted Load Detected
图 20. DC Load Diagnostic Reporting Thresholds
9.3.7.2 Line Output Diagnostics
The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load
that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL
condition is detected on a channel, if the line output detection bit is also set, the channel checks if a line-output
load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.
9.3.7.3 AC Load Diagnostics
The AC load diagnostic is used to determine the proper connection of a capacitively coupled speaker or tweeter
when used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnostics
requires an external input signal and reports the approximate load impedance and phase. The selected signal
frequency should create current flow through the desired speaker for proper detection. If multiple channels must
be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.
For load-impedance detection, use the following test procedure:
1. Set the channels to be tested into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency
(recommended 10 kHz to 20 kHz).
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注
The device ramps the signal up and down automatically to prevent pops and clicks.
4. Set the device into the AC diagnostic mode (set bits 3:0 in register 0x15 to 1 for CH1 to CH4, set bit 3 in
register 0x15 to 1, and set bit 1 in register 0x15 to 1 for PBTL12 and PBTL34).
5. Read back the AC impedance (register 0x17 through register 0x1A).
When the test is complete the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:
•
BTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Apply a 0-dBFS 19K signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of
CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register
0x15 to 1)
3. Read back the AC_LDG_PHASE1 value (register 0x1B and register 0x1C).
When the test is complete, the channel reporting register indicates the status change from the AC
diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
•
PBTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL
mode only for load diagnostics.
3. Apply a 0 dBFS 19K signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of
CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in
register 0x15 to 1).
4. Read back the AC_LDG_PHASE1 (register 0x1B and register 0x1C).
5. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load
diagnostics.
表 4. AC Impedance Code to Magnitude
MAPPING FROM CODE
MEASUREMENT RANGE
SETTING
GAIN AT 19 kHz
I(A)
TO MAGNITUDE
(Ω)
(Ω/Code)
Gain = 4, I = 10 mA
(recommended)
4.28
4.28
1
0.01
0.019
0.01
12
6
0.05832
0.0307
0.2496
0.1314
Gain = 4, I = 19 mA
Gain = 1, I = 10 mA
(recommended)
48
24
Gain = 1, I = 19 mA
1
0.019
9.3.8 Protection and Monitoring
9.3.8.1 Overcurrent Limit (ILIMIT
)
The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT) is
exceeded. Power is limited but operation continues without disruption and prevents undesired shutdown for
transient music events. ILIMIT is not reported as a fault condition to either registers or the FAULT pin. Each
channel is independently monitored and limited. The two programable levels can be set by bit 4 in the
miscellaneous control 1 register (address 0x01).
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9.3.8.2 Overcurrent Shutdown (ISD
)
If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs which
shuts down the channel. The time to shutdown the channel varies depending on the severity of the short
condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT
pin is asserted. If the diagnostics are enabled then the device automatically starts diagnostics on the channel
and, if no load failure is found, the device restarts. If a load fault is found the device continues to rerun the
diagnostics once per second. Because this hiccup mode is using the diagnostics, no high current is created. If
the diagnostics are disabled the device sets the state for that channel to Hi-Z and requires the MCU to take the
appropriate action.
Two programable levels can be set by bit 4 in the miscellaneous control 1 register (address 0x01).
9.3.8.3 DC Detect
This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC
offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I2C register, and
the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.
9.3.8.4 Clip Detect
The clip detect is reported on the WARN pin if 100% duty-cycle PWM if reached for a minimum of 20 cycles. If
any channel is clipping, the clipping is reported to the pin. The clip detect is latched and can be cleared by I2C .
Masking the clip reporting to the pin is possible through I2C.
9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
Four overtemperature warning levels are available in the device that can be selected (see the Register Maps
section for thresholds). When the junction temperature exceeds the warning level, the WARN pin is asserted
unless the mask bit has been set to disable reporting. The device functions until the OTSD value is reached at
which point all channels are placed in the Hi-Z state and the FAULT pin is asserted. When the junction
temperature returns to normal levels, the device automatically recovers and places all channels into the state
indicated by the register settings.
9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If a
channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted unless the
mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then that
channel goes to the Hi-Z state until the temperature drops below the OTW(i) threshold at which point the channel
goes to the state indicated by the state control register.
9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV
condition, the FAULT pin is asserted and the I2C register is updated. A power-on reset (POR) on the VDD pin
causes the I2C to goes to the high-impedance (Hi-Z) state and all registers are reset to default values. At power-
on or after a POR event, the POR warning bit and WARN pin are asserted.
9.3.8.8 Overvoltage (OV) and Load Dump
The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV
threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dump
voltage spikes.
9.3.9 Power Supply
The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:
VDD
This pin is a 3.3V supply pin that provides power to the low voltage circuitry.
VBAT
This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated
voltage rail in a boosted system within the recommended limits. For best performance, this rail
should be 10 V or higher. See the Recommended Operating Conditions table for the maximum
supply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs.
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PVDD
This pin is a high-voltage supply that can either be connected to the vehicle battery or to another
voltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be
within the recommended operating limits, even if that is below the VBAT supply, to allow for
dynamic voltage systems.
Several on-chip regulators are included generating the voltages necessary for the internal circuitry. The external
pins are provided only for bypass capacitors to filter the supply and should not be used to power other circuits.
The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings for
the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a
second ground path through the body diode in the output FETs.
9.3.9.1 Vehicle-Battery Power-Supply Sequence
The device can accept any sequence of the VBAT, PVDD and VDD supply.
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the
same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended
operating range. When removing power from the device, TI recommends to deassert the VDD supply first then
the VBAT, PVDD, or both supplies which provides the lowest click and pop performance.
9.3.10 Hardware Control Pins
The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.
9.3.10.1 FAULT
The FAULT pin reports faults and is active low under any of the following conditions:
•
•
•
•
Any channel faults (overcurrent or DC detection)
Overtemperature shutdown
Overvoltage or undervoltage conditions on the VBAT or PVDD pins
Clock errors
The FAULT pin is deactivated when none of the previously listed conditions exist.
Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the
setting of the pin and do not affect the register reporting or protection of the device. By default all faults are
reported to the pin. See the Register Maps section for a description of the mask settings.
This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.
9.3.10.2 WARN
This active-low output pin reports audio clipping, overtemperature warnings, and POR events.
Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks which results in
a 10-µs delay to report the onset of clipping. The warning bit is sticky and can be cleared by the CLEAR FAULT
bit (bit 7) in register 0x21.
An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature
warnings are set. The warning temperature can be set through bits 5 and 6 in register 0x01.
Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting
of the pin and do not affect the register reporting. By default both clipping and OTW are reported.
The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.
This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.
9.3.10.3 MUTE
This active-low input pin is used for hardware control of the mute and unmute function for all channels.
This pin has a 100 kΩ internal pulldown resistor.
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9.3.10.4 STANDBY
When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin
can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not
already in the Hi-Z state. The I2C bus goes into the high-impedance (Hi-Z) state when in STANDBY.
This pin has a 100 kΩ internal pulldown resistor.
9.4 Device Functional Modes
9.4.1 Operating Modes and Faults
The operating modes and faults are listed in the following tables.
表 5. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z
OSCILLATOR
Stopped
Active
I2C
Stopped
Active
Active
Active
Hi-Z
MUTE
Switching at 50%
Switching with audio
Active
PLAY
Active
表 6. Global Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
RESULT
POR
VBAT UV
PVDD UV
VBAT or PVDD OV
OTW
All
I2C + WARN pin
Standby
Voltage fault
Hi-Z, mute, normal
I2C + FAULT pin
Hi-Z
Thermal warning
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + WARN pin
I2C + FAULT pin
None
Hi-Z
OTSD
Thermal shutdown
表 7. Channel Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
Clipping
Overcurrent limiting
Overcurrent fault
DC detect
Warning
None
WARN pin
Protection
Current limit
Mute and play
Output channel fault
I2C + FAULT pin
Hi-Z
9.5 Programming
9.5.1 I2C Serial Communication Bus
The device communicates with the system processor through the I2C serial communication bus as an I2C slave-
only device. The processor can poll the device through I2C to determine the operating status, configure settings,
or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.
The device includes two I2C address pins, so up to four devices can be used together in a system with no
additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in 表 8.
表 8. I2C Addresses
DESCRIPTION
I2C ADDR1
I2C ADDR0
I2C Write
0xD4
I2C Read
0xD5
Device 0
Device 1
Device 2
Device 3
0
0
1
1
0
1
0
1
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
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9.5.2 I2C Bus Protocol
The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The
TAS6424L-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-
bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit
slave address and the read/write (R/W) bit to open communication with another device and then wait for an
acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and
SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and
stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the
bus.
R/
W
8-Bit Register Data for
Address (N)
8-Bit Register Data for
Address (N)
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
图 21. Typical I2C Sequence
t
t
t
r
t
f
w(H)
w(L)
SCL
t
t
h1
su1
SDA
图 22. SCL and SDA Timing
Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using
single-byte or multiple-byte data transfers.
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9.5.3 Random Write
As shown in 图 23, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer.
For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/W bit, the
device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to
the internal memory address being accessed. After receiving the address byte, the device again responds with
an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being
accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 23. Random Write Transfer
9.5.4 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in 图 24. After receiving each data byte, the device responds
with an acknowledge bit and the I2C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
A4 A3
A0
A6
A1
R/W ACK
A7
A6
A5
A1
ACK
D7
D0
ACK
D7
D0
ACK
D7
ACK
D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图 24. Sequential Write Transfer
9.5.5 Random Read
As shown in 图 25, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a read
occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be read. As
a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an
acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1,
indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an
acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 25. Random Read Transfer
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9.5.6 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in 图 26. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图 26. Sequential Read Transfer
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9.6 Register Maps
表 9. I2C Address Register Definitions
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Register Description
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Mode control
Miscellaneous control 1
Miscellaneous control 2
SAP control (serial audio-port control)
Channel state control
Channel 1 volume control
Channel 2 volume control
Channel 3 volume control
Channel 4 volume control
DC diagnostic control 1
DC diagnostic control 2
DC diagnostic control 3l
DC load diagnostic report 1 (channels 1 and 2)
DC load diagnostic report 2 (channels 3 and 4)
DC load diagnostic report 3-line output
Channel state reporting
Channel faults (overcurrent, DC detection)
Global faults 1
R
R
R
R
R
R
Global faults 2
R
Warnings
R/W
R/W
R/W
R
Pin control
AC load diagnostic control 1
AC load diagnostic control 2
AC load diagnostic report channel 1
AC load diagnostic report channel 2
AC load diagnostic report channels 3
AC load diagnostic report channels 4
AC load diagnostic phase report high
AC load diagnostic phase report low
AC load diagnostic STI report high
AC load diagnostic STI report low
RESERVED
R
R
R
R
R
R
R
R
R
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R
Miscellaneous control 3
Clip control
Go
Go
Go
Go
Go
Go
Clip window
Clip warning
ILIMIT status
Miscellaneous control 4
RESERVED
R/W
RESERVED
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9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
The Mode Control register is shown in 图 27 and described in 表 10.
图 27. Mode Control Register
7
6
5
4
3
2
1
0
RESET
R/W-0
RESERVED
R/W-0
PBTL CH34
R/W-0
PBTL CH12
R/W-0
CH1 LO MODE CH2 LO MODE CH3 LO MODE CH4 LO MODE
R/W-0 R/W-0 R/W-0 R/W-0
表 10. Mode Control Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0
0: Normal operation
1: Resets the device
6
5
RESERVED
PBTL CH34
R/W
R/W
0
0
RESERVED
0: Channels 3 and 4 are in BTL mode
1: Channels 3 and 4 are in parallel BTL mode
4
3
2
1
0
PBTL CH12
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0: Channels 1 and 2 are in BTL mode
1: Channels 1 and 2 are in parallel BTL mode
CH1 LO MODE
CH2 LO MODE
CH3 LO MODE
CH4 LO MODE
0: Channel 1 is in normal/speaker mode
1: Channel 1 is in line output mode
0: Channel 2 is in normal/speaker mode
1: Channel 2 is in line output mode
0: Channel 3 is in normal/speaker mode
1: Channel 3 is in line output mode
0: Channel 4 is in normal/speaker mode
1: Channel 4 is in line output mode
9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
The Miscellaneous Control 1 register is shown in 图 28 and described in 表 11.
图 28. Miscellaneous Control 1 Register
7
6
5
4
3
2
1
0
HPF BYPASS
R/W-0
OTW CONTROL
R/W-01
OC CONTROL
R/W-1
VOLUME RATE
R/W-00
GAIN
R/W-10
表 11. Misc Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
HPF BYPASS
R/W
0
0: High pass filter eneabled
1: High pass filter disabled
6–5
OTW CONTROL
R/W
01
00: Global overtemperature warning set to 140°C
01: Global overtemperature warning set to 130C
10: Global overtemperature warning set to 120°C
11: Global overtemperature warning set to 110°C
4
OC CONTROL
VOLUME RATE
R/W
R/W
1
0: Overcurrent is level 1
1: Overcurrent is level 2
3–2
00
00: Volume update rate is 1 step / FSYNC
01: Volume update rate is 1 step / 2 FSYNCs
10: Volume update rate is 1 step / 4 FSYNCs
11: Volume update rate is 1 step / 8 FSYNCs
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表 11. Misc Control 1 Field Descriptions (接下页)
Bit
Field
GAIN
Type
Reset
Description
1–0
R/W
10
00: Gain level 1 = 7.6 V peak output voltage
01: Gain Level 2 = 15 V peak output voltage
10: Gain Level 3 = 21 V peak output voltage
11: Gain Level 4 = 29 V peak output voltage
9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
The Miscellaneous Control 2 register is shown in 图 29 and described in 表 12.
图 29. Miscellaneous Control 2 Register
7
6
5
4
3
2
1
0
RESERVED
PWM FREQUENCY
R/W-110
RESERVED
SDM_OSR
R/W-0
OUTPUT PHASE
R/W-10
表 12. Misc Control 2 Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
0
7
6–4
PWM FREQUENCY
R/W
110
000: 8 × fS (352.8 kHz / 384 kHz)
001: 10 × fS (441 kHz / 480 kHz)
010: RESERVED
011: RESERVED
100: RESERVED
101: 38 × fS (1.68 MHz / 1.82 MHz)
110: 44 × fS (1.94 MHz / 2.11 MHz)
111: 48 × fS (2.12 MHz / not supported)
0
3
2
RESERVED
SDM_OSR
0
0
R/W
R/W
0: 64x OSR
1: 128x OSR
1–0
OUTPUT PHASE
10
00: 0 degrees output-phase switching offset
01: 30 degrees output-phase switching offset
10: 45 degrees output-phase switching offset
11: 60 degrees output-phase switching offset
9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
The SAP Control (serial audio-port control) register is shown in 图 30 and described in 表 13.
图 30. SAP Control Register
7
6
5
4
3
2
1
0
INPUT SAMPLING RATE
8 Ch TDM
SLOT SELECT
TDM SLOT
SIZE
TDM SLOT
SELECT 2
INPUT FORMAT
R/W-00
R/W-0
R/W-0
R/W-0
R/W-100
表 13. SAP Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
INPUT SAMPLING RATE
R/W
00
00: 44.1 kHz
01: 48 kHz
10: 96 kHz
11: RESERVED
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表 13. SAP Control Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
5
8 Ch TDM SLOT SELECT
R/W
0
0: First four TDM slots
1: Last four TDM slots
4
3
TDM SLOT SIZE
R/W
R/W
R/W
0
0: TDM slot size is 24-bit or 32-bit
1: TDM slot size is 16-bit
TDM SLOT SELECT 2
INPUT FORMAT
0
0: Normal
1: swap channel 1/2 with channel 3/4
2–0
100
000: 24-bit right justified
001: 20-bit right justified
010: 18-bit right justified
011: 16-bit right justified
100: I2S (16-bit or 24-bit)
101: Left justified (16-bit or 24-bit)
110: DSP mode (16-bit or 24-bit)
111: RESERVED
9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
The Channel State Control register is shown in 图 31 and described in 表 14.
图 31. Channel State Control Register
7
6
5
4
3
2
1
0
CH1 STATE CONTROL
R/W-01
CH2 STATE CONTROL
R/W-01
CH3 STATE CONTROL
R/W-01
CH4 STATE CONTROL
R/W-01
表 14. Channel State Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
5–4
3–2
1–0
CH1 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
CH2 STATE CONTROL
CH3 STATE CONTROL
CH4 STATE CONTROL
R/W
R/W
R/W
01
01
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
32
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9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
The Channel 1 Through 4 Volume Control registers are shown in 图 32 and described in 表 15.
图 32. Channel x Volume Control Register
7
6
5
4
3
2
1
0
CH x VOLUME
R/W-CF
表 15. Ch x Volume Control Field Descriptions
Bit
Field
CH x VOLUME
Type
Reset
Description
7–0
R/W
CF
8-Bit Volume Control for each channel, register address for Ch1
is 0x05, Ch2 is 0x06, Ch3 is 0x07 and Ch4 is 0x08, 0.5 dB/step:
0xFF: 24 dB
0xCF: 0 dB
0x07: –100 dB
< 0x07: MUTE
9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
The DC Diagnostic Control 1 register is shown in 图 33 and described in 表 16.
图 33. DC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
DC LDG
ABORT
2x_RAMP
2x_SETTLE
RESERVED
LDG LO
ENABLE
LDG BYPASS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 16. DC Load Diagnostics Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
DC LDG ABORT
R/W
0
0: Default state, clear after abort
1: Aborts the load diagnostics in progress
6
5
2x_RAMP
R/W
R/W
0
0
0: Normal ramp time
1: Double ramp time
2x_SETTLE
0: Normal Settle time
1: Double settling time
4–2
1
RESERVED
0
0
0
LDG LO ENABLE
R/W
R/W
0: Line output diagnostics are disabled
1: Line output diagnostics are enabled
0
LDG BYPASS
0
0: Automatic diagnostics when leaving Hi-Z and after
channel fault
1: Diagnostics are not run automatically
9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
The DC Diagnostic Control 2 register is shown in 图 34 and described in 表 17.
图 34. DC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
CH1 DC LDG SL
R/W-0001
CH2 DC LDG SL
R/W-0001
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表 17. DC Load Diagnostics Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH1 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH2 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
The DC Diagnostic Control 3 register is shown in 图 35 and described in 表 18.
图 35. DC Load Diagnostic Control 3 Register
7
6
5
4
3
2
1
0
CH3 DC LDG SL
R/W-0001
CH4 DC LDG SL
R/W-0001
表 18. DC Load Diagnostics Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH3 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH4 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
DC Load Diagnostic Report 1 register is shown in 图 36 and described in 表 19.
图 36. DC Load Diagnostic Report 1 Register
7
6
5
4
3
2
1
0
CH1 S2G
R-0
CH1 S2P
R-0
CH1 OL
R-0
CH1 SL
R-0
CH2 S2G
R-0
CH2 S2P
R-0
CH2 OL
R-0
CH2 SL
R-0
表 19. DC Load Diagnostics Report 1 Field Descriptions
Bit
Field
CH1 S2G
Type
Reset
Description
7
R
0
0: No short-to-GND detected
1: Short-To-GND Detected
34
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表 19. DC Load Diagnostics Report 1 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
6
CH1 S2P
CH1 OL
CH1 SL
CH2 S2G
CH2 S2P
CH2 OL
CH2 SL
R
0
0: No short-to-power detected
1: Short-to-power detected
5
4
3
2
1
0
R
R
R
R
R
R
0
0
0
0
0
0
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
0: No short-to-GND detected
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
The DC Load Diagnostic Report 2 register is shown in 图 37 and described in 表 20.
图 37. DC Load Diagnostic Report 2 Register
7
6
5
4
3
2
1
0
CH3 S2G
R-0
CH3 S2P
R-0
CH3 OL
R-0
CH3 SL
R-0
CH4 S2G
R-0
CH4 S2P
R-0
CH4 OL
R-0
CH4 SL
R-0
表 20. DC Load Diagnostics Report 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3 S2G
CH3 S2P
CH3 OL
CH3 SL
R
0
0: No short-to-GND detected
1: Short-to-GND detected
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
CH4 S2G
CH4 S2P
CH4 OL
CH4 SL
0: No short-to-GND detected
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
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9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
The DC Load Diagnostic Report, Line Output, register is shown in 图 38 and described in 表 21.
图 38. DC Load Diagnostics Report 3 Line Output Register
7
6
5
4
3
2
1
0
RESERVED
CH1 LO LDG
R-0
CH2 LO LDG
R-0
CH3 LO LDG
R-0
CH4 LO LDG
R-0
表 21. DC Load Diagnostics Report 3 Line Output Field Descriptions
Bit
Field
Type
Reset
Description
0
7–4
RESERVED
3
2
1
0
CH1 LO LDG
CH2 LO LDG
CH3 LO LDG
CH4 LO LDG
R
0
0
0
0
0: No line output detected on channel 1
1: Line output detected on channel 1
R
0: No line output detected on channel 2
1: Line output detected on channel 2
R
0: No line output detected on channel 3
1: Line output detected on channel 3
R
0: No line output detected on channel 4
1: Line output detected on channel 4
9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
The Channel State Reporting register is shown in 图 39 and described in 表 22.
图 39. Channel State-Reporting Register
7
6
5
4
3
2
1
0
CH1 STATE REPORT
R-01
CH2 STATE REPORT
R-01
CH3 STATE REPORT
R-01
CH4 STATE REPORT
R-01
表 22. State-Reporting Field Descriptions
Bit
Field
Type
Reset
Description
7–6
5–4
3–2
1–0
CH1 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
CH2 STATE REPORT
CH3 STATE REPORT
CH4 STATE REPORT
R
R
R
01
01
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
36
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9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
The Channel Faults (overcurrent, DC detection) register is shown in 图 40 and described in 表 23.
图 40. Channel Faults Register
7
6
5
4
3
2
1
0
CH1 OC
R-0
CH2 OC
R-0
CH3 OC
R-0
CH4 OC
R-0
CH1 DC
R-0
CH2 DC
R-0
CH3 DC
R-0
CH4 DC
R-0
表 23. Channel Faults Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 OC
R
0
0: No overcurrent fault detected
1: Overcurrent fault detected
6
5
4
3
2
1
0
CH2 OC
CH3 OC
CH4 OC
CH1 DC
CH2 DC
CH3 DC
CH4 DC
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
The Global Faults 1 register is shown in 图 41 and described in 表 24.
图 41. Global Faults 1 Register
7
6
5
4
3
2
1
0
RESERVED
INVALID
CLOCK
PVDD OV
VBAT OV
PVDD UV
VBAT UV
R-0
R-0
R-0
R-0
R-0
表 24. Global Faults 1 Field Descriptions
Bit
Field
Type
Reset
Description
0
7–5
RESERVED
0
4
3
2
1
INVALID CLOCK
R
0
0
0
0
0: No clock fault detected
1: Clock fault detected
PVDD OV
VBAT OV
PVDD UV
R
0: No PVDD overvoltage fault detected
1: PVDD overvoltage fault detected
R
0: No VBAT overvoltage fault detected
1: VBAT overvoltage fault detected
R
0: No PVDD undervoltage fault detected
1: PVDD undervoltage fault detected
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表 24. Global Faults 1 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
0
VBAT UV
R
0
0: No VBAT undervoltage fault detected
1: VBAT undervoltage fault detected
9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
The Global Faults 2 register is shown in 图 42 and described in 表 25.
图 42. Global Faults 2 Register
7
6
5
4
3
2
1
0
RESERVED
OTSD
R-0
CH1 OTSD
R-0
CH2 OTSD
R-0
CH3 OTSD
R-0
CH4 OTSD
R-0
表 25. Global Faults 2 Field Descriptions
Bit
Field
Type
Reset
Description
0
7–5
RESERVED
OTSD
4
3
2
1
0
R
0
0
0
0
0
0: No global overtemperature shutdown
1: Global overtemperature shutdown
CH1 OTSD
CH2 OTSD
CH3 OTSD
CH4 OTSD
R
0: No overtemperature shutdown on Ch1
1: Overtemperature shutdown on Ch1
R
0: No overtemperature shutdown on Ch2
1: Overtemperature shutdown on Ch2
R
0: No overtemperature shutdown on Ch3
1: Overtemperature shutdown on Ch3
R
0: No overtemperature shutdown on Ch4
1: Overtemperature shutdown on Ch4
9.6.17 Warnings Register (address = 0x13) [default = 0x20]
The Warnings register is shown in 图 43 and described in 表 26.
图 43. Warnings Register
7
6
5
4
3
2
1
0
RESERVED
VDD POR
R-0
OTW
R-0
OTW CH1
R-0
OTW CH2
R-0
OTW CH3
R-0
OTW CH4
R-0
表 26. Warnings Field Descriptions
Bit
Field
Type
Reset
Description
0
7 -6
5
RESERVED
00
VDD POR
R
0
0
0
0
0: No VDD POR has occurred
1 VDD POR occurred
4
3
2
OTW
R
0: No global overtemperature warning
1: Global overtemperature warning
OTW CH1
OTW CH2
R
0: No overtemperature warning on channel 1
1: Overtemperature warning on channel 1
R
0: No overtemperature warning on channel 2
1: Overtemperature warning on channel 2
38
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表 26. Warnings Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
1
OTW CH3
R
0
0: No overtemperature warning on channel 3
1: Overtemperature warning on channel 4
0
OTW CH4
R
0
0: No overtemperature warning on channel 4
1: Overtemperature warning on channel 4
9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
The Pin Control register is shown in 图 44 and described in 表 27.
图 44. Pin Control Register
7
6
5
4
3
2
1
0
MASK OC
R/W-1
MASK OTSD
R/W-1
MASK UV
R/W-1
MASK OV
R/W-1
MASK DC
R/W-1
MASK ILIMIT
R/W-1
MASK CLIP
R/W-1
MASK OTW
R/W-1
表 27. Pin Control Field Descriptions
Bit
Field
MASK OC
Type
Reset
Description
7
R/W
0
0: Report overcurrent faults on the FAULT pin
1: Do not report overcurrent faults on the FAULT Pin
6
5
4
3
2
1
0
MASK OTSD
MASK UV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0: Report overtemperature faults on the FAULT pin
1: Do not report overtemperature faults on the FAULT pin
0: Report undervoltage faults on the FAULT pin
1: Do not report undervoltage faults on the FAULT pin
MASK OV
0: Report overvoltage faults on the FAULT pin
1: Do not report overvoltage faults on the FAULT pin
MASK DC
0: Report DC faults on the FAULT pin
1: Do not report DC faults on the FAULT pin
MASK ILIMIT
MASK CLIP
MASK OTW
0: Report Ilimit on the FAULT pin
1: Do not report Ilimit on the FAULT pin
0: Report clipping on the WARN pin
1: Do not report clipping on the WARN pin
0: Report overtemperature warnings on the WARN pin
1: Do not report overtemperature warnings on the WARN pin
9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
The AC Load Diagnostic Control 1 register is shown in 图 45 and described in 表 28.
图 45. AC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
CH1 GAIN
R/W-0
RESERVED
R/W-0
CH3 GAIN
R/W-0
RESERVED
R/W-0
CH1 ENABLE
R/W-0
CH2 ENABLE
R/W-0
CH3 ENABLE
R/W-0
CH4 ENABLE
R/W-0
表 28. AC Load Diagnostic Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1, CH2, PBTL12: GAIN
RESERVED
R/W
0
0: Gain 1
1: Gain 4
0
6
R/W
0
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表 28. AC Load Diagnostic Control 1 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
5
CH3, CH4, PBTL34: GAIN
R/W
0
0: Gain 1
1: Gain 4
0
4
3
RESERVED
R/W
R/W
0
0
CH1 ENABLE
0: AC diagnostics disabled
1: Enable AC diagnostics
2
1
0
CH2 ENABLE
CH3 ENABLE
CH4 ENABLE
R/W
R/W
R/W
0
0
0
0: AC diagnostics disabled
1: Enable AC diagnostics
0: AC diagnostics disabled
1: Enable AC diagnostics
0: AC diagnostics disabled
1: Enable AC diagnostics
9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
The AC Load Diagnostic Control 2 register is shown in 图 46 and described in 表 29.
图 46. AC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
AC_DIAGS_LO
OPBACK
RESERVED
AC TIMING
AC CURRENT
RESERVED
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 29. AC Load Diagnostic Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
AC_DIAGS_LOOPBACK
R/W
0
0: disable AC Diag loopback
1: Enable AC Diag loopback
00
6-5
4
RESERVED
AC TIMING
R/W
R/W
00
0
0: 32 Cycles
1: 64 Cycles
3-2
AC CURRENT
R/W
00
00: 10mA
01: 19 mA
10: RESERVED
11: RESERVED
00
1-0
RESERVED
R/W
00
9.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A)
[default = 0x00]
The AC Load Diagnostic Report Ch1 through CH4 registers are shown in 图 47 and described in 表 30.
图 47. AC Load Diagnostic Impedance Report Chx Register
7
6
5
4
3
2
1
0
CHx IMPEDANCE
R-00
40
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表 30. Chx AC LDG Impedance Report Field Descriptions
Bit
Field
CH x IMPEDANCE
Type
Reset
Description
7–0
R
00
8-bit AC-load diagnostic report for each channel with a step size
of 0.2496 Ω/bit (control by register 0x15 and register 0x16)
0x00: 0 Ω
0x01: 0.2496 Ω
...
0xFF: 63.65 Ω
9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
The AC Load Diagnostic Phase High value registers are shown in 图 48 and described in 表 31.
图 48. AC Load Diagnostic (LDG) Phase High Report Register
7
6
5
4
3
2
1
0
0
0
AC Phase High
R-00
表 31. AC LDG Phase High Report Field Descriptions
Bit
Field
AC Phase High
Type
Reset
Description
7–0
R
00
Bit 15:8
9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
The AC Load Diagnostic Phase Low value registers are shown in 图 49 and described in 表 32.
图 49. AC Load Diagnostic (LDG) Phase Low Report Register
7
6
5
4
3
2
1
AC Phase Low
R-00
表 32. AC LDG Phase Low Report Field Descriptions
Bit
Field
AC Phase Low
Type
Reset
Description
7–0
R
00
Bit 7:0
9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
The AC Load Diagnostic STI High value registers are shown in 图 50 and described in 表 33.
图 50. AC Load Diagnostic (LDG) STI High Report Register
7
6
5
4
3
2
1
AC STI High
R-00
表 33. AC LDG STI High Report Field Descriptions
Bit
Field
AC STI High
Type
Reset
Description
7–0
R
00
Bit 15:8
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9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
The AC Load Diagnostic STI Low value registers are shown in 图 51 and described in 表 34.
图 51. AC Load Diagnostic (LDG) STI Low Report Register
7
6
5
4
3
2
1
0
AC STI Low
R-00
表 34. Chx AC LDG STI Low Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI Low
R
00
Bit 7:0
9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
The Miscellaneous Control 3 register is shown in 图 52 and described in 表 35.
图 52. Miscellaneous Control 3 Register
7
6
5
4
3
2
1
0
CLEAR FAULT PBTL_CH_SEL MASK ILIMIT
WARNING
RESERVED
OTSD AUTO
RECOVERY
RESERVED
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
表 35. Misc Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
CLEAR FAULT
R/W
0
0: Normal operation
1: Clear fault
PBTL_CH_SEL
R/W
R/W
0
0
0: PBTL normal signal source
1: PBTL flip signal source
MASK ILIMIT WARNING
0: Report ILIMIT on the WARN pin
1: Do not report ILIMIT on the WARN pin
4
3
RESERVED
R/W
R/W
0
0
OTSD AUTO RECOVERY
0: OTSD is latched
0: OTSD is autorecovery
2–0
RESERVED
0
0
9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
The Clip Detect register is shown in 图 53 and described in 表 36.
图 53. Clip Control Register
7
6
5
4
3
2
1
0
RESERVED
CLIPDET_EN
R/W-1
表 36. Clip Control Field Descriptions
Bit
Field
Type
Reset
Description
0
7-1
RESERVED
0
CLIPDET_EN
R/W
1
0: Clip detect disable
1: Clip Detect Enable
42
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9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
The Clip Window register is shown in 图 54 and described in 表 37.
图 54. Clip Window Register
7
6
5
4
3
2
1
0
CLIP_WINDOW_SEL[7:1]
R/W-00001110
表 37. Clip Window Field Descriptions
Bit
Field
CLIP_WINDOW_SEL[7:1]
Type
Reset
Description
7-0
R/W
00010100
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001110
00010100
9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
The Clip Window register is shown in 图 55 and described in 表 38.
图 55. Clip Warning Register
7
6
5
4
3
2
1
0
RESERVED
CH4_CLIP
R-0
CH3_CLIP
R-0
CH2_CLIP
R-0
CH1_CLIP
R-0
表 38. Clip Warning Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
0
RESERVED
3
2
1
0
CH4_CLIP
CH3_CLIP
CH2_CLIP
CH1_CLIP
R
0
0
0
0
0: No Clip Detect
1: Clip Detect
R
0: No Clip Detect
1: Clip Detect
R
0: No Clip Detect
1: Clip Detect
R
0: No Clip Detect
1: Clip Detect
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9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
The ILIMIT Status register is shown in 图 56 and described in 表 39.
图 56. ILIMIT Status Register
7
6
5
4
3
2
1
0
RESERVED
CH4_ILIMIT_W CH3_ILIMIT_W CH2_ILIMIT_W CH1_ILIMIT_W
ARN
ARN
ARN
ARN
R-0
R-0
R-0
R-0
表 39. ILIMIT Status Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
6
5
4
3
CH4_ILIMIT_WARN
CH3_ILIMIT_WARN
CH2_ILIMIT_WARN
CH1_ILIMIT_WARN
R
R
R
R
0: No ILIMIT
1: ILIMIT Warning
2
1
0
0
0
0
0: No ILIMIT
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
The Miscellaneous Control 4 register is shown in 图 57 and described in 表 40.
图 57. Miscellaneous Control 4 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-00000
HPF_CORNER[2:0]
R/W-000
表 40. Misc Control 4 Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
01000
01000: DEFAULT
2-0
HPF_CORNER[2:0]
R/W
000
000: 3.7 Hz
001: 7.4 Hz
010: 15 Hz
011: 30 Hz
100: 59 Hz
101: 118 Hz
110: 235 Hz
111: 463 Hz
44
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TAS6424L-Q1 is a four-channel class-D digital-input audio-amplifier design for use in automotive head units
and external amplifier modules. The TAS6424L-Q1 incorporates the necessary functionality to perform in
demanding OEM applications.
10.1.1 AM-Radio Band Avoidance
AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM
band. The switching frequency options available are 38 fs, 44 fs, and 48 fs. If the switch frequency cannot be set
above the AM band, then use the two options of 8 fs and 10 fs. These options should be changed to avoid AM
active channels.
10.1.2 Parallel BTL Operation (PBTL)
The device can drive more current-paralleling BTL channels on the load side of the LC output filter. For parallel
operation, the parallel BTL mode, PBTL, must be used and the paralleled channels must have the same state in
the state control register. If the two states are not aligned the device reports a fault condition.
To set the requested channels to PBTL mode the device must be in standby mode for the commands to take
effect.
A load diagnostic is supported for PBTL channels. Paralleling on the device side of the LC output filter is not
supported.
10.1.3 Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal.
The filter attenuates the high-frequency components of the output signals that are out of the audio band. The
design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to
meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully
considered.
10.1.4 Line Driver Applications
In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of
impedance) or an external amplifier input (with several kiloohms of impedance). The design is capable of
supporting both applications and has special line-drive gain and diagnostics. Coupled with the high switching
frequency, the device is well suited for this type of application. Set the desired channel in line driver mode
through I2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to
4.7 kΩ for the DC line diagnostic to detect the connected external amplifier. 图 58 shows the recommended
external amplifier input configuration.
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Application Information (接下页)
Output Filter
External Amplifier
3.3 µH
1 …F
1 …F
1 …F
1 nF
600 ꢀ
to
4.7 kꢀ
1 …F
1 nF
3.3 µH
100 kꢀ
100 kꢀ
图 58. External Amplifier Input Configuration for Line Driver
10.2 Typical Applications
10.2.1 BTL Application
图 59 shows the schematic of a typical 4-channel solution for a head-unit application.
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Typical Applications (接下页)
PVDD
Input
PVDD
1 •F
1 nF
470 •F
56
55
PVDD
PVDD
1
1 •F
GND
0.1 •F
10 •F
10 •F
10 •F
2
PVDD
PVDD
VBAT
AREF
VREG
PVDD
3
4
54
53
52
51
BST_4P
OUT_4P
GND
1 •F
L
L
5
C
C
1 nF
1 nF
1 •F
4 •
6
VCOM
OUT_4M
1 •F
50
49
7
1 •F
1 •F
BST_4M
GND
AVSS
AVDD
8
1 •F
48
47
46
45
9
BST_3P
OUT_3P
GND
GVDD
2.2 •F
L
L
10
GVDD
GND
C
C
1 nF
1 nF
2.2 •F
4 •
11
OUT_3M
12
13
MCLK
SCLK
44
43
1 •F
BST_3M
PVDD
PVDD
14
FSYNC
SDIN1
SDIN2
DSP
0.1 •F
42
15
16
PVDD
41
40
39
38
BST_2P
OUT_2P
GND
1 •F
17
18
GND
GND
L
L
C
C
1 nF
1 nF
4 •
19
VDD
SCL
VDD
OUT_2M
2 k•
2 k•
20
21
37
36
1 •F
1 •F
BST_2M
GND
SDA
22
23
I2C_ADDR0
35
34
33
32
BST_1P
OUT_1P
GND
L
L
I2C_ADDR1
MUTE
Micro
24
25
C
C
1 nF
1 nF
4 •
STANDBY
WARN
FAULT
GND
OUT_1M
26
27
28
31
30
1 •F
BST_1M
PVDD
PVDD
0.1 •F
29
PVDD
图 59. TAS6424L-Q1 Typical 4-Channel BTL Application Schematic
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Typical Applications (接下页)
10.2.1.1 Design Requirements
Use the following requirements for this design:
•
•
•
This head-unit example is focused on the smallest solution size for 4 × 25 W output power into 4 Ω with a
battery supply of 14.4 V.
The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
10.2.1.2 Communication
All communications to the TAS6424L-Q1 are through the I2C protocol. A system controller can communicate with
the device through the SDA pins and SCL pins. The TAS6424L-Q1 is an I2C slave device and requires a master.
The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the
device is 400 kHz. If multiple TAS6424L-Q1 devices are on the same I2C bus, the I2C address must be different
for each device. Up to four TAS6424L-Q1 devices can be on the same I2C bus.
The I2C bus is shared internally.
注
Complete any internal operations, such as load diagnostics, before reading the registers
for the results.
10.2.1.3 Detailed Design Procedure
10.2.1.3.1 Hardware Design
Use the following procedure for the hardware design:
•
Determine the input format. The input format can be either I2S or TDM mode. The mode determines the
correct pin connections and the I2C register settings.
•
Determine the power output that is required into the load. The power requirement determines the required
power-supply voltage and current. The output reconstruction-filter components that are required are also
driven by the output power.
•
With the requirements, adjust the typical application schematic in 图 59 for the input connections.
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Typical Applications (接下页)
10.2.1.3.2 Digital Input and the Serial Audio Port
The TAS6424L-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left
Justified, and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The
supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see 表 13 for the I2C register, SAP Control, for
the complete matrix to set up the serial audio port.
注
Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up
all the control registers to the system requirements should be done before the device is
placed in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21
to clear any faults. Then read the fault registers to make sure no faults are present. When
no faults are present, use register 0x04 to place the device properly into play mode.
10.2.1.3.3 Bootstrap Capacitors
The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be
sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the
capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less
than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for
driving subwoofers that require frequencies below 30 Hz may be necessary.
10.2.1.3.4 Output Reconstruction Filter
The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or
fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the
audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor
to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces
electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. refer to the Class-D
LC Filter Design, (SLOA119) for a detailed description of proper component description and design of the LC
filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency of the
LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as 100
kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency should be
less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value is given
at zero current, but the TAS6424L-Q1 device will have current. Use the inductance versus current curve for the
inductor to make sure the inductance does not drop below 1 µH (for fSW = 2.1 MHz) at the maximum current
provided by the system design. The DCR of the inductor directly affects the output power of the system design.
The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4 Ω system is 40
to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ.
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Typical Applications (接下页)
10.2.1.4 Application Curves
10
10
1
2 W Load
4 W Load
2 W Load
4 W Load
1
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
10
50
20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
D056
D006
1 kHz
PVDD = 14.4 V
1 W
PVDD = 14.4 V
图 60. THD vs Output Power
图 61. THD vs Frequency
10.2.2 PBTL Application
图 62 shows a schematic of a typical 2-channel solution for a head unit or external amplifier application where
high power into 2 Ω is required.
To operate in PBTL mode the output stage must be paralleled according to the schematic in 图 62. The device
can operate in a mix of PBTL and BTL mode. This application can be set up for 3-channels, with one channel in
PBTL mode and two channels in BTL mode. The device does not support a parallel configuration of all four
channels for a one channel amplifier.
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Typical Applications (接下页)
PVDD
Input
PVDD
1 •F
1 nF
470 •F
Chassis
GND
56
55
PVDD
PVDD
1
1 •F
GND
0.1 •F
10 •F
2
PVDD
PVDD
VBAT
AREF
VREG
PVDD
3
4
54
53
52
51
BST_4P
OUT_4P
GND
1 •F
L
L
5
C
C
1 •F
6
VCOM
OUT_4M
1 •F
50
49
7
1 •F
1 •F
BST_4M
GND
AVSS
AVDD
1 nF
1 nF
8
2 •
1 •F
48
47
46
45
9
BST_3P
OUT_3P
GND
GVDD
2.2 •F
L
L
10
GVDD
GND
C
C
2.2 •F
11
OUT_3M
12
13
MCLK
SCLK
44
43
1 •F
BST_3M
PVDD
PVDD
14
FSYNC
SDIN1
SDIN2
DSP
0.1 •F
10 •F
42
15
16
PVDD
41
40
39
38
BST_2P
OUT_2P
GND
1 •F
17
18
GND
GND
L
L
C
C
19
VDD
SCL
OUT_2M
2 k•
2 k•
20
21
37
36
1 •F
1 •F
BST_2M
GND
1 nF
1 nF
2 •
SDA
22
23
I2C_ADDR0
36
34
33
32
BST_1P
OUT_1P
GND
L
L
I2C_ADDR1
MUTE
Micro
24
25
C
C
STANDBY
WARN
FAULT
GND
OUT_1M
26
27
28
31
30
1 •F
BST_1M
PVDD
PVDD
0.1 •F
10 •F
29
PVDD
图 62. TAS6424L-Q1 Typical 2-Channel PBTL Application Schematic
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Typical Applications (接下页)
10.2.2.1 Design Requirements
Use the following requirements for this design:
•
This head-unit example is focused on the smallest solution size for 2 times 50 W output power into 2 Ω with a
battery supply of 14.4 V
•
The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
•
.
The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
10.2.2.1.1 Detailed Design Procedure
As a starting point, refer to the Detailed Design Procedure section for the BTL application. PBTL mode requires
schematic changes in the output stage as shown in 图 62. The other required changes include setting up the I2C
registers correctly (see 表 13) and selecting which frame or channel to use on each output. Bit 6 in register 0x21
controls the frame selection.
10.2.2.2 Application Curves
10
10
1
2 W Load
4 W Load
2 W Load
4 W Load
1
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
10 20
100
20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
D033
D031
1 kHz
PVDD = 14.4 V
1 W
PVDD = 14.4 V
图 63. THD vs Output Power
图 64. Frequency Response
11 Power Supply Recommendations
The TAS6424L-Q1 requires three power supplies. The PVDD supply is the high-current supply in the
recommended supply range. The VBAT supply is lower current supply that must be in the recommended supply
range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply range for
VBAT is maintained. The VDD supply is the 3.3 Vdc logic supply and must be maintained in the tolerance as
shown in the Recommended Operating Conditions table.
12 Layout
12.1 Layout Guidelines
The pinout of the TAS6424L-Q1 was selected to provide flowthrough layout with all high-power connections on
the right side, and all low-power signals and supply decoupling on the left side.
图 65 shows the area for the components in the application example (see the Typical Applications section).
The TAS6424L-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power
loss.
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Layout Guidelines (接下页)
The small value of the output filter provides a small size and, in this case, the low height of the inductor enables
double-sided mounting.
The EVM PCB shown in 图 65 is the basis for the layout guidelines.
12.1.1 Electrical Connection of Thermal pad and Heat Sink
For the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND.
The heat slug must not be connected to any other electrical node.
12.1.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design. The design has minimal parasitic inductances because of the short leads on the package which reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The design also incorporates circuitry that optimizes output transitions that cause EMI.
For optimizing the EMI a solid ground layer plane is recommended, for a PCB design the fulfills the CISPR25
level 5 requirements, see the TAS6424L-Q1 EVM layout.
12.1.3 General Guidelines
The EVM layout is optimized for low noise and EMC performance.
The TAS6424L-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an
external heat sink.
Refer to 图 65 for the following guidelines:
•
•
•
A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop
impedance for the high-frequency switching current.
The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the
ground pins.
The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also
the ground return for each channel is the shared. This direct path allows for improved common mode EMI
rejection.
•
•
•
The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the
smallest loop of large switching currents.
Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to
ground.
Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power
supply.
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12.2 Layout Example
Power Supply
and
Amplifier
Section
B
C
F
A
D
E
图 65. EVM Layout
12.3 Thermal Considerations
The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output
power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6424L-Q1
and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be
continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design
because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,
therefore, RθJC will be used as the thermal resistance from junction to the exposed metal package. This
resistance will dominate the thermal management, so other thermal transfers will not be considered. The thermal
resistance of RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance
is comprised of the following components:
•
•
•
RθJC of the TAS6424L-Q1
Thermal resistance of the thermal interface material
Thermal resistance of the heat sink
The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the
area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a
typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The
TAS6424L-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance
by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of
the thermal grease is 0.094°C/W
表 41 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be
115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example
previously described is used for the thermal interface material. Use 公式 1 to design the thermal system.
54
版权 © 2017, Texas Instruments Incorporated
TAS6424L-Q1
www.ti.com.cn
ZHCSG71 –MARCH 2017
Thermal Considerations (接下页)
RθJA = RθJC + thermal interface resistance + heat sink resistance
(1)
表 41. Thermal Modeling
Description
Ambient Temperature
Value
25°C
Average Power to load
40W (4x 10w)
8W (4x 2w)
115°C
Power dissipation
Junction Temperature
ΔT inside package
5.6°C (0.7°C/W × 8W)
ΔT through thermal interface material
Required heat sink thermal resistance
System thermal resistance to ambient RθJA
0.75°C (0.094°C/W × 8W)
10.45°C/W ([115°C – 25°C – 5.6°C – 0.75°C] / 8W)
11.24°C/W
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
《PurePath™ Console 3 用户手册》（文献编号：SLOU408）
《TAS6424-Q1 EVM 用户指南》（文献编号：SLOU453）
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
13.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
E2E 音频放大器论坛 TI 的音频放大器工程师对工程师 (E2E) 社区此社区的创建目的在于促进工程师之间的协作。
用户可进行实时问答。
13.4 商标
PowerPAD, 《PurePath, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
55
TAS6424L-Q1
ZHCSG71 –MARCH 2017
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
56
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS6424LQDKQRQ1
ACTIVE
HSSOP
DKQ
56
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TAS
6424L
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC SMALL OUTLINE
C
10.67
10.03
TYP
SEATING PLANE
A
PIN 1 ID AREA
0.1 C
54X 0.635
56
1
EXPOSED
THERMAL PAD
18.54
18.29
NOTE 3
8.661
8.611
2X
17.15
5.533
5.483
28
29
0.37
56X
0.17
0.13
(2.29)
7.59
7.39
B
C A B
NOTE 4
0.25
0.13
2.29 0.05
TYP
2.475
2.240
NOTE 6
0.25
GAGE PLANE
SEE DETAIL A
0.08
0.00
1.02
0.51
0 - 8
DETAIL A
TYPICAL
4221870/D 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body
thickness dimension.
www.ti.com
EXAMPLE BOARD LAYOUT
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SEE DETAILS
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221870/D 01/2019
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE:6X
4221870/D 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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