TB5T1DRE4 [TI]

DUAL LINE TRANSCEIVER, PDSO16, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16;


型号：	TB5T1DRE4
厂家：	TEXAS INSTRUMENTS
描述：	DUAL LINE TRANSCEIVER, PDSO16, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16 驱动光电二极管接口集成电路驱动器
文件：	总22页 (文件大小：1008K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TB5T1

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

DUAL DIFFERENTIAL PECL DRIVER/RECEIVER

In circuits with termination resistors, the line remains

impedance- matched when the circuit is powered

down. The driver does not load the line when it is

powered down.

FEATURES

•

Functional Replacement for the Agere BTF1A

•

Driver Features

–

Third-State Logic Low Output

ESD Protection HBM > 3 kV, CDM > 2 kV

No Line Loading when V_CC= 0

Capable of Driving 50-Ω loads

2.0-ns Maximum Propagation Delay

0.2-ns Output Skew (typical)

All devices are characterized for operation from -40°C

to 85°C.

The logic inputs of this device include internal pull-up

resistors of approximately 40 kΩ that are connected

to V_CCto ensure a logical high level input if the inputs

are open circuited.

PIN ASSIGNMENTS

DW AND D PACKAGE

(TOP VIEW)

Receiver Features

–

High-Input Impedance Approximately 8 kΩ

4.0-ns Maximum Propagation Delay

50-mV Hysteresis

RO1

DI1

RI1

VCC

DO1

Slew Rate Limited (1 ns min 80% to 20%)

ESD Protection HBM > 3 kV, CDM > 2 kV

-1.1-V to 7.1-V Input Voltage Range

DO1

DO2

GND

DI2

Common Device Features

RI2

RO2

–

Common Enable for Each Driver/Receiver

Pair

FUNCTIONAL BLOCK DIAGRAM

–

Operating Temperature Range: -40°C to

85°C

DO1

DI1

–

Single 5.0 V ± 10% Supply

DO1

Available in Gull-Wing SOIC (JEDEC

MS-013, DW) and SOIC (D) Package

DO2

DI2

DO2

DESCRIPTION

The TB5T1 device is a dual differential driver/receiver

circuit that transmits and receives digital data over

balanced transmission lines. The dual drivers

translate input TTL logic levels to differential

pseudo-ECL output levels. The dual receivers convert

differential-input logic levels to TTL output levels.

Each driver or receiver pair has its own common

enable control allowing serial data and a control clock

to be transmitted and received on a single integrated

circuit. The TB5T1 requires the customer to supply

termination resistors on the circuit board.

RI1

RO1

RI1

RI2

RO2

RI2

Enable Truth Table

Active

The power-down loading characteristics of the

receiver input circuit are approximately 8 kΩ relative

to the power supplies; hence, it does not load the

transmission line when the circuit is powered down.

Disabled Disabled

Active Active

Disabled Disabled Disabled Disabled

Disabled Disabled

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TB5T1

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

TB5T1DW

PART MARKING

TB5T1

PACKAGE⁽¹⁾

Gull-Wing SOIC

SOIC

LEAD FINISH

NiPdAu

STATUS

Production

TB5T1D

TB5T1

NiPdAu

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

POWER DISSIPATION RATINGS

THERMAL RESISTANCE,

JUNCTION-TO-AMBIENT

WITH NO AIR FLOW

DERATING FACTOR

PACKAG

CIRCUIT

BOARD MODEL

POWER RATING

_A≤ 25°C

POWER RATING

(1)

T_A= 85°C

T_A≥ 25°C

Low-K⁽²⁾

High-K⁽³⁾

Low-K⁽²⁾

High-K⁽³⁾

752 mW

1160 mW

814 mW

1200 mW

132.8°C/W

85.8°C/W

122.7°C/W

83.1°C/W

7.5 mW/°C

11.7 mW/°C

8.2 mW/°C

12 mW/°C

301 mW

466 mW

325 mW

481 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.

(2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.

(3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.

THERMAL CHARACTERISTICS

PARAMETER

PACKAGE

VALUE

48.4

UNIT

°C/W

θ_JB

Junction-to-board thermal resistance

55.2

45.1

θ_JC

Junction-to-case thermal resistance

48.1

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

UNIT

0 V to 6 V

Supply voltage, V_CC

Magnitude of differential bus (input) voltage, |V_RI1- V_RI1|, |V_RI2- V_RI2

8.4 V

(2)

Human Body Model

All pins

±3 kV

ESD

(3)

Charged-Device Model

±2 kV

Continuous power dissipation

Storage temperature, T_stg

See Dissipation Rating Table

-65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(3) Tested in accordance with JEDEC Standard 22, Test Method C101.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

Supply voltage, V_CC

4.5

-1.2⁽¹⁾

0.1

5.5

7.2

Bus pin input voltage, V_RI1, V_RI1, V_RI2, or V_RI2

Magnitude of differential input voltage, |V_RI1- V_RI1|, |V_RI2- V_RI2

Operating free-air temperature, T_A

-40

°C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless

otherwise noted.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

Outputs disabled

MIN

TYP

MAX UNIT

I_CC

Supply current

Outputs enabled

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

THIRD STATE

A TB5T1 driver produces pseudo-ECL levels and has a third state mode, which is different from a conventional

TTL device. When a TB5T1 driver is placed in the third state, the base of the output transistors are pulled low,

bringing the outputs below the active-low level of standard PECL devices. (For example: The TB5T1 low output

level is typically 2.7 V, while the third state noninverting output level is typically 1.2 V.) In a bidirectional,

multipoint bus application, the driver of one device, which is in its third state, can be back driven by another

driver on the bus whose voltage in the low state is lower than the 3-stated device. This could be due to

differences between individual driver's power supplies. In this case, the device in the third state controls the line,

thus clamping the line and reducing the signal swing. If the difference between the driver power supplies is small,

this consideration can be ignored. Again using the TB5T1 driver as an example, a typical supply voltage

difference between separate drivers of > 2 V can exist without significantly affecting the amplitude of the signal.

DRIVER ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

Output high voltage⁽¹⁾

Output low voltage⁽¹⁾

TEST CONDITIONS

MIN

V_CC- 1.8

V_OH- 1.4

0.7

TYP

V_CC- 1.3

V_OH- 1.2

1.1

MAX

V_CC- 0.8

V_OH- 0.7

1.4

UNIT

V_OH

V_OL

V_OD

V_OH

V_OL

V_OD

Differential output voltage, |V_OH- V_OL

Output high voltage⁽¹⁾

Output low voltage⁽¹⁾

V_CC- 1.8

V_OH- 1.4

0.5

V_CC- 1.3

V_OH- 1.1

1.1

V_CC- 0.8

V_OH- 0.5

1.4

T_A= 0C to 85C

Differential output voltage, |V_OH- V_OL

V_OC(PP)Peak-to-peak common-mode output voltage

C_L= 5 pF, See Figure 7

V_CC= 4.5 V

230

600

V_OZH

Third state output high voltage⁽¹⁾

DO1, DO2

1.4

1.8

2.2

Third state deferential output

voltage⁽¹⁾

V_OZD

V_DOn- V_DOn

-0.47⁽²⁾

-0.6

V_IL

V_IH

V_IK

Input low voltage⁽³⁾

Input high voltage

Input clamp voltage

V_CC= 5.5 V

0.8

V_CC= 4.5 V

V_CC= 4.5 V, I_I= -5 mA

V_CC= 5.5 V, V_O= 0 V

V_CC= 5.5 V, V_OD= 0 V

V_CC= 5.5 V, V_I= 0.4 V

V_CC= 5.5 V, V_I= 2.7 V

V_CC= 5.5 V, V_I= 5.5 V

-1⁽²⁾

-250⁽²⁾

10⁽²⁾

-400⁽²⁾

I_OS

Short-circuit output current⁽⁴⁾

I_IL

Input low current

Input high current

Input reverse current

Input Capacitance

I_IH

C_IN

100

(1) Values are with terminations as per Figure 6.

(2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original

Agere data sheet.

(3) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.

(4) Test must be performed one lead at a time to prevent damage to the device. No test circuit attached.

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

RECEIVER ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

V_CC= 4.5 V, I_OL= 8.0 mA

V_CC= 4.5 V, I_OH= -400 µA

V_CC= 5.5 V

MIN TYP

MAX

0.4

UNIT

V_OL

V_OH

V_IL

Output low voltage

Output high voltage

2.4

Enable input low voltage⁽¹⁾

Enable input high voltage⁽¹⁾

Enable input clamp voltage

Positive-going differential input threshold voltage⁽¹⁾

0.8

V_IH

V_CC= 4.5 V

V_IK

V_CC= 4.5 V, I_I= -5 mA

n = 1 or 2

-1⁽²⁾

V_TH+

V_TH-

|V_Rin- V_Rin

100 mV

-100⁽²⁾mV

Negative-going differential input threshold voltage⁽¹⁾|V_Rin- V_Rin

n = 1 or 2

V_HYSTDifferential input threshold voltage hysteresis

(V_TH+- V_TH-

)

I_OZL

I_OZH

I_OS

I_IL

Off-state output low current (high Z)

Off-state output high current (high Z)

Short circuit output current⁽³⁾

Enable input low current

V_CC= 5.5 V, V_O= 0.4 V

V_CC= 5.5 V, V_O= 2.4 V

V_CC= 5.5 V

-20⁽²⁾µA

20 µA

-100⁽²⁾mA

-400⁽²⁾µA

20 µA

V_CC= 5.5 V, V_IN= 0.4 V

V_CC= 5.5 V, V_IN= 2.7 V

V_CC= 5.5 V, V_IN= 5.5 V

V_CC= 5.5V, V_IN= -1.2 V

V_CC= 5.5V, V_IN= 7.2 V

I_IH

Enable input high current

I_IH

Enable input reverse current

Differential input low current

Differential input high current

Output resistance

100 µA

-2⁽²⁾mA

II_L

I_IH

R_O

Ω

(1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.

(2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original

Agere data sheet.

(3) Test must be performed one lead at a time to prevent damage to the device.

DRIVER SWITCHING CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

1.2

MAX

UNIT

t_P1

Propagation delay time, input high to output⁽¹⁾

Propagation delay time, input low to output⁽¹⁾

Capacitive delay

C_L= 5 pF, See Figure 2 and Figure 6

t_P2

1.2

0.01

Δt_P

t_PHZ

0.03 ns/pF

Propagation delay time,

high-level-to-high-impedance output

C_L= 5 pF, See Figure 3 and Figure 6

t_PLZ

t_PZH

t_PZL

Propagation delay time,

low-level-to-high-impedance output

Propagation delay time,

high-impedance-to-high-level output

Propagation delay time,

high-impedance-to-low-level output

t_skew1

t_skew2

t_skew(pp)

Δt_skew

t_TLH

Output skew, |t_P1- t_P2

C_L= 5 pF, See Figure 2 andFigure 6

0.15

0.1

0.3

1.1

Output skew, |t_PHH- t_PHL|, |t_PLH- t_PLL

Part-to-part skew⁽²⁾

Output skew, difference between drivers

Rise time (20%-80%)

0.3

0.7

t_THL

Fall time (80%-20%)

(1) Parameters t_P1and t_P2are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).

(2) t_skew(pp)is the magnitude of the difference in propagation delay times between any specified outputs of two devices when both devices

operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

RECEIVER SWITCHING CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

2.5

MAX

UNIT

t_PLH

t_PHL

t_PLH

t_PHL

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

C_L= 0 pF⁽¹⁾, See Figure 4 and Figure 8

2.5

5.5

C_L= 15 pF, See Figure 4 and Figure 8

C_L= 5 pF, See Figure 5 and Figure 9

Propagation delay time,

high-level-to-high-impedance output

t_PHZ

t_PLZ

0.7

Propagation delay time,

low-level-to-high-impedance output

Load capacitance (C_L) = 10 pF, See

Figure 4 and Figure 8

t_skew1

Pulse width distortion, |t_PHL- t_PLH|

Load capacitance (C_L) = 150 pF, See

Figure 4 and Figure 8

C_L= 10 pF, T_A= 75°C, See Figure 4

and Figure 8

0.8

1.4

Δt_skew1pp

Part-to-part output waveform skew⁽²⁾

Same part output waveform skew⁽²⁾

C_L= 10 pF, T_A= -40°C to 85°C, See

Figure 4 and Figure 8

1.5

0.3

Δt_skew

C_L= 10 pF, See Figure 4 and Figure 8

Propagation delay time,

high-impedance-to-high-level output

t_PZH

C_L= 10 pF, See Figure 5 and Figure 8

Propagation delay time,

high-impedance-to-low-level output

t_PZL

t_TLH

t_THL

Rise time (20%—80%)

Fall time (80%—20%)

C_L= 10 pF, See Figure 5 and Figure 8

(1) The propagation delay values with a 0 pF load are based on design and simulation.

(2) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the

same test circuits.

PLH

PHL

100

150

200

C − Load Capacitance − pF

NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total

delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed

in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and

the actual total load capacitance represents the extrinsic, or external delay contributed by the load.

Figure 1. Typical Propagation Delay vs Load Capacitance at 25°C

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

PARAMETER MEASUREMENT INFORMATION

2.4 V

1.5 V

0.4 V

INPUT

OUTPUTS

OUTPUT

PHH

PLL

+ V )/2

PLH

PHL

+ V )/2

OUTPUT

80%

20%

80%

20%

TLH

THL

Figure 2. Driver Propagation Delay Times

2.4 V

1.5 V

0.4 V

PZH

PHZ

+0.2 V

−0.1 V

OUTPUT

OUTPUT −0.47 V

PLZ

PZL

−0.1 V

OUTPUT

A. NOTE^:In the third state, OUTPUT is 0.47 V (minimum) more negative than OUTPUT.

Figure 3. Driver Enable and Disable Delay Times for a High Input

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PARAMETER MEASUREMENT INFORMATION (continued)

3.7 V

3.2 V

2.7 V

INPUT

PLH

PHL

OUTPUT

80%

1.5 V

20%

THL

TLH

Figure 4. Receiver Propagation Delay Times

2.4 V

1.5 V

0.4 V

PZH

PZL

PLZ

PHZ

OUTPUT

0.2 V

Figure 5. Receiver Enable and Disable Timing

Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data

transmission driver devices are measured with the following output load circuits.

100 W

200 W

C_Lincludes test−fixture and probe capacitance.

Figure 6. Driver Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

50 W

OUTPUTS

200 W

2 pF

C_Lincludes test−fixture and probe capacitance.

OC(PP)

A. NOTE: All input pulses are supplied by a generator having the following characteristics: t_ror t_f= 1 ns, pulse repetition

rate (PRR) = 0.25 Mbps, pulse width = 500 ± 10 ns. C_Pincludes the instrumentation and fixture capacitance within

0,06 m of the D.U.T. The measurement of V_OS(PP)is made on test equipment with a -3 dB bandwidth of at least 1

GHz.

Figure 7. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

5 V

2 k

TO OUTPUT

OF DEVICE

UNDER TEST

DIODES TYPE

458E, 1N4148,

OR EQUIVALENT

5 k

Figure 8. Receiver Propagation Delay Time and Enable Time (t_PZH, t_PZL) Test Circuit

TO OUTPUT

OF DEVICE

500

1.5 V

UNDER TEST

C_L

Figure 9. Receiver Disable Time (t_PHZ, t_PLZ) Test Circuit

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TYPICAL CHARACTERISTICS

OUTPUT-VOLTAGE

OUTPUT CURRENT, DRIVER

V_OLAND V_OHEXTREMES

FREE-AIR TEMPERATURE, DRIVER

= 4.5 V to 5.5 V,

= 255C

Load = 100 W

−0.5

−1

−0.5

Max

−1

−1.5

−2

−1.5

−2

Min

Max

−2.5

−3

Min

−2.5

−3

−3.5

−50

−40

−30

−20

−10

−50

100

150

T − Free-Air Temperature − 5C

− Output Current − mA

Figure 10.

Figure 11.

DIFFERENTIAL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE, DRIVER

MINIMUM V_OHAND V_OL

FREE-AIR TEMPERATURE, RECEIVER

1.6

1.4

1.2

3.5

= 4.5 V to 5.5 V

= 4.5 V

Load = 100 W

Min

Max

Nom

2.5

1.5

Min

VOL Min

0.5

0.8

−50

100

150

−50

100

150

− Free−Air T emperature − °C

− Free-Air Temperature − °C

Figure 12.

Figure 13.

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TYPICAL CHARACTERISTICS (continued)

PROPAGATION DELAY TIME t_P1or t_P2

FREE-AIR TEMPERATURE, DRIVER

LOW-TO-HIGH PROPAGATION DELAY

FREE-AIR TEMPERATURE, RECEIVER

1.6

= 4.5 V to 5.5 V

= 5 V

Load = 100 W

1.4

1.2

Max

Max Delay

Nom

Min

Min Delay

0.8

−50

100

150

−50

100

150

T − Free−Air Temperature − 5C

T − Temperature For Driver− 5 C

Figure 14.

Figure 15.

HIGH-TO-LOW PROPAGATION DELAY

FREE-AIR TEMPERATURE, RECEIVER

= 5 V

Max

Nom

Min

−50

100

150

− Free−Air Temperature − 5C

Figure 16.

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APPLICATION INFORMATION

140

120

100

Power Dissipation

The power dissipation rating, often listed as the

package dissipation rating, is a function of the

ambient temperature, T_A, and the airflow around the

device. This rating correlates with the device's

maximum junction temperature, sometimes listed in

the absolute maximum ratings tables. The maximum

junction temperature accounts for the processes and

materials used to fabricate and package the device,

in addition to the desired life expectancy.

D, Low−K

DW, Low−K

There are two common approaches to estimating the

internal die junction temperature, T_J. In both of these

methods, the device internal power dissipation P_D

needs to be calculated This is done by totaling the

supply power(s) to arrive at the system power

dissipation:

DW, High−K

D, High−K

100

200

300

400

500

V_Sn I_Sn

Air Flow − LFM

Figure 17. Thermal Impedance vs Air Flow

and then subtracting the total power dissipation of the

external load(s):

The standardized θ_JAvalues may not accurately

represent the conditions under which the device is

used. This can be due to adjacent devices acting as

heat sources or heat sinks, to nonuniform airflow, or

to the system PCB having significantly different

thermal characteristics than the standardized test

PCBs. The second method of system thermal

analysis is more accurate. This calculation uses the

power dissipation and ambient temperature, along

with two device and two system-level parameters:

ȍ₍

)

V_Ln I_Ln

The first T_Jcalculation uses the power dissipation

and ambient temperature, along with one parameter:

θ_JA, the junction-to-ambient thermal resistance, in

degrees Celsius per watt.

The product of P_Dand θ_JAis the junction temperature

rise above the ambient temperature. Therefore:

•

θ_JC, the junction-to-case thermal resistance, in

degrees Celsius per watt

θ_JB, the junction-to-board thermal resistance, in

degrees Celsius per watt

θ_CA, the case-to-ambient thermal resistance, in

degrees Celsius per watt

θ_BA, the board-to-ambient thermal resistance, in

degrees Celsius per watt.

T_J+ T_A) P_D q_JA

Note that θ_JAis highly dependent on the PCB on

which the device is mounted and on the airflow over

the device and PCB. JEDEC/EIA has defined

standardized test conditions for measuring θ_JA. Two

commonly used conditions are the low-K and the

high-K boards, covered by EIA/JESD51-3 and

EIA/JESD51-7 respectively. Figure 17 shows the

low-K and high-K values of θ_JAversus air flow for this

device and its package options.

In this analysis, there are two parallel paths, one

through the case (package) to the ambient, and

another through the device to the PCB to the

ambient. The system-level junction-to-ambient

thermal impedance, θ_JA(S), is the equivalent parallel

impedance of the two parallel paths:

T_J+ T_A) P_D q_JA(S)

where

ƪǒ

q_JC)q_CA q_JB)q_BA

q_JA(S)

q_JC)q_CA)q_JB)q_BA

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SLLS589C–NOVEMBER 2003–REVISED OCTOBER 2007

Load Circuits

The test load circuits shown in Figure 6 and Figure 7 are based on a recommended pi type of load circuit shown

in Figure 18. The 100-Ω differential load resistor R_Tat the receiver provide proper termination for the

interconnecting transmission line, assuming it has a 100-Ω characteristic impedance. The two resistors R_Sto

ground at the driver end of the transmission line link provide dc current paths for the emitter follower output

transistors. The two resistors to ground normally should not be placed at the receiver end, as they shunt the

termination resistor, potentially creating an impedance mismatch with undesirable reflections.

Transmission Line

R = 100 Ω

INPUT

OUTPUT

Recommended Resistor Values:

For 5 V Nom Supplies, R = 200 Ω.

For 3.3 V Nom Supplies, R = 75 Ω.

Figure 18. A Recommended pi Load Circuit

Another common load circuit, a Y load, is shown in Figure 19. The receiver-end line termination of R_Tis provided

by the series combination of the two R_T/2resistors, while the dc current path to ground is provided by the single

resistor R_S. Recommended values, as a function of the nominal supply voltage range, are indicated in the figure.

Transmission Line

INPUT

OUTPUT

R /2

Recommended Resistor Values:

For 5 V Nom Supplies, R = 200 Ω, R = 90 Ω

For 3.3 V Nom Supplies, R = 100 Ω, R = 30 Ω

Figure 19. A Recommended Y Load Circuit

An additional load circuit, similar to one commonly used with ECL and PECL, is shown in Figure 20.

Transmission Line

INPUT

OUTPUT

R /2

Recommended Resistor Values:

For 5 V and 3.3 V Nom Supplies, R = 100 Ω,

V = V − 2.55 V

Figure 20. A Recommended PECL-Style Load Circuit

An important feature of all of these recommended load circuits is that they ensure that both of the emitter follower

output transistors remain active (conducting current) at all times. When deviating from these recommended

values, it is important to make sure that the low-side output transistor does not turn off. Failure to do so

increases the t_skew2and V_OC(PP)values, increasing the potential for electromagnetic radiation.

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TB5T1D

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Pb-Free

(RoHS)

CU NIPDAU

Level-2-250C-1YEAR/

Level-1-220C-UNLIM

TB5T1

TB5T1DE4

ACTIVE

Pb-Free

(RoHS)

Level-2-250C-1YEAR/

Level-1-220C-UNLIM

TB5T1

TB5T1DW

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

TB5T1DWE4

TB5T1DWR

TB5T1DWRE4

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

2000

Pb-Free

(RoHS)

Level-2-250C-1YEAR/

Level-1-220C-UNLIM

Pb-Free

(RoHS)

Level-2-250C-1YEAR/

Level-1-220C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TB5T1DWR

SOIC

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TB5T1DWR

2000

Pack Materials-Page 2

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