TCA9517-Q1 [TI]
具有断电高阻抗的汽车类 2 位电平转换 400kHz I2C/SMBus 缓冲器/中继器;
| 型号： | TCA9517-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电高阻抗的汽车类 2 位电平转换 400kHz I2C/SMBus 缓冲器/中继器 中继器 |
| 文件： | 总25页 (文件大小：1682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCA9517-Q1
ZHCSIF1A –JUNE 2018 –REVISED FEBRUARY 2022
TCA9517-Q1 电平转换I2C 总线中继器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TCA9517-Q1 是一款具有电平转换功能的双向缓冲
器，适用于 I2C 和 SMBus 系统。它能够在混合模式应
用中提供低压（ 低至 0.9V） 和更高压（ 2.7V 至
5.25V）之间的双向电压电平转换（上升转换和/或下降
转换）。该器件能够扩展 I2C 和 SMBus 系统，甚至在
电平转换期间也不会降低系统性能。
– 器件温度：–40°C 至125°C TA
– 器件HBM 分级等级：±5500V
– 器件CDM 分级等级：±1000V
• 提供功能安全
– 有助于进行功能安全系统设计的文档
• 双通道双向缓冲器
• 与I2C 总线和SMBus 兼容
• 在A 侧上，工作电源电压范围为
0.9V 至5.25V
TCA9517-Q1 可缓冲 I2C 总线上的串行数据 (SDA) 和
串行时钟 (SCL) 信号，因而能够在 I2C 应用中连接两
条总线电容高达400pF 的总线。
TCA9517-Q1 具有两种类型的驱动器：A 侧驱动器和
B 侧驱动器。所有输入和 I/O 都能够承受 5.25V 的过
• 在B 侧上，工作电源电压范围为
2.7V 至5.25V
压，即使器件未通电时也是如此（VCCB 和/或 VCCA
0V）。
=
• 可将电压电平从0.9V 和2.7V 转换到5.25V
• 高电平有效中继器使能输入
• 漏极开路I2C I/O
• 5.25V 耐压I2C 和使能输入支持混合模式信号操作
• 适应标准模式和快速模式I2C 器件和多个控制器
• 器件断电时I2C 引脚呈高阻抗状态
• 闩锁性能超过100mA，符合JESD 78 II 类规范的
要求
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TCA9517-Q1
VSSOP (8)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 服务器
• 路由器（电信交换设备）
• 工业设备
• 包含多个I2C 目标和/或长PCB 迹线的产品
1
8
VCCA
VCCB
3
2
5
SDAA
SCLA
EN
SDAB
6
7
I2C or SMBus Controller
(e.g. Processor)
I2C Target Devices
TCA9517
SCLB
GND
4
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS237
TCA9517-Q1
ZHCSIF1A –JUNE 2018 –REVISED FEBRUARY 2022
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Table of Contents
9.2 Functional Block Diagram......................................... 11
9.3 Feature Description...................................................12
9.4 Device Functional Modes..........................................12
10 Application and Implementation................................13
10.1 Application Information........................................... 13
10.2 Typical Application.................................................. 13
11 Power Supply Recommendations..............................16
12 Layout...........................................................................17
12.1 Layout Guidelines................................................... 17
12.2 Layout Example...................................................... 17
13 Device and Documentation Support..........................18
13.1 Device Support....................................................... 18
13.2 Receiving Notification of Documentation Updates..18
13.3 支持资源..................................................................18
13.4 Trademarks.............................................................18
13.5 Electrostatic Discharge Caution..............................18
13.6 术语表..................................................................... 18
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................7
7.7 I2C Interface Switching Characteristics.......................8
7.8 Typical Characteristics................................................9
8 Parameter Measurement Information..........................10
9 Detailed Description......................................................11
9.1 Overview................................................................... 11
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (June 2018) to Revision A (February 2022)
Page
• 将提到的旧术语实例全部更改为控制器和目标....................................................................................................1
• 添加了特性“提供功能安全”............................................................................................................................1
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5 说明（续）
B 侧上的缓冲器按照无法与使用静态电压偏移的器件串联使用进行设计。器件并不将经缓冲的低电平信号识别为
有效低电平，并且不再将它作为经缓冲的低电平进行传送。
B 侧驱动器的运行电压介于 2.7V 至 5.25V 之间。此内部缓冲器的输出低电平大约为 0.5V。当输出在内部被驱动
为低电平时，输出电压必须比输出低电平低 70mV 或者更多。更高的电压低信号被称为经缓冲的低电平。当 B 侧
I/O 在内部被驱动为低电平时，输入并不将此低电平识别为低电平。当输入低电平状态被释放时，这一特性防止了
锁定情况的发生。
A 侧驱动器运行电压介于 0.9V 至5.25V 之间并且能够驱动更大的电流。它们不需要经缓冲的低电平特性（或者静
态失调电压）。B 侧低电平信号在 A 侧转换为接近 0V 的低电平。它可以适应低电压逻辑更小的电压摆幅。A 侧
输出下拉驱动硬低电平。输入电平设置为 0.3 × VCCA 以满足低电压侧电源低至 0.9V 的系统中对较低电平的需
求。
两个或多个 TCA9517-Q1 器件的 A 侧可以连接在一起。将 A 侧作为公共总线，实现多个拓扑结构（请参阅图 8
和图9）。可以将 A 侧直接连接至具有静态或动态失调电压的任意其他缓冲器。可以将多个 TCA9517-Q1 串联在
一起（相邻器件间通过 A 侧和B 侧相连），失调电压不会增大，只是需要考虑飞行时间延迟。由于B 侧缓冲低电
压的原因，TCA9517-Q1 不能通过B 侧相连。B 侧不能连接配有上升时间加速器的器件。
VCCA 只能用于为A 侧输入比较器提供0.3 × VCCA 参考电压，或者用于电源正常状态检测电路。TCA9517-Q1 逻
辑和所有I/O 均由VCCB 引脚供电。
当与标准 I2C 系统一同工作时，需要用上拉电阻在经缓冲的总线上提供逻辑高电平。TCA9517-Q1 具有 I2C 总线
的标准开漏配置。这些上拉电阻器的尺寸由系统决定，但中继器的每一侧都必须有一个上拉电阻器。此器件专为
与标准模式及快速模式 I2C 器件（而不单是SMBus 器件）一同工作而设计。在可以接受标准模式器件和多个控制
器的通用型I2C 系统中，标准模式I2C 器件的额定值仅为3mA。在某些情况下，可以采用更高的结束电流。
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6 Pin Configuration and Functions
VCCA
SCLA
SDAA
GND
1
2
3
4
8
7
6
5
VCCB
SCLB
SDAB
EN
Not to scale
图6-1. DGK (VSSOP) Package, 8-Pin, Top View
表6-1. Pin Functions
DESCRIPTION
PIN
NAME
TYPE
NO.
1
VCCA
SCLA
Supply
A-side supply voltage (0.9 V to 5.25 V)
Serial clock bus, A-side. Connect to VCCA through a pull-up resistor. If unused, connect directly to
ground.
2
3
Input/Output
Serial data bus, A-side. Connect to VCCA through a pull-up resistor. If unused, connect directly to
ground.
SDAA
Input/Output
4
5
GND
EN
Ground
Input
Ground
Active-high repeater enable input
Serial data bus, B-side. Connect to VCCB through a pull-up resistor. If unused, connect directly to
ground.
6
SDAB
Input/Output
Serial clock bus, B-side. Connect to VCCB through a pull-up resistor. If unused, connect directly to
ground.
7
8
SCLB
VCCB
Input/Output
Supply
B-side and device supply voltage (2.7 V to 5.25 V)
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCCB
VCCA
VI
Supply voltage range
7
7
7
7
V
V
V
V
–0.5
–0.5
–0.5
–0.5
Supply voltage range
Enable input voltage range(2)
I2C bus voltage range(2)
Input clamp current
VI/O
IIK
VI < 0
–50
–50
±50
mA
IOK
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Storage temperature range
mA
mA
°C
IO
±100
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±5500
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
Electrostatic discharge
±1000
±200
V
Machine model (A115-A)
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VCCA
VCCB
Supply voltage, A-side bus
Supply voltage, B-side bus
0.9(2)
5.25
5.25
V
2.7
V
CCA ≤VCCB
V
VCCA > VCCB
SDAA, SCLA
SDAB, SCLB
EN
2.9
5.25
0.7 × VCCA
0.7 × VCCB
0.7 × VCCB
5.25
VIH
High-level input voltage
Low-level input voltage
5.25
V
V
5.25
SDAA, SCLA
SDAB, SCLB(1)
EN
0.3 × VCCA
0.3 × VCCB
0.3 × VCCB
6
VIL
IOL
TA
Low-level output current
mA
°C
Operating free-air temperature
125
–40
(1) VIL specification is for the first low level seen by the SDAB and SCLB lines. VILc is for the second and subsequent low levels seen by
the SDAB and SCLB lines. See 节10.2.2.2 for VILC application information
(2) Low-level supply voltage
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7.4 Thermal Information
TCA9517-Q1
DGK (VSSOP)
8 PINS
187.6
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
59.3
108.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.4
106.9
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
VCCB = 2.7 V to 5.25 V, GND = 0 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCB
MIN
TYP
MAX UNIT
VIK
Input clamp voltage
2.7 V to 5.25 V
V
II = –18 mA
–1.2
0.6
IOL = 100 μA or 6 mA,
VILA = VILB = 0 V
SDAB, SCLB
0.45
0.52
0.1
Low-level output
voltage
VOL
2.7 V to 5.25 V
V
SDAA, SCLA IOL = 6 mA
0.2
Low-level input voltage
below low-level output SDAB, SCLB ensured by design
voltage
2.7 V to 5.25 V
2.7 V to 5.25 V
70
mV
V
VOL –VILc
SDA and SCL low-level
SDAB, SCLB
VILC
0.4
input voltage contention
Both channels low,
SDAA = SCLA = GND and
ICC
Quiescent supply current for VCCA
SDAB = SCLB = open, or
SDAA = SCLA = open and
SDAB = SCLB = GND
1
5
mA
Both channels high,
SDAA = SCLA = VCCA and
SDAB = SCLB = VCCB and
EN = VCCB
1.5
Both channels low,
SDAA = SCLA = GND and
SDAB = SCLB = open
ICC
Quiescent supply current
5.25 V
mA
1.5
3
5
5
In contention,
SDAA = SCLA = GND and
SDAB = SCLB = GND
VI = VCCB
VI = 0.2 V
VI = VCCB
VI = 0.2 V
VI = VCCB
VI = 0.2 V
±1
10
SDAB, SCLB
±1
SDAA, SCLA
EN
II
Input leakage current
2.7 V to 5.25 V
2.7 V to 5.25 V
μA
10
±1
–10
–30
10
SDAB, SCLB
SDAA, SCLA
EN
High-level output
leakage current
IOH
VO = 3.6 V
μA
pF
10
VI = 3 V or 0 V
3.3 V
3.3 V
0 V
6
8
7
8
7
10
CI
Input capacitance
13
SCLA, SCLB VI = 3 V or 0 V
SDAA, SDAB VI = 3 V or 0 V
11
3.3 V
0 V
13
Input/output
capacitance
CIO
pF
11
7.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
100
100
MAX UNIT
tsu
th
Setup time, EN high before Start condition(1)
Hold time, EN high after Stop condition(1)
ns
ns
(1) EN should change state only when the global bus and the repeater port are in an idle state.
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7.7 I2C Interface Switching Characteristics
VCCB = 2.7 V to 5.25 V, GND = 0 V, TA = –40°C to 125°C (unless otherwise noted)(1) (4)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN TYP(5) MAX UNIT
SDAB, SCLB(3) SDAA, SCLA(3)
(see 图8-4) (see 图8-4)
141 250
ns
tPLZ
Propagation delay
SDAA, SCLA(2) SDAB, SCLB(2)
74 110
(see 图8-3)
(see 图8-3)
V
8-2)
CCA ≤2.7 V (see 图
76(6) 110
95 290 ns
107 230
12
SDAB, SCLB
SDAA, SCLA
V
CCA ≥3 V
tPZL
Propagation delay
(see 图8-2)
SDAA, SCLA(2) SDAB, SCLB(2)
(see 图8-3)
(see 图8-3)
V
CCA ≤2.7 V
(see 图8-3)
B-side to A side
V
CCA ≥3 V
tTLH
Transition time
Transition time
80%
20%
ns
42
(see 图8-3)
A side to B-side
(see 图8-2)
125
V
CCA ≤2.7 V
67(6) 200
86 240
48 120
(see 图8-3)
B-side to A side
V
CCA ≥3 V
tTHL
80%
20%
ns
(see 图8-3)
A side to B-side
(see 图8-2)
(1) Times are specified with loads of 1.35-kΩ pull-up resistance and 50-pF load capacitance on the B-side. On the A side, for 0.9-V ≤
CCA ≤2.7-V, a 167-Ω pull-up and 57-pF load capacitance. For VCCA ≥3.0-V, a 450-Ω pull-up and 57-pF load capacitance. Different
V
load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
(2) The proportional delay data from A to B-side is measured at 0.3 VCCA on the A side to 1.5 V on the B-side.
(3) The tPLH delay data from B to A side is measured at 0.4 V on the B-side to 0.5 VCCA on the A side when VCCA is less than 2 V, and
1.5 V on the A side if VCCA is greater than 2 V.
(4) pull-up voltages are VCCA on the A side and VCCB on the B-side.
(5) Typical values were measured with VCCA = VCCB = 3.3 V at TA = 25°C, unless otherwise noted.
(6) Typical value measured with VCCA = 2.7 V at TA = 25°C
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7.8 Typical Characteristics
VCCA = 0.9 V, VCCB = 2.7 V
0.15
-40C
25C
125C
0.125
0.545
0.535
0.525
0.515
0.505
0.495
-40C
25C
125C
0.1
0.075
0.05
0.025
0
0
1
2
3
Port B IOL (mA)
4
5
6
0
1
2
3
Port A IOL (mA)
4
5
6
D002
D001
图7-2. Port B VOL vs IOL
图7-1. Port A VOL vs IOL
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8 Parameter Measurement Information
VCC
VCC
RL
(see Note A)
VIN
VOUT
S1
PULSE
DUT
GND
GENERATOR
R
T
C = 57 pF
L
(see Note B)
(see Note C)
TEST
tPLZ/tPZL
S1
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
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A. RL = 167 Ω (0.9 V to 2.7 V) and RL = 450 Ω(3.0 V to 5.25 V) on the A side and 1.35 kΩ on the B-side
B. RT termination resistance should be equal to ZOUT of pulse generators.
C. CL includes probe and jig capacitance. CL = 50 pF when on the B-side.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, slew rate ≥1 V/ns.
E. The outputs are measured one at a time, with one transition per measurement.
F. tPLH and tPHL are the same as tpd
G. tPLZ and tPHZ are the same as tdis
H. tPZL and tPZH are the same as ten
.
.
.
图8-1. Test Circuit
3 V
VCCA
VCCA
INPUT
1.5 V
1.5 V
INPUT
0.3 VCCA
0.3 VCCA
0.1 V
tPZL
80%
tPLZ
80%
tPZL
80%
20%
tPLZ
1.2 V
3 V
80%
1.5 V
OUTPUT
0.6 V
20%
0.6 V
20%
OUTPUT
1.5 V
20%
VOL
tTHL
tTLH
图8-3. Waveform 2 –Propagation Delay and
Transition Times for A-side to B-side
图8-2. Waveform 1 –Propagation Delay and
Transition Times for B-side to A-side
INPUT
SDAB, SCLB
0.4 V
OUTPUT
SCLA, SDAA
50% is VCCA is less than 2 V
1.5 V if VCCA is greater than 2 V
tPLH
图8-4. Waveform 3 –Propagation Delay for B-side to A-side
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9 Detailed Description
9.1 Overview
The TCA9517-Q1 is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It provides
bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and
higher voltages (2.7 V to 5.25 V) in mixed-mode applications. This device enables I2C and SMBus systems to be
extended without degradation of performance, even during level shifting.
The TCA9517-Q1 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus
allowing two buses of up to 400-pF bus capacitance to be connected in an I2C application.
The TCA9517-Q1 has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage
tolerant to 5.25 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).
9.2 Functional Block Diagram
VCCA
VCCB
1
8
6
3
SDAA
SDAB
7
2
SCLA
SCLB
V
CCB
Pullup
Resistor
5
EN
4
GND
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9.3 Feature Description
9.3.1 Two-Channel Bidirectional Buffer
The TCA9517-Q1 is a two-channel bidirectional buffer with level-shifting capabilities
9.3.2 Active-High Repeater-Enable Input
The TCA9517-Q1 has an active-high enable (EN) input with an internal pull-up to VCCB, which allows the user to
select when the repeater is active. This can be used to isolate a badly behaved target on power-up reset. The
EN input should change state only when the global bus and repeater port are in an idle state, to prevent system
failures.
9.3.3 VOL B-Side Offset Voltage
The B-side drivers operate from 2.7 V to 5.25 V. The output low level for this internal buffer is approximately
0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is
driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally,
the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the
input low condition is released. This type of design prevents 2 B-side ports from being connected to each other.
9.3.4 Standard Mode and Fast Mode Support
The TCA9517-Q1 supports standard mode as well as fast mode I2C. The maximum system operating frequency
will depend on system design and the delays added by the repeater.
9.3.5 Clock Stretching Support
The TCA9517-Q1 can support clock stretching, but care needs to be taken to minimize the overshoot voltage
presented during the hand-off between the target and controller. This is best done by increasing the pull-up
resistor value.
9.4 Device Functional Modes
表9-1. Function Table
INPUT
FUNCTION
EN
L
Outputs disabled
SDAA = SDAB
SCLA = SCLB
H
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
A typical application is shown in 图 10-1. In this example, the system controller is running on a 3.3 V I2C bus,
and the target is connected to a 1.2 V I2C bus. Both buses run at 400 kHz. Controller devices can be placed on
either bus.
The TCA9517-Q1 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.25
V bus voltages and 2.7 V to 5.25 V bus voltages.
When the A side of the TCA9517-Q1 is pulled low by a driver on the I2C bus, a comparator detects the falling
edge when it goes below 0.3 × VCCA and causes the internal driver on the B-side to turn on, causing the B-side
to pull down to about 0.5 V. When the B-side of the TCA9517-Q1 falls, first a CMOS hysteresis-type input
detects the falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to
ground. In order to illustrate what would be seen in a typical application, refer to 图 10-3 and 图 10-4. If the bus
controller in 图 10-1 were to write to the target through the TCA9517-Q1, waveforms shown in 图 10-3 would be
observed on the A bus. This looks like a normal I2C transmission, except that the high level may be as low as
0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed.
On the B-side bus of the TCA9517-Q1, the clock and data lines would have a positive offset from ground equal
to the VOL of the TCA9517-Q1. After the eighth clock pulse, the data line is pulled to the VOL of the target device,
which is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level
set by the driver in the TCA9517-Q1 for a short delay, while the A-bus side rises above 0.3 × VCCA and then
continues high.
10.2 Typical Application
3.3 V
1.2 V
10 kW
VCCA
10 kW
10 kW
VCCB
10 kW
SDA
SCL
SDA
SCL
SDAB
SCLB
SDAA
SCLA
BUS
CONTROLLER
400 kHz
TARGET
400 kHz
EN
TCA9517-Q1
BUS A
BUS B
图10-1. Typical Application Schematic
10.2.1 Design Requirements
For the level translating application, the following should be true:
• VCCA = 0.9 V to 5.25 V
• VCCB = 2.7 to 5.25 V
• B-side ports must not be connected together
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10.2.2 Detailed Design Procedure
10.2.2.1 Clock Stretching Support
The TCA9517-Q1 can support clock stretching, but care needs to be taken to minimize the overshoot voltage
presented during the hand-off between the target and controller. This is best done by increasing the pull-up
resistor value.
10.2.2.2 VILC and Pullup Resistor Sizing
For the TCA9517-Q1 to function correctly, all devices on the B-side must be able to pull the B-side below the
voltage input low contention level (VILC). This means that the VOL of any device on the B-side must be below
0.4 V.
VOL of a device can be adjusted by changing the IOL through the device which is set by the pull-up resistance
value. The pull-up resistance on the B-side must be carefully selected to ensure that logic levels will be
transferred correctly to the A-side.
VCCA
VCCB
10 kW
10 kW
10 kW
10 kW
SDAA
SCLA
SDA
SCL
SDAB
SCLB
SDA
SCL
TARGET
400 kHz
BUS
CONTROLLER
EN
TCA9517-Q1
10 kW
10 kW
SDAA
SDAB
SDA
SCL
SCLA
SCLB
TARGET
400 kHz
EN
TCA9517-Q1
10 kW
10 kW
SDAA
SCLA
SDAB
SCLB
SDA
SCL
TARGET
400 kHz
EN
TCA9517-Q1
图10-2. Typical Star Application
Multiple A sides of TCA9517-Q1s can be connected in a star configuration, allowing all nodes to communicate
with each other.
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VCCB
10 kW
10 kW
SDA
SCL
10 kW
10 kW
10 kW
10 kW
SDA
SCL
10 kW
10 kW
SDAB
SDAA SDAB
SDAA SDAB
SDAA
SCLA
SCLB
SCLA SCLB
SCLA SCLB
BUS
CONTROLLER
TARGET
400 kHz
EN
EN
EN
TCA9517-Q1
TCA9517-Q1
TCA9517-Q1
图10-3. Typical Series Application
To further extend the I2C bus for long traces/cables, multiple TCA9517-Q1s can be connected in series as long
as the A-side is connected to the B-side. I2C bus target devices can be connected to any of the bus segments.
The number of devices that can be connected in series is limited by repeater delay/time-of-flight considerations
on the maximum bus speed requirements.
9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
图10-4. Bus A (0.9 V to 5.25 V Bus) Waveform
9th CLOCK PULSE — ACKNOWLEDGE
SCL
SDA
VOL OF TCA9517
VOL OF TARGET
图10-5. Bus B (2.7 V to 5.25 V Bus) Waveform
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10.2.3 Application Curve
3
Port A
Port B
2.5
2
1.5
1
0.5
0
D003
图10-6. Voltage Translation at 400 kHz, VCCA = 0.9 V, VCCB = 2.7 V
11 Power Supply Recommendations
VCCB and VCCA can be applied in any sequence at power up. The TCA9517-Q1 includes a power-up circuit that
keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. After power up and
with the EN high, a low level on the A-side (below 0.3 × VCCA) turns the corresponding B-side driver (either SDA
or SCL) on and drives the B-side down to approximately 0.5 V. When the A-side rises above 0.3 × VCCA, the B-
side pull-down driver is turned off and the external pull-up resistor pulls the pin high. When the B-side falls first
and goes below 0.3 × VCCB, the A-side driver is turned on and the A-side pulls down to 0 V. The B-side pull-
down is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5
V, the A-side driver turns off when the B-side voltage is above 0.7 × VCCB. If the B-side low voltage goes below
0.4 V, the B-side pull-down driver is enabled, and the B-side is able to rise to only 0.5 V until the A-side rises
above 0.3 × VCCA
.
TI recommends using a decoupling capacitor and placing it close to the VCCA and VCCB pins of a value of
about 100 nF.
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12 Layout
12.1 Layout Guidelines
There are no special layout procedures required for the TCA9517-Q1.
It is recommended that the decoupling capacitors be placed as close to the VCC pins as possible.
12.2 Layout Example
图12-1 shows an example layout of the DGK package.
= Via to GND Plane
To VCCA Plane
VCCA
SCLA
SDAA
GND
VCCB
SCLB
SDAB
EN
To VCCB Plane
图12-1. TCA9517-Q1A Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA9517DGKRQ1
ACTIVE
VSSOP
DGK
8
2500 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1N2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA9517-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2022
Catalog : TCA9517
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9517DGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TCA9517DGKRQ1
8
2500
Pack Materials-Page 2
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