TCA9538 [TI]

具有中断输出、复位和配置寄存器的 8 位 1.65V 至 5.5V I2C/SMBus I/O 扩展器;


型号：	TCA9538
厂家：	TEXAS INSTRUMENTS
描述：	具有中断输出、复位和配置寄存器的 8 位 1.65V 至 5.5V I2C/SMBus I/O 扩展器
文件：	总40页 (文件大小：1017K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

TCA9538 具有中断输出、复位和配置寄存器的低压 8 位 I²C 和 SMBus 低

功耗 I/O 扩展器

1 特性

2 应用范围

•

待机流耗低

I²C 至并行端口扩展器

•

服务器

路由器（电信交换设备）

个人计算机

开漏电路低电平有效中断输出

低电平有效复位输入

个人电子产品（例如：游戏机）

工业自动化

1.65V 至 5.5V 的工作电源电压范围

可耐受 5V 电压的 I/O 端口

400kHz 快速 I²C 总线

采用 GPIO 受限处理器的产品

3 说明

两个硬件地址引脚可在 I²C/SMBus 上支持最多四个

TCA9538 是一款 16 引脚器件，可为两线双向 I²C 总

线（或 SMBus）协议提供 8 位通用并行输入输出 (I/O)

扩展。该器件的工作电源电压范围是 1.65V 到 5.5V。

器件支持 100kHz（标准模式）和 400kHz（快速模

式）时钟频率。当开关、传感器、按钮、LED、风扇等

设备需要额外的 I/O 时，I/O 扩展器（如 TCA9538）

可提供简单解决方案。

器件

•

输入和输出配置寄存器

极性反转寄存器

所用通道在加电时被配置为输入

加电时无毛刺脉冲

SCL/SDA 输入端上的噪声滤波器

具有最大高电流驱动能力的锁存输出，适用于直接

驱动 LED

当输入端口状态发生变化时，TCA9538 可在 INT 引

脚上生成中断。硬件可选地址引脚 A0 和 A1 最多允许

四个 TCA9538 器件位于同一 I²C 总线上。该器件还可

通过 RESET 功能或电源循环供电生成加电复位，从而

复位到默认状态。

•

锁断性能超过 100mA （符合 JESD 78 Class II 规

范的要求）

静电放电 (ESD) 保护性能超过 JESD 22 规范要求

–

2000V 人体模型 (A114-A)

1000V 组件充电模式 (C101)

器件信息⁽¹⁾

器件型号

TCA9538

封装

TSSOP (16)

SSOP (16)

封装尺寸（标称值）

5.00mm x 4.40mm

6.20mm x 5.30mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

简化框图

VCC

SDA

SCL

Peripheral

Devices

I2C or SMBus

Master

(e.g. Processor)

INT

• RESET,

ENABLE, or

control

inputs

• INT or

status

RESET

TCA9538

outputs

• LEDs

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SCPS199

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

8.4 Device Functional Modes........................................ 17

8.5 Programming........................................................... 17

8.6 Register Map........................................................... 19

Application and Implementation ........................ 23

9.1 Application Information............................................ 23

9.2 Typical Application ................................................. 23

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 I²C Interface Timing Requirements........................... 6

6.7 RESET Timing Requirements................................... 7

6.8 Switching Characteristics.......................................... 7

6.9 Typical Characteristics.............................................. 8

Parameter Measurement Information ................ 10

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

8.3 Feature Description................................................. 16

10 Power Supply Recommendations ..................... 26

10.1 Power-On Reset Requirements ........................... 26

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 28

12 器件和文档支持 ..................................................... 29

12.1 文档支持................................................................ 29

12.2 接收文档更新通知 ................................................. 29

12.3 社区资源................................................................ 29

12.4 商标....................................................................... 29

12.5 静电放电警告......................................................... 29

12.6 Glossary................................................................ 29

13 机械、封装和可订购信息....................................... 29

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (October 2015) to Revision D

Page

•

Updated Figure 18 ............................................................................................................................................................... 19

Changes from Revision B (September 2015) to Revision C

Page

•

Added "Time to reset; V_CC= 1.65 V-2.3 V" parameter to RESET Timing Requirements table. ............................................ 7

Added "Output data valid; V_CC= 1.65 V-2.3 V" to Switching Characteristics table................................................................ 7

Updated V_{CC_GW}parameter. ................................................................................................................................................ 26

Changes from Revision A (September 2014) to Revision B

Page

•

已添加 DB 封装至数据表。..................................................................................................................................................... 1

Changes from Original (August 2014) to Revision A

Page

•

已将文档更新为完整版。 ........................................................................................................................................................ 1

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

5 Pin Configuration and Functions

PW, DB Package

16-Pin TSSOP, SSOP

Top View

VCC

SDA

SCL

INT

RESET

GND

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Address input. Connect directly to V_CCor ground

Ground

GND

INT

—

Interrupt output. Connect to V_CCthrough a pull-up resistor

P-port input-output. Push-pull design structure. At power on, P0 is

configured as an input

I/O

P-port input-output. Push-pull design structure. At power on, P1 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P2 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P3 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P4 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P5 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P6 is

configured as an input

P-port input-output. Push-pull design structure. At power on, P7 is

configured as an input

Active-low reset input. Connect to V_CCthrough a pull-up resistor if no active

connection is used

RESET

SCL

SDA

VCC

Serial clock bus. Connect to V_CCthrough a pull-up resistor

Serial data bus. Connect to V_CCthrough a pull-up resistor

Supply voltage

I/O

—

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

UNIT

V_CC

V_I

Supply voltage

(2)

Input voltage

V_O

I_IK

Output voltage⁽²⁾

Input clamp current

V_I< 0

–20

±20

I_OK

I_IOK

I_OL

I_OH

Output clamp current

V_O< 0

Input-output clamp current

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

Continuous output low current through a single P-port

Continuous output high current through a single P-port

Continuous current through GND by all P-ports, INT, and SDA

Continuous current through V_CCby all P-ports

Storage temperature

–50

250

–160

150

I_CC

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

2000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

MIN

1.65

MAX UNIT

V_CC

Supply voltage

5.5

(1)

SCL, SDA

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V to 2.7 V

V_CC= 3 V to 5.5 V

0.7 × V_CC

0.8 × V_CC

–0.5

V_CC

V_IH

High-level input voltage

5.5

A0, A1, RESET, P7–P0

SCL, SDA

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V to 2.7 V

V_CC= 3 V to 5.5 V

0.3 × V_CC

0.2 × V_CC

V_IL

Low-level input voltage

–0.5

A0, A1, RESET, P7–P0

–0.5

I_OL

I_OH

Low-level output current

High-level output current

Any P-port, P7–P0

–10

Continuous current through

GND

All P-ports P7-P0, INT, and SDA

200

I_CC

°C

Continuous current through V_CCAll P-ports P7-P0

Operating free-air temperature

–80

T_A

–40

(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage V_CCin the application, or an increase in supply current,

I_CC, will result.

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

6.4 Thermal Information

TCA9538

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

122

DB (SSOP)

16 PINS

113.2

63.6

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

56.4

67.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

10.8

21.2

ψ_JB

66.5

63.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_I= –18 mA

V_CC

MIN

TYP⁽¹⁾

MAX UNIT

V_IK

Input diode clamp voltage

1.65 V to 5.5 V

–1.2

V_PORRPower-on reset voltage, V_CCrising V_I= V_CCor GND, I_O= 0

Power-on reset voltage, V_CC

1.2

1.5

V_PORF

V_I= V_CCor GND, I_O= 0

0.75

falling

1.65 V

2.3 V

1.2

1.8

2.6

4.1

1.1

1.7

2.5

I_OH= –8 mA

3 V

4.5 V

V_OH

P-port high-level output voltage⁽²⁾

1.65 V

2.3 V

I_OH= –10 mA

V_OL= 0.4 V

V_OL= 0.5 V

3 V

4.5 V

(3)

SDA

1.65 V to 5.5 V

1.65 V

2.3 V

3 V

4.5 V

I_OL

P port⁽⁴⁾

1.65 V

2.3 V

V_OL= 0.7 V

3 V

4.5 V

(5)

INT

V_OL= 0.4 V

1.65 V to 5.5 V

SCL, SDA

A0, A1, RESET

P port

±1

I_I

V_I= V_CCor GND

1.65 V to 5.5 V

μA

I_IH

I_IL

V_I= V_CC

1.65 V to 5.5 V

μA

P port

V_I= GND

–1

(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V V_CC) and T_A= 25°C.

(2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os

(P-ports P7-P0) through V_CCmust be limited to a maximum current of 80 mA.

(3) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)

through GND must be limited to a maximum current of 200 mA.

(4) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-

ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

(5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)

through GND must be limited to a maximum current of 200 mA.

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP⁽¹⁾

MAX UNIT

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_scl= 400 kHz, No load

t_r= 3 ns

5.5 V

3.6 V

2.7 V

1.65 V

5.5 V

3.6 V

2.7 V

1.65 V

5.5 V

3.6 V

2.7 V

1.65 V

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_scl= 400 kHz, No load

t_r,max= 300 ns

Operating mode

μA

I_CC

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_scl= 100 kHz, No load

t_r,max= 1 µs

1.9

1.1

3.5

1.8

μA

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_scl= 0 kHz, No load

Standby mode

1.6

0.4

Additional current in standby

mode

One P-port input at V_CC– 0.6 V,

Other P-port inputs at V_CCor GND

ΔI_CC

1.65 V to 5.5 V

µA

C_i

SCL

V_I= V_CCor GND

5.5

6.5

9.5

SDA

P port

C_io

V_IO= V_CCor GND

1.65 V to 5.5 V

6.6 I²C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 9)

MIN

MAX

UNIT

STANDARD MODE

I²C clock frequency

f_scl

100

kHz

μs

I²C clock high time

t_sch

I²C clock low time

t_scl

4.7

I²C spike time

t_sp

I²C serial-data setup time

t_sds

250

I²C serial-data hold time

t_sdh

I²C input rise time

t_icr

1000

300

I²C input fall time

t_icf

I²C output fall time

t_ocf

10-pF to 400-pF bus

300

I²C bus free time between Stop and Start

I²C Start or repeated Start condition setup

I²C Start or repeated Start condition hold

I²C Stop condition setup

t_buf

4.7

t_sts

t_sth

t_sps

t_vd(data)

Valid data time

SCL low to SDA output valid

3.45

400

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

Valid data time of ACK condition

I²C bus capacitive load

μs

C_b

FAST MODE

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

f_scl

t_sch

t_scl

t_sp

0.6

1.3

400

kHz

μs

I²C serial-data setup time

t_sds

100

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

I²C Interface Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted) (see Figure 9)

MIN

MAX

UNIT

I²C serial-data hold time

t_sdh

I²C input rise time

t_icr

300

20 × (V_DD

I²C input fall time

t_icf

5.5 V)

20 × (V_DD

I²C output fall time

t_ocf

10-pF to 400-pF bus

300

5.5 V)

I²C bus free time between Stop and Start

I²C Start or repeated Start condition setup

I²C Start or repeated Start condition hold

I²C Stop condition setup

t_buf

1.3

μs

t_sts

0.6

t_sth

0.6

t_sps

0.6

t_vd(data)

Valid data time

SCL low to SDA output valid

0.9

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

μs

400

6.7 RESET Timing Requirements

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

STANDARD and FAST MODE

t_w

Reset pulse duration

t_REC

Reset recovery time

Time to reset; V_CC= 2.3 V-5.5 V

Time to reset; V_CC= 1.65 V-2.3 V

400

550

t_RESET

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 10 and Figure 11)

FROM

(INPUT)

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

STANDARD and FAST MODE

t_iv

t_ir

Interrupt valid time

P port

SCL

INT

μs

Interrupt reset delay time

Output data valid; V_CC= 2.3 V-5.5 V

Output data valid; V_CC= 1.65 V-2.3 V

Input data setup time

200

300

t_pv

SCL

P7–P0

t_ps

t_ph

P port

SCL

100

Input data hold time

μs

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

6.9 Typical Characteristics

T_A= 25°C (unless otherwise noted)

1.8

1.6

1.4

1.2

1.8 V

2.5 V

3.3 V

5 V

0.8

0.6

0.4

0.2

1.8 V

2.5 V

3.3 V

5 V

-40

-15

-40

-15

T_A- Free-Air Temperature (°C)

D001

D002

f_SCL= 400 kHz

I/Os = High or Low

Inputs

f_SCL= 0 kHz

I/Os = High or Low

Inputs

Figure 1. Supply Current (I_CC, Operating Mode) vs

Temperature (T_A) at Four Supply Voltages

Figure 2. Supply Current (ICC, Standby Mode) vs

Temperature (T_A) at Four Supply Voltages

250

200

150

100

V_CC= 1.8 V, I_OL= 8 mA

V_CC= 5 V, I_OL= 8 mA

V_CC= 1.8 V, I_OL= 10 mA

V_CC= 5 V, I_OL= 10 mA

0.5

1.5

2.5

3.5

4.5

5.5

-40

-15

V_CC- Supply Voltage (V)

T_A- Free-Air Temperature (°C)

D003

D004

f_SCL= 400 kHz

I/Os = High or Low

Inputs

T_A= 25°C

I/Os = High or Low

Inputs

Figure 3. Supply Current (I_CC, Operating Mode) vs Supply

Voltage (V_CC

Figure 4. Output Low Voltage (V_OL) vs Temperature (T_A) for

P-Port I/Os

)

500

1.8 V

2.5 V

3.3 V

5 V

V_CC= 1.8 V, I_OH= 8 mA

V_CC= 5 V, I_OH= 8 mA

V_CC= 1.65 V, I_OH= 10 mA

V_CC= 5 V, I_OH= 10 mA

450

400

350

300

250

200

150

100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

-40

-15

V_OL- Output Low Voltage - (V)

T_A- Free-Air Temperature (°C)

D005

D006

T_A= 25°C

Figure 5. Sink Current (I_OL) vs Output Low Voltage (V_OL) for

P-Ports at Four Supply Voltages

Figure 6. Output High Voltage (V_CC– V_OH) vs Temperature

(T_A) for P-Ports

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

Typical Characteristics (continued)

T_A= 25°C (unless otherwise noted)

1.8 V

2.5 V

3.3 V

5 V

I_OH= -8 mA

I_OH= -10 mA

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

(V_CC- V_OH) - Output High Voltage (V)

V_CC- Supply Voltage (V)

D007

D008

T_A= 25°C

Figure 7. Source Current (I_OH) vs Output High Voltage (V_OH

)

Figure 8. Output High Voltage (V_OH) vs Supply Voltage (V_CC

)

for P-Ports at Four Supply Voltages

for P-Ports

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

7 Parameter Measurement Information

= 1 kΩ

SDA

DUT

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Data

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

Bit 0

(LSB)

Bit 07

(MSB)

Bit 10 Condition

(LSB)

(P)

scl

sch

0.7 × V

0.3 × V

SCL

SDA

icr

sts

PHL

icf

buf

PLH

0.7 × V

0.3 × V

icf

icr

sdh

sps

sth

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

DESCRIPTION

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 9. I²C Interface Load Circuit and Voltage Waveforms

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

Parameter Measurement Information (continued)

= 4.7 kΩ

INT

DUT

= 100 pF

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

Start

8 Bits

From Slave

Condition

R/W

(One Data Byte)

From Port

Slave Address

Data From Port

Data 2

Data 1

A1 A0

INT

sps

Data

Into

Port

Address

Data 1

Data 2

0.7 × V

0.3 × V

0.7 × V

0.3 × V

SCL

INT

R/W

0.7 × V

0.3 × V

0.7 × V

0.3 × V

INT

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 10. Interrupt Load Circuit and Voltage Waveforms

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

Parameter Measurement Information (continued)

500 Ω

DUT

2 × V

= 50 pF

500 Ω

(see Note A)

P-PORT LOAD CONFIGURATION

0.7 × V

SCL

0.3 × V

Slave

ACK

SDA

(see Note B)

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 × V

0.3 × V

SCL

0.7 × V

0.3 × V

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. All parameters and waveforms are not applicable to all devices.

Figure 11. P-Port Load Circuit and Voltage Waveforms

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

Parameter Measurement Information (continued)

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

Figure 12. Reset Load Circuits and Voltage Waveforms

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TCA9538 is an 8-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 1.65-V to 5.5-V

V_CCoperation. It provides general-purpose remote I/O expansion for most micro-controller families via the

I²C interface (serial clock, SCL, and serial data, SDA, pins).

The TCA9538 open-drain interrupt (INT) output is activated when any input state differs from its

corresponding Input Port register state and is used to indicate to the system master that an input state has

changed. The INT pin can be connected to the interrupt input of a micro-controller. By sending an interrupt

signal on this line, the remote I/O can inform the micro-controller if there is incoming data on its ports without

having to communicate via the I2C bus. Thus, the TCA9538 can remain a simple slave device. The device

outputs (latched) have high-current drive capability for directly driving LEDs.

Two hardware pins (A0 and A1) are used to program and vary the fixed I²C slave address and allow up to

four devices to share the same I²C bus or SMBus.

The system master can reset the TCA9538 in the event of a timeout or other improper operation by asserting

a low on the RESET input pin or by cycling the power supply and causing a power-on reset (POR). A reset

puts the registers in their default state and initializes the I²C /SMBus state machine. The RESET feature and

a POR cause the same reset/initialization to occur, but the RESET feature does so without powering down

the part.

The TCA9538 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and

Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs.

However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O

configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port

registers can be read by the system master.

The TCA9538 is identical to the TCA9554 except for the removal of the internal I/O pull-up resistors, which

greatly reduces power consumption when the I/Os are held LOW, the replacement of A2 with RESET, and

different slave address range.

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

8.2 Functional Block Diagram

Interrupt

Logic

INT

LP Filter

P7−P0

SCL

Input

I C Bus

Control

Shift

I/O

8 Bits

Port

Filter

SDA

Write Pulse

Read Pulse

RESET

Power-On

Reset

VCC

GND

Pin numbers shown are for the PW package.

Figure 13. Functional Block Diagram

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

Functional Block Diagram (continued)

Data From

Shift Register

Configuration

Output Port

Data From

Shift Register

Write Configuration

Pulse

P0 to P7

Write Pulse

ESD Protection

Diode

Output Port

Input Port

GND

Input Port

Read Pulse

To INT

Data From

Polarity

Shift Register

Write Polarity

Pulse

Polarity

Inversion

At power-on reset, all registers return to default values.

Figure 14. Simplified Schematic of P0 to P7

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input

voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In

this case, there are low impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of any P-port I/O configured as an input. After time t_iv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the ports is changed back to the

original state or when data is read from the Input Port register. Resetting occurs in the read mode at the

acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse

can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after

resetting is detected and is transmitted as an interrupt on the INT pin.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to V_CC

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

Feature Description (continued)

8.3.3 RESET Input

The RESET input can be asserted to reset the system while keeping the V_CCat its operating level. A reset can

be accomplished by holding the RESET pin low for a minimum of t_W. The TCA9538 registers and I²C/SMBus

state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels

at the P port can be changed externally or through the master. This input requires a pull-up resistor to V_CCif no

active connection is used.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9538 in a reset condition

until V_CChas reached V_PORR. At that point, the reset condition is released and the TCA9538 registers and

SMBus/I²C state machine initialize to their default states. After that, V_CCmust be lowered to below V_PORFand

then back up to the operating voltage for a power-on reset cycle.

8.5 Programming

8.5.1 I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 15). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device must

not be changed between the Start and the Stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 16).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 15).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 17). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

Start Condition

Stop Condition

Figure 15. Definition of Start and Stop Conditions

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

Programming (continued)

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 16. Bit Transfer

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

Start

Clock Pulse for

Condition

Acknowledgment

Figure 17. Acknowledgment on I²C Bus

Table 1 shows the TCA9538 interface definition.

Table 1. Interface Definition Table

BIT

BYTE

7 (MSB)

0 (LSB)

I²C slave address

Px I/O data bus

R/W

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

8.6 Register Map

8.6.1 Device Address

Figure 18 shows the address byte of the TCA9538.

R/W

Slave Address

A1 A0

Fixed

Programmable

Figure 18. TCA9538 Address

Table 2 shows the Address Reference of the TCA9538.

Table 2. Address Reference Table

INPUTS

I²C BUS SLAVE ADDRESS

112 (decimal), 70 (hexadecimal)

113 (decimal), 71 (hexadecimal)

114 (decimal), 72 (hexadecimal)

115 (decimal), 73 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the TCA9538 (see Figure 19). Two bits of this command byte state the operation

(read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

B2 B1 B0

Figure 19. Control Register Bits

Table 3 shows the TCA9538 Command byte.

Table 3. Command Byte Table

CONTROL REGISTER BITS

COMMAND BYTE

PROTOCOL

POWER-UP DEFAULT

(HEX)

0x00

0x01

0x02

0x03

Input Port

Output Port

Read byte

XXXX XXXX

1111 1111

0000 0000

1111 1111

Read/write byte

Polarity Inversion

Configuration

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these

registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the

Input Port register is accessed next. See Table 4.

Table 4. Register 0 (Input Port Register) Table

BIT

DEFAULT

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

Table 5.

Table 5. Register 1 (Output Port Register) Table

BIT

DEFAULT

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration

register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this

Table 6. Register 2 (Polarity Inversion Register) Table

BIT

DEFAULT

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output. See Table 7.

Table 7. Register 3 (Configuration Register) Table

BIT

DEFAULT

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9538 through write and read commands.

8.6.3.1.1 Writes

Data is transmitted to the TCA9538 by sending the device address and setting the least-significant bit (LSB) to a

logic 0 (see Figure 18 for device address). The command byte is sent after the address and determines which

the number of data bytes sent in one write transmission.

SCL

Slave Address

Command Byte

Data to Port

Data 1

A1 A0

SDA

ACK From Slave

R/W ACK From Slave

Start Condition

Write to Port

Data Out

Data 1 Valid

From Port

Figure 20. Write to Output Port Register

<br/>

SCL

Slave Address

Command Byte

Data to Register

Data

SDA

A1 A0

1/0

Start Condition

R/W ACK From Slave

ACK From Slave

Data to

Figure 21. Write to Configuration or Polarity Inversion Registers

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

8.6.3.1.2 Reads

The bus master first must send the TCA9538 address with the LSB set to a logic 0 (see Figure 18 for device

address). The command byte is sent after the address and determines which register is accessed. After a restart,

the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the

command byte then is sent by the TCA9538 (see Figure 22 and Figure 23). After a restart, the value of the

clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data

bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data.

ACK From

Master

ACK From

Slave

ACK From

Slave

ACK From

Slave

Data from Register

Data

Slave Address

Command Byte

A1 A0 1

R/W

0 A1 A0 0

R/W

NACK From

Data from Register

Master

Data

Last Byte

Figure 22. Read From Register

<br/>

SCL

SDA

Data From Port

Data 1

Slave Address

Data From Port

Data 4

A1 A0

R/W

Start

Condition

NACK From

Master

ACK From

Slave

ACK From

Master

Stop

Condition

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

INT

A. This figure assumes the command byte has previously been programmed with 00h.

B. Transfer of data can be stopped at any moment by a Stop condition.

C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port. See Figure 22 for these details.

Figure 23. Read From Input Port Register

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 24 shows an application in which the TCA9538 can be used.

9.2 Typical Application

100 kΩ

2 kΩ

10 kΩ⁽¹⁾10 kΩ⁽¹⁾

(x 3)

10 kΩ 10 kΩ

VCC

Subsystem 1

SDA

SCL

SDA

(e.g., temperature sensor)

Master

Controller

SCL

INT

RESET

GND

Subsystem 2

(e.g., counter)

TCA9538

Controlled Device

(e.g., CBT device)

ENABLE

GND

ALARM

Subsystem 3

(e.g., alarm system)

(1) The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply

that could be powered on while VCC is powered off, then the supply current, ICC, increases as a result.

A. Device address is configured as 1110000 for this example.

B. P0, P2, and P3 are configured as outputs.

C. P1, P4, and P5 are configured as inputs.

D. P6 and P7 are not used and must be configured as outputs.

Figure 24. Application Schematic

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Minimizing I_CCWhen I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to V_CCthrough a resistor as shown in

Figure 24. For a P-port configured as an input, I_CCincreases as V_Ibecomes lower than V_CC. The LED is a diode,

with threshold voltage V_T, and when a P-port is configured as an input the LED is off but V_Iis a V_Tdrop below

V_CC

For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or

equal to V_CCwhen the P-ports are configured as input to minimize current consumption. Figure 25 shows a high-

value resistor in parallel with the LED. Figure 26 shows V_CCless than the LED supply voltage by at least V_T.

Both of these methods maintain the I/O V_Iat or above V_CCand prevents additional supply current consumption

when the P-port is configured as an input and the LED is off.

LED

100 k

LEDx

Figure 25. High-Value Resistor in Parallel with LED

5 V

3.3 V

LED

LEDx

Figure 26. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, R_P, for the SCL and SDA lines need to be selected appropriately and take into

consideration the total capacitance of all slaves on the I²C bus. The minimum pull-up resistance is a function of

V_CC, V_OL,(max), and I_OLas shown in Equation 1:

V_CC- V_OL(max)

R_p(min)

I_OL

(1)

The maximum pull-up resistance is a function of the maximum rise time, t_r(300 ns for fast-mode operation, f_SCL

400 kHz) and bus capacitance, C_bas shown in Equation 2:

t_r

R_p(max)

0.8473´C_b

(2)

The maximum bus capacitance for an I²C bus must not exceed 400 pF for standard-mode or fast-mode

operation. The bus capacitance can be approximated by adding the capacitance of the TCA9538, C_ifor SCL or

C_iofor SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

Typical Application (continued)

9.2.3 Application Curves

1.8

1.6

1.4

1.2

Standard-mode

Fast-mode

0.8

0.6

0.4

0.2

V_CC> 2V

V_CC<= 2

100 150 200 250 300 350 400 450

C_b(pF)

0.5

1.5

2.5

V_CC(V)

3.5

4.5

5.5

D008

D009

Standard-mode

Fast-mode

V_OL= 0.2*V_CC, I_OL= 2 mA

when V_CC≤ 2 V

(f_SCL= 100 kHz, t_r= 1 µs)

(f_SCL= 400 kHz, t_r= 300 ns)

V_OL= 0.4 V, I_OL= 3 mA

when V_CC> 2 V

Figure 27. Maximum Pull-Up Resistance (R_p(max)) vs Bus

Capacitance (C_b)

Figure 28. Minimum Pull-Up Resistance (R_p(min)) vs Pull-Up

Reference Voltage (V_CC

)

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the TCA9538 can be reset to its default conditions by using the power-

on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in and Figure 29.

Ramp-Down

Ramp-Up

CC_TRR

drops below V_PORF– 50 mV

Time

Time to Re-Ramp

CC_FT

CC_RT

Figure 29. V_CCis Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 8 specifies the performance of the power-on reset feature for the TCA9538 for both types of power-on

reset.

Table 8. Recommended Supply Sequencing And Ramp Rates⁽¹⁾

PARAMETER

MIN

MAX UNIT

V_{CC_FT}

V_{CC_RT}

Fall rate

See Figure 29

Rise rate

0.1

Time to re-ramp (when V_CCdrops to V_{POR_MIN}– 50 mV or when

V_CCdrops to GND)

V_{CC_TRR}

V_{CC_GH}

V_{CC_GW}

See Figure 29

See Figure 30

μs

Level that V_CCcan glitch down to, but not cause a functional

disruption when V_{CC_GW}= 1 µs

1.2

Glitch width that does not cause a functional disruption when

V_{CC_GH}= 0.5 × V_CC(For VCC > 3 V)

μs

(1) All supply sequencing and ramp rate values are measured at T_A= 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. Figure 30 and Table 8 provide more

information on how to measure these specifications.

CC_GH

Time

CC_GW

Figure 30. Glitch Width and Glitch Height

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition is released and all the

registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers based

on the V_CCbeing lowered to or from 0. Figure 31 and Table 8 provide more details on this specification.

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

POR

PORF

Time

POR

Time

Figure 31. V_POR

TCA9538

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9538, common PCB layout practices must be followed but

additional concerns related to high-speed data transfer such as matched impedances and differential pairs are

not a concern for I²C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors

are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in

the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors must be placed as close to the TCA9538 as possible. These best practices are shown in Figure 32.

For the layout example provided in Figure 32, it would be possible to fabricate a PCB with only 2 layers by using

the top layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND). However,

a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to

route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other

internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are

placed directly next to the surface mount component pad which needs to attach to V_CCor GND and the via is

connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace

needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 32.

11.2 Layout Example

LEGEND

Power or GND Plane

To I2C Master

VIA to Power Plane

V_CC

VIA to GND Plane

By-pass/De-coupling

capacitors

VCC

SDA

SCL

INT

RESET

GND

Figure 32. TCA9538 Layout

TCA9538

www.ti.com.cn

ZHCSCT9D –AUGUST 2014–REVISED OCTOBER 2016

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ

TCA9538 [TI]

相关型号：

TCA9538DBR

TCA9538PWR

TCA9539

TCA9539-Q1

TCA9539PWR

TCA9539QPWRQ1

TCA9539RGER

TCA9539RTWR

TCA9539_15

TCA9543A

TCA9543ADR

TCA9543APWR